drivers/net/wireless/rockchip_wlan/rtl8723bu/include/rtl8723b_spec.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *******************************************************************************/\r
  19 #ifndef __RTL8723B_SPEC_H__\r
  20 #define __RTL8723B_SPEC_H__\r
  21 \r
  22 #include <drv_conf.h>\r
  23 \r
  24 \r
  25 #define HAL_NAV_UPPER_UNIT_8723B                128             // micro-second\r
  26 \r
  27 //-----------------------------------------------------\r
  28 //\r
  29 //      0x0000h ~ 0x00FFh       System Configuration\r
  30 //\r
  31 //-----------------------------------------------------\r
  32 #define REG_RSV_CTRL_8723B                              0x001C  // 3 Byte\r
  33 #define REG_BT_WIFI_ANTENNA_SWITCH_8723B        0x0038\r
  34 #define REG_HSISR_8723B                                 0x005c\r
  35 #define REG_PAD_CTRL1_8723B             0x0064\r
  36 #define REG_AFE_CTRL_4_8723B            0x0078\r
  37 #define REG_HMEBOX_DBG_0_8723B  0x0088\r
  38 #define REG_HMEBOX_DBG_1_8723B  0x008A\r
  39 #define REG_HMEBOX_DBG_2_8723B  0x008C\r
  40 #define REG_HMEBOX_DBG_3_8723B  0x008E\r
  41 #define REG_HIMR0_8723B                                 0x00B0\r
  42 #define REG_HISR0_8723B                                 0x00B4\r
  43 #define REG_HIMR1_8723B                                 0x00B8\r
  44 #define REG_HISR1_8723B                                 0x00BC\r
  45 #define REG_PMC_DBG_CTRL2_8723B                 0x00CC\r
  46 \r
  47 //-----------------------------------------------------\r
  48 //\r
  49 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
  50 //\r
  51 //-----------------------------------------------------\r
  52 #define REG_C2HEVT_CMD_ID_8723B 0x01A0\r
  53 #define REG_C2HEVT_CMD_LEN_8723B        0x01AE\r
  54 #define REG_WOWLAN_WAKE_REASON 0x01C7\r
  55 #define REG_WOWLAN_GTK_DBG1     0x630\r
  56 #define REG_WOWLAN_GTK_DBG2     0x634\r
  57 \r
  58 #define REG_HMEBOX_EXT0_8723B                   0x01F0\r
  59 #define REG_HMEBOX_EXT1_8723B                   0x01F4\r
  60 #define REG_HMEBOX_EXT2_8723B                   0x01F8\r
  61 #define REG_HMEBOX_EXT3_8723B                   0x01FC\r
  62 \r
  63 //-----------------------------------------------------\r
  64 //\r
  65 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
  66 //\r
  67 //-----------------------------------------------------\r
  68 \r
  69 //-----------------------------------------------------\r
  70 //\r
  71 //      0x0280h ~ 0x02FFh       RXDMA Configuration\r
  72 //\r
  73 //-----------------------------------------------------\r
  74 #define REG_RXDMA_CONTROL_8723B         0x0286 // Control the RX DMA.\r
  75 #define REG_RXDMA_MODE_CTRL_8723B               0x0290\r
  76 \r
  77 //-----------------------------------------------------\r
  78 //\r
  79 //      0x0300h ~ 0x03FFh       PCIe\r
  80 //\r
  81 //-----------------------------------------------------\r
  82 #define REG_PCIE_CTRL_REG_8723B         0x0300\r
  83 #define REG_INT_MIG_8723B                               0x0304  // Interrupt Migration \r
  84 #define REG_BCNQ_DESA_8723B                     0x0308  // TX Beacon Descriptor Address\r
  85 #define REG_HQ_DESA_8723B                               0x0310  // TX High Queue Descriptor Address\r
  86 #define REG_MGQ_DESA_8723B                      0x0318  // TX Manage Queue Descriptor Address\r
  87 #define REG_VOQ_DESA_8723B                      0x0320  // TX VO Queue Descriptor Address\r
  88 #define REG_VIQ_DESA_8723B                              0x0328  // TX VI Queue Descriptor Address\r
  89 #define REG_BEQ_DESA_8723B                      0x0330  // TX BE Queue Descriptor Address\r
  90 #define REG_BKQ_DESA_8723B                      0x0338  // TX BK Queue Descriptor Address\r
  91 #define REG_RX_DESA_8723B                               0x0340  // RX Queue     Descriptor Address\r
  92 #define REG_DBI_WDATA_8723B                     0x0348  // DBI Write Data\r
  93 #define REG_DBI_RDATA_8723B                     0x034C  // DBI Read Data\r
  94 #define REG_DBI_ADDR_8723B                              0x0350  // DBI Address\r
  95 #define REG_DBI_FLAG_8723B                              0x0352  // DBI Read/Write Flag\r
  96 #define REG_MDIO_WDATA_8723B            0x0354  // MDIO for Write PCIE PHY\r
  97 #define REG_MDIO_RDATA_8723B                    0x0356  // MDIO for Reads PCIE PHY\r
  98 #define REG_MDIO_CTL_8723B                      0x0358  // MDIO for Control\r
  99 #define REG_DBG_SEL_8723B                               0x0360  // Debug Selection Register\r
 100 #define REG_PCIE_HRPWM_8723B                    0x0361  //PCIe RPWM\r
 101 #define REG_PCIE_HCPWM_8723B                    0x0363  //PCIe CPWM\r
 102 #define REG_PCIE_MULTIFET_CTRL_8723B    0x036A  //PCIE Multi-Fethc Control\r
 103 \r
 104 //-----------------------------------------------------\r
 105 //\r
 106 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
 107 //\r
 108 //-----------------------------------------------------\r
 109 #define REG_TXPKTBUF_BCNQ_BDNY_8723B    0x0424\r
 110 #define REG_TXPKTBUF_MGQ_BDNY_8723B     0x0425\r
 111 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B       0x045D\r
 112 #ifdef CONFIG_WOWLAN\r
 113 #define REG_TXPKTBUF_IV_LOW             0x0484\r
 114 #define REG_TXPKTBUF_IV_HIGH            0x0488\r
 115 #endif\r
 116 #define REG_AMPDU_BURST_MODE_8723B      0x04BC\r
 117 \r
 118 //-----------------------------------------------------\r
 119 //\r
 120 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
 121 //\r
 122 //-----------------------------------------------------\r
 123 #define REG_SECONDARY_CCA_CTRL_8723B    0x0577\r
 124 \r
 125 //-----------------------------------------------------\r
 126 //\r
 127 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
 128 //\r
 129 //-----------------------------------------------------\r
 130 \r
 131 \r
 132 //============================================================\r
 133 // SDIO Bus Specification\r
 134 //============================================================\r
 135 \r
 136 //-----------------------------------------------------\r
 137 // SDIO CMD Address Mapping\r
 138 //-----------------------------------------------------\r
 139 \r
 140 //-----------------------------------------------------\r
 141 // I/O bus domain (Host)\r
 142 //-----------------------------------------------------\r
 143 \r
 144 //-----------------------------------------------------\r
 145 // SDIO register\r
 146 //-----------------------------------------------------\r
 147 #define SDIO_REG_HCPWM1_8723B   0x025 // HCI Current Power Mode 1\r
 148 \r
 149 \r
 150 //============================================================================\r
 151 //      8723 Regsiter Bit and Content definition\r
 152 //============================================================================\r
 153 \r
 154 //2 HSISR\r
 155 // interrupt mask which needs to clear\r
 156 #define MASK_HSISR_CLEAR                (HSISR_GPIO12_0_INT |\\r
 157                                                                 HSISR_SPS_OCP_INT |\\r
 158                                                                 HSISR_RON_INT |\\r
 159                                                                 HSISR_PDNINT |\\r
 160                                                                 HSISR_GPIO9_INT)\r
 161 \r
 162 //-----------------------------------------------------\r
 163 //\r
 164 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
 165 //\r
 166 //-----------------------------------------------------\r
 167 #undef IS_E_CUT\r
 168 #define IS_E_CUT(version)               FALSE\r
 169 #undef IS_F_CUT\r
 170 #define IS_F_CUT(version)               ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)\r
 171 \r
 172 //-----------------------------------------------------\r
 173 //\r
 174 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
 175 //\r
 176 //-----------------------------------------------------\r
 177 \r
 178 //-----------------------------------------------------\r
 179 //\r
 180 //      0x0280h ~ 0x02FFh       RXDMA Configuration\r
 181 //\r
 182 //-----------------------------------------------------\r
 183 #define BIT_USB_RXDMA_AGG_EN    BIT(31)\r
 184 #define RXDMA_AGG_MODE_EN               BIT(1)\r
 185 \r
 186 #ifdef CONFIG_WOWLAN\r
 187 #define RXPKT_RELEASE_POLL              BIT(16)\r
 188 #define RXDMA_IDLE                              BIT(17)\r
 189 #define RW_RELEASE_EN                   BIT(18)\r
 190 #endif\r
 191 \r
 192 //-----------------------------------------------------\r
 193 //\r
 194 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
 195 //\r
 196 //-----------------------------------------------------\r
 197 \r
 198 //----------------------------------------------------------------------------\r
 199 //       8723B REG_CCK_CHECK                                            (offset 0x454)\r
 200 //----------------------------------------------------------------------------\r
 201 #define BIT_BCN_PORT_SEL                BIT5\r
 202 \r
 203 //-----------------------------------------------------\r
 204 //\r
 205 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
 206 //\r
 207 //-----------------------------------------------------\r
 208 \r
 209 //-----------------------------------------------------\r
 210 //\r
 211 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
 212 //\r
 213 //-----------------------------------------------------\r
 214 #ifdef CONFIG_RF_GAIN_OFFSET\r
 215 \r
 216 #ifdef CONFIG_RTL8723B\r
 217 #define EEPROM_RF_GAIN_OFFSET                   0xC1\r
 218 #endif\r
 219 \r
 220 #define EEPROM_RF_GAIN_VAL                              0x1F6\r
 221 #endif //CONFIG_RF_GAIN_OFFSET\r
 222 \r
 223 \r
 224 //----------------------------------------------------------------------------\r
 225 //       8195 IMR/ISR bits                                              (offset 0xB0,  8bits)\r
 226 //----------------------------------------------------------------------------\r
 227 #define IMR_DISABLED_8723B                                      0\r
 228 // IMR DW0(0x00B0-00B3) Bit 0-31\r
 229 #define IMR_TIMER2_8723B                                        BIT31           // Timeout interrupt 2\r
 230 #define IMR_TIMER1_8723B                                        BIT30           // Timeout interrupt 1  \r
 231 #define IMR_PSTIMEOUT_8723B                             BIT29           // Power Save Time Out Interrupt\r
 232 #define IMR_GTINT4_8723B                                        BIT28           // When GTIMER4 expires, this bit is set to 1   \r
 233 #define IMR_GTINT3_8723B                                        BIT27           // When GTIMER3 expires, this bit is set to 1   \r
 234 #define IMR_TXBCN0ERR_8723B                             BIT26           // Transmit Beacon0 Error                       \r
 235 #define IMR_TXBCN0OK_8723B                              BIT25           // Transmit Beacon0 OK                  \r
 236 #define IMR_TSF_BIT32_TOGGLE_8723B              BIT24           // TSF Timer BIT32 toggle indication interrupt                  \r
 237 #define IMR_BCNDMAINT0_8723B                            BIT20           // Beacon DMA Interrupt 0                       \r
 238 #define IMR_BCNDERR0_8723B                              BIT16           // Beacon Queue DMA OK0                 \r
 239 #define IMR_HSISR_IND_ON_INT_8723B              BIT15           // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\r
 240 #define IMR_BCNDMAINT_E_8723B                   BIT14           // Beacon DMA Interrupt Extension for Win7                      \r
 241 #define IMR_ATIMEND_8723B                               BIT12           // CTWidnow End or ATIM Window End\r
 242 #define IMR_C2HCMD_8723B                                        BIT10           // CPU to Host Command INT Status, Write 1 clear        \r
 243 #define IMR_CPWM2_8723B                                 BIT9                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 244 #define IMR_CPWM_8723B                                  BIT8                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 245 #define IMR_HIGHDOK_8723B                               BIT7                    // High Queue DMA OK    \r
 246 #define IMR_MGNTDOK_8723B                               BIT6                    // Management Queue DMA OK      \r
 247 #define IMR_BKDOK_8723B                                 BIT5                    // AC_BK DMA OK         \r
 248 #define IMR_BEDOK_8723B                                 BIT4                    // AC_BE DMA OK \r
 249 #define IMR_VIDOK_8723B                                 BIT3                    // AC_VI DMA OK         \r
 250 #define IMR_VODOK_8723B                                 BIT2                    // AC_VO DMA OK \r
 251 #define IMR_RDU_8723B                                   BIT1                    // Rx Descriptor Unavailable    \r
 252 #define IMR_ROK_8723B                                   BIT0                    // Receive DMA OK\r
 253 \r
 254 // IMR DW1(0x00B4-00B7) Bit 0-31\r
 255 #define IMR_BCNDMAINT7_8723B                            BIT27           // Beacon DMA Interrupt 7\r
 256 #define IMR_BCNDMAINT6_8723B                            BIT26           // Beacon DMA Interrupt 6\r
 257 #define IMR_BCNDMAINT5_8723B                            BIT25           // Beacon DMA Interrupt 5\r
 258 #define IMR_BCNDMAINT4_8723B                            BIT24           // Beacon DMA Interrupt 4\r
 259 #define IMR_BCNDMAINT3_8723B                            BIT23           // Beacon DMA Interrupt 3\r
 260 #define IMR_BCNDMAINT2_8723B                            BIT22           // Beacon DMA Interrupt 2\r
 261 #define IMR_BCNDMAINT1_8723B                            BIT21           // Beacon DMA Interrupt 1\r
 262 #define IMR_BCNDOK7_8723B                                       BIT20           // Beacon Queue DMA OK Interrup 7\r
 263 #define IMR_BCNDOK6_8723B                                       BIT19           // Beacon Queue DMA OK Interrup 6\r
 264 #define IMR_BCNDOK5_8723B                                       BIT18           // Beacon Queue DMA OK Interrup 5\r
 265 #define IMR_BCNDOK4_8723B                                       BIT17           // Beacon Queue DMA OK Interrup 4\r
 266 #define IMR_BCNDOK3_8723B                                       BIT16           // Beacon Queue DMA OK Interrup 3\r
 267 #define IMR_BCNDOK2_8723B                                       BIT15           // Beacon Queue DMA OK Interrup 2\r
 268 #define IMR_BCNDOK1_8723B                                       BIT14           // Beacon Queue DMA OK Interrup 1\r
 269 #define IMR_ATIMEND_E_8723B                             BIT13           // ATIM Window End Extension for Win7\r
 270 #define IMR_TXERR_8723B                                 BIT11           // Tx Error Flag Interrupt Status, write 1 clear.\r
 271 #define IMR_RXERR_8723B                                 BIT10           // Rx Error Flag INT Status, Write 1 clear\r
 272 #define IMR_TXFOVW_8723B                                        BIT9                    // Transmit FIFO Overflow\r
 273 #define IMR_RXFOVW_8723B                                        BIT8                    // Receive FIFO Overflow\r
 274 \r
 275 #ifdef CONFIG_PCI_HCI\r
 276 //#define IMR_RX_MASK           (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B)\r
 277 #define IMR_TX_MASK                     (IMR_VODOK_8723B|IMR_VIDOK_8723B|IMR_BEDOK_8723B|IMR_BKDOK_8723B|IMR_MGNTDOK_8723B|IMR_HIGHDOK_8723B)\r
 278 \r
 279 #define RT_BCN_INT_MASKS        (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)\r
 280 \r
 281 #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B|IMR_BKDOK_8723B)\r
 282 #endif\r
 283 \r
 284 //========================================================\r
 285 // General definitions\r
 286 //========================================================\r
 287 \r
 288 #define MACID_NUM_8723B 128\r
 289 #define CAM_ENTRY_NUM_8723B 64\r
 290 \r
 291 #endif /* __RTL8723B_SPEC_H__ */\r
 292 \r