1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __HAL_COMMON_REG_H__
21 #define __HAL_COMMON_REG_H__
24 #define MAC_ADDR_LEN 6
26 #define HAL_NAV_UPPER_UNIT 128 // micro-second
28 // 8188E PKT_BUFF_ACCESS_CTRL value
29 #define TXPKT_BUF_SELECT 0x69
30 #define RXPKT_BUF_SELECT 0xA5
31 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
33 //============================================================
35 //============================================================
37 //-----------------------------------------------------
39 // 0x0000h ~ 0x00FFh System Configuration
41 //-----------------------------------------------------
42 #define REG_SYS_ISO_CTRL 0x0000
43 #define REG_SYS_FUNC_EN 0x0002
44 #define REG_APS_FSMCO 0x0004
45 #define REG_SYS_CLKR 0x0008
46 #define REG_SYS_CLK_CTRL REG_SYS_CLKR
47 #define REG_9346CR 0x000A
48 #define REG_SYS_EEPROM_CTRL 0x000A
49 #define REG_EE_VPD 0x000C
50 #define REG_AFE_MISC 0x0010
51 #define REG_SPS0_CTRL 0x0011
52 #define REG_SPS0_CTRL_6 0x0016
53 #define REG_POWER_OFF_IN_PROCESS 0x0017
54 #define REG_SPS_OCP_CFG 0x0018
55 #define REG_RSV_CTRL 0x001C
56 #define REG_RF_CTRL 0x001F
57 #define REG_LDOA15_CTRL 0x0020
58 #define REG_LDOV12D_CTRL 0x0021
59 #define REG_LDOHCI12_CTRL 0x0022
60 #define REG_LPLDO_CTRL 0x0023
61 #define REG_AFE_XTAL_CTRL 0x0024
62 #define REG_AFE_LDO_CTRL 0x0027 // 1.5v for 8188EE test chip, 1.4v for MP chip
63 #define REG_AFE_PLL_CTRL 0x0028
64 #define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl
65 #define REG_APE_PLL_CTRL_EXT 0x002c
66 #define REG_EFUSE_CTRL 0x0030
67 #define REG_EFUSE_TEST 0x0034
68 #define REG_PWR_DATA 0x0038
69 #define REG_CAL_TIMER 0x003C
70 #define REG_ACLK_MON 0x003E
71 #define REG_GPIO_MUXCFG 0x0040
72 #define REG_GPIO_IO_SEL 0x0042
73 #define REG_MAC_PINMUX_CFG 0x0043
74 #define REG_GPIO_PIN_CTRL 0x0044
75 #define REG_GPIO_INTM 0x0048
76 #define REG_LEDCFG0 0x004C
77 #define REG_LEDCFG1 0x004D
78 #define REG_LEDCFG2 0x004E
79 #define REG_LEDCFG3 0x004F
80 #define REG_FSIMR 0x0050
81 #define REG_FSISR 0x0054
82 #define REG_HSIMR 0x0058
83 #define REG_HSISR 0x005c
84 #define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control.
85 #define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select.
86 #define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source.
87 #define REG_GSSR 0x006c
88 #define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E
89 #define REG_XCK_OUT_CTRL 0x007c //RTL8188E
90 #define REG_MCUFWDL 0x0080
91 #define REG_WOL_EVENT 0x0081 //RTL8188E
92 #define REG_MCUTSTCFG 0x0084
93 #define REG_FDHM0 0x0088
94 #define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform
95 #define REG_SYSTEM_ON_CTRL 0x00CC // For 8723AE Reset after S3
96 #define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723
97 #define REG_BIST_SCAN 0x00D0
98 #define REG_BIST_RPT 0x00D4
99 #define REG_BIST_ROM_RPT 0x00D8
100 #define REG_USB_SIE_INTF 0x00E0
101 #define REG_PCIE_MIO_INTF 0x00E4
102 #define REG_PCIE_MIO_INTD 0x00E8
103 #define REG_HPON_FSM 0x00EC
104 #define REG_SYS_CFG 0x00F0
105 #define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only.
106 #define REG_TYPE_ID 0x00FC
109 // 2010/12/29 MH Add for 92D
111 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8
114 //-----------------------------------------------------
116 // 0x0100h ~ 0x01FFh MACTOP General Configuration
118 //-----------------------------------------------------
119 #define REG_CR 0x0100
120 #define REG_PBP 0x0104
121 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106
122 #define REG_TRXDMA_CTRL 0x010C
123 #define REG_TRXFF_BNDY 0x0114
124 #define REG_TRXFF_STATUS 0x0118
125 #define REG_RXFF_PTR 0x011C
126 #define REG_HIMR 0x0120
127 #define REG_HISR 0x0124
128 #define REG_HIMRE 0x0128
129 #define REG_HISRE 0x012C
130 #define REG_CPWM 0x012F
131 #define REG_FWIMR 0x0130
132 #define REG_FWISR 0x0134
133 #define REG_FTIMR 0x0138
134 #define REG_FTISR 0x013C //RTL8192C
135 #define REG_PKTBUF_DBG_CTRL 0x0140
136 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
137 #define REG_PKTBUF_DBG_DATA_L 0x0144
138 #define REG_PKTBUF_DBG_DATA_H 0x0148
140 #define REG_TC0_CTRL 0x0150
141 #define REG_TC1_CTRL 0x0154
142 #define REG_TC2_CTRL 0x0158
143 #define REG_TC3_CTRL 0x015C
144 #define REG_TC4_CTRL 0x0160
145 #define REG_TCUNIT_BASE 0x0164
146 #define REG_MBIST_START 0x0174
147 #define REG_MBIST_DONE 0x0178
148 #define REG_MBIST_FAIL 0x017C
149 #define REG_32K_CTRL 0x0194 //RTL8188E
150 #define REG_C2HEVT_MSG_NORMAL 0x01A0
151 #define REG_C2HEVT_CLEAR 0x01AF
152 #define REG_MCUTST_1 0x01c0
153 #define REG_MCUTST_WOWLAN 0x01C7 // Defined after 8188E series.
154 #define REG_FMETHR 0x01C8
155 #define REG_HMETFR 0x01CC
156 #define REG_HMEBOX_0 0x01D0
157 #define REG_HMEBOX_1 0x01D4
158 #define REG_HMEBOX_2 0x01D8
159 #define REG_HMEBOX_3 0x01DC
160 #define REG_LLT_INIT 0x01E0
163 //-----------------------------------------------------
165 // 0x0200h ~ 0x027Fh TXDMA Configuration
167 //-----------------------------------------------------
168 #define REG_RQPN 0x0200
169 #define REG_FIFOPAGE 0x0204
170 #define REG_TDECTRL 0x0208
171 #define REG_TXDMA_OFFSET_CHK 0x020C
172 #define REG_TXDMA_STATUS 0x0210
173 #define REG_RQPN_NPQ 0x0214
174 #define REG_AUTO_LLT 0x0224
177 //-----------------------------------------------------
179 // 0x0280h ~ 0x02FFh RXDMA Configuration
181 //-----------------------------------------------------
182 #define REG_RXDMA_AGG_PG_TH 0x0280
183 #define REG_RXPKT_NUM 0x0284
184 #define REG_RXDMA_STATUS 0x0288
186 //-----------------------------------------------------
188 // 0x0300h ~ 0x03FFh PCIe
190 //-----------------------------------------------------
191 #define REG_PCIE_CTRL_REG 0x0300
192 #define REG_INT_MIG 0x0304 // Interrupt Migration
193 #define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
194 #define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
195 #define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
196 #define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address
197 #define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address
198 #define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address
199 #define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address
200 #define REG_RX_DESA 0x0340 // RX Queue Descriptor Address
201 //sherry added for DBI Read/Write 20091126
202 #define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration
203 #define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
204 #define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration
205 #define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration
206 #define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
207 #define REG_DBG_SEL 0x0360 // Debug Selection Register
208 #define REG_PCIE_HRPWM 0x0361 //PCIe RPWM
209 #define REG_PCIE_HCPWM 0x0363 //PCIe CPWM
210 #define REG_WATCH_DOG 0x0368
212 // RTL8723 series -------------------------------
213 #define REG_PCIE_HISR_EN 0x0394 //PCIE Local Interrupt Enable Register
214 #define REG_PCIE_HISR 0x03A0
215 #define REG_PCIE_HISRE 0x03A4
216 #define REG_PCIE_HIMR 0x03A8
217 #define REG_PCIE_HIMRE 0x03AC
219 #define REG_USB_HIMR 0xFE38
220 #define REG_USB_HIMRE 0xFE3C
221 #define REG_USB_HISR 0xFE78
222 #define REG_USB_HISRE 0xFE7C
225 //-----------------------------------------------------
227 // 0x0400h ~ 0x047Fh Protocol Configuration
229 //-----------------------------------------------------
232 #define REG_VOQ_INFO 0x0400
233 #define REG_VIQ_INFO 0x0404
234 #define REG_BEQ_INFO 0x0408
235 #define REG_BKQ_INFO 0x040C
237 /* 88E, 8723A, 8812A, 8821A, 92E, 8723B */
238 #define REG_Q0_INFO 0x400
239 #define REG_Q1_INFO 0x404
240 #define REG_Q2_INFO 0x408
241 #define REG_Q3_INFO 0x40C
243 #define REG_MGQ_INFO 0x0410
244 #define REG_HGQ_INFO 0x0414
245 #define REG_BCNQ_INFO 0x0418
246 #define REG_TXPKT_EMPTY 0x041A
247 #define REG_CPU_MGQ_INFORMATION 0x041C
248 #define REG_FWHW_TXQ_CTRL 0x0420
249 #define REG_HWSEQ_CTRL 0x0423
250 #define REG_BCNQ_BDNY 0x0424
251 #define REG_MGQ_BDNY 0x0425
252 #define REG_LIFETIME_CTRL 0x0426
253 #define REG_MULTI_BCNQ_OFFSET 0x0427
254 #define REG_SPEC_SIFS 0x0428
255 #define REG_RL 0x042A
256 #define REG_DARFRC 0x0430
257 #define REG_RARFRC 0x0438
258 #define REG_RRSR 0x0440
259 #define REG_ARFR0 0x0444
260 #define REG_ARFR1 0x0448
261 #define REG_ARFR2 0x044C
262 #define REG_ARFR3 0x0450
263 #define REG_BCNQ1_BDNY 0x0457
265 #define REG_AGGLEN_LMT 0x0458
266 #define REG_AMPDU_MIN_SPACE 0x045C
267 #define REG_WMAC_LBK_BF_HD 0x045D
268 #define REG_FAST_EDCA_CTRL 0x0460
269 #define REG_RD_RESP_PKT_TH 0x0463
271 /* 8723A, 8812A, 8821A, 92E, 8723B */
272 #define REG_Q4_INFO 0x468
273 #define REG_Q5_INFO 0x46C
274 #define REG_Q6_INFO 0x470
275 #define REG_Q7_INFO 0x474
277 #define REG_INIRTS_RATE_SEL 0x0480
278 #define REG_INIDATA_RATE_SEL 0x0484
280 /* 8723B, 92E, 8812A, 8821A*/
281 #define REG_MACID_SLEEP_3 0x0484
282 #define REG_MACID_SLEEP_1 0x0488
284 #define REG_POWER_STAGE1 0x04B4
285 #define REG_POWER_STAGE2 0x04B8
286 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0
287 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2
288 #define REG_STBC_SETTING 0x04C4
289 #define REG_QUEUE_CTRL 0x04C6
290 #define REG_SINGLE_AMPDU_CTRL 0x04c7
291 #define REG_PROT_MODE_CTRL 0x04C8
292 #define REG_MAX_AGGR_NUM 0x04CA
293 #define REG_RTS_MAX_AGGR_NUM 0x04CB
294 #define REG_BAR_MODE_CTRL 0x04CC
295 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
298 #define REG_MACID_DROP 0x04D0
301 #define REG_EARLY_MODE_CONTROL 0x04D0
303 /* 8723B, 92E, 8812A, 8821A */
304 #define REG_MACID_SLEEP_2 0x04D0
306 /* 8723A, 8723B, 92E, 8812A, 8821A */
307 #define REG_MACID_SLEEP 0x04D4
309 #define REG_NQOS_SEQ 0x04DC
310 #define REG_QOS_SEQ 0x04DE
311 #define REG_NEED_CPU_HANDLE 0x04E0
312 #define REG_PKT_LOSE_RPT 0x04E1
313 #define REG_PTCL_ERR_STATUS 0x04E2
314 #define REG_TX_RPT_CTRL 0x04EC
315 #define REG_TX_RPT_TIME 0x04F0 // 2 byte
316 #define REG_DUMMY 0x04FC
318 //-----------------------------------------------------
320 // 0x0500h ~ 0x05FFh EDCA Configuration
322 //-----------------------------------------------------
323 #define REG_EDCA_VO_PARAM 0x0500
324 #define REG_EDCA_VI_PARAM 0x0504
325 #define REG_EDCA_BE_PARAM 0x0508
326 #define REG_EDCA_BK_PARAM 0x050C
327 #define REG_BCNTCFG 0x0510
328 #define REG_PIFS 0x0512
329 #define REG_RDG_PIFS 0x0513
330 #define REG_SIFS_CTX 0x0514
331 #define REG_SIFS_TRX 0x0516
332 #define REG_TSFTR_SYN_OFFSET 0x0518
333 #define REG_AGGR_BREAK_TIME 0x051A
334 #define REG_SLOT 0x051B
335 #define REG_TX_PTCL_CTRL 0x0520
336 #define REG_TXPAUSE 0x0522
337 #define REG_DIS_TXREQ_CLR 0x0523
338 #define REG_RD_CTRL 0x0524
340 // Format for offset 540h-542h:
341 // [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
343 // [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
347 // |<--Setup--|--Hold------------>|
348 // --------------|----------------------
351 // Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
352 // Described by Designer Tim and Bruce, 2011-01-14.
354 #define REG_TBTT_PROHIBIT 0x0540
355 #define REG_RD_NAV_NXT 0x0544
356 #define REG_NAV_PROT_LEN 0x0546
357 #define REG_BCN_CTRL 0x0550
358 #define REG_BCN_CTRL_1 0x0551
359 #define REG_MBID_NUM 0x0552
360 #define REG_DUAL_TSF_RST 0x0553
361 #define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE
362 #define REG_DRVERLYINT 0x0558
363 #define REG_BCNDMATIM 0x0559
364 #define REG_ATIMWND 0x055A
365 #define REG_USTIME_TSF 0x055C
366 #define REG_BCN_MAX_ERR 0x055D
367 #define REG_RXTSF_OFFSET_CCK 0x055E
368 #define REG_RXTSF_OFFSET_OFDM 0x055F
369 #define REG_TSFTR 0x0560
370 #define REG_TSFTR1 0x0568 // HW Port 1 TSF Register
371 #define REG_ATIMWND_1 0x0570
372 #define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU)
373 #define REG_PSTIMER 0x0580
374 #define REG_TIMER0 0x0584
375 #define REG_TIMER1 0x0588
376 #define REG_ACMHWCTRL 0x05C0
377 #define REG_NOA_DESC_SEL 0x05CF
378 #define REG_NOA_DESC_DURATION 0x05E0
379 #define REG_NOA_DESC_INTERVAL 0x05E4
380 #define REG_NOA_DESC_START 0x05E8
381 #define REG_NOA_DESC_COUNT 0x05EC
383 #define REG_DMC 0x05F0 //Dual MAC Co-Existence Register
384 #define REG_SCH_TX_CMD 0x05F8
386 #define REG_FW_RESET_TSF_CNT_1 0x05FC
387 #define REG_FW_RESET_TSF_CNT_0 0x05FD
388 #define REG_FW_BCN_DIS_CNT 0x05FE
390 //-----------------------------------------------------
392 // 0x0600h ~ 0x07FFh WMAC Configuration
394 //-----------------------------------------------------
395 #define REG_APSD_CTRL 0x0600
396 #define REG_BWOPMODE 0x0603
397 #define REG_TCR 0x0604
398 #define REG_RCR 0x0608
399 #define REG_RX_PKT_LIMIT 0x060C
400 #define REG_RX_DLK_TIME 0x060D
401 #define REG_RX_DRVINFO_SZ 0x060F
403 #define REG_MACID 0x0610
404 #define REG_BSSID 0x0618
405 #define REG_MAR 0x0620
406 #define REG_MBIDCAMCFG 0x0628
408 #define REG_PNO_STATUS 0x0631
409 #define REG_USTIME_EDCA 0x0638
410 #define REG_MAC_SPEC_SIFS 0x063A
411 // 20100719 Joseph: Hardware register definition change. (HW datasheet v54)
412 #define REG_RESP_SIFS_CCK 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK
413 #define REG_RESP_SIFS_OFDM 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK
415 #define REG_ACKTO 0x0640
416 #define REG_CTS2TO 0x0641
417 #define REG_EIFS 0x0642
421 #define RXERR_TYPE_OFDM_PPDU 0
422 #define RXERR_TYPE_OFDM_FALSE_ALARM 1
423 #define RXERR_TYPE_OFDM_MPDU_OK 2
424 #define RXERR_TYPE_OFDM_MPDU_FAIL 3
425 #define RXERR_TYPE_CCK_PPDU 4
426 #define RXERR_TYPE_CCK_FALSE_ALARM 5
427 #define RXERR_TYPE_CCK_MPDU_OK 6
428 #define RXERR_TYPE_CCK_MPDU_FAIL 7
429 #define RXERR_TYPE_HT_PPDU 8
430 #define RXERR_TYPE_HT_FALSE_ALARM 9
431 #define RXERR_TYPE_HT_MPDU_TOTAL 10
432 #define RXERR_TYPE_HT_MPDU_OK 11
433 #define RXERR_TYPE_HT_MPDU_FAIL 12
434 #define RXERR_TYPE_RX_FULL_DROP 15
436 #define RXERR_COUNTER_MASK 0xFFFFF
437 #define RXERR_RPT_RST BIT(27)
438 #define _RXERR_RPT_SEL(type) ((type) << 28)
442 // The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is
443 // always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending
444 // CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.
445 // The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented
447 // By Bruce, 2011-07-18.
449 #define REG_NAV_UPPER 0x0652 // unit of 128
452 #define REG_NAV_CTRL 0x0650
453 #define REG_BACAMCMD 0x0654
454 #define REG_BACAMCONTENT 0x0658
455 #define REG_LBDLY 0x0660
456 #define REG_FWDLY 0x0661
457 #define REG_RXERR_RPT 0x0664
458 #define REG_WMAC_TRXPTCL_CTL 0x0668
461 #define REG_CAMCMD 0x0670
462 #define REG_CAMWRITE 0x0674
463 #define REG_CAMREAD 0x0678
464 #define REG_CAMDBG 0x067C
465 #define REG_SECCFG 0x0680
468 #define REG_WOW_CTRL 0x0690
469 #define REG_PS_RX_INFO 0x0692
470 #define REG_UAPSD_TID 0x0693
471 #define REG_WKFMCAM_CMD 0x0698
472 #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD
473 #define REG_WKFMCAM_RWD 0x069C
474 #define REG_RXFLTMAP0 0x06A0
475 #define REG_RXFLTMAP1 0x06A2
476 #define REG_RXFLTMAP2 0x06A4
477 #define REG_BCN_PSR_RPT 0x06A8
478 #define REG_BT_COEX_TABLE 0x06C0
481 #define REG_MACID1 0x0700
482 #define REG_BSSID1 0x0708
485 //-----------------------------------------------------
487 // 0xFE00h ~ 0xFE55h USB Configuration
489 //-----------------------------------------------------
490 #define REG_USB_INFO 0xFE17
491 #define REG_USB_SPECIAL_OPTION 0xFE55
492 #define REG_USB_DMA_AGG_TO 0xFE5B
493 #define REG_USB_AGG_TO 0xFE5C
494 #define REG_USB_AGG_TH 0xFE5D
496 #define REG_USB_HRPWM 0xFE58
497 #define REG_USB_HCPWM 0xFE57
499 // for 92DU high_Queue low_Queue Normal_Queue select
500 #define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44
501 //#define REG_USB_LOW_Queue_Select_MAC0 0xFE45
502 #define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47
503 //#define REG_USB_LOW_Queue_Select_MAC1 0xFE48
506 #define REG_TEST_USB_TXQS 0xFE48
507 #define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61
508 #define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63
509 #define REG_TEST_SIE_OPTIONAL 0xFE64
510 #define REG_TEST_SIE_CHIRP_K 0xFE65
511 #define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B
512 #define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
513 #define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9
517 #define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61
518 #define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63
519 #define REG_NORMAL_SIE_OPTIONAL 0xFE64
520 #define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67
521 #define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B
522 #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C
523 #define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only.
524 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75
525 #define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF
528 //-----------------------------------------------------
530 // Redifine 8192C register definition for compatibility
532 //-----------------------------------------------------
534 // TODO: use these definition when using REG_xxx naming rule.
535 // NOTE: DO NOT Remove these definition. Use later.
537 #define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control.
538 #define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test.
539 #define MSR (REG_CR + 2) // Media Status register
540 //#define ISR REG_HISR
542 #define TSFR REG_TSFTR // Timing Sync Function Timer Register.
543 #define TSFR1 REG_TSFTR1 // HW Port 1 TSF Register
547 // Redifine MACID register, to compatible prior ICs.
548 #define IDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053
549 #define IDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055
553 // 9. Security Control Registers (Offset: )
555 #define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd
556 #define WCAMI REG_CAMWRITE // Software write CAM input content
557 #define RCAMO REG_CAMREAD // Software read/write CAM config
558 #define CAMDBG REG_CAMDBG
559 #define SECR REG_SECCFG //Security Configuration Register
562 #define UnusedRegister 0x1BF
563 #define DCAM UnusedRegister
564 #define PSR UnusedRegister
565 #define BBAddr UnusedRegister
566 #define PhyDataR UnusedRegister
568 // Min Spacing related settings.
569 #define MAX_MSS_DENSITY_2T 0x13
570 #define MAX_MSS_DENSITY_1T 0x0A
572 //----------------------------------------------------------------------------
573 // 8192C Cmd9346CR bits (Offset 0xA, 16bit)
574 //----------------------------------------------------------------------------
575 #define CmdEEPROM_En BIT5 // EEPROM enable when set 1
576 #define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
577 #define Cmd9346CR_9356SEL BIT4
579 //----------------------------------------------------------------------------
580 // 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
581 //----------------------------------------------------------------------------
582 #define GPIOSEL_GPIO 0
583 #define GPIOSEL_ENBT BIT5
585 //----------------------------------------------------------------------------
586 // 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
587 //----------------------------------------------------------------------------
588 #define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
589 #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
590 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
591 #define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
593 //----------------------------------------------------------------------------
594 // 8811A GPIO PIN Control Register (offset 0x60, 4 byte)
595 //----------------------------------------------------------------------------
596 #define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 // GPIO pins input value
597 #define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) // GPIO pins output value
598 #define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
599 #define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3)
601 //----------------------------------------------------------------------------
602 // 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte)
603 //----------------------------------------------------------------------------
604 #define HSIMR_GPIO12_0_INT_EN BIT0
605 #define HSIMR_SPS_OCP_INT_EN BIT5
606 #define HSIMR_RON_INT_EN BIT6
607 #define HSIMR_PDN_INT_EN BIT7
608 #define HSIMR_GPIO9_INT_EN BIT25
610 //----------------------------------------------------------------------------
611 // 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
612 //----------------------------------------------------------------------------
613 #define HSISR_GPIO12_0_INT BIT0
614 #define HSISR_SPS_OCP_INT BIT5
615 #define HSISR_RON_INT BIT6
616 #define HSISR_PDNINT BIT7
617 #define HSISR_GPIO9_INT BIT25
619 //----------------------------------------------------------------------------
620 // 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
621 //----------------------------------------------------------------------------
625 01: Link in ad hoc network
626 10: Link in infrastructure network
630 #define MSR_NOLINK 0x00
631 #define MSR_ADHOC 0x01
632 #define MSR_INFRA 0x02
635 //----------------------------------------------------------------------------
637 //----------------------------------------------------------------------------
638 #define USB_C2H_CMDID_OFFSET 0
639 #define USB_C2H_SEQ_OFFSET 1
640 #define USB_C2H_EVENT_OFFSET 2
641 #define USB_INTR_CPWM_OFFSET 16
642 #define USB_INTR_CONTENT_C2H_OFFSET 0
643 #define USB_INTR_CONTENT_CPWM1_OFFSET 16
644 #define USB_INTR_CONTENT_CPWM2_OFFSET 20
645 #define USB_INTR_CONTENT_HISR_OFFSET 48
646 #define USB_INTR_CONTENT_HISRE_OFFSET 52
647 #define USB_INTR_CONTENT_LENGTH 56
649 //----------------------------------------------------------------------------
650 // Response Rate Set Register (offset 0x440, 24bits)
651 //----------------------------------------------------------------------------
654 #define RRSR_5_5M BIT2
655 #define RRSR_11M BIT3
658 #define RRSR_12M BIT6
659 #define RRSR_18M BIT7
660 #define RRSR_24M BIT8
661 #define RRSR_36M BIT9
662 #define RRSR_48M BIT10
663 #define RRSR_54M BIT11
664 #define RRSR_MCS0 BIT12
665 #define RRSR_MCS1 BIT13
666 #define RRSR_MCS2 BIT14
667 #define RRSR_MCS3 BIT15
668 #define RRSR_MCS4 BIT16
669 #define RRSR_MCS5 BIT17
670 #define RRSR_MCS6 BIT18
671 #define RRSR_MCS7 BIT19
673 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M)
674 #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M)
676 // WOL bit information
677 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
678 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
679 #define HAL92C_WOL_DISASSOC_EVENT BIT2
680 #define HAL92C_WOL_DEAUTH_EVENT BIT3
681 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4
683 //----------------------------------------------------------------------------
685 //----------------------------------------------------------------------------
687 #define RATR_1M 0x00000001
688 #define RATR_2M 0x00000002
689 #define RATR_55M 0x00000004
690 #define RATR_11M 0x00000008
692 #define RATR_6M 0x00000010
693 #define RATR_9M 0x00000020
694 #define RATR_12M 0x00000040
695 #define RATR_18M 0x00000080
696 #define RATR_24M 0x00000100
697 #define RATR_36M 0x00000200
698 #define RATR_48M 0x00000400
699 #define RATR_54M 0x00000800
700 //MCS 1 Spatial Stream
701 #define RATR_MCS0 0x00001000
702 #define RATR_MCS1 0x00002000
703 #define RATR_MCS2 0x00004000
704 #define RATR_MCS3 0x00008000
705 #define RATR_MCS4 0x00010000
706 #define RATR_MCS5 0x00020000
707 #define RATR_MCS6 0x00040000
708 #define RATR_MCS7 0x00080000
709 //MCS 2 Spatial Stream
710 #define RATR_MCS8 0x00100000
711 #define RATR_MCS9 0x00200000
712 #define RATR_MCS10 0x00400000
713 #define RATR_MCS11 0x00800000
714 #define RATR_MCS12 0x01000000
715 #define RATR_MCS13 0x02000000
716 #define RATR_MCS14 0x04000000
717 #define RATR_MCS15 0x08000000
720 #define RATE_1M BIT(0)
721 #define RATE_2M BIT(1)
722 #define RATE_5_5M BIT(2)
723 #define RATE_11M BIT(3)
725 #define RATE_6M BIT(4)
726 #define RATE_9M BIT(5)
727 #define RATE_12M BIT(6)
728 #define RATE_18M BIT(7)
729 #define RATE_24M BIT(8)
730 #define RATE_36M BIT(9)
731 #define RATE_48M BIT(10)
732 #define RATE_54M BIT(11)
733 //MCS 1 Spatial Stream
734 #define RATE_MCS0 BIT(12)
735 #define RATE_MCS1 BIT(13)
736 #define RATE_MCS2 BIT(14)
737 #define RATE_MCS3 BIT(15)
738 #define RATE_MCS4 BIT(16)
739 #define RATE_MCS5 BIT(17)
740 #define RATE_MCS6 BIT(18)
741 #define RATE_MCS7 BIT(19)
742 //MCS 2 Spatial Stream
743 #define RATE_MCS8 BIT(20)
744 #define RATE_MCS9 BIT(21)
745 #define RATE_MCS10 BIT(22)
746 #define RATE_MCS11 BIT(23)
747 #define RATE_MCS12 BIT(24)
748 #define RATE_MCS13 BIT(25)
749 #define RATE_MCS14 BIT(26)
750 #define RATE_MCS15 BIT(27)
754 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
755 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
756 RATR_36M|RATR_48M|RATR_54M
757 #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
758 RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
759 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
760 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
762 #define RATE_BITMAP_ALL 0xFFFFF
764 // Only use CCK 1M rate for ACK
765 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
766 #define RATE_RRSR_WITHOUT_CCK 0xFFFF0
768 //----------------------------------------------------------------------------
769 // BW_OPMODE bits (Offset 0x603, 8bit)
770 //----------------------------------------------------------------------------
771 #define BW_OPMODE_20MHZ BIT2
772 #define BW_OPMODE_5G BIT1
774 //----------------------------------------------------------------------------
775 // CAM Config Setting (offset 0x680, 1 byte)
776 //----------------------------------------------------------------------------
777 #define CAM_VALID BIT15
778 #define CAM_NOTVALID 0x0000
779 #define CAM_USEDK BIT5
781 #define CAM_CONTENT_COUNT 8
784 #define CAM_WEP40 0x01
785 #define CAM_TKIP 0x02
787 #define CAM_WEP104 0x05
790 #define TOTAL_CAM_ENTRY 32
791 #define HALF_CAM_ENTRY 16
793 #define CAM_CONFIG_USEDK _TRUE
794 #define CAM_CONFIG_NO_USEDK _FALSE
796 #define CAM_WRITE BIT16
797 #define CAM_READ 0x00000000
798 #define CAM_POLLINIG BIT31
801 // 10. Power Save Control Registers
803 #define WOW_PMEN BIT0 // Power management Enable.
804 #define WOW_WOMEN BIT1 // WoW function on or off.
805 #define WOW_MAGIC BIT2 // Magic packet
806 #define WOW_UWF BIT3 // Unicast Wakeup frame.
809 // 12. Host Interrupt Status Registers
811 //----------------------------------------------------------------------------
813 //----------------------------------------------------------------------------
814 #define IMR8190_DISABLED 0x0
815 #define IMR_DISABLED 0x0
817 #define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6
818 #define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5
819 #define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4
820 #define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3
821 #define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2
822 #define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1
823 #define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8
824 #define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7
825 #define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6
826 #define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5
827 #define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4
828 #define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3
829 #define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2
830 #define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1
831 #define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
832 #define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
833 #define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
834 #define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
835 #define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
836 #define IMR_RXFOVW BIT12 // Receive FIFO Overflow
837 #define IMR_RDU BIT11 // Receive Descriptor Unavailable
838 #define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt.
839 #define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
840 #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
841 #define IMR_TBDOK BIT7 // Transmit Beacon OK interrup
842 #define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
843 #define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt
844 #define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
845 #define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
846 #define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
847 #define IMR_VODOK BIT1 // AC_VO DMA Interrupt
848 #define IMR_ROK BIT0 // Receive DMA OK Interrupt
850 // 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh)
851 #define IMR_TSF_BIT32_TOGGLE BIT15
852 #define IMR_BcnInt_E BIT12
853 #define IMR_TXERR BIT11
854 #define IMR_RXERR BIT10
855 #define IMR_C2HCMD BIT9
856 #define IMR_CPWM BIT8
858 #define IMR_OCPINT BIT1
859 #define IMR_WLANOFF BIT0
861 //----------------------------------------------------------------------------
862 // 8723E series PCIE Host IMR/ISR bit
863 //----------------------------------------------------------------------------
865 #define PHIMR_TIMEOUT2 BIT31
866 #define PHIMR_TIMEOUT1 BIT30
867 #define PHIMR_PSTIMEOUT BIT29
868 #define PHIMR_GTINT4 BIT28
869 #define PHIMR_GTINT3 BIT27
870 #define PHIMR_TXBCNERR BIT26
871 #define PHIMR_TXBCNOK BIT25
872 #define PHIMR_TSF_BIT32_TOGGLE BIT24
873 #define PHIMR_BCNDMAINT3 BIT23
874 #define PHIMR_BCNDMAINT2 BIT22
875 #define PHIMR_BCNDMAINT1 BIT21
876 #define PHIMR_BCNDMAINT0 BIT20
877 #define PHIMR_BCNDOK3 BIT19
878 #define PHIMR_BCNDOK2 BIT18
879 #define PHIMR_BCNDOK1 BIT17
880 #define PHIMR_BCNDOK0 BIT16
881 #define PHIMR_HSISR_IND_ON BIT15
882 #define PHIMR_BCNDMAINT_E BIT14
883 #define PHIMR_ATIMEND_E BIT13
884 #define PHIMR_ATIM_CTW_END BIT12
885 #define PHIMR_HISRE_IND BIT11 // RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1)
886 #define PHIMR_C2HCMD BIT10
887 #define PHIMR_CPWM2 BIT9
888 #define PHIMR_CPWM BIT8
889 #define PHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt
890 #define PHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
891 #define PHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt
892 #define PHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt
893 #define PHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt
894 #define PHIMR_VODOK BIT2 // AC_VO DMA Interrupt
895 #define PHIMR_RDU BIT1 // Receive Descriptor Unavailable
896 #define PHIMR_ROK BIT0 // Receive DMA OK Interrupt
898 // PCIE Host Interrupt Status Extension bit
899 #define PHIMR_BCNDMAINT7 BIT23
900 #define PHIMR_BCNDMAINT6 BIT22
901 #define PHIMR_BCNDMAINT5 BIT21
902 #define PHIMR_BCNDMAINT4 BIT20
903 #define PHIMR_BCNDOK7 BIT19
904 #define PHIMR_BCNDOK6 BIT18
905 #define PHIMR_BCNDOK5 BIT17
906 #define PHIMR_BCNDOK4 BIT16
908 #define PHIMR_TXERR BIT11
909 #define PHIMR_RXERR BIT10
910 #define PHIMR_TXFOVW BIT9
911 #define PHIMR_RXFOVW BIT8
913 #define PHIMR_OCPINT BIT1
916 #define UHIMR_TIMEOUT2 BIT31
917 #define UHIMR_TIMEOUT1 BIT30
918 #define UHIMR_PSTIMEOUT BIT29
919 #define UHIMR_GTINT4 BIT28
920 #define UHIMR_GTINT3 BIT27
921 #define UHIMR_TXBCNERR BIT26
922 #define UHIMR_TXBCNOK BIT25
923 #define UHIMR_TSF_BIT32_TOGGLE BIT24
924 #define UHIMR_BCNDMAINT3 BIT23
925 #define UHIMR_BCNDMAINT2 BIT22
926 #define UHIMR_BCNDMAINT1 BIT21
927 #define UHIMR_BCNDMAINT0 BIT20
928 #define UHIMR_BCNDOK3 BIT19
929 #define UHIMR_BCNDOK2 BIT18
930 #define UHIMR_BCNDOK1 BIT17
931 #define UHIMR_BCNDOK0 BIT16
932 #define UHIMR_HSISR_IND BIT15
933 #define UHIMR_BCNDMAINT_E BIT14
935 #define UHIMR_CTW_END BIT12
937 #define UHIMR_C2HCMD BIT10
938 #define UHIMR_CPWM2 BIT9
939 #define UHIMR_CPWM BIT8
940 #define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt
941 #define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
942 #define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt
943 #define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt
944 #define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt
945 #define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt
946 #define UHIMR_RDU BIT1 // Receive Descriptor Unavailable
947 #define UHIMR_ROK BIT0 // Receive DMA OK Interrupt
949 // USB Host Interrupt Status Extension bit
950 #define UHIMR_BCNDMAINT7 BIT23
951 #define UHIMR_BCNDMAINT6 BIT22
952 #define UHIMR_BCNDMAINT5 BIT21
953 #define UHIMR_BCNDMAINT4 BIT20
954 #define UHIMR_BCNDOK7 BIT19
955 #define UHIMR_BCNDOK6 BIT18
956 #define UHIMR_BCNDOK5 BIT17
957 #define UHIMR_BCNDOK4 BIT16
959 #define UHIMR_ATIMEND_E BIT13
960 #define UHIMR_ATIMEND BIT12
961 #define UHIMR_TXERR BIT11
962 #define UHIMR_RXERR BIT10
963 #define UHIMR_TXFOVW BIT9
964 #define UHIMR_RXFOVW BIT8
966 #define UHIMR_OCPINT BIT1
970 #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI.
971 #define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA // The value when the NIC is unplugged for PCI in PCI interrupt (page 3).
973 //----------------------------------------------------------------------------
975 //----------------------------------------------------------------------------
976 #define IMR_DISABLED_88E 0x0
977 // IMR DW0(0x0060-0063) Bit 0-31
978 #define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set
979 #define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt
980 #define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1
981 #define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1
982 #define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error
983 #define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK
984 #define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt
985 #define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0
986 #define IMR_BCNDERR0_88E BIT16 // Beacon Queue DMA Error 0
987 #define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
988 #define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7
989 #define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End
990 #define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)
991 #define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear
992 #define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear
993 #define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear
994 #define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK
995 #define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK
996 #define IMR_BKDOK_88E BIT5 // AC_BK DMA OK
997 #define IMR_BEDOK_88E BIT4 // AC_BE DMA OK
998 #define IMR_VIDOK_88E BIT3 // AC_VI DMA OK
999 #define IMR_VODOK_88E BIT2 // AC_VO DMA OK
1000 #define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable
1001 #define IMR_ROK_88E BIT0 // Receive DMA OK
1003 // IMR DW1(0x00B4-00B7) Bit 0-31
1004 #define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7
1005 #define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6
1006 #define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5
1007 #define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4
1008 #define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3
1009 #define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2
1010 #define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1
1011 #define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7
1012 #define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6
1013 #define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5
1014 #define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4
1015 #define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3
1016 #define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2
1017 #define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1
1018 #define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7
1019 #define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
1020 #define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear
1021 #define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow
1022 #define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow
1024 /*===================================================================
1025 =====================================================================
1026 Here the register defines are for 92C. When the define is as same with 92C,
1027 we will use the 92C's define for the consistency
1028 So the following defines for 92C is not entire!!!!!!
1029 =====================================================================
1030 =====================================================================*/
1032 Based on Datasheet V33---090401
1035 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
1036 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
1037 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
1038 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
1039 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
1040 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
1041 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
1042 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
1043 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
1045 //----------------------------------------------------------------------------
1046 // 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits)
1047 //----------------------------------------------------------------------------
1049 // The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong,
1050 // the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3.
1051 // 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim.
1052 // By Bruce, 2011-09-22.
1053 #define StopBecon BIT6
1054 #define StopHigh BIT5
1055 #define StopMgt BIT4
1061 //----------------------------------------------------------------------------
1062 // 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits)
1063 //----------------------------------------------------------------------------
1064 #define RCR_APPFCS BIT31 // WMAC append FCS after pauload
1065 #define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet.
1066 #define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet.
1067 #define RCR_APP_PHYST_RXFF BIT28 // PHY Status is appended before RX packet in RXFF
1068 #define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC.
1069 #define RCR_NONQOS_VHT BIT26 // Reserved
1070 #define RCR_RSVD_BIT25 BIT25 // Reserved
1071 #define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries.
1072 #define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set.
1073 #define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response.
1074 #define RCR_RSVD_BIT21 BIT21 // Reserved
1075 #define RCR_RSVD_BIT20 BIT20 // Reserved
1076 #define RCR_RSVD_BIT19 BIT19 // Reserved
1077 #define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser.
1078 #define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable.
1079 #define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable.
1080 #define RCR_RSVD_BIT15 BIT15 // Reserved
1081 #define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0
1082 #define RCR_AMF BIT13 // Accept management type frame
1083 #define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF.
1084 #define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only).
1085 #define RCR_RSVD_BIT10 BIT10 // Reserved
1086 #define RCR_AICV BIT9 // Accept ICV error packet
1087 #define RCR_ACRC32 BIT8 // Accept CRC32 error packet
1088 #define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp)
1089 #define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data)
1090 #define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet
1091 #define RCR_APWRMGT BIT5 // Accept power management packet
1092 #define RCR_ADD3 BIT4 // Accept address 3 match packet
1093 #define RCR_AB BIT3 // Accept broadcast packet
1094 #define RCR_AM BIT2 // Accept multicast packet
1095 #define RCR_APM BIT1 // Accept physical match packet
1096 #define RCR_AAP BIT0 // Accept all unicast packet
1099 //-----------------------------------------------------
1101 // 0x0000h ~ 0x00FFh System Configuration
1103 //-----------------------------------------------------
1106 #define ISO_MD2PP BIT(0)
1107 #define ISO_UA2USB BIT(1)
1108 #define ISO_UD2CORE BIT(2)
1109 #define ISO_PA2PCIE BIT(3)
1110 #define ISO_PD2CORE BIT(4)
1111 #define ISO_IP2MAC BIT(5)
1112 #define ISO_DIOP BIT(6)
1113 #define ISO_DIOE BIT(7)
1114 #define ISO_EB2CORE BIT(8)
1115 #define ISO_DIOR BIT(9)
1116 #define PWC_EV12V BIT(15)
1120 #define FEN_BBRSTB BIT(0)
1121 #define FEN_BB_GLB_RSTn BIT(1)
1122 #define FEN_USBA BIT(2)
1123 #define FEN_UPLL BIT(3)
1124 #define FEN_USBD BIT(4)
1125 #define FEN_DIO_PCIE BIT(5)
1126 #define FEN_PCIEA BIT(6)
1127 #define FEN_PPLL BIT(7)
1128 #define FEN_PCIED BIT(8)
1129 #define FEN_DIOE BIT(9)
1130 #define FEN_CPUEN BIT(10)
1131 #define FEN_DCORE BIT(11)
1132 #define FEN_ELDR BIT(12)
1133 #define FEN_EN_25_1 BIT(13)
1134 #define FEN_HWPDN BIT(14)
1135 #define FEN_MREGEN BIT(15)
1138 #define PFM_LDALL BIT(0)
1139 #define PFM_ALDN BIT(1)
1140 #define PFM_LDKP BIT(2)
1141 #define PFM_WOWL BIT(3)
1142 #define EnPDN BIT(4)
1143 #define PDN_PL BIT(5)
1144 #define APFM_ONMAC BIT(8)
1145 #define APFM_OFF BIT(9)
1146 #define APFM_RSM BIT(10)
1147 #define AFSM_HSUS BIT(11)
1148 #define AFSM_PCIE BIT(12)
1149 #define APDM_MAC BIT(13)
1150 #define APDM_HOST BIT(14)
1151 #define APDM_HPDN BIT(15)
1152 #define RDY_MACON BIT(16)
1153 #define SUS_HOST BIT(17)
1154 #define ROP_ALD BIT(20)
1155 #define ROP_PWR BIT(21)
1156 #define ROP_SPS BIT(22)
1157 #define SOP_MRST BIT(25)
1158 #define SOP_FUSE BIT(26)
1159 #define SOP_ABG BIT(27)
1160 #define SOP_AMB BIT(28)
1161 #define SOP_RCK BIT(29)
1162 #define SOP_A8M BIT(30)
1163 #define XOP_BTCK BIT(31)
1166 #define ANAD16V_EN BIT(0)
1167 #define ANA8M BIT(1)
1168 #define MACSLP BIT(4)
1169 #define LOADER_CLK_EN BIT(5)
1172 //2 9346CR /REG_SYS_EEPROM_CTRL
1173 #define BOOT_FROM_EEPROM BIT(4)
1174 #define EEPROMSEL BIT(4)
1175 #define EEPROM_EN BIT(5)
1179 #define RF_EN BIT(0)
1180 #define RF_RSTB BIT(1)
1181 #define RF_SDMRSTB BIT(2)
1185 #define LDV12_EN BIT(0)
1186 #define LDV12_SDBY BIT(1)
1187 #define LPLDO_HSM BIT(2)
1188 #define LPLDO_LSM_DIS BIT(3)
1189 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
1193 //2 EFUSE_TEST (For RTL8723 partially)
1194 #define EF_TRPT BIT(7)
1195 #define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2
1196 #define LDOE25_EN BIT(31)
1197 #define EFUSE_SEL(x) (((x) & 0x3) << 8)
1198 #define EFUSE_SEL_MASK 0x300
1199 #define EFUSE_WIFI_SEL_0 0x0
1200 #define EFUSE_BT_SEL_0 0x1
1201 #define EFUSE_BT_SEL_1 0x2
1202 #define EFUSE_BT_SEL_2 0x3
1207 #define MCUFWDL_EN BIT(0)
1208 #define MCUFWDL_RDY BIT(1)
1209 #define FWDL_ChkSum_rpt BIT(2)
1210 #define MACINI_RDY BIT(3)
1211 #define BBINI_RDY BIT(4)
1212 #define RFINI_RDY BIT(5)
1213 #define WINTINI_RDY BIT(6)
1214 #define RAM_DL_SEL BIT(7)
1215 #define CPU_DL_READY BIT(15) /* add flag by gw for fw download ready 20130826 */
1216 #define ROM_DLEN BIT(19)
1217 #define CPRST BIT(23)
1221 #define XCLK_VLD BIT(0)
1222 #define ACLK_VLD BIT(1)
1223 #define UCLK_VLD BIT(2)
1224 #define PCLK_VLD BIT(3)
1225 #define PCIRSTB BIT(4)
1226 #define V15_VLD BIT(5)
1227 #define SW_OFFLOAD_EN BIT(7)
1228 #define SIC_IDLE BIT(8)
1229 #define BD_MAC2 BIT(9)
1230 #define BD_MAC1 BIT(10)
1231 #define IC_MACPHY_MODE BIT(11)
1232 #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15))
1233 #define BT_FUNC BIT(16)
1234 #define VENDOR_ID BIT(19)
1235 #define EXT_VENDOR_ID (BIT(18)|BIT(19)) //Currently only for RTL8723B
1236 #define PAD_HWPD_IDN BIT(22)
1237 #define TRP_VAUX_EN BIT(23) // RTL ID
1238 #define TRP_BT_EN BIT(24)
1239 #define BD_PKG_SEL BIT(25)
1240 #define BD_HCI_SEL BIT(26)
1241 #define TYPE_ID BIT(27)
1242 #define RF_TYPE_ID BIT(27)
1244 #define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL)
1245 #define SPS_SEL BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode
1248 #define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15
1249 #define CHIP_VER_RTL_SHIFT 12
1250 #define EXT_VENDOR_ID_SHIFT 18
1252 //2 REG_GPIO_OUTSTS (For RTL8723 only)
1253 #define EFS_HCI_SEL (BIT(0)|BIT(1))
1254 #define PAD_HCI_SEL (BIT(2)|BIT(3))
1255 #define HCI_SEL (BIT(4)|BIT(5))
1256 #define PKG_SEL_HCI BIT(6)
1257 #define FEN_GPS BIT(7)
1258 #define FEN_BT BIT(8)
1259 #define FEN_WL BIT(9)
1260 #define FEN_PCI BIT(10)
1261 #define FEN_USB BIT(11)
1262 #define BTRF_HWPDN_N BIT(12)
1263 #define WLRF_HWPDN_N BIT(13)
1264 #define PDN_BT_N BIT(14)
1265 #define PDN_GPS_N BIT(15)
1266 #define BT_CTL_HWPDN BIT(16)
1267 #define GPS_CTL_HWPDN BIT(17)
1268 #define PPHY_SUSB BIT(20)
1269 #define UPHY_SUSB BIT(21)
1270 #define PCI_SUSEN BIT(22)
1271 #define USB_SUSEN BIT(23)
1272 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
1275 //-----------------------------------------------------
1277 // 0x0100h ~ 0x01FFh MACTOP General Configuration
1279 //-----------------------------------------------------
1281 //2 Function Enable Registers
1283 #define HCI_TXDMA_EN BIT(0)
1284 #define HCI_RXDMA_EN BIT(1)
1285 #define TXDMA_EN BIT(2)
1286 #define RXDMA_EN BIT(3)
1287 #define PROTOCOL_EN BIT(4)
1288 #define SCHEDULE_EN BIT(5)
1289 #define MACTXEN BIT(6)
1290 #define MACRXEN BIT(7)
1291 #define ENSWBCN BIT(8)
1292 #define ENSEC BIT(9)
1293 #define CALTMR_EN BIT(10) // 32k CAL TMR enable
1296 #define _NETTYPE(x) (((x) & 0x3) << 16)
1297 #define MASK_NETTYPE 0x30000
1298 #define NT_NO_LINK 0x0
1299 #define NT_LINK_AD_HOC 0x1
1300 #define NT_LINK_AP 0x2
1301 #define NT_AS_AP 0x3
1303 //2 PBP - Page Size Register
1304 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
1305 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
1306 #define _PSRX_MASK 0xF
1307 #define _PSTX_MASK 0xF0
1308 #define _PSRX(x) (x)
1309 #define _PSTX(x) ((x) << 4)
1315 #define PBP_1024 0x4
1319 #define RXDMA_ARBBW_EN BIT(0)
1320 #define RXSHFT_EN BIT(1)
1321 #define RXDMA_AGG_EN BIT(2)
1322 #define QS_VO_QUEUE BIT(8)
1323 #define QS_VI_QUEUE BIT(9)
1324 #define QS_BE_QUEUE BIT(10)
1325 #define QS_BK_QUEUE BIT(11)
1326 #define QS_MANAGER_QUEUE BIT(12)
1327 #define QS_HIGH_QUEUE BIT(13)
1329 #define HQSEL_VOQ BIT(0)
1330 #define HQSEL_VIQ BIT(1)
1331 #define HQSEL_BEQ BIT(2)
1332 #define HQSEL_BKQ BIT(3)
1333 #define HQSEL_MGTQ BIT(4)
1334 #define HQSEL_HIQ BIT(5)
1336 // For normal driver, 0x10C
1337 #define _TXDMA_CMQ_MAP(x) (((x)&0x3) << 16)
1338 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
1339 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
1340 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
1341 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
1342 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
1343 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
1345 #define QUEUE_EXTRA 0
1347 #define QUEUE_NORMAL 2
1348 #define QUEUE_HIGH 3
1355 #define _LLT_NO_ACTIVE 0x0
1356 #define _LLT_WRITE_ACCESS 0x1
1357 #define _LLT_READ_ACCESS 0x2
1359 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
1360 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1361 #define _LLT_OP(x) (((x) & 0x3) << 30)
1362 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1365 //-----------------------------------------------------
1367 // 0x0200h ~ 0x027Fh TXDMA Configuration
1369 //-----------------------------------------------------
1371 #define _HPQ(x) ((x) & 0xFF)
1372 #define _LPQ(x) (((x) & 0xFF) << 8)
1373 #define _PUBQ(x) (((x) & 0xFF) << 16)
1374 #define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register
1375 #define _EPQ(x) (((x) & 0xFF) << 16) // NOTE: in RQPN_EPQ register
1378 #define HPQ_PUBLIC_DIS BIT(24)
1379 #define LPQ_PUBLIC_DIS BIT(25)
1380 #define LD_RQPN BIT(31)
1384 #define BLK_DESC_NUM_SHIFT 4
1385 #define BLK_DESC_NUM_MASK 0xF
1388 //2 TXDMA_OFFSET_CHK
1389 #define DROP_DATA_EN BIT(9)
1392 #define BIT_SHIFT_TXPKTNUM 24
1393 #define BIT_MASK_TXPKTNUM 0xff
1394 #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
1396 #define BIT_TDE_DBG_SEL BIT(23)
1397 #define BIT_AUTO_INIT_LLT BIT(16)
1399 #define BIT_SHIFT_Tx_OQT_free_space 8
1400 #define BIT_MASK_Tx_OQT_free_space 0xff
1401 #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
1404 //-----------------------------------------------------
1406 // 0x0280h ~ 0x028Bh RX DMA Configuration
1408 //-----------------------------------------------------
1410 //2 REG_RXDMA_CONTROL, 0x0286h
1411 // Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
1412 // this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
1413 //#define RXPKT_RELEASE_POLL BIT(0)
1414 // Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
1415 // this bit. FW can start releasing packets after RXDMA entering idle mode.
1416 //#define RXDMA_IDLE BIT(1)
1417 // When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
1418 // completed, and stop DMA packet to host. RXDMA will then report Default: 0;
1419 //#define RW_RELEASE_EN BIT(2)
1421 //2 REG_RXPKT_NUM, 0x0284
1422 #define RXPKT_RELEASE_POLL BIT(16)
1423 #define RXDMA_IDLE BIT(17)
1424 #define RW_RELEASE_EN BIT(18)
1426 //-----------------------------------------------------
1428 // 0x0400h ~ 0x047Fh Protocol Configuration
1430 //-----------------------------------------------------
1432 #define EN_AMPDU_RTY_NEW BIT(7)
1436 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1437 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1440 #define RETRY_LIMIT_SHORT_SHIFT 8
1441 #define RETRY_LIMIT_LONG_SHIFT 0
1443 //-----------------------------------------------------
1445 // 0x0500h ~ 0x05FFh EDCA Configuration
1447 //-----------------------------------------------------
1450 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
1451 #define AC_PARAM_ECW_MAX_OFFSET 12
1452 #define AC_PARAM_ECW_MIN_OFFSET 8
1453 #define AC_PARAM_AIFS_OFFSET 0
1456 #define _LRL(x) ((x) & 0x3F)
1457 #define _SRL(x) (((x) & 0x3F) << 8)
1461 #define EN_TXBCN_RPT BIT(2)
1462 #define EN_BCN_FUNCTION BIT(3)
1463 #define STOP_BCNQ BIT(6)
1464 #define DIS_RX_BSSID_FIT BIT(6)
1466 #define DIS_ATIM BIT(0)
1467 #define DIS_BCNQ_SUB BIT(1)
1468 #define DIS_TSF_UDT BIT(4)
1470 // The same function but different bit field.
1471 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1472 #define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1476 #define AcmHw_HwEn BIT(0)
1477 #define AcmHw_BeqEn BIT(1)
1478 #define AcmHw_ViqEn BIT(2)
1479 #define AcmHw_VoqEn BIT(3)
1480 #define AcmHw_BeqStatus BIT(4)
1481 #define AcmHw_ViqStatus BIT(5)
1482 #define AcmHw_VoqStatus BIT(6)
1484 //2 //REG_DUAL_TSF_RST (0x553)
1485 #define DUAL_TSF_RST_P2P BIT(4)
1487 //2 // REG_NOA_DESC_SEL (0x5CF)
1488 #define NOA_DESC_SEL_0 0
1489 #define NOA_DESC_SEL_1 BIT(4)
1491 //-----------------------------------------------------
1493 // 0x0600h ~ 0x07FFh WMAC Configuration
1495 //-----------------------------------------------------
1498 #define APSDOFF BIT(6)
1501 #define TSFRST BIT(0)
1502 #define DIS_GCLK BIT(1)
1503 #define PAD_SEL BIT(2)
1504 #define PWR_ST BIT(6)
1505 #define PWRBIT_OW_EN BIT(7)
1507 #define CFENDFORM BIT(9)
1517 #define APWRMGT BIT(5)
1518 #define CBSSID BIT(6)
1519 #define CBSSID_DATA BIT(6)
1520 #define CBSSID_BCN BIT(7)
1521 #define ACRC32 BIT(8)
1526 #define HTC_LOC_CTRL BIT(14)
1527 #define UC_DATA_EN BIT(16)
1528 #define BM_DATA_EN BIT(17)
1529 #define MFBEN BIT(22)
1530 #define LSIGEN BIT(23)
1531 #define EnMBID BIT(24)
1532 #define FORCEACK BIT(26)
1533 #define APP_BASSN BIT(27)
1534 #define APP_PHYSTS BIT(28)
1535 #define APP_ICV BIT(29)
1536 #define APP_MIC BIT(30)
1537 #define APP_FCS BIT(31)
1541 #define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
1542 #define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
1543 #define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
1544 #define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
1545 #define SCR_SKByA2 BIT(4) //Search kEY BY A2
1546 #define SCR_NoSKMC BIT(5) //No Key Search Multicast
1547 #define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
1548 #define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
1549 #define SCR_CHK_KEYID BIT(8)
1551 //-----------------------------------------------------
1553 // SDIO Bus Specification
1555 //-----------------------------------------------------
1557 // I/O bus domain address mapping
1558 #define SDIO_LOCAL_BASE 0x10250000
1559 #define WLAN_IOREG_BASE 0x10260000
1560 #define FIRMWARE_FIFO_BASE 0x10270000
1561 #define TX_HIQ_BASE 0x10310000
1562 #define TX_MIQ_BASE 0x10320000
1563 #define TX_LOQ_BASE 0x10330000
1564 #define TX_EPQ_BASE 0x10350000
1565 #define RX_RX0FF_BASE 0x10340000
1567 //SDIO host local register space mapping.
1568 #define SDIO_LOCAL_MSK 0x0FFF
1569 #define WLAN_IOREG_MSK 0x7FFF
1570 #define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0]
1571 #define WLAN_RX0FF_MSK 0x0003
1573 #define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID
1574 #define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13]
1575 #define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
1576 #define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
1577 #define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
1578 #define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13]
1579 #define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
1580 #define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
1582 //SDIO Tx Free Page Index
1583 #define HI_QUEUE_IDX 0
1584 #define MID_QUEUE_IDX 1
1585 #define LOW_QUEUE_IDX 2
1586 #define PUBLIC_QUEUE_IDX 3
1588 #define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ
1589 #define SDIO_MAX_RX_QUEUE 1
1591 #define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control
1592 #define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask
1593 #define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine
1594 #define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode
1595 #define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
1596 #define SDIO_REG_OQT_FREE_PG 0x001E // OQT Free Page
1597 #define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
1598 #define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1
1599 #define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
1600 #define SDIO_REG_FREE_TXPG_SEQ 0x0028 // Free Tx Page Sequence
1601 #define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion
1602 #define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
1603 #define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
1604 #define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
1605 #define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control
1606 #define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always
1607 #define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always
1609 #define SDIO_HIMR_DISABLED 0
1611 // RTL8723/RTL8188E SDIO Host Interrupt Mask Register
1612 #define SDIO_HIMR_RX_REQUEST_MSK BIT0
1613 #define SDIO_HIMR_AVAL_MSK BIT1
1614 #define SDIO_HIMR_TXERR_MSK BIT2
1615 #define SDIO_HIMR_RXERR_MSK BIT3
1616 #define SDIO_HIMR_TXFOVW_MSK BIT4
1617 #define SDIO_HIMR_RXFOVW_MSK BIT5
1618 #define SDIO_HIMR_TXBCNOK_MSK BIT6
1619 #define SDIO_HIMR_TXBCNERR_MSK BIT7
1620 #define SDIO_HIMR_BCNERLY_INT_MSK BIT16
1621 #define SDIO_HIMR_C2HCMD_MSK BIT17
1622 #define SDIO_HIMR_CPWM1_MSK BIT18
1623 #define SDIO_HIMR_CPWM2_MSK BIT19
1624 #define SDIO_HIMR_HSISR_IND_MSK BIT20
1625 #define SDIO_HIMR_GTINT3_IND_MSK BIT21
1626 #define SDIO_HIMR_GTINT4_IND_MSK BIT22
1627 #define SDIO_HIMR_PSTIMEOUT_MSK BIT23
1628 #define SDIO_HIMR_OCPINT_MSK BIT24
1629 #define SDIO_HIMR_ATIMEND_MSK BIT25
1630 #define SDIO_HIMR_ATIMEND_E_MSK BIT26
1631 #define SDIO_HIMR_CTWEND_MSK BIT27
1633 //RTL8188E SDIO Specific
1634 #define SDIO_HIMR_MCU_ERR_MSK BIT28
1635 #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29
1637 // SDIO Host Interrupt Service Routine
1638 #define SDIO_HISR_RX_REQUEST BIT0
1639 #define SDIO_HISR_AVAL BIT1
1640 #define SDIO_HISR_TXERR BIT2
1641 #define SDIO_HISR_RXERR BIT3
1642 #define SDIO_HISR_TXFOVW BIT4
1643 #define SDIO_HISR_RXFOVW BIT5
1644 #define SDIO_HISR_TXBCNOK BIT6
1645 #define SDIO_HISR_TXBCNERR BIT7
1646 #define SDIO_HISR_BCNERLY_INT BIT16
1647 #define SDIO_HISR_C2HCMD BIT17
1648 #define SDIO_HISR_CPWM1 BIT18
1649 #define SDIO_HISR_CPWM2 BIT19
1650 #define SDIO_HISR_HSISR_IND BIT20
1651 #define SDIO_HISR_GTINT3_IND BIT21
1652 #define SDIO_HISR_GTINT4_IND BIT22
1653 #define SDIO_HISR_PSTIMEOUT BIT23
1654 #define SDIO_HISR_OCPINT BIT24
1655 #define SDIO_HISR_ATIMEND BIT25
1656 #define SDIO_HISR_ATIMEND_E BIT26
1657 #define SDIO_HISR_CTWEND BIT27
1659 //RTL8188E SDIO Specific
1660 #define SDIO_HISR_MCU_ERR BIT28
1661 #define SDIO_HISR_TSF_BIT32_TOGGLE BIT29
1663 #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\
1667 SDIO_HISR_TXBCNOK |\
1668 SDIO_HISR_TXBCNERR |\
1672 SDIO_HISR_HSISR_IND |\
1673 SDIO_HISR_GTINT3_IND |\
1674 SDIO_HISR_GTINT4_IND |\
1675 SDIO_HISR_PSTIMEOUT |\
1678 // SDIO HCI Suspend Control Register
1679 #define HCI_RESUME_PWR_RDY BIT1
1680 #define HCI_SUS_CTRL BIT0
1682 // SDIO Tx FIFO related
1683 #define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page
1684 #define SDIO_TX_FIFO_PAGE_SZ 128
1686 #ifdef CONFIG_SDIO_HCI
1687 #define MAX_TX_AGG_PACKET_NUMBER 0x8
1689 #define MAX_TX_AGG_PACKET_NUMBER 0xFF
1690 #define MAX_TX_AGG_PACKET_NUMBER_8812 64
1693 //-----------------------------------------------------
1695 // 0xFE00h ~ 0xFE55h USB Configuration
1697 //-----------------------------------------------------
1699 //2 USB Information (0xFE17)
1700 #define USB_IS_HIGH_SPEED 0
1701 #define USB_IS_FULL_SPEED 1
1702 #define USB_SPEED_MASK BIT(5)
1704 #define USB_NORMAL_SIE_EP_MASK 0xF
1705 #define USB_NORMAL_SIE_EP_SHIFT 4
1708 #define USB_AGG_EN BIT(3)
1710 // 0; Use interrupt endpoint to upload interrupt pkt
1711 // 1; Use bulk endpoint to upload interrupt pkt,
1712 #define INT_BULK_SEL BIT(4)
1715 #define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
1716 #define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
1719 //2REG_MULTI_FUNC_CTRL(For RTL8723 Only)
1720 #define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source
1721 #define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control
1722 #define WL_FUNC_EN BIT2 // WiFi function enable
1723 #define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source
1724 #define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source
1725 #define BT_HWPDN_SL BIT17 // BT HW PDn polarity control
1726 #define BT_FUNC_EN BIT18 // BT function enable
1727 #define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source
1728 #define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source
1729 #define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control
1730 #define GPS_FUNC_EN BIT22 // GPS function enable
1732 //3 REG_LIFECTRL_CTRL
1733 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
1734 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
1735 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
1736 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
1738 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
1741 #define PARTNO_92D_NIC (BIT7|BIT6)
1742 #define PARTNO_92D_NIC_REMARK (BIT5|BIT4)
1743 #define PARTNO_SINGLE_BAND_VS BIT3
1744 #define PARTNO_SINGLE_BAND_VS_REMARK BIT1
1745 #define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2)
1746 #define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0)
1748 //========================================================
1749 // General definitions
1750 //========================================================
1752 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) ( IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175 )
1753 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255
1754 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255
1755 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255
1756 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
1758 #define POLLING_LLT_THRESHOLD 20
1759 #if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
1760 #define POLLING_READY_TIMEOUT_COUNT 6000
1762 #define POLLING_READY_TIMEOUT_COUNT 1000
1767 #define HAL_8812A_HW_GPIO_WPS_BIT BIT2
1768 #define HAL_8192C_HW_GPIO_WPS_BIT BIT2
1769 #define HAL_8192EU_HW_GPIO_WPS_BIT BIT7
1770 #define HAL_8188E_HW_GPIO_WPS_BIT BIT7
1772 #endif //__HAL_COMMON_H__
projects / firefly-linux-kernel-4.4.55.git / blob