1 /******************************************************************************
\r
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
\r
5 * This program is free software; you can redistribute it and/or modify it
\r
6 * under the terms of version 2 of the GNU General Public License as
\r
7 * published by the Free Software Foundation.
\r
9 * This program is distributed in the hope that it will be useful, but WITHOUT
\r
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
14 * You should have received a copy of the GNU General Public License along with
\r
15 * this program; if not, write to the Free Software Foundation, Inc.,
\r
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
\r
19 ******************************************************************************/
\r
20 //============================================================
\r
21 // File Name: odm_reg.h
\r
25 // This file is for general register definition.
\r
28 //============================================================
\r
29 #ifndef __HAL_ODM_REG_H__
\r
30 #define __HAL_ODM_REG_H__
\r
33 // Register Definition
\r
37 #define ODM_BB_RESET 0x002
\r
38 #define ODM_DUMMY 0x4fe
\r
39 #define RF_T_METER_OLD 0x24
\r
40 #define RF_T_METER_NEW 0x42
\r
42 #define ODM_EDCA_VO_PARAM 0x500
\r
43 #define ODM_EDCA_VI_PARAM 0x504
\r
44 #define ODM_EDCA_BE_PARAM 0x508
\r
45 #define ODM_EDCA_BK_PARAM 0x50C
\r
46 #define ODM_TXPAUSE 0x522
\r
49 #define ODM_FPGA_PHY0_PAGE8 0x800
\r
50 #define ODM_PSD_SETTING 0x808
\r
51 #define ODM_AFE_SETTING 0x818
\r
52 #define ODM_TXAGC_B_24_54 0x834
\r
53 #define ODM_TXAGC_B_MCS32_5 0x838
\r
54 #define ODM_TXAGC_B_MCS0_MCS3 0x83c
\r
55 #define ODM_TXAGC_B_MCS4_MCS7 0x848
\r
56 #define ODM_TXAGC_B_MCS8_MCS11 0x84c
\r
57 #define ODM_ANALOG_REGISTER 0x85c
\r
58 #define ODM_RF_INTERFACE_OUTPUT 0x860
\r
59 #define ODM_TXAGC_B_MCS12_MCS15 0x868
\r
60 #define ODM_TXAGC_B_11_A_2_11 0x86c
\r
61 #define ODM_AD_DA_LSB_MASK 0x874
\r
62 #define ODM_ENABLE_3_WIRE 0x88c
\r
63 #define ODM_PSD_REPORT 0x8b4
\r
64 #define ODM_R_ANT_SELECT 0x90c
\r
65 #define ODM_CCK_ANT_SELECT 0xa07
\r
66 #define ODM_CCK_PD_THRESH 0xa0a
\r
67 #define ODM_CCK_RF_REG1 0xa11
\r
68 #define ODM_CCK_MATCH_FILTER 0xa20
\r
69 #define ODM_CCK_RAKE_MAC 0xa2e
\r
70 #define ODM_CCK_CNT_RESET 0xa2d
\r
71 #define ODM_CCK_TX_DIVERSITY 0xa2f
\r
72 #define ODM_CCK_FA_CNT_MSB 0xa5b
\r
73 #define ODM_CCK_FA_CNT_LSB 0xa5c
\r
74 #define ODM_CCK_NEW_FUNCTION 0xa75
\r
75 #define ODM_OFDM_PHY0_PAGE_C 0xc00
\r
76 #define ODM_OFDM_RX_ANT 0xc04
\r
77 #define ODM_R_A_RXIQI 0xc14
\r
78 #define ODM_R_A_AGC_CORE1 0xc50
\r
79 #define ODM_R_A_AGC_CORE2 0xc54
\r
80 #define ODM_R_B_AGC_CORE1 0xc58
\r
81 #define ODM_R_AGC_PAR 0xc70
\r
82 #define ODM_R_HTSTF_AGC_PAR 0xc7c
\r
83 #define ODM_TX_PWR_TRAINING_A 0xc90
\r
84 #define ODM_TX_PWR_TRAINING_B 0xc98
\r
85 #define ODM_OFDM_FA_CNT1 0xcf0
\r
86 #define ODM_OFDM_PHY0_PAGE_D 0xd00
\r
87 #define ODM_OFDM_FA_CNT2 0xda0
\r
88 #define ODM_OFDM_FA_CNT3 0xda4
\r
89 #define ODM_OFDM_FA_CNT4 0xda8
\r
90 #define ODM_TXAGC_A_6_18 0xe00
\r
91 #define ODM_TXAGC_A_24_54 0xe04
\r
92 #define ODM_TXAGC_A_1_MCS32 0xe08
\r
93 #define ODM_TXAGC_A_MCS0_MCS3 0xe10
\r
94 #define ODM_TXAGC_A_MCS4_MCS7 0xe14
\r
95 #define ODM_TXAGC_A_MCS8_MCS11 0xe18
\r
96 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c
\r
99 #define ODM_GAIN_SETTING 0x00
\r
100 #define ODM_CHANNEL 0x18
\r
103 #define ODM_DPDT 0x300
\r
106 #define ODM_PSDREG 0x808
\r
109 #define PATHDIV_REG 0xB30
\r
110 #define PATHDIV_TRI 0xBA0
\r
114 // Bitmap Definition
\r
117 #define BIT_FA_RESET BIT0
\r