drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/odm_RegDefine11N.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20  \r
  21 #ifndef __ODM_REGDEFINE11N_H__\r
  22 #define __ODM_REGDEFINE11N_H__\r
  23 \r
  24 \r
  25 //2 RF REG LIST\r
  26 #define ODM_REG_RF_MODE_11N                             0x00\r
  27 #define ODM_REG_RF_0B_11N                               0x0B\r
  28 #define ODM_REG_CHNBW_11N                               0x18\r
  29 #define ODM_REG_T_METER_11N                             0x24\r
  30 #define ODM_REG_RF_25_11N                               0x25\r
  31 #define ODM_REG_RF_26_11N                               0x26\r
  32 #define ODM_REG_RF_27_11N                               0x27\r
  33 #define ODM_REG_RF_2B_11N                               0x2B\r
  34 #define ODM_REG_RF_2C_11N                               0x2C\r
  35 #define ODM_REG_RXRF_A3_11N                             0x3C\r
  36 #define ODM_REG_T_METER_92D_11N                 0x42\r
  37 #define ODM_REG_T_METER_88E_11N                 0x42\r
  38 \r
  39 \r
  40 \r
  41 //2 BB REG LIST\r
  42 //PAGE 8\r
  43 #define ODM_REG_BB_CTRL_11N                             0x800\r
  44 #define ODM_REG_RF_PIN_11N                              0x804\r
  45 #define ODM_REG_PSD_CTRL_11N                            0x808\r
  46 #define ODM_REG_TX_ANT_CTRL_11N                 0x80C\r
  47 #define ODM_REG_BB_PWR_SAV5_11N         0x818\r
  48 #define ODM_REG_CCK_RPT_FORMAT_11N              0x824\r
  49 #define ODM_REG_RX_DEFUALT_A_11N                0x858\r
  50 #define ODM_REG_RX_DEFUALT_B_11N                0x85A\r
  51 #define ODM_REG_BB_PWR_SAV3_11N         0x85C\r
  52 #define ODM_REG_ANTSEL_CTRL_11N                 0x860\r
  53 #define ODM_REG_RX_ANT_CTRL_11N                 0x864\r
  54 #define ODM_REG_PIN_CTRL_11N                            0x870\r
  55 #define ODM_REG_BB_PWR_SAV1_11N         0x874\r
  56 #define ODM_REG_ANTSEL_PATH_11N                 0x878\r
  57 #define ODM_REG_BB_3WIRE_11N                    0x88C\r
  58 #define ODM_REG_SC_CNT_11N                              0x8C4\r
  59 #define ODM_REG_PSD_DATA_11N                            0x8B4\r
  60 #define ODM_REG_PSD_DATA_11N                            0x8B4\r
  61 #define ODM_REG_NHM_TIMER_11N                   0x894\r
  62 #define ODM_REG_NHM_TH9_TH10_11N                0x890\r
  63 #define ODM_REG_NHM_TH3_TO_TH0_11N              0x898\r
  64 #define ODM_REG_NHM_TH7_TO_TH4_11N              0x89c\r
  65 #define ODM_REG_NHM_CNT_11N                             0x8d8\r
  66 //PAGE 9\r
  67 #define ODM_REG_DBG_RPT_11N                             0x908\r
  68 #define ODM_REG_ANT_MAPPING1_11N                0x914\r
  69 #define ODM_REG_ANT_MAPPING2_11N                0x918\r
  70 //PAGE A\r
  71 #define ODM_REG_CCK_ANTDIV_PARA1_11N    0xA00\r
  72 #define ODM_REG_CCK_CCA_11N                             0xA0A\r
  73 #define ODM_REG_CCK_ANTDIV_PARA2_11N    0xA0C\r
  74 #define ODM_REG_CCK_ANTDIV_PARA3_11N    0xA10\r
  75 #define ODM_REG_CCK_ANTDIV_PARA4_11N    0xA14\r
  76 #define ODM_REG_CCK_FILTER_PARA1_11N    0xA22\r
  77 #define ODM_REG_CCK_FILTER_PARA2_11N    0xA23\r
  78 #define ODM_REG_CCK_FILTER_PARA3_11N    0xA24\r
  79 #define ODM_REG_CCK_FILTER_PARA4_11N    0xA25\r
  80 #define ODM_REG_CCK_FILTER_PARA5_11N    0xA26\r
  81 #define ODM_REG_CCK_FILTER_PARA6_11N    0xA27\r
  82 #define ODM_REG_CCK_FILTER_PARA7_11N    0xA28\r
  83 #define ODM_REG_CCK_FILTER_PARA8_11N    0xA29\r
  84 #define ODM_REG_CCK_FA_RST_11N                  0xA2C\r
  85 #define ODM_REG_CCK_FA_MSB_11N                  0xA58\r
  86 #define ODM_REG_CCK_FA_LSB_11N                  0xA5C\r
  87 #define ODM_REG_CCK_CCA_CNT_11N                 0xA60\r
  88 #define ODM_REG_BB_PWR_SAV4_11N         0xA74\r
  89 //PAGE B\r
  90 #define ODM_REG_LNA_SWITCH_11N                  0xB2C\r
  91 #define ODM_REG_PATH_SWITCH_11N                 0xB30\r
  92 #define ODM_REG_RSSI_CTRL_11N                   0xB38\r
  93 #define ODM_REG_CONFIG_ANTA_11N                 0xB68\r
  94 #define ODM_REG_RSSI_BT_11N                             0xB9C\r
  95 //PAGE C\r
  96 #define ODM_REG_OFDM_FA_HOLDC_11N               0xC00\r
  97 #define ODM_REG_BB_RX_PATH_11N                  0xC04\r
  98 #define ODM_REG_TRMUX_11N                               0xC08\r
  99 #define ODM_REG_OFDM_FA_RSTC_11N                0xC0C\r
 100 #define ODM_REG_RXIQI_MATRIX_11N                        0xC14\r
 101 #define ODM_REG_TXIQK_MATRIX_LSB1_11N   0xC4C\r
 102 #define ODM_REG_IGI_A_11N                                       0xC50\r
 103 #define ODM_REG_ANTDIV_PARA2_11N                0xC54\r
 104 #define ODM_REG_IGI_B_11N                                       0xC58\r
 105 #define ODM_REG_ANTDIV_PARA3_11N                0xC5C\r
 106 #define   ODM_REG_L1SBD_PD_CH_11N                       0XC6C\r
 107 #define ODM_REG_BB_PWR_SAV2_11N         0xC70\r
 108 #define ODM_REG_RX_OFF_11N                              0xC7C\r
 109 #define ODM_REG_TXIQK_MATRIXA_11N               0xC80\r
 110 #define ODM_REG_TXIQK_MATRIXB_11N               0xC88\r
 111 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N  0xC94\r
 112 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N  0xC9C\r
 113 #define ODM_REG_RXIQK_MATRIX_LSB_11N    0xCA0\r
 114 #define ODM_REG_ANTDIV_PARA1_11N                0xCA4\r
 115 #define ODM_REG_OFDM_FA_TYPE1_11N               0xCF0\r
 116 //PAGE D\r
 117 #define ODM_REG_OFDM_FA_RSTD_11N                0xD00\r
 118 #define ODM_REG_BB_ATC_11N                              0xD2C\r
 119 #define ODM_REG_OFDM_FA_TYPE2_11N               0xDA0\r
 120 #define ODM_REG_OFDM_FA_TYPE3_11N               0xDA4\r
 121 #define ODM_REG_OFDM_FA_TYPE4_11N               0xDA8\r
 122 #define ODM_REG_RPT_11N                                 0xDF4\r
 123 //PAGE E\r
 124 #define ODM_REG_TXAGC_A_6_18_11N                0xE00\r
 125 #define ODM_REG_TXAGC_A_24_54_11N               0xE04\r
 126 #define ODM_REG_TXAGC_A_1_MCS32_11N     0xE08\r
 127 #define ODM_REG_TXAGC_A_MCS0_3_11N              0xE10\r
 128 #define ODM_REG_TXAGC_A_MCS4_7_11N              0xE14\r
 129 #define ODM_REG_TXAGC_A_MCS8_11_11N     0xE18\r
 130 #define ODM_REG_TXAGC_A_MCS12_15_11N    0xE1C\r
 131 #define ODM_REG_FPGA0_IQK_11N                   0xE28\r
 132 #define ODM_REG_TXIQK_TONE_A_11N                0xE30\r
 133 #define ODM_REG_RXIQK_TONE_A_11N                0xE34\r
 134 #define ODM_REG_TXIQK_PI_A_11N                  0xE38\r
 135 #define ODM_REG_RXIQK_PI_A_11N                  0xE3C\r
 136 #define ODM_REG_TXIQK_11N                               0xE40\r
 137 #define ODM_REG_RXIQK_11N                               0xE44\r
 138 #define ODM_REG_IQK_AGC_PTS_11N                 0xE48\r
 139 #define ODM_REG_IQK_AGC_RSP_11N                 0xE4C\r
 140 #define ODM_REG_BLUETOOTH_11N                   0xE6C\r
 141 #define ODM_REG_RX_WAIT_CCA_11N                 0xE70\r
 142 #define ODM_REG_TX_CCK_RFON_11N                 0xE74\r
 143 #define ODM_REG_TX_CCK_BBON_11N                 0xE78\r
 144 #define ODM_REG_OFDM_RFON_11N                   0xE7C\r
 145 #define ODM_REG_OFDM_BBON_11N                   0xE80\r
 146 #define         ODM_REG_TX2RX_11N                               0xE84\r
 147 #define ODM_REG_TX2TX_11N                               0xE88\r
 148 #define ODM_REG_RX_CCK_11N                              0xE8C\r
 149 #define ODM_REG_RX_OFDM_11N                             0xED0\r
 150 #define ODM_REG_RX_WAIT_RIFS_11N                0xED4\r
 151 #define ODM_REG_RX2RX_11N                               0xED8\r
 152 #define ODM_REG_STANDBY_11N                             0xEDC\r
 153 #define ODM_REG_SLEEP_11N                               0xEE0\r
 154 #define ODM_REG_PMPD_ANAEN_11N                  0xEEC\r
 155 #define ODM_REG_IGI_C_11N                                       0xF84\r
 156 #define ODM_REG_IGI_D_11N                                       0xF88\r
 157 \r
 158 //2 MAC REG LIST\r
 159 #define ODM_REG_BB_RST_11N                              0x02\r
 160 #define ODM_REG_ANTSEL_PIN_11N                  0x4C\r
 161 #define ODM_REG_EARLY_MODE_11N                  0x4D0\r
 162 #define ODM_REG_RSSI_MONITOR_11N                0x4FE\r
 163 #define ODM_REG_EDCA_VO_11N                             0x500\r
 164 #define ODM_REG_EDCA_VI_11N                             0x504\r
 165 #define ODM_REG_EDCA_BE_11N                             0x508\r
 166 #define ODM_REG_EDCA_BK_11N                             0x50C\r
 167 #define ODM_REG_TXPAUSE_11N                             0x522\r
 168 #define ODM_REG_RESP_TX_11N                             0x6D8\r
 169 #define ODM_REG_ANT_TRAIN_PARA1_11N             0x7b0\r
 170 #define ODM_REG_ANT_TRAIN_PARA2_11N             0x7b4\r
 171 \r
 172 \r
 173 //DIG Related\r
 174 #define ODM_BIT_IGI_11N                                 0x0000007F\r
 175 #define ODM_BIT_CCK_RPT_FORMAT_11N              BIT9\r
 176 #define ODM_BIT_BB_RX_PATH_11N                  0xF\r
 177 #define ODM_BIT_BB_ATC_11N                              BIT11\r
 178 \r
 179 #endif\r
 180 \r