1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
57 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
59 /* Module parameters */
61 static int watchdog = TX_TIMEO;
62 module_param(watchdog, int, S_IRUGO | S_IWUSR);
63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
65 static int debug = -1;
66 module_param(debug, int, S_IRUGO | S_IWUSR);
67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
69 static int phyaddr = -1;
70 module_param(phyaddr, int, S_IRUGO);
71 MODULE_PARM_DESC(phyaddr, "Physical device address");
73 #define DMA_TX_SIZE 256
74 static int dma_txsize = DMA_TX_SIZE;
75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
78 #define DMA_RX_SIZE 256
79 static int dma_rxsize = DMA_RX_SIZE;
80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
83 static int flow_ctrl = FLOW_OFF;
84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
87 static int pause = PAUSE_TIME;
88 module_param(pause, int, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
92 static int tc = TC_DEFAULT;
93 module_param(tc, int, S_IRUGO | S_IWUSR);
94 MODULE_PARM_DESC(tc, "DMA threshold control value");
96 #define DEFAULT_BUFSIZE 1536
97 static int buf_sz = DEFAULT_BUFSIZE;
98 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
102 NETIF_MSG_LINK | NETIF_MSG_IFUP |
103 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
105 #define STMMAC_DEFAULT_LPI_TIMER 1000
106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
107 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
111 /* By default the driver will use the ring mode to manage tx and rx descriptors
112 * but passing this value so user can force to use the chain instead of the ring
114 static unsigned int chain_mode;
115 module_param(chain_mode, int, S_IRUGO);
116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
120 #ifdef CONFIG_DEBUG_FS
121 static int stmmac_init_fs(struct net_device *dev);
122 static void stmmac_exit_fs(struct net_device *dev);
125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
128 * stmmac_verify_args - verify the driver parameters.
129 * Description: it checks the driver parameters and set a default in case of
132 static void stmmac_verify_args(void)
134 if (unlikely(watchdog < 0))
136 if (unlikely(dma_rxsize < 0))
137 dma_rxsize = DMA_RX_SIZE;
138 if (unlikely(dma_txsize < 0))
139 dma_txsize = DMA_TX_SIZE;
140 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
141 buf_sz = DEFAULT_BUFSIZE;
142 if (unlikely(flow_ctrl > 1))
143 flow_ctrl = FLOW_AUTO;
144 else if (likely(flow_ctrl < 0))
145 flow_ctrl = FLOW_OFF;
146 if (unlikely((pause < 0) || (pause > 0xffff)))
149 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
153 * stmmac_clk_csr_set - dynamically set the MDC clock
154 * @priv: driver private structure
155 * Description: this is to dynamically set the MDC clock according to the csr
158 * If a specific clk_csr value is passed from the platform
159 * this means that the CSR Clock Range selection cannot be
160 * changed at run-time and it is fixed (as reported in the driver
161 * documentation). Viceversa the driver will try to set the MDC
162 * clock dynamically according to the actual clock input.
164 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
168 clk_rate = clk_get_rate(priv->stmmac_clk);
170 /* Platform provided default clk_csr would be assumed valid
171 * for all other cases except for the below mentioned ones.
172 * For values higher than the IEEE 802.3 specified frequency
173 * we can not estimate the proper divider as it is not known
174 * the frequency of clk_csr_i. So we do not change the default
177 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
178 if (clk_rate < CSR_F_35M)
179 priv->clk_csr = STMMAC_CSR_20_35M;
180 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
181 priv->clk_csr = STMMAC_CSR_35_60M;
182 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
183 priv->clk_csr = STMMAC_CSR_60_100M;
184 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
185 priv->clk_csr = STMMAC_CSR_100_150M;
186 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
187 priv->clk_csr = STMMAC_CSR_150_250M;
188 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
189 priv->clk_csr = STMMAC_CSR_250_300M;
193 static void print_pkt(unsigned char *buf, int len)
195 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
196 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
202 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
204 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
208 * stmmac_hw_fix_mac_speed - callback for speed selection
209 * @priv: driver private structure
210 * Description: on some platforms (e.g. ST), some HW system configuraton
211 * registers have to be set according to the link speed negotiated.
213 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
215 struct phy_device *phydev = priv->phydev;
217 if (likely(priv->plat->fix_mac_speed))
218 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
222 * stmmac_enable_eee_mode - check and enter in LPI mode
223 * @priv: driver private structure
224 * Description: this function is to verify and enter in LPI mode in case of
227 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
229 /* Check and enter in LPI mode */
230 if ((priv->dirty_tx == priv->cur_tx) &&
231 (priv->tx_path_in_lpi_mode == false))
232 priv->hw->mac->set_eee_mode(priv->hw);
236 * stmmac_disable_eee_mode - disable and exit from LPI mode
237 * @priv: driver private structure
238 * Description: this function is to exit and disable EEE in case of
239 * LPI state is true. This is called by the xmit.
241 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
243 priv->hw->mac->reset_eee_mode(priv->hw);
244 del_timer_sync(&priv->eee_ctrl_timer);
245 priv->tx_path_in_lpi_mode = false;
249 * stmmac_eee_ctrl_timer - EEE TX SW timer.
252 * if there is no data transfer and if we are not in LPI state,
253 * then MAC Transmitter can be moved to LPI state.
255 static void stmmac_eee_ctrl_timer(unsigned long arg)
257 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
259 stmmac_enable_eee_mode(priv);
260 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
264 * stmmac_eee_init - init EEE
265 * @priv: driver private structure
267 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
268 * can also manage EEE, this function enable the LPI state and start related
271 bool stmmac_eee_init(struct stmmac_priv *priv)
273 char *phy_bus_name = priv->plat->phy_bus_name;
277 /* Using PCS we cannot dial with the phy registers at this stage
278 * so we do not support extra feature like EEE.
280 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
281 (priv->pcs == STMMAC_PCS_RTBI))
284 /* Never init EEE in case of a switch is attached */
285 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
288 /* MAC core supports the EEE feature. */
289 if (priv->dma_cap.eee) {
290 int tx_lpi_timer = priv->tx_lpi_timer;
292 /* Check if the PHY supports EEE */
293 if (phy_init_eee(priv->phydev, 1)) {
294 /* To manage at run-time if the EEE cannot be supported
295 * anymore (for example because the lp caps have been
297 * In that case the driver disable own timers.
299 spin_lock_irqsave(&priv->lock, flags);
300 if (priv->eee_active) {
301 pr_debug("stmmac: disable EEE\n");
302 del_timer_sync(&priv->eee_ctrl_timer);
303 priv->hw->mac->set_eee_timer(priv->hw, 0,
306 priv->eee_active = 0;
307 spin_unlock_irqrestore(&priv->lock, flags);
310 /* Activate the EEE and start timers */
311 spin_lock_irqsave(&priv->lock, flags);
312 if (!priv->eee_active) {
313 priv->eee_active = 1;
314 setup_timer(&priv->eee_ctrl_timer,
315 stmmac_eee_ctrl_timer,
316 (unsigned long)priv);
317 mod_timer(&priv->eee_ctrl_timer,
318 STMMAC_LPI_T(eee_timer));
320 priv->hw->mac->set_eee_timer(priv->hw,
321 STMMAC_DEFAULT_LIT_LS,
324 /* Set HW EEE according to the speed */
325 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
328 spin_unlock_irqrestore(&priv->lock, flags);
330 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
336 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
337 * @priv: driver private structure
338 * @entry : descriptor index to be used.
339 * @skb : the socket buffer
341 * This function will read timestamp from the descriptor & pass it to stack.
342 * and also perform some sanity checks.
344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
345 unsigned int entry, struct sk_buff *skb)
347 struct skb_shared_hwtstamps shhwtstamp;
351 if (!priv->hwts_tx_en)
354 /* exit if skb doesn't support hw tstamp */
355 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
359 desc = (priv->dma_etx + entry);
361 desc = (priv->dma_tx + entry);
363 /* check tx tstamp status */
364 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
367 /* get the valid tstamp */
368 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
370 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
371 shhwtstamp.hwtstamp = ns_to_ktime(ns);
372 /* pass tstamp to stack */
373 skb_tstamp_tx(skb, &shhwtstamp);
378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
379 * @priv: driver private structure
380 * @entry : descriptor index to be used.
381 * @skb : the socket buffer
383 * This function will read received packet's timestamp from the descriptor
384 * and pass it to stack. It also perform some sanity checks.
386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
387 unsigned int entry, struct sk_buff *skb)
389 struct skb_shared_hwtstamps *shhwtstamp = NULL;
393 if (!priv->hwts_rx_en)
397 desc = (priv->dma_erx + entry);
399 desc = (priv->dma_rx + entry);
401 /* exit if rx tstamp is not valid */
402 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
405 /* get valid tstamp */
406 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
407 shhwtstamp = skb_hwtstamps(skb);
408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
409 shhwtstamp->hwtstamp = ns_to_ktime(ns);
413 * stmmac_hwtstamp_ioctl - control hardware timestamping.
414 * @dev: device pointer.
415 * @ifr: An IOCTL specefic structure, that can contain a pointer to
416 * a proprietary structure used to pass information to the driver.
418 * This function configures the MAC to enable/disable both outgoing(TX)
419 * and incoming(RX) packets time stamping based on user input.
421 * 0 on success and an appropriate -ve integer on failure.
423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
425 struct stmmac_priv *priv = netdev_priv(dev);
426 struct hwtstamp_config config;
427 struct timespec64 now;
431 u32 ptp_over_ipv4_udp = 0;
432 u32 ptp_over_ipv6_udp = 0;
433 u32 ptp_over_ethernet = 0;
434 u32 snap_type_sel = 0;
435 u32 ts_master_en = 0;
439 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
440 netdev_alert(priv->dev, "No support for HW time stamping\n");
441 priv->hwts_tx_en = 0;
442 priv->hwts_rx_en = 0;
447 if (copy_from_user(&config, ifr->ifr_data,
448 sizeof(struct hwtstamp_config)))
451 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
452 __func__, config.flags, config.tx_type, config.rx_filter);
454 /* reserved for future extensions */
458 if (config.tx_type != HWTSTAMP_TX_OFF &&
459 config.tx_type != HWTSTAMP_TX_ON)
463 switch (config.rx_filter) {
464 case HWTSTAMP_FILTER_NONE:
465 /* time stamp no incoming packet at all */
466 config.rx_filter = HWTSTAMP_FILTER_NONE;
469 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
470 /* PTP v1, UDP, any kind of event packet */
471 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
472 /* take time stamp for all event messages */
473 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
475 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
476 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
479 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
480 /* PTP v1, UDP, Sync packet */
481 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
482 /* take time stamp for SYNC messages only */
483 ts_event_en = PTP_TCR_TSEVNTENA;
485 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
486 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
489 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
490 /* PTP v1, UDP, Delay_req packet */
491 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
492 /* take time stamp for Delay_Req messages only */
493 ts_master_en = PTP_TCR_TSMSTRENA;
494 ts_event_en = PTP_TCR_TSEVNTENA;
496 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
497 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
500 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
501 /* PTP v2, UDP, any kind of event packet */
502 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
503 ptp_v2 = PTP_TCR_TSVER2ENA;
504 /* take time stamp for all event messages */
505 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
507 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
508 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
511 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
512 /* PTP v2, UDP, Sync packet */
513 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
514 ptp_v2 = PTP_TCR_TSVER2ENA;
515 /* take time stamp for SYNC messages only */
516 ts_event_en = PTP_TCR_TSEVNTENA;
518 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
519 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
523 /* PTP v2, UDP, Delay_req packet */
524 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
525 ptp_v2 = PTP_TCR_TSVER2ENA;
526 /* take time stamp for Delay_Req messages only */
527 ts_master_en = PTP_TCR_TSMSTRENA;
528 ts_event_en = PTP_TCR_TSEVNTENA;
530 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
531 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
534 case HWTSTAMP_FILTER_PTP_V2_EVENT:
535 /* PTP v2/802.AS1 any layer, any kind of event packet */
536 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
537 ptp_v2 = PTP_TCR_TSVER2ENA;
538 /* take time stamp for all event messages */
539 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
541 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
542 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
543 ptp_over_ethernet = PTP_TCR_TSIPENA;
546 case HWTSTAMP_FILTER_PTP_V2_SYNC:
547 /* PTP v2/802.AS1, any layer, Sync packet */
548 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
549 ptp_v2 = PTP_TCR_TSVER2ENA;
550 /* take time stamp for SYNC messages only */
551 ts_event_en = PTP_TCR_TSEVNTENA;
553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
555 ptp_over_ethernet = PTP_TCR_TSIPENA;
558 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
559 /* PTP v2/802.AS1, any layer, Delay_req packet */
560 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
561 ptp_v2 = PTP_TCR_TSVER2ENA;
562 /* take time stamp for Delay_Req messages only */
563 ts_master_en = PTP_TCR_TSMSTRENA;
564 ts_event_en = PTP_TCR_TSEVNTENA;
566 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
567 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
568 ptp_over_ethernet = PTP_TCR_TSIPENA;
571 case HWTSTAMP_FILTER_ALL:
572 /* time stamp any incoming packet */
573 config.rx_filter = HWTSTAMP_FILTER_ALL;
574 tstamp_all = PTP_TCR_TSENALL;
581 switch (config.rx_filter) {
582 case HWTSTAMP_FILTER_NONE:
583 config.rx_filter = HWTSTAMP_FILTER_NONE;
586 /* PTP v1, UDP, any kind of event packet */
587 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
591 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
592 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
594 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
595 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
597 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
598 tstamp_all | ptp_v2 | ptp_over_ethernet |
599 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
600 ts_master_en | snap_type_sel);
602 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
604 /* program Sub Second Increment reg */
605 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
607 /* calculate default added value:
609 * addend = (2^32)/freq_div_ratio;
610 * where, freq_div_ratio = clk_ptp_ref_i/50MHz
611 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
612 * NOTE: clk_ptp_ref_i should be >= 50MHz to
613 * achieve 20ns accuracy.
615 * 2^x * y == (y << x), hence
616 * 2^32 * 50000000 ==> (50000000 << 32)
618 temp = (u64) (50000000ULL << 32);
619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
620 priv->hw->ptp->config_addend(priv->ioaddr,
621 priv->default_addend);
623 /* initialize system time */
624 ktime_get_real_ts64(&now);
626 /* lower 32 bits of tv_sec are safe until y2106 */
627 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
631 return copy_to_user(ifr->ifr_data, &config,
632 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
636 * stmmac_init_ptp - init PTP
637 * @priv: driver private structure
638 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
639 * This is done by looking at the HW cap. register.
640 * This function also registers the ptp driver.
642 static int stmmac_init_ptp(struct stmmac_priv *priv)
644 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
647 /* Fall-back to main clock in case of no PTP ref is passed */
648 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
649 if (IS_ERR(priv->clk_ptp_ref)) {
650 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
651 priv->clk_ptp_ref = NULL;
653 clk_prepare_enable(priv->clk_ptp_ref);
654 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
658 if (priv->dma_cap.atime_stamp && priv->extend_desc)
661 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
662 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
664 if (netif_msg_hw(priv) && priv->adv_ts)
665 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
667 priv->hw->ptp = &stmmac_ptp;
668 priv->hwts_tx_en = 0;
669 priv->hwts_rx_en = 0;
671 return stmmac_ptp_register(priv);
674 static void stmmac_release_ptp(struct stmmac_priv *priv)
676 if (priv->clk_ptp_ref)
677 clk_disable_unprepare(priv->clk_ptp_ref);
678 stmmac_ptp_unregister(priv);
682 * stmmac_adjust_link - adjusts the link parameters
683 * @dev: net device structure
684 * Description: this is the helper called by the physical abstraction layer
685 * drivers to communicate the phy link status. According the speed and duplex
686 * this driver can invoke registered glue-logic as well.
687 * It also invoke the eee initialization because it could happen when switch
688 * on different networks (that are eee capable).
690 static void stmmac_adjust_link(struct net_device *dev)
692 struct stmmac_priv *priv = netdev_priv(dev);
693 struct phy_device *phydev = priv->phydev;
696 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
701 spin_lock_irqsave(&priv->lock, flags);
704 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
706 /* Now we make sure that we can be in full duplex mode.
707 * If not, we operate in half-duplex mode. */
708 if (phydev->duplex != priv->oldduplex) {
710 if (!(phydev->duplex))
711 ctrl &= ~priv->hw->link.duplex;
713 ctrl |= priv->hw->link.duplex;
714 priv->oldduplex = phydev->duplex;
716 /* Flow Control operation */
718 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
721 if (phydev->speed != priv->speed) {
723 switch (phydev->speed) {
725 if (likely(priv->plat->has_gmac))
726 ctrl &= ~priv->hw->link.port;
727 stmmac_hw_fix_mac_speed(priv);
731 if (priv->plat->has_gmac) {
732 ctrl |= priv->hw->link.port;
733 if (phydev->speed == SPEED_100) {
734 ctrl |= priv->hw->link.speed;
736 ctrl &= ~(priv->hw->link.speed);
739 ctrl &= ~priv->hw->link.port;
741 stmmac_hw_fix_mac_speed(priv);
744 if (netif_msg_link(priv))
745 pr_warn("%s: Speed (%d) not 10/100\n",
746 dev->name, phydev->speed);
750 priv->speed = phydev->speed;
753 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
755 if (!priv->oldlink) {
759 } else if (priv->oldlink) {
763 priv->oldduplex = -1;
766 if (new_state && netif_msg_link(priv))
767 phy_print_status(phydev);
769 spin_unlock_irqrestore(&priv->lock, flags);
771 /* At this stage, it could be needed to setup the EEE or adjust some
772 * MAC related HW registers.
774 priv->eee_enabled = stmmac_eee_init(priv);
778 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
779 * @priv: driver private structure
780 * Description: this is to verify if the HW supports the PCS.
781 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
782 * configured for the TBI, RTBI, or SGMII PHY interface.
784 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
786 int interface = priv->plat->interface;
788 if (priv->dma_cap.pcs) {
789 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
790 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
791 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
792 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
793 pr_debug("STMMAC: PCS RGMII support enable\n");
794 priv->pcs = STMMAC_PCS_RGMII;
795 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
796 pr_debug("STMMAC: PCS SGMII support enable\n");
797 priv->pcs = STMMAC_PCS_SGMII;
803 * stmmac_init_phy - PHY initialization
804 * @dev: net device structure
805 * Description: it initializes the driver's PHY state, and attaches the PHY
810 static int stmmac_init_phy(struct net_device *dev)
812 struct stmmac_priv *priv = netdev_priv(dev);
813 struct phy_device *phydev;
814 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
815 char bus_id[MII_BUS_ID_SIZE];
816 int interface = priv->plat->interface;
817 int max_speed = priv->plat->max_speed;
820 priv->oldduplex = -1;
822 if (priv->plat->phy_node) {
823 phydev = of_phy_connect(dev, priv->plat->phy_node,
824 &stmmac_adjust_link, 0, interface);
826 if (priv->plat->phy_bus_name)
827 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
828 priv->plat->phy_bus_name, priv->plat->bus_id);
830 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
833 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
834 priv->plat->phy_addr);
835 pr_debug("stmmac_init_phy: trying to attach to %s\n",
838 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
842 if (IS_ERR_OR_NULL(phydev)) {
843 pr_err("%s: Could not attach to PHY\n", dev->name);
847 return PTR_ERR(phydev);
850 /* Stop Advertising 1000BASE Capability if interface is not GMII */
851 if ((interface == PHY_INTERFACE_MODE_MII) ||
852 (interface == PHY_INTERFACE_MODE_RMII) ||
853 (max_speed < 1000 && max_speed > 0))
854 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
855 SUPPORTED_1000baseT_Full);
858 * Broken HW is sometimes missing the pull-up resistor on the
859 * MDIO line, which results in reads to non-existent devices returning
860 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
862 * Note: phydev->phy_id is the result of reading the UID PHY registers.
864 if (!priv->plat->phy_node && phydev->phy_id == 0) {
865 phy_disconnect(phydev);
868 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
869 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
871 priv->phydev = phydev;
877 * stmmac_display_ring - display ring
878 * @head: pointer to the head of the ring passed.
879 * @size: size of the ring.
880 * @extend_desc: to verify if extended descriptors are used.
881 * Description: display the control/status and buffer descriptors.
883 static void stmmac_display_ring(void *head, int size, int extend_desc)
886 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
887 struct dma_desc *p = (struct dma_desc *)head;
889 for (i = 0; i < size; i++) {
893 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
894 i, (unsigned int)virt_to_phys(ep),
895 (unsigned int)x, (unsigned int)(x >> 32),
896 ep->basic.des2, ep->basic.des3);
900 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
901 i, (unsigned int)virt_to_phys(p),
902 (unsigned int)x, (unsigned int)(x >> 32),
910 static void stmmac_display_rings(struct stmmac_priv *priv)
912 unsigned int txsize = priv->dma_tx_size;
913 unsigned int rxsize = priv->dma_rx_size;
915 if (priv->extend_desc) {
916 pr_info("Extended RX descriptor ring:\n");
917 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
918 pr_info("Extended TX descriptor ring:\n");
919 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
921 pr_info("RX descriptor ring:\n");
922 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
923 pr_info("TX descriptor ring:\n");
924 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
928 static int stmmac_set_bfsize(int mtu, int bufsize)
932 if (mtu >= BUF_SIZE_4KiB)
934 else if (mtu >= BUF_SIZE_2KiB)
936 else if (mtu > DEFAULT_BUFSIZE)
939 ret = DEFAULT_BUFSIZE;
945 * stmmac_clear_descriptors - clear descriptors
946 * @priv: driver private structure
947 * Description: this function is called to clear the tx and rx descriptors
948 * in case of both basic and extended descriptors are used.
950 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
953 unsigned int txsize = priv->dma_tx_size;
954 unsigned int rxsize = priv->dma_rx_size;
956 /* Clear the Rx/Tx descriptors */
957 for (i = 0; i < rxsize; i++)
958 if (priv->extend_desc)
959 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
960 priv->use_riwt, priv->mode,
963 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
964 priv->use_riwt, priv->mode,
966 for (i = 0; i < txsize; i++)
967 if (priv->extend_desc)
968 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
972 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
978 * stmmac_init_rx_buffers - init the RX descriptor buffer.
979 * @priv: driver private structure
980 * @p: descriptor pointer
981 * @i: descriptor index
983 * Description: this function is called to allocate a receive buffer, perform
984 * the DMA mapping and init the descriptor.
986 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
991 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
993 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
996 priv->rx_skbuff[i] = skb;
997 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1000 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1001 pr_err("%s: DMA mapping error\n", __func__);
1002 dev_kfree_skb_any(skb);
1006 p->des2 = priv->rx_skbuff_dma[i];
1008 if ((priv->hw->mode->init_desc3) &&
1009 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1010 priv->hw->mode->init_desc3(p);
1015 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1017 if (priv->rx_skbuff[i]) {
1018 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1019 priv->dma_buf_sz, DMA_FROM_DEVICE);
1020 dev_kfree_skb_any(priv->rx_skbuff[i]);
1022 priv->rx_skbuff[i] = NULL;
1026 * init_dma_desc_rings - init the RX/TX descriptor rings
1027 * @dev: net device structure
1029 * Description: this function initializes the DMA RX/TX descriptors
1030 * and allocates the socket buffers. It suppors the chained and ring
1033 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1036 struct stmmac_priv *priv = netdev_priv(dev);
1037 unsigned int txsize = priv->dma_tx_size;
1038 unsigned int rxsize = priv->dma_rx_size;
1039 unsigned int bfsize = 0;
1042 if (priv->hw->mode->set_16kib_bfsize)
1043 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1045 if (bfsize < BUF_SIZE_16KiB)
1046 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1048 priv->dma_buf_sz = bfsize;
1050 if (netif_msg_probe(priv))
1051 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1052 txsize, rxsize, bfsize);
1054 if (netif_msg_probe(priv)) {
1055 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1056 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1058 /* RX INITIALIZATION */
1059 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1061 for (i = 0; i < rxsize; i++) {
1063 if (priv->extend_desc)
1064 p = &((priv->dma_erx + i)->basic);
1066 p = priv->dma_rx + i;
1068 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1070 goto err_init_rx_buffers;
1072 if (netif_msg_probe(priv))
1073 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1074 priv->rx_skbuff[i]->data,
1075 (unsigned int)priv->rx_skbuff_dma[i]);
1078 priv->dirty_rx = (unsigned int)(i - rxsize);
1081 /* Setup the chained descriptor addresses */
1082 if (priv->mode == STMMAC_CHAIN_MODE) {
1083 if (priv->extend_desc) {
1084 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1086 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1089 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1091 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1096 /* TX INITIALIZATION */
1097 for (i = 0; i < txsize; i++) {
1099 if (priv->extend_desc)
1100 p = &((priv->dma_etx + i)->basic);
1102 p = priv->dma_tx + i;
1104 priv->tx_skbuff_dma[i].buf = 0;
1105 priv->tx_skbuff_dma[i].map_as_page = false;
1106 priv->tx_skbuff[i] = NULL;
1111 netdev_reset_queue(priv->dev);
1113 stmmac_clear_descriptors(priv);
1115 if (netif_msg_hw(priv))
1116 stmmac_display_rings(priv);
1119 err_init_rx_buffers:
1121 stmmac_free_rx_buffers(priv, i);
1125 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1129 for (i = 0; i < priv->dma_rx_size; i++)
1130 stmmac_free_rx_buffers(priv, i);
1133 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1137 for (i = 0; i < priv->dma_tx_size; i++) {
1140 if (priv->extend_desc)
1141 p = &((priv->dma_etx + i)->basic);
1143 p = priv->dma_tx + i;
1145 if (priv->tx_skbuff_dma[i].buf) {
1146 if (priv->tx_skbuff_dma[i].map_as_page)
1147 dma_unmap_page(priv->device,
1148 priv->tx_skbuff_dma[i].buf,
1149 priv->hw->desc->get_tx_len(p),
1152 dma_unmap_single(priv->device,
1153 priv->tx_skbuff_dma[i].buf,
1154 priv->hw->desc->get_tx_len(p),
1158 if (priv->tx_skbuff[i] != NULL) {
1159 dev_kfree_skb_any(priv->tx_skbuff[i]);
1160 priv->tx_skbuff[i] = NULL;
1161 priv->tx_skbuff_dma[i].buf = 0;
1162 priv->tx_skbuff_dma[i].map_as_page = false;
1168 * alloc_dma_desc_resources - alloc TX/RX resources.
1169 * @priv: private structure
1170 * Description: according to which descriptor can be used (extend or basic)
1171 * this function allocates the resources for TX and RX paths. In case of
1172 * reception, for example, it pre-allocated the RX socket buffer in order to
1173 * allow zero-copy mechanism.
1175 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1177 unsigned int txsize = priv->dma_tx_size;
1178 unsigned int rxsize = priv->dma_rx_size;
1181 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1183 if (!priv->rx_skbuff_dma)
1186 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1188 if (!priv->rx_skbuff)
1191 priv->tx_skbuff_dma = kmalloc_array(txsize,
1192 sizeof(*priv->tx_skbuff_dma),
1194 if (!priv->tx_skbuff_dma)
1195 goto err_tx_skbuff_dma;
1197 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1199 if (!priv->tx_skbuff)
1202 if (priv->extend_desc) {
1203 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1211 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1216 if (!priv->dma_etx) {
1217 dma_free_coherent(priv->device, priv->dma_rx_size *
1218 sizeof(struct dma_extended_desc),
1219 priv->dma_erx, priv->dma_rx_phy);
1223 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1224 sizeof(struct dma_desc),
1230 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1231 sizeof(struct dma_desc),
1234 if (!priv->dma_tx) {
1235 dma_free_coherent(priv->device, priv->dma_rx_size *
1236 sizeof(struct dma_desc),
1237 priv->dma_rx, priv->dma_rx_phy);
1245 kfree(priv->tx_skbuff);
1247 kfree(priv->tx_skbuff_dma);
1249 kfree(priv->rx_skbuff);
1251 kfree(priv->rx_skbuff_dma);
1255 static void free_dma_desc_resources(struct stmmac_priv *priv)
1257 /* Release the DMA TX/RX socket buffers */
1258 dma_free_rx_skbufs(priv);
1259 dma_free_tx_skbufs(priv);
1261 /* Free DMA regions of consistent memory previously allocated */
1262 if (!priv->extend_desc) {
1263 dma_free_coherent(priv->device,
1264 priv->dma_tx_size * sizeof(struct dma_desc),
1265 priv->dma_tx, priv->dma_tx_phy);
1266 dma_free_coherent(priv->device,
1267 priv->dma_rx_size * sizeof(struct dma_desc),
1268 priv->dma_rx, priv->dma_rx_phy);
1270 dma_free_coherent(priv->device, priv->dma_tx_size *
1271 sizeof(struct dma_extended_desc),
1272 priv->dma_etx, priv->dma_tx_phy);
1273 dma_free_coherent(priv->device, priv->dma_rx_size *
1274 sizeof(struct dma_extended_desc),
1275 priv->dma_erx, priv->dma_rx_phy);
1277 kfree(priv->rx_skbuff_dma);
1278 kfree(priv->rx_skbuff);
1279 kfree(priv->tx_skbuff_dma);
1280 kfree(priv->tx_skbuff);
1284 * stmmac_dma_operation_mode - HW DMA operation mode
1285 * @priv: driver private structure
1286 * Description: it is used for configuring the DMA operation mode register in
1287 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1289 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1291 int rxfifosz = priv->plat->rx_fifo_size;
1293 if (priv->plat->force_thresh_dma_mode)
1294 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1295 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1297 * In case of GMAC, SF mode can be enabled
1298 * to perform the TX COE in HW. This depends on:
1299 * 1) TX COE if actually supported
1300 * 2) There is no bugged Jumbo frame support
1301 * that needs to not insert csum in the TDES.
1303 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1305 priv->xstats.threshold = SF_DMA_MODE;
1307 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1312 * stmmac_tx_clean - to manage the transmission completion
1313 * @priv: driver private structure
1314 * Description: it reclaims the transmit resources after transmission completes.
1316 static void stmmac_tx_clean(struct stmmac_priv *priv)
1318 unsigned int txsize = priv->dma_tx_size;
1319 unsigned int bytes_compl = 0, pkts_compl = 0;
1321 spin_lock(&priv->tx_lock);
1323 priv->xstats.tx_clean++;
1325 while (priv->dirty_tx != priv->cur_tx) {
1327 unsigned int entry = priv->dirty_tx % txsize;
1328 struct sk_buff *skb = priv->tx_skbuff[entry];
1331 if (priv->extend_desc)
1332 p = (struct dma_desc *)(priv->dma_etx + entry);
1334 p = priv->dma_tx + entry;
1336 /* Check if the descriptor is owned by the DMA. */
1337 if (priv->hw->desc->get_tx_owner(p))
1340 /* Verify tx error by looking at the last segment. */
1341 last = priv->hw->desc->get_tx_ls(p);
1344 priv->hw->desc->tx_status(&priv->dev->stats,
1347 if (likely(tx_error == 0)) {
1348 priv->dev->stats.tx_packets++;
1349 priv->xstats.tx_pkt_n++;
1351 priv->dev->stats.tx_errors++;
1353 stmmac_get_tx_hwtstamp(priv, entry, skb);
1355 if (netif_msg_tx_done(priv))
1356 pr_debug("%s: curr %d, dirty %d\n", __func__,
1357 priv->cur_tx, priv->dirty_tx);
1359 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1360 if (priv->tx_skbuff_dma[entry].map_as_page)
1361 dma_unmap_page(priv->device,
1362 priv->tx_skbuff_dma[entry].buf,
1363 priv->hw->desc->get_tx_len(p),
1366 dma_unmap_single(priv->device,
1367 priv->tx_skbuff_dma[entry].buf,
1368 priv->hw->desc->get_tx_len(p),
1370 priv->tx_skbuff_dma[entry].buf = 0;
1371 priv->tx_skbuff_dma[entry].map_as_page = false;
1373 priv->hw->mode->clean_desc3(priv, p);
1375 if (likely(skb != NULL)) {
1377 bytes_compl += skb->len;
1378 dev_consume_skb_any(skb);
1379 priv->tx_skbuff[entry] = NULL;
1382 priv->hw->desc->release_tx_desc(p, priv->mode);
1387 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1389 if (unlikely(netif_queue_stopped(priv->dev) &&
1390 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1391 netif_tx_lock(priv->dev);
1392 if (netif_queue_stopped(priv->dev) &&
1393 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1394 if (netif_msg_tx_done(priv))
1395 pr_debug("%s: restart transmit\n", __func__);
1396 netif_wake_queue(priv->dev);
1398 netif_tx_unlock(priv->dev);
1401 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1402 stmmac_enable_eee_mode(priv);
1403 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1405 spin_unlock(&priv->tx_lock);
1408 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1410 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1413 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1415 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1419 * stmmac_tx_err - to manage the tx error
1420 * @priv: driver private structure
1421 * Description: it cleans the descriptors and restarts the transmission
1422 * in case of transmission errors.
1424 static void stmmac_tx_err(struct stmmac_priv *priv)
1427 int txsize = priv->dma_tx_size;
1428 netif_stop_queue(priv->dev);
1430 priv->hw->dma->stop_tx(priv->ioaddr);
1431 dma_free_tx_skbufs(priv);
1432 for (i = 0; i < txsize; i++)
1433 if (priv->extend_desc)
1434 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1438 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1443 netdev_reset_queue(priv->dev);
1444 priv->hw->dma->start_tx(priv->ioaddr);
1446 priv->dev->stats.tx_errors++;
1447 netif_wake_queue(priv->dev);
1451 * stmmac_dma_interrupt - DMA ISR
1452 * @priv: driver private structure
1453 * Description: this is the DMA ISR. It is called by the main ISR.
1454 * It calls the dwmac dma routine and schedule poll method in case of some
1457 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1460 int rxfifosz = priv->plat->rx_fifo_size;
1462 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1463 if (likely((status & handle_rx)) || (status & handle_tx)) {
1464 if (likely(napi_schedule_prep(&priv->napi))) {
1465 stmmac_disable_dma_irq(priv);
1466 __napi_schedule(&priv->napi);
1469 if (unlikely(status & tx_hard_error_bump_tc)) {
1470 /* Try to bump up the dma threshold on this failure */
1471 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1474 if (priv->plat->force_thresh_dma_mode)
1475 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1478 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1479 SF_DMA_MODE, rxfifosz);
1480 priv->xstats.threshold = tc;
1482 } else if (unlikely(status == tx_hard_error))
1483 stmmac_tx_err(priv);
1487 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1488 * @priv: driver private structure
1489 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1491 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1493 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1494 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1496 dwmac_mmc_intr_all_mask(priv->ioaddr);
1498 if (priv->dma_cap.rmon) {
1499 dwmac_mmc_ctrl(priv->ioaddr, mode);
1500 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1502 pr_info(" No MAC Management Counters available\n");
1506 * stmmac_get_synopsys_id - return the SYINID.
1507 * @priv: driver private structure
1508 * Description: this simple function is to decode and return the SYINID
1509 * starting from the HW core register.
1511 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1513 u32 hwid = priv->hw->synopsys_uid;
1515 /* Check Synopsys Id (not available on old chips) */
1517 u32 uid = ((hwid & 0x0000ff00) >> 8);
1518 u32 synid = (hwid & 0x000000ff);
1520 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1529 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1530 * @priv: driver private structure
1531 * Description: select the Enhanced/Alternate or Normal descriptors.
1532 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1533 * supported by the HW capability register.
1535 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1537 if (priv->plat->enh_desc) {
1538 pr_info(" Enhanced/Alternate descriptors\n");
1540 /* GMAC older than 3.50 has no extended descriptors */
1541 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1542 pr_info("\tEnabled extended descriptors\n");
1543 priv->extend_desc = 1;
1545 pr_warn("Extended descriptors not supported\n");
1547 priv->hw->desc = &enh_desc_ops;
1549 pr_info(" Normal descriptors\n");
1550 priv->hw->desc = &ndesc_ops;
1555 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1556 * @priv: driver private structure
1558 * new GMAC chip generations have a new register to indicate the
1559 * presence of the optional feature/functions.
1560 * This can be also used to override the value passed through the
1561 * platform and necessary for old MAC10/100 and GMAC chips.
1563 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1567 if (priv->hw->dma->get_hw_feature) {
1568 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1570 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1571 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1572 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1573 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1574 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1575 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1576 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1577 priv->dma_cap.pmt_remote_wake_up =
1578 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1579 priv->dma_cap.pmt_magic_frame =
1580 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1582 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1583 /* IEEE 1588-2002 */
1584 priv->dma_cap.time_stamp =
1585 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1586 /* IEEE 1588-2008 */
1587 priv->dma_cap.atime_stamp =
1588 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1589 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1590 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1591 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1592 /* TX and RX csum */
1593 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1594 priv->dma_cap.rx_coe_type1 =
1595 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1596 priv->dma_cap.rx_coe_type2 =
1597 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1598 priv->dma_cap.rxfifo_over_2048 =
1599 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1600 /* TX and RX number of channels */
1601 priv->dma_cap.number_rx_channel =
1602 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1603 priv->dma_cap.number_tx_channel =
1604 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1605 /* Alternate (enhanced) DESC mode */
1606 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1613 * stmmac_check_ether_addr - check if the MAC addr is valid
1614 * @priv: driver private structure
1616 * it is to verify if the MAC address is valid, in case of failures it
1617 * generates a random MAC address
1619 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1621 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1622 priv->hw->mac->get_umac_addr(priv->hw,
1623 priv->dev->dev_addr, 0);
1624 if (likely(priv->plat->get_eth_addr))
1625 priv->plat->get_eth_addr(priv->plat->bsp_priv,
1626 priv->dev->dev_addr);
1627 if (!is_valid_ether_addr(priv->dev->dev_addr))
1628 eth_hw_addr_random(priv->dev);
1629 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1630 priv->dev->dev_addr);
1635 * stmmac_init_dma_engine - DMA init.
1636 * @priv: driver private structure
1638 * It inits the DMA invoking the specific MAC/GMAC callback.
1639 * Some DMA parameters can be passed from the platform;
1640 * in case of these are not passed a default is kept for the MAC or GMAC.
1642 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1644 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1645 int mixed_burst = 0;
1648 if (priv->plat->dma_cfg) {
1649 pbl = priv->plat->dma_cfg->pbl;
1650 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1651 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1652 burst_len = priv->plat->dma_cfg->burst_len;
1655 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1658 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1659 burst_len, priv->dma_tx_phy,
1660 priv->dma_rx_phy, atds);
1664 * stmmac_tx_timer - mitigation sw timer for tx.
1665 * @data: data pointer
1667 * This is the timer handler to directly invoke the stmmac_tx_clean.
1669 static void stmmac_tx_timer(unsigned long data)
1671 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1673 stmmac_tx_clean(priv);
1677 * stmmac_init_tx_coalesce - init tx mitigation options.
1678 * @priv: driver private structure
1680 * This inits the transmit coalesce parameters: i.e. timer rate,
1681 * timer handler and default threshold used for enabling the
1682 * interrupt on completion bit.
1684 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1686 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1687 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1688 init_timer(&priv->txtimer);
1689 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1690 priv->txtimer.data = (unsigned long)priv;
1691 priv->txtimer.function = stmmac_tx_timer;
1692 add_timer(&priv->txtimer);
1696 * stmmac_hw_setup - setup mac in a usable state.
1697 * @dev : pointer to the device structure.
1699 * this is the main function to setup the HW in a usable state because the
1700 * dma engine is reset, the core registers are configured (e.g. AXI,
1701 * Checksum features, timers). The DMA is ready to start receiving and
1704 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1707 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1709 struct stmmac_priv *priv = netdev_priv(dev);
1712 /* DMA initialization and SW reset */
1713 ret = stmmac_init_dma_engine(priv);
1715 pr_err("%s: DMA engine initialization failed\n", __func__);
1719 /* Copy the MAC addr into the HW */
1720 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1722 /* If required, perform hw setup of the bus. */
1723 if (priv->plat->bus_setup)
1724 priv->plat->bus_setup(priv->ioaddr);
1726 /* Initialize the MAC Core */
1727 priv->hw->mac->core_init(priv->hw, dev->mtu);
1729 ret = priv->hw->mac->rx_ipc(priv->hw);
1731 pr_warn(" RX IPC Checksum Offload disabled\n");
1732 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1733 priv->hw->rx_csum = 0;
1736 /* Enable the MAC Rx/Tx */
1737 stmmac_set_mac(priv->ioaddr, true);
1739 /* Set the HW DMA mode and the COE */
1740 stmmac_dma_operation_mode(priv);
1742 stmmac_mmc_setup(priv);
1745 ret = stmmac_init_ptp(priv);
1746 if (ret && ret != -EOPNOTSUPP)
1747 pr_warn("%s: failed PTP initialisation\n", __func__);
1750 #ifdef CONFIG_DEBUG_FS
1752 ret = stmmac_init_fs(dev);
1754 pr_warn("%s: failed debugFS registration\n", __func__);
1757 /* Start the ball rolling... */
1758 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1759 priv->hw->dma->start_tx(priv->ioaddr);
1760 priv->hw->dma->start_rx(priv->ioaddr);
1762 /* Dump DMA/MAC registers */
1763 if (netif_msg_hw(priv)) {
1764 priv->hw->mac->dump_regs(priv->hw);
1765 priv->hw->dma->dump_regs(priv->ioaddr);
1767 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1769 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1770 priv->rx_riwt = MAX_DMA_RIWT;
1771 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1774 if (priv->pcs && priv->hw->mac->ctrl_ane)
1775 priv->hw->mac->ctrl_ane(priv->hw, 0);
1781 * stmmac_open - open entry point of the driver
1782 * @dev : pointer to the device structure.
1784 * This function is the open entry point of the driver.
1786 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1789 static int stmmac_open(struct net_device *dev)
1791 struct stmmac_priv *priv = netdev_priv(dev);
1794 stmmac_check_ether_addr(priv);
1796 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1797 priv->pcs != STMMAC_PCS_RTBI) {
1798 ret = stmmac_init_phy(dev);
1800 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1806 /* Extra statistics */
1807 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1808 priv->xstats.threshold = tc;
1810 /* Create and initialize the TX/RX descriptors chains. */
1811 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1812 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1813 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1815 ret = alloc_dma_desc_resources(priv);
1817 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1818 goto dma_desc_error;
1821 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1823 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1827 ret = stmmac_hw_setup(dev, true);
1829 pr_err("%s: Hw setup failed\n", __func__);
1833 stmmac_init_tx_coalesce(priv);
1836 phy_start(priv->phydev);
1838 /* Request the IRQ lines */
1839 ret = request_irq(dev->irq, stmmac_interrupt,
1840 IRQF_SHARED, dev->name, dev);
1841 if (unlikely(ret < 0)) {
1842 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1843 __func__, dev->irq, ret);
1847 /* Request the Wake IRQ in case of another line is used for WoL */
1848 if (priv->wol_irq != dev->irq) {
1849 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1850 IRQF_SHARED, dev->name, dev);
1851 if (unlikely(ret < 0)) {
1852 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1853 __func__, priv->wol_irq, ret);
1858 /* Request the IRQ lines */
1859 if (priv->lpi_irq > 0) {
1860 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1862 if (unlikely(ret < 0)) {
1863 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1864 __func__, priv->lpi_irq, ret);
1869 napi_enable(&priv->napi);
1870 netif_start_queue(dev);
1875 if (priv->wol_irq != dev->irq)
1876 free_irq(priv->wol_irq, dev);
1878 free_irq(dev->irq, dev);
1881 free_dma_desc_resources(priv);
1884 phy_disconnect(priv->phydev);
1890 * stmmac_release - close entry point of the driver
1891 * @dev : device pointer.
1893 * This is the stop entry point of the driver.
1895 static int stmmac_release(struct net_device *dev)
1897 struct stmmac_priv *priv = netdev_priv(dev);
1899 if (priv->eee_enabled)
1900 del_timer_sync(&priv->eee_ctrl_timer);
1902 /* Stop and disconnect the PHY */
1904 phy_stop(priv->phydev);
1905 phy_disconnect(priv->phydev);
1906 priv->phydev = NULL;
1909 netif_stop_queue(dev);
1911 napi_disable(&priv->napi);
1913 del_timer_sync(&priv->txtimer);
1915 /* Free the IRQ lines */
1916 free_irq(dev->irq, dev);
1917 if (priv->wol_irq != dev->irq)
1918 free_irq(priv->wol_irq, dev);
1919 if (priv->lpi_irq > 0)
1920 free_irq(priv->lpi_irq, dev);
1922 /* Stop TX/RX DMA and clear the descriptors */
1923 priv->hw->dma->stop_tx(priv->ioaddr);
1924 priv->hw->dma->stop_rx(priv->ioaddr);
1926 /* Release and free the Rx/Tx resources */
1927 free_dma_desc_resources(priv);
1929 /* Disable the MAC Rx/Tx */
1930 stmmac_set_mac(priv->ioaddr, false);
1932 netif_carrier_off(dev);
1934 #ifdef CONFIG_DEBUG_FS
1935 stmmac_exit_fs(dev);
1938 stmmac_release_ptp(priv);
1944 * stmmac_xmit - Tx entry point of the driver
1945 * @skb : the socket buffer
1946 * @dev : device pointer
1947 * Description : this is the tx entry point of the driver.
1948 * It programs the chain or the ring and supports oversized frames
1951 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1953 struct stmmac_priv *priv = netdev_priv(dev);
1954 unsigned int txsize = priv->dma_tx_size;
1956 int i, csum_insertion = 0, is_jumbo = 0;
1957 int nfrags = skb_shinfo(skb)->nr_frags;
1958 struct dma_desc *desc, *first;
1959 unsigned int nopaged_len = skb_headlen(skb);
1960 unsigned int enh_desc = priv->plat->enh_desc;
1962 spin_lock(&priv->tx_lock);
1964 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1965 spin_unlock(&priv->tx_lock);
1966 if (!netif_queue_stopped(dev)) {
1967 netif_stop_queue(dev);
1968 /* This is a hard error, log it. */
1969 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1971 return NETDEV_TX_BUSY;
1974 if (priv->tx_path_in_lpi_mode)
1975 stmmac_disable_eee_mode(priv);
1977 entry = priv->cur_tx % txsize;
1979 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1981 if (priv->extend_desc)
1982 desc = (struct dma_desc *)(priv->dma_etx + entry);
1984 desc = priv->dma_tx + entry;
1988 /* To program the descriptors according to the size of the frame */
1990 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1992 if (likely(!is_jumbo)) {
1993 desc->des2 = dma_map_single(priv->device, skb->data,
1994 nopaged_len, DMA_TO_DEVICE);
1995 if (dma_mapping_error(priv->device, desc->des2))
1997 priv->tx_skbuff_dma[entry].buf = desc->des2;
1998 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1999 csum_insertion, priv->mode);
2002 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2003 if (unlikely(entry < 0))
2007 for (i = 0; i < nfrags; i++) {
2008 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2009 int len = skb_frag_size(frag);
2011 priv->tx_skbuff[entry] = NULL;
2012 entry = (++priv->cur_tx) % txsize;
2013 if (priv->extend_desc)
2014 desc = (struct dma_desc *)(priv->dma_etx + entry);
2016 desc = priv->dma_tx + entry;
2018 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2020 if (dma_mapping_error(priv->device, desc->des2))
2021 goto dma_map_err; /* should reuse desc w/o issues */
2023 priv->tx_skbuff_dma[entry].buf = desc->des2;
2024 priv->tx_skbuff_dma[entry].map_as_page = true;
2025 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2028 priv->hw->desc->set_tx_owner(desc);
2032 priv->tx_skbuff[entry] = skb;
2034 /* Finalize the latest segment. */
2035 priv->hw->desc->close_tx_desc(desc);
2038 /* According to the coalesce parameter the IC bit for the latest
2039 * segment could be reset and the timer re-started to invoke the
2040 * stmmac_tx function. This approach takes care about the fragments.
2042 priv->tx_count_frames += nfrags + 1;
2043 if (priv->tx_coal_frames > priv->tx_count_frames) {
2044 priv->hw->desc->clear_tx_ic(desc);
2045 priv->xstats.tx_reset_ic_bit++;
2046 mod_timer(&priv->txtimer,
2047 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2049 priv->tx_count_frames = 0;
2051 /* To avoid raise condition */
2052 priv->hw->desc->set_tx_owner(first);
2057 if (netif_msg_pktdata(priv)) {
2058 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2059 __func__, (priv->cur_tx % txsize),
2060 (priv->dirty_tx % txsize), entry, first, nfrags);
2062 if (priv->extend_desc)
2063 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2065 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2067 pr_debug(">>> frame to be transmitted: ");
2068 print_pkt(skb->data, skb->len);
2070 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2071 if (netif_msg_hw(priv))
2072 pr_debug("%s: stop transmitted packets\n", __func__);
2073 netif_stop_queue(dev);
2076 dev->stats.tx_bytes += skb->len;
2078 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2079 priv->hwts_tx_en)) {
2080 /* declare that device is doing timestamping */
2081 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2082 priv->hw->desc->enable_tx_timestamp(first);
2085 if (!priv->hwts_tx_en)
2086 skb_tx_timestamp(skb);
2088 netdev_sent_queue(dev, skb->len);
2089 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2091 spin_unlock(&priv->tx_lock);
2092 return NETDEV_TX_OK;
2095 spin_unlock(&priv->tx_lock);
2096 dev_err(priv->device, "Tx dma map failed\n");
2098 priv->dev->stats.tx_dropped++;
2099 return NETDEV_TX_OK;
2102 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2104 struct ethhdr *ehdr;
2107 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2108 NETIF_F_HW_VLAN_CTAG_RX &&
2109 !__vlan_get_tag(skb, &vlanid)) {
2110 /* pop the vlan tag */
2111 ehdr = (struct ethhdr *)skb->data;
2112 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2113 skb_pull(skb, VLAN_HLEN);
2114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2120 * stmmac_rx_refill - refill used skb preallocated buffers
2121 * @priv: driver private structure
2122 * Description : this is to reallocate the skb for the reception process
2123 * that is based on zero-copy.
2125 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2127 unsigned int rxsize = priv->dma_rx_size;
2128 int bfsize = priv->dma_buf_sz;
2130 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2131 unsigned int entry = priv->dirty_rx % rxsize;
2134 if (priv->extend_desc)
2135 p = (struct dma_desc *)(priv->dma_erx + entry);
2137 p = priv->dma_rx + entry;
2139 if (likely(priv->rx_skbuff[entry] == NULL)) {
2140 struct sk_buff *skb;
2142 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2144 if (unlikely(skb == NULL))
2147 priv->rx_skbuff[entry] = skb;
2148 priv->rx_skbuff_dma[entry] =
2149 dma_map_single(priv->device, skb->data, bfsize,
2151 if (dma_mapping_error(priv->device,
2152 priv->rx_skbuff_dma[entry])) {
2153 dev_err(priv->device, "Rx dma map failed\n");
2157 p->des2 = priv->rx_skbuff_dma[entry];
2159 priv->hw->mode->refill_desc3(priv, p);
2161 if (netif_msg_rx_status(priv))
2162 pr_debug("\trefill entry #%d\n", entry);
2165 priv->hw->desc->set_rx_owner(p);
2171 * stmmac_rx - manage the receive process
2172 * @priv: driver private structure
2173 * @limit: napi bugget.
2174 * Description : this the function called by the napi poll method.
2175 * It gets all the frames inside the ring.
2177 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2179 unsigned int rxsize = priv->dma_rx_size;
2180 unsigned int entry = priv->cur_rx % rxsize;
2181 unsigned int next_entry;
2182 unsigned int count = 0;
2183 int coe = priv->hw->rx_csum;
2185 if (netif_msg_rx_status(priv)) {
2186 pr_debug("%s: descriptor ring:\n", __func__);
2187 if (priv->extend_desc)
2188 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2190 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2192 while (count < limit) {
2196 if (priv->extend_desc)
2197 p = (struct dma_desc *)(priv->dma_erx + entry);
2199 p = priv->dma_rx + entry;
2201 if (priv->hw->desc->get_rx_owner(p))
2206 next_entry = (++priv->cur_rx) % rxsize;
2207 if (priv->extend_desc)
2208 prefetch(priv->dma_erx + next_entry);
2210 prefetch(priv->dma_rx + next_entry);
2212 /* read the status of the incoming frame */
2213 status = priv->hw->desc->rx_status(&priv->dev->stats,
2215 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2216 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2220 if (unlikely(status == discard_frame)) {
2221 priv->dev->stats.rx_errors++;
2222 if (priv->hwts_rx_en && !priv->extend_desc) {
2223 /* DESC2 & DESC3 will be overwitten by device
2224 * with timestamp value, hence reinitialize
2225 * them in stmmac_rx_refill() function so that
2226 * device can reuse it.
2228 priv->rx_skbuff[entry] = NULL;
2229 dma_unmap_single(priv->device,
2230 priv->rx_skbuff_dma[entry],
2235 struct sk_buff *skb;
2238 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2240 /* check if frame_len fits the preallocated memory */
2241 if (frame_len > priv->dma_buf_sz) {
2242 priv->dev->stats.rx_length_errors++;
2246 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2247 * Type frames (LLC/LLC-SNAP)
2249 if (unlikely(status != llc_snap))
2250 frame_len -= ETH_FCS_LEN;
2252 if (netif_msg_rx_status(priv)) {
2253 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2255 if (frame_len > ETH_FRAME_LEN)
2256 pr_debug("\tframe size %d, COE: %d\n",
2259 skb = priv->rx_skbuff[entry];
2260 if (unlikely(!skb)) {
2261 pr_err("%s: Inconsistent Rx descriptor chain\n",
2263 priv->dev->stats.rx_dropped++;
2266 prefetch(skb->data - NET_IP_ALIGN);
2267 priv->rx_skbuff[entry] = NULL;
2269 stmmac_get_rx_hwtstamp(priv, entry, skb);
2271 skb_put(skb, frame_len);
2272 dma_unmap_single(priv->device,
2273 priv->rx_skbuff_dma[entry],
2274 priv->dma_buf_sz, DMA_FROM_DEVICE);
2276 if (netif_msg_pktdata(priv)) {
2277 pr_debug("frame received (%dbytes)", frame_len);
2278 print_pkt(skb->data, frame_len);
2281 stmmac_rx_vlan(priv->dev, skb);
2283 skb->protocol = eth_type_trans(skb, priv->dev);
2286 skb_checksum_none_assert(skb);
2288 skb->ip_summed = CHECKSUM_UNNECESSARY;
2290 napi_gro_receive(&priv->napi, skb);
2292 priv->dev->stats.rx_packets++;
2293 priv->dev->stats.rx_bytes += frame_len;
2298 stmmac_rx_refill(priv);
2300 priv->xstats.rx_pkt_n += count;
2306 * stmmac_poll - stmmac poll method (NAPI)
2307 * @napi : pointer to the napi structure.
2308 * @budget : maximum number of packets that the current CPU can receive from
2311 * To look at the incoming frames and clear the tx resources.
2313 static int stmmac_poll(struct napi_struct *napi, int budget)
2315 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2318 priv->xstats.napi_poll++;
2319 stmmac_tx_clean(priv);
2321 work_done = stmmac_rx(priv, budget);
2322 if (work_done < budget) {
2323 napi_complete(napi);
2324 stmmac_enable_dma_irq(priv);
2331 * @dev : Pointer to net device structure
2332 * Description: this function is called when a packet transmission fails to
2333 * complete within a reasonable time. The driver will mark the error in the
2334 * netdev structure and arrange for the device to be reset to a sane state
2335 * in order to transmit a new packet.
2337 static void stmmac_tx_timeout(struct net_device *dev)
2339 struct stmmac_priv *priv = netdev_priv(dev);
2341 /* Clear Tx resources and restart transmitting again */
2342 stmmac_tx_err(priv);
2346 * stmmac_set_rx_mode - entry point for multicast addressing
2347 * @dev : pointer to the device structure
2349 * This function is a driver entry point which gets called by the kernel
2350 * whenever multicast addresses must be enabled/disabled.
2354 static void stmmac_set_rx_mode(struct net_device *dev)
2356 struct stmmac_priv *priv = netdev_priv(dev);
2358 priv->hw->mac->set_filter(priv->hw, dev);
2362 * stmmac_change_mtu - entry point to change MTU size for the device.
2363 * @dev : device pointer.
2364 * @new_mtu : the new MTU size for the device.
2365 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2366 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2367 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2369 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2372 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2374 struct stmmac_priv *priv = netdev_priv(dev);
2377 if (netif_running(dev)) {
2378 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2382 if (priv->plat->enh_desc)
2383 max_mtu = JUMBO_LEN;
2385 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2387 if (priv->plat->maxmtu < max_mtu)
2388 max_mtu = priv->plat->maxmtu;
2390 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2391 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2396 netdev_update_features(dev);
2401 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2402 netdev_features_t features)
2404 struct stmmac_priv *priv = netdev_priv(dev);
2406 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2407 features &= ~NETIF_F_RXCSUM;
2409 if (!priv->plat->tx_coe)
2410 features &= ~NETIF_F_ALL_CSUM;
2412 /* Some GMAC devices have a bugged Jumbo frame support that
2413 * needs to have the Tx COE disabled for oversized frames
2414 * (due to limited buffer sizes). In this case we disable
2415 * the TX csum insertionin the TDES and not use SF.
2417 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2418 features &= ~NETIF_F_ALL_CSUM;
2423 static int stmmac_set_features(struct net_device *netdev,
2424 netdev_features_t features)
2426 struct stmmac_priv *priv = netdev_priv(netdev);
2428 /* Keep the COE Type in case of csum is supporting */
2429 if (features & NETIF_F_RXCSUM)
2430 priv->hw->rx_csum = priv->plat->rx_coe;
2432 priv->hw->rx_csum = 0;
2433 /* No check needed because rx_coe has been set before and it will be
2434 * fixed in case of issue.
2436 priv->hw->mac->rx_ipc(priv->hw);
2442 * stmmac_interrupt - main ISR
2443 * @irq: interrupt number.
2444 * @dev_id: to pass the net device pointer.
2445 * Description: this is the main driver interrupt service routine.
2447 * o DMA service routine (to manage incoming frame reception and transmission
2449 * o Core interrupts to manage: remote wake-up, management counter, LPI
2452 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2454 struct net_device *dev = (struct net_device *)dev_id;
2455 struct stmmac_priv *priv = netdev_priv(dev);
2458 pm_wakeup_event(priv->device, 0);
2460 if (unlikely(!dev)) {
2461 pr_err("%s: invalid dev pointer\n", __func__);
2465 /* To handle GMAC own interrupts */
2466 if (priv->plat->has_gmac) {
2467 int status = priv->hw->mac->host_irq_status(priv->hw,
2469 if (unlikely(status)) {
2470 /* For LPI we need to save the tx status */
2471 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2472 priv->tx_path_in_lpi_mode = true;
2473 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2474 priv->tx_path_in_lpi_mode = false;
2478 /* To handle DMA interrupts */
2479 stmmac_dma_interrupt(priv);
2484 #ifdef CONFIG_NET_POLL_CONTROLLER
2485 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2486 * to allow network I/O with interrupts disabled.
2488 static void stmmac_poll_controller(struct net_device *dev)
2490 disable_irq(dev->irq);
2491 stmmac_interrupt(dev->irq, dev);
2492 enable_irq(dev->irq);
2497 * stmmac_ioctl - Entry point for the Ioctl
2498 * @dev: Device pointer.
2499 * @rq: An IOCTL specefic structure, that can contain a pointer to
2500 * a proprietary structure used to pass information to the driver.
2501 * @cmd: IOCTL command
2503 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2505 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2507 struct stmmac_priv *priv = netdev_priv(dev);
2508 int ret = -EOPNOTSUPP;
2510 if (!netif_running(dev))
2519 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2522 ret = stmmac_hwtstamp_ioctl(dev, rq);
2531 #ifdef CONFIG_DEBUG_FS
2532 static struct dentry *stmmac_fs_dir;
2534 static void sysfs_display_ring(void *head, int size, int extend_desc,
2535 struct seq_file *seq)
2538 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2539 struct dma_desc *p = (struct dma_desc *)head;
2541 for (i = 0; i < size; i++) {
2545 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2546 i, (unsigned int)virt_to_phys(ep),
2547 (unsigned int)x, (unsigned int)(x >> 32),
2548 ep->basic.des2, ep->basic.des3);
2552 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2553 i, (unsigned int)virt_to_phys(ep),
2554 (unsigned int)x, (unsigned int)(x >> 32),
2558 seq_printf(seq, "\n");
2562 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2564 struct net_device *dev = seq->private;
2565 struct stmmac_priv *priv = netdev_priv(dev);
2566 unsigned int txsize = priv->dma_tx_size;
2567 unsigned int rxsize = priv->dma_rx_size;
2569 if (priv->extend_desc) {
2570 seq_printf(seq, "Extended RX descriptor ring:\n");
2571 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2572 seq_printf(seq, "Extended TX descriptor ring:\n");
2573 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2575 seq_printf(seq, "RX descriptor ring:\n");
2576 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2577 seq_printf(seq, "TX descriptor ring:\n");
2578 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2584 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2586 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2589 static const struct file_operations stmmac_rings_status_fops = {
2590 .owner = THIS_MODULE,
2591 .open = stmmac_sysfs_ring_open,
2593 .llseek = seq_lseek,
2594 .release = single_release,
2597 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2599 struct net_device *dev = seq->private;
2600 struct stmmac_priv *priv = netdev_priv(dev);
2602 if (!priv->hw_cap_support) {
2603 seq_printf(seq, "DMA HW features not supported\n");
2607 seq_printf(seq, "==============================\n");
2608 seq_printf(seq, "\tDMA HW features\n");
2609 seq_printf(seq, "==============================\n");
2611 seq_printf(seq, "\t10/100 Mbps %s\n",
2612 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2613 seq_printf(seq, "\t1000 Mbps %s\n",
2614 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2615 seq_printf(seq, "\tHalf duple %s\n",
2616 (priv->dma_cap.half_duplex) ? "Y" : "N");
2617 seq_printf(seq, "\tHash Filter: %s\n",
2618 (priv->dma_cap.hash_filter) ? "Y" : "N");
2619 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2620 (priv->dma_cap.multi_addr) ? "Y" : "N");
2621 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2622 (priv->dma_cap.pcs) ? "Y" : "N");
2623 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2624 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2625 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2626 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2627 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2628 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2629 seq_printf(seq, "\tRMON module: %s\n",
2630 (priv->dma_cap.rmon) ? "Y" : "N");
2631 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2632 (priv->dma_cap.time_stamp) ? "Y" : "N");
2633 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2634 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2635 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2636 (priv->dma_cap.eee) ? "Y" : "N");
2637 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2638 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2639 (priv->dma_cap.tx_coe) ? "Y" : "N");
2640 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2641 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2642 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2643 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2644 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2645 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2646 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2647 priv->dma_cap.number_rx_channel);
2648 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2649 priv->dma_cap.number_tx_channel);
2650 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2651 (priv->dma_cap.enh_desc) ? "Y" : "N");
2656 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2658 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2661 static const struct file_operations stmmac_dma_cap_fops = {
2662 .owner = THIS_MODULE,
2663 .open = stmmac_sysfs_dma_cap_open,
2665 .llseek = seq_lseek,
2666 .release = single_release,
2669 static int stmmac_init_fs(struct net_device *dev)
2671 struct stmmac_priv *priv = netdev_priv(dev);
2673 /* Create per netdev entries */
2674 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2676 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2677 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2678 STMMAC_RESOURCE_NAME, dev->name);
2683 /* Entry to report DMA RX/TX rings */
2684 priv->dbgfs_rings_status =
2685 debugfs_create_file("descriptors_status", S_IRUGO,
2686 priv->dbgfs_dir, dev,
2687 &stmmac_rings_status_fops);
2689 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2690 pr_info("ERROR creating stmmac ring debugfs file\n");
2691 debugfs_remove_recursive(priv->dbgfs_dir);
2696 /* Entry to report the DMA HW features */
2697 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2699 dev, &stmmac_dma_cap_fops);
2701 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2702 pr_info("ERROR creating stmmac MMC debugfs file\n");
2703 debugfs_remove_recursive(priv->dbgfs_dir);
2711 static void stmmac_exit_fs(struct net_device *dev)
2713 struct stmmac_priv *priv = netdev_priv(dev);
2715 debugfs_remove_recursive(priv->dbgfs_dir);
2717 #endif /* CONFIG_DEBUG_FS */
2719 static const struct net_device_ops stmmac_netdev_ops = {
2720 .ndo_open = stmmac_open,
2721 .ndo_start_xmit = stmmac_xmit,
2722 .ndo_stop = stmmac_release,
2723 .ndo_change_mtu = stmmac_change_mtu,
2724 .ndo_fix_features = stmmac_fix_features,
2725 .ndo_set_features = stmmac_set_features,
2726 .ndo_set_rx_mode = stmmac_set_rx_mode,
2727 .ndo_tx_timeout = stmmac_tx_timeout,
2728 .ndo_do_ioctl = stmmac_ioctl,
2729 #ifdef CONFIG_NET_POLL_CONTROLLER
2730 .ndo_poll_controller = stmmac_poll_controller,
2732 .ndo_set_mac_address = eth_mac_addr,
2736 * stmmac_hw_init - Init the MAC device
2737 * @priv: driver private structure
2738 * Description: this function is to configure the MAC device according to
2739 * some platform parameters or the HW capability register. It prepares the
2740 * driver to use either ring or chain modes and to setup either enhanced or
2741 * normal descriptors.
2743 static int stmmac_hw_init(struct stmmac_priv *priv)
2745 struct mac_device_info *mac;
2747 /* Identify the MAC HW device */
2748 if (priv->plat->has_gmac) {
2749 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2750 mac = dwmac1000_setup(priv->ioaddr,
2751 priv->plat->multicast_filter_bins,
2752 priv->plat->unicast_filter_entries);
2754 mac = dwmac100_setup(priv->ioaddr);
2761 /* Get and dump the chip ID */
2762 priv->synopsys_id = stmmac_get_synopsys_id(priv);
2764 /* To use the chained or ring mode */
2766 priv->hw->mode = &chain_mode_ops;
2767 pr_info(" Chain mode enabled\n");
2768 priv->mode = STMMAC_CHAIN_MODE;
2770 priv->hw->mode = &ring_mode_ops;
2771 pr_info(" Ring mode enabled\n");
2772 priv->mode = STMMAC_RING_MODE;
2775 /* Get the HW capability (new GMAC newer than 3.50a) */
2776 priv->hw_cap_support = stmmac_get_hw_features(priv);
2777 if (priv->hw_cap_support) {
2778 pr_info(" DMA HW capability register supported");
2780 /* We can override some gmac/dma configuration fields: e.g.
2781 * enh_desc, tx_coe (e.g. that are passed through the
2782 * platform) with the values from the HW capability
2783 * register (if supported).
2785 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2786 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2788 /* TXCOE doesn't work in thresh DMA mode */
2789 if (priv->plat->force_thresh_dma_mode)
2790 priv->plat->tx_coe = 0;
2792 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2794 if (priv->dma_cap.rx_coe_type2)
2795 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2796 else if (priv->dma_cap.rx_coe_type1)
2797 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2800 pr_info(" No HW DMA feature register supported");
2802 /* To use alternate (extended) or normal descriptor structures */
2803 stmmac_selec_desc_mode(priv);
2805 if (priv->plat->rx_coe) {
2806 priv->hw->rx_csum = priv->plat->rx_coe;
2807 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2808 priv->plat->rx_coe);
2810 if (priv->plat->tx_coe)
2811 pr_info(" TX Checksum insertion supported\n");
2813 if (priv->plat->pmt) {
2814 pr_info(" Wake-Up On Lan supported\n");
2815 device_set_wakeup_capable(priv->device, 1);
2823 * @device: device pointer
2824 * @plat_dat: platform data pointer
2825 * @res: stmmac resource pointer
2826 * Description: this is the main probe function used to
2827 * call the alloc_etherdev, allocate the priv structure.
2829 * returns 0 on success, otherwise errno.
2831 int stmmac_dvr_probe(struct device *device,
2832 struct plat_stmmacenet_data *plat_dat,
2833 struct stmmac_resources *res)
2836 struct net_device *ndev = NULL;
2837 struct stmmac_priv *priv;
2839 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2843 SET_NETDEV_DEV(ndev, device);
2845 priv = netdev_priv(ndev);
2846 priv->device = device;
2849 stmmac_set_ethtool_ops(ndev);
2850 priv->pause = pause;
2851 priv->plat = plat_dat;
2852 priv->ioaddr = res->addr;
2853 priv->dev->base_addr = (unsigned long)res->addr;
2855 priv->dev->irq = res->irq;
2856 priv->wol_irq = res->wol_irq;
2857 priv->lpi_irq = res->lpi_irq;
2860 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2862 dev_set_drvdata(device, priv->dev);
2864 /* Verify driver arguments */
2865 stmmac_verify_args();
2867 /* Override with kernel parameters if supplied XXX CRS XXX
2868 * this needs to have multiple instances
2870 if ((phyaddr >= 0) && (phyaddr <= 31))
2871 priv->plat->phy_addr = phyaddr;
2873 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2874 if (IS_ERR(priv->stmmac_clk)) {
2875 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2877 /* If failed to obtain stmmac_clk and specific clk_csr value
2878 * is NOT passed from the platform, probe fail.
2880 if (!priv->plat->clk_csr) {
2881 ret = PTR_ERR(priv->stmmac_clk);
2884 priv->stmmac_clk = NULL;
2887 clk_prepare_enable(priv->stmmac_clk);
2889 priv->pclk = devm_clk_get(priv->device, "pclk");
2890 if (IS_ERR(priv->pclk)) {
2891 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2892 ret = -EPROBE_DEFER;
2893 goto error_pclk_get;
2897 clk_prepare_enable(priv->pclk);
2899 priv->stmmac_rst = devm_reset_control_get(priv->device,
2900 STMMAC_RESOURCE_NAME);
2901 if (IS_ERR(priv->stmmac_rst)) {
2902 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2903 ret = -EPROBE_DEFER;
2906 dev_info(priv->device, "no reset control found\n");
2907 priv->stmmac_rst = NULL;
2909 if (priv->stmmac_rst)
2910 reset_control_deassert(priv->stmmac_rst);
2912 /* Init MAC and get the capabilities */
2913 ret = stmmac_hw_init(priv);
2917 ndev->netdev_ops = &stmmac_netdev_ops;
2919 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2921 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2922 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2923 #ifdef STMMAC_VLAN_TAG_USED
2924 /* Both mac100 and gmac support receive VLAN tag detection */
2925 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2927 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2930 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2932 /* Rx Watchdog is available in the COREs newer than the 3.40.
2933 * In some case, for example on bugged HW this feature
2934 * has to be disable and this can be done by passing the
2935 * riwt_off field from the platform.
2937 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2939 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2942 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2944 spin_lock_init(&priv->lock);
2945 spin_lock_init(&priv->tx_lock);
2947 /* If a specific clk_csr value is passed from the platform
2948 * this means that the CSR Clock Range selection cannot be
2949 * changed at run-time and it is fixed. Viceversa the driver'll try to
2950 * set the MDC clock dynamically according to the csr actual
2953 if (!priv->plat->clk_csr)
2954 stmmac_clk_csr_set(priv);
2956 priv->clk_csr = priv->plat->clk_csr;
2958 stmmac_check_pcs_mode(priv);
2960 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2961 priv->pcs != STMMAC_PCS_RTBI) {
2962 /* MDIO bus Registration */
2963 ret = stmmac_mdio_register(ndev);
2965 pr_debug("%s: MDIO bus (id: %d) registration failed",
2966 __func__, priv->plat->bus_id);
2967 goto error_mdio_register;
2971 ret = register_netdev(ndev);
2973 netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
2975 goto error_netdev_register;
2980 error_netdev_register:
2981 if (priv->pcs != STMMAC_PCS_RGMII &&
2982 priv->pcs != STMMAC_PCS_TBI &&
2983 priv->pcs != STMMAC_PCS_RTBI)
2984 stmmac_mdio_unregister(ndev);
2985 error_mdio_register:
2986 netif_napi_del(&priv->napi);
2988 clk_disable_unprepare(priv->pclk);
2990 clk_disable_unprepare(priv->stmmac_clk);
2996 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3000 * @ndev: net device pointer
3001 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3002 * changes the link status, releases the DMA descriptor rings.
3004 int stmmac_dvr_remove(struct net_device *ndev)
3006 struct stmmac_priv *priv = netdev_priv(ndev);
3008 pr_info("%s:\n\tremoving driver", __func__);
3010 priv->hw->dma->stop_rx(priv->ioaddr);
3011 priv->hw->dma->stop_tx(priv->ioaddr);
3013 stmmac_set_mac(priv->ioaddr, false);
3014 netif_carrier_off(ndev);
3015 unregister_netdev(ndev);
3016 if (priv->stmmac_rst)
3017 reset_control_assert(priv->stmmac_rst);
3018 clk_disable_unprepare(priv->pclk);
3019 clk_disable_unprepare(priv->stmmac_clk);
3020 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3021 priv->pcs != STMMAC_PCS_RTBI)
3022 stmmac_mdio_unregister(ndev);
3027 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3030 * stmmac_suspend - suspend callback
3031 * @ndev: net device pointer
3032 * Description: this is the function to suspend the device and it is called
3033 * by the platform driver to stop the network queue, release the resources,
3034 * program the PMT register (for WoL), clean and release driver resources.
3036 int stmmac_suspend(struct net_device *ndev)
3038 struct stmmac_priv *priv = netdev_priv(ndev);
3039 unsigned long flags;
3041 if (!ndev || !netif_running(ndev))
3045 phy_stop(priv->phydev);
3047 netif_device_detach(ndev);
3048 netif_stop_queue(ndev);
3050 napi_disable(&priv->napi);
3052 spin_lock_irqsave(&priv->lock, flags);
3054 /* Stop TX/RX DMA */
3055 priv->hw->dma->stop_tx(priv->ioaddr);
3056 priv->hw->dma->stop_rx(priv->ioaddr);
3058 /* Enable Power down mode by programming the PMT regs */
3059 if (device_may_wakeup(priv->device)) {
3060 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3063 stmmac_set_mac(priv->ioaddr, false);
3064 pinctrl_pm_select_sleep_state(priv->device);
3065 /* Disable clock in case of PWM is off */
3066 clk_disable(priv->pclk);
3067 clk_disable(priv->stmmac_clk);
3069 spin_unlock_irqrestore(&priv->lock, flags);
3073 priv->oldduplex = -1;
3076 EXPORT_SYMBOL_GPL(stmmac_suspend);
3079 * stmmac_resume - resume callback
3080 * @ndev: net device pointer
3081 * Description: when resume this function is invoked to setup the DMA and CORE
3082 * in a usable state.
3084 int stmmac_resume(struct net_device *ndev)
3086 struct stmmac_priv *priv = netdev_priv(ndev);
3087 unsigned long flags;
3089 if (!netif_running(ndev))
3092 /* Power Down bit, into the PM register, is cleared
3093 * automatically as soon as a magic packet or a Wake-up frame
3094 * is received. Anyway, it's better to manually clear
3095 * this bit because it can generate problems while resuming
3096 * from another devices (e.g. serial console).
3098 if (device_may_wakeup(priv->device)) {
3099 spin_lock_irqsave(&priv->lock, flags);
3100 priv->hw->mac->pmt(priv->hw, 0);
3101 spin_unlock_irqrestore(&priv->lock, flags);
3104 pinctrl_pm_select_default_state(priv->device);
3105 /* enable the clk prevously disabled */
3106 clk_enable(priv->stmmac_clk);
3107 clk_enable(priv->pclk);
3108 /* reset the phy so that it's ready */
3110 stmmac_mdio_reset(priv->mii);
3113 netif_device_attach(ndev);
3115 spin_lock_irqsave(&priv->lock, flags);
3121 stmmac_clear_descriptors(priv);
3123 stmmac_hw_setup(ndev, false);
3124 stmmac_init_tx_coalesce(priv);
3125 stmmac_set_rx_mode(ndev);
3127 napi_enable(&priv->napi);
3129 netif_start_queue(ndev);
3131 spin_unlock_irqrestore(&priv->lock, flags);
3134 phy_start(priv->phydev);
3138 EXPORT_SYMBOL_GPL(stmmac_resume);
3141 static int __init stmmac_cmdline_opt(char *str)
3147 while ((opt = strsep(&str, ",")) != NULL) {
3148 if (!strncmp(opt, "debug:", 6)) {
3149 if (kstrtoint(opt + 6, 0, &debug))
3151 } else if (!strncmp(opt, "phyaddr:", 8)) {
3152 if (kstrtoint(opt + 8, 0, &phyaddr))
3154 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3155 if (kstrtoint(opt + 11, 0, &dma_txsize))
3157 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3158 if (kstrtoint(opt + 11, 0, &dma_rxsize))
3160 } else if (!strncmp(opt, "buf_sz:", 7)) {
3161 if (kstrtoint(opt + 7, 0, &buf_sz))
3163 } else if (!strncmp(opt, "tc:", 3)) {
3164 if (kstrtoint(opt + 3, 0, &tc))
3166 } else if (!strncmp(opt, "watchdog:", 9)) {
3167 if (kstrtoint(opt + 9, 0, &watchdog))
3169 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3170 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3172 } else if (!strncmp(opt, "pause:", 6)) {
3173 if (kstrtoint(opt + 6, 0, &pause))
3175 } else if (!strncmp(opt, "eee_timer:", 10)) {
3176 if (kstrtoint(opt + 10, 0, &eee_timer))
3178 } else if (!strncmp(opt, "chain_mode:", 11)) {
3179 if (kstrtoint(opt + 11, 0, &chain_mode))
3186 pr_err("%s: ERROR broken module parameter conversion", __func__);
3190 __setup("stmmaceth=", stmmac_cmdline_opt);
3193 static int __init stmmac_init(void)
3195 #ifdef CONFIG_DEBUG_FS
3196 /* Create debugfs main directory if it doesn't exist yet */
3197 if (!stmmac_fs_dir) {
3198 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3200 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3201 pr_err("ERROR %s, debugfs create directory failed\n",
3202 STMMAC_RESOURCE_NAME);
3212 static void __exit stmmac_exit(void)
3214 #ifdef CONFIG_DEBUG_FS
3215 debugfs_remove_recursive(stmmac_fs_dir);
3219 module_init(stmmac_init)
3220 module_exit(stmmac_exit)
3222 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3223 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3224 MODULE_LICENSE("GPL");