drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/soc/rockchip/rk_vendor_storage.h>
  35 #include "stmmac_platform.h"
  36
  37 struct rk_priv_data;
  38 struct rk_gmac_ops {
  39         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  40                              int tx_delay, int rx_delay);
  41         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  42         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  43         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  44 };
  45
  46 struct rk_priv_data {
  47         struct platform_device *pdev;
  48         int phy_iface;
  49         struct regulator *regulator;
  50         const struct rk_gmac_ops *ops;
  51
  52         bool clk_enabled;
  53         bool clock_input;
  54
  55         struct clk *clk_mac;
  56         struct clk *gmac_clkin;
  57         struct clk *mac_clk_rx;
  58         struct clk *mac_clk_tx;
  59         struct clk *clk_mac_ref;
  60         struct clk *clk_mac_refout;
  61         struct clk *aclk_mac;
  62         struct clk *pclk_mac;
  63
  64         int tx_delay;
  65         int rx_delay;
  66
  67         struct regmap *grf;
  68 };
  69
  70 #define HIWORD_UPDATE(val, mask, shift) \
  71                 ((val) << (shift) | (mask) << ((shift) + 16))
  72
  73 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  74 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  75
  76 #define RK3228_GRF_MAC_CON0     0x0900
  77 #define RK3228_GRF_MAC_CON1     0x0904
  78
  79 /* RK3228_GRF_MAC_CON0 */
  80 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
  81 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
  82
  83 /* RK3228_GRF_MAC_CON1 */
  84 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
  85                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
  86 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
  87                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
  88 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
  89 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
  90 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
  91 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
  92 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
  93 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
  94 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
  95 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
  96 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
  97 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
  98 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
  99 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 100 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 101 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 102 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 103
 104 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 105                                 int tx_delay, int rx_delay)
 106 {
 107         struct device *dev = &bsp_priv->pdev->dev;
 108
 109         if (IS_ERR(bsp_priv->grf)) {
 110                 dev_err(dev, "Missing rockchip,grf property\n");
 111                 return;
 112         }
 113
 114         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 115                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 116                      RK3228_GMAC_RMII_MODE_CLR |
 117                      RK3228_GMAC_RXCLK_DLY_ENABLE |
 118                      RK3228_GMAC_TXCLK_DLY_ENABLE);
 119
 120         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 121                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 122                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 123 }
 124
 125 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 126 {
 127         struct device *dev = &bsp_priv->pdev->dev;
 128
 129         if (IS_ERR(bsp_priv->grf)) {
 130                 dev_err(dev, "Missing rockchip,grf property\n");
 131                 return;
 132         }
 133
 134         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 135                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 136                      RK3228_GMAC_RMII_MODE);
 137
 138         /* set MAC to RMII mode */
 139         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 140 }
 141
 142 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 143 {
 144         struct device *dev = &bsp_priv->pdev->dev;
 145
 146         if (IS_ERR(bsp_priv->grf)) {
 147                 dev_err(dev, "Missing rockchip,grf property\n");
 148                 return;
 149         }
 150
 151         if (speed == 10)
 152                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 153                              RK3228_GMAC_CLK_2_5M);
 154         else if (speed == 100)
 155                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 156                              RK3228_GMAC_CLK_25M);
 157         else if (speed == 1000)
 158                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 159                              RK3228_GMAC_CLK_125M);
 160         else
 161                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 162 }
 163
 164 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 165 {
 166         struct device *dev = &bsp_priv->pdev->dev;
 167
 168         if (IS_ERR(bsp_priv->grf)) {
 169                 dev_err(dev, "Missing rockchip,grf property\n");
 170                 return;
 171         }
 172
 173         if (speed == 10)
 174                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 175                              RK3228_GMAC_RMII_CLK_2_5M |
 176                              RK3228_GMAC_SPEED_10M);
 177         else if (speed == 100)
 178                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 179                              RK3228_GMAC_RMII_CLK_25M |
 180                              RK3228_GMAC_SPEED_100M);
 181         else
 182                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 183 }
 184
 185 static const struct rk_gmac_ops rk3228_ops = {
 186         .set_to_rgmii = rk3228_set_to_rgmii,
 187         .set_to_rmii = rk3228_set_to_rmii,
 188         .set_rgmii_speed = rk3228_set_rgmii_speed,
 189         .set_rmii_speed = rk3228_set_rmii_speed,
 190 };
 191
 192 #define RK3288_GRF_SOC_CON1     0x0248
 193 #define RK3288_GRF_SOC_CON3     0x0250
 194
 195 /*RK3288_GRF_SOC_CON1*/
 196 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 197                                          GRF_CLR_BIT(8))
 198 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 199                                          GRF_BIT(8))
 200 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 201 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 202 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 203 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 204 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 205 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 206 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 207 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 208 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 209 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 210 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 211
 212 /*RK3288_GRF_SOC_CON3*/
 213 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 214 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 215 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 216 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 217 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 218 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 219
 220 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 221                                 int tx_delay, int rx_delay)
 222 {
 223         struct device *dev = &bsp_priv->pdev->dev;
 224
 225         if (IS_ERR(bsp_priv->grf)) {
 226                 dev_err(dev, "Missing rockchip,grf property\n");
 227                 return;
 228         }
 229
 230         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 231                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 232                      RK3288_GMAC_RMII_MODE_CLR);
 233         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 234                      RK3288_GMAC_RXCLK_DLY_ENABLE |
 235                      RK3288_GMAC_TXCLK_DLY_ENABLE |
 236                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 237                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 238 }
 239
 240 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 241 {
 242         struct device *dev = &bsp_priv->pdev->dev;
 243
 244         if (IS_ERR(bsp_priv->grf)) {
 245                 dev_err(dev, "Missing rockchip,grf property\n");
 246                 return;
 247         }
 248
 249         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 250                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 251 }
 252
 253 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 254 {
 255         struct device *dev = &bsp_priv->pdev->dev;
 256
 257         if (IS_ERR(bsp_priv->grf)) {
 258                 dev_err(dev, "Missing rockchip,grf property\n");
 259                 return;
 260         }
 261
 262         if (speed == 10)
 263                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 264                              RK3288_GMAC_CLK_2_5M);
 265         else if (speed == 100)
 266                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 267                              RK3288_GMAC_CLK_25M);
 268         else if (speed == 1000)
 269                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 270                              RK3288_GMAC_CLK_125M);
 271         else
 272                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 273 }
 274
 275 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 276 {
 277         struct device *dev = &bsp_priv->pdev->dev;
 278
 279         if (IS_ERR(bsp_priv->grf)) {
 280                 dev_err(dev, "Missing rockchip,grf property\n");
 281                 return;
 282         }
 283
 284         if (speed == 10) {
 285                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 286                              RK3288_GMAC_RMII_CLK_2_5M |
 287                              RK3288_GMAC_SPEED_10M);
 288         } else if (speed == 100) {
 289                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 290                              RK3288_GMAC_RMII_CLK_25M |
 291                              RK3288_GMAC_SPEED_100M);
 292         } else {
 293                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 294         }
 295 }
 296
 297 static const struct rk_gmac_ops rk3288_ops = {
 298         .set_to_rgmii = rk3288_set_to_rgmii,
 299         .set_to_rmii = rk3288_set_to_rmii,
 300         .set_rgmii_speed = rk3288_set_rgmii_speed,
 301         .set_rmii_speed = rk3288_set_rmii_speed,
 302 };
 303
 304 #define RK3328_GRF_MAC_CON0     0x0900
 305 #define RK3328_GRF_MAC_CON1     0x0904
 306
 307 /* RK3328_GRF_MAC_CON0 */
 308 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 309 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 310
 311 /* RK3328_GRF_MAC_CON1 */
 312 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 313                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 314 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 315                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 316 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 317 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 318 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 319 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 320 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 321 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 322 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 323 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 324 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 325 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 326 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 327 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 328 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 329 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 330 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 331
 332 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 333                                 int tx_delay, int rx_delay)
 334 {
 335         struct device *dev = &bsp_priv->pdev->dev;
 336
 337         if (IS_ERR(bsp_priv->grf)) {
 338                 dev_err(dev, "Missing rockchip,grf property\n");
 339                 return;
 340         }
 341
 342         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 343                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 344                      RK3328_GMAC_RMII_MODE_CLR |
 345                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 346                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 347
 348         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 349                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 350                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 351 }
 352
 353 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 354 {
 355         struct device *dev = &bsp_priv->pdev->dev;
 356
 357         if (IS_ERR(bsp_priv->grf)) {
 358                 dev_err(dev, "Missing rockchip,grf property\n");
 359                 return;
 360         }
 361
 362         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 363                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 364                      RK3328_GMAC_RMII_MODE);
 365
 366         /* set MAC to RMII mode */
 367         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
 368 }
 369
 370 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 371 {
 372         struct device *dev = &bsp_priv->pdev->dev;
 373
 374         if (IS_ERR(bsp_priv->grf)) {
 375                 dev_err(dev, "Missing rockchip,grf property\n");
 376                 return;
 377         }
 378
 379         if (speed == 10)
 380                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 381                              RK3328_GMAC_CLK_2_5M);
 382         else if (speed == 100)
 383                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 384                              RK3328_GMAC_CLK_25M);
 385         else if (speed == 1000)
 386                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 387                              RK3328_GMAC_CLK_125M);
 388         else
 389                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 390 }
 391
 392 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 393 {
 394         struct device *dev = &bsp_priv->pdev->dev;
 395
 396         if (IS_ERR(bsp_priv->grf)) {
 397                 dev_err(dev, "Missing rockchip,grf property\n");
 398                 return;
 399         }
 400
 401         if (speed == 10)
 402                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 403                              RK3328_GMAC_RMII_CLK_2_5M |
 404                              RK3328_GMAC_SPEED_10M);
 405         else if (speed == 100)
 406                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 407                              RK3328_GMAC_RMII_CLK_25M |
 408                              RK3328_GMAC_SPEED_100M);
 409         else
 410                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 411 }
 412
 413 static const struct rk_gmac_ops rk3328_ops = {
 414         .set_to_rgmii = rk3328_set_to_rgmii,
 415         .set_to_rmii = rk3328_set_to_rmii,
 416         .set_rgmii_speed = rk3328_set_rgmii_speed,
 417         .set_rmii_speed = rk3328_set_rmii_speed,
 418 };
 419
 420 #define RK3366_GRF_SOC_CON6     0x0418
 421 #define RK3366_GRF_SOC_CON7     0x041c
 422
 423 /* RK3366_GRF_SOC_CON6 */
 424 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 425                                          GRF_CLR_BIT(11))
 426 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 427                                          GRF_BIT(11))
 428 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 429 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 430 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 431 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 432 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 433 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 434 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 435 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 436 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 437 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 438 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 439
 440 /* RK3366_GRF_SOC_CON7 */
 441 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 442 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 443 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 444 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 445 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 446 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 447
 448 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 449                                 int tx_delay, int rx_delay)
 450 {
 451         struct device *dev = &bsp_priv->pdev->dev;
 452
 453         if (IS_ERR(bsp_priv->grf)) {
 454                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 455                 return;
 456         }
 457
 458         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 459                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 460                      RK3366_GMAC_RMII_MODE_CLR);
 461         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 462                      RK3366_GMAC_RXCLK_DLY_ENABLE |
 463                      RK3366_GMAC_TXCLK_DLY_ENABLE |
 464                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 465                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 466 }
 467
 468 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 469 {
 470         struct device *dev = &bsp_priv->pdev->dev;
 471
 472         if (IS_ERR(bsp_priv->grf)) {
 473                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 474                 return;
 475         }
 476
 477         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 478                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 479 }
 480
 481 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 482 {
 483         struct device *dev = &bsp_priv->pdev->dev;
 484
 485         if (IS_ERR(bsp_priv->grf)) {
 486                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 487                 return;
 488         }
 489
 490         if (speed == 10)
 491                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 492                              RK3366_GMAC_CLK_2_5M);
 493         else if (speed == 100)
 494                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 495                              RK3366_GMAC_CLK_25M);
 496         else if (speed == 1000)
 497                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 498                              RK3366_GMAC_CLK_125M);
 499         else
 500                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 501 }
 502
 503 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 504 {
 505         struct device *dev = &bsp_priv->pdev->dev;
 506
 507         if (IS_ERR(bsp_priv->grf)) {
 508                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 509                 return;
 510         }
 511
 512         if (speed == 10) {
 513                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 514                              RK3366_GMAC_RMII_CLK_2_5M |
 515                              RK3366_GMAC_SPEED_10M);
 516         } else if (speed == 100) {
 517                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 518                              RK3366_GMAC_RMII_CLK_25M |
 519                              RK3366_GMAC_SPEED_100M);
 520         } else {
 521                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 522         }
 523 }
 524
 525 static const struct rk_gmac_ops rk3366_ops = {
 526         .set_to_rgmii = rk3366_set_to_rgmii,
 527         .set_to_rmii = rk3366_set_to_rmii,
 528         .set_rgmii_speed = rk3366_set_rgmii_speed,
 529         .set_rmii_speed = rk3366_set_rmii_speed,
 530 };
 531
 532 #define RK3368_GRF_SOC_CON15    0x043c
 533 #define RK3368_GRF_SOC_CON16    0x0440
 534
 535 /* RK3368_GRF_SOC_CON15 */
 536 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 537                                          GRF_CLR_BIT(11))
 538 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 539                                          GRF_BIT(11))
 540 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 541 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 542 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 543 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 544 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 545 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 546 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 547 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 548 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 549 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 550 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 551
 552 /* RK3368_GRF_SOC_CON16 */
 553 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 554 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 555 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 556 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 557 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 558 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 559
 560 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 561                                 int tx_delay, int rx_delay)
 562 {
 563         struct device *dev = &bsp_priv->pdev->dev;
 564
 565         if (IS_ERR(bsp_priv->grf)) {
 566                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 567                 return;
 568         }
 569
 570         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 571                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 572                      RK3368_GMAC_RMII_MODE_CLR);
 573         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 574                      RK3368_GMAC_RXCLK_DLY_ENABLE |
 575                      RK3368_GMAC_TXCLK_DLY_ENABLE |
 576                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 577                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 578 }
 579
 580 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 581 {
 582         struct device *dev = &bsp_priv->pdev->dev;
 583
 584         if (IS_ERR(bsp_priv->grf)) {
 585                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 586                 return;
 587         }
 588
 589         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 590                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 591 }
 592
 593 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 594 {
 595         struct device *dev = &bsp_priv->pdev->dev;
 596
 597         if (IS_ERR(bsp_priv->grf)) {
 598                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 599                 return;
 600         }
 601
 602         if (speed == 10)
 603                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 604                              RK3368_GMAC_CLK_2_5M);
 605         else if (speed == 100)
 606                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 607                              RK3368_GMAC_CLK_25M);
 608         else if (speed == 1000)
 609                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 610                              RK3368_GMAC_CLK_125M);
 611         else
 612                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 613 }
 614
 615 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 616 {
 617         struct device *dev = &bsp_priv->pdev->dev;
 618
 619         if (IS_ERR(bsp_priv->grf)) {
 620                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 621                 return;
 622         }
 623
 624         if (speed == 10) {
 625                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 626                              RK3368_GMAC_RMII_CLK_2_5M |
 627                              RK3368_GMAC_SPEED_10M);
 628         } else if (speed == 100) {
 629                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 630                              RK3368_GMAC_RMII_CLK_25M |
 631                              RK3368_GMAC_SPEED_100M);
 632         } else {
 633                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 634         }
 635 }
 636
 637 static const struct rk_gmac_ops rk3368_ops = {
 638         .set_to_rgmii = rk3368_set_to_rgmii,
 639         .set_to_rmii = rk3368_set_to_rmii,
 640         .set_rgmii_speed = rk3368_set_rgmii_speed,
 641         .set_rmii_speed = rk3368_set_rmii_speed,
 642 };
 643
 644 #define RK3399_GRF_SOC_CON5     0xc214
 645 #define RK3399_GRF_SOC_CON6     0xc218
 646
 647 /* RK3399_GRF_SOC_CON5 */
 648 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 649                                          GRF_CLR_BIT(11))
 650 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 651                                          GRF_BIT(11))
 652 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 653 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 654 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 655 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 656 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 657 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 658 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 659 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 660 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 661 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 662 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 663
 664 /* RK3399_GRF_SOC_CON6 */
 665 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 666 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 667 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 668 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 669 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 670 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 671
 672 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 673                                 int tx_delay, int rx_delay)
 674 {
 675         struct device *dev = &bsp_priv->pdev->dev;
 676
 677         if (IS_ERR(bsp_priv->grf)) {
 678                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 679                 return;
 680         }
 681
 682         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 683                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 684                      RK3399_GMAC_RMII_MODE_CLR);
 685         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 686                      RK3399_GMAC_RXCLK_DLY_ENABLE |
 687                      RK3399_GMAC_TXCLK_DLY_ENABLE |
 688                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 689                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 690 }
 691
 692 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 693 {
 694         struct device *dev = &bsp_priv->pdev->dev;
 695
 696         if (IS_ERR(bsp_priv->grf)) {
 697                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 698                 return;
 699         }
 700
 701         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 702                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 703 }
 704
 705 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 706 {
 707         struct device *dev = &bsp_priv->pdev->dev;
 708
 709         if (IS_ERR(bsp_priv->grf)) {
 710                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 711                 return;
 712         }
 713
 714         if (speed == 10)
 715                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 716                              RK3399_GMAC_CLK_2_5M);
 717         else if (speed == 100)
 718                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 719                              RK3399_GMAC_CLK_25M);
 720         else if (speed == 1000)
 721                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 722                              RK3399_GMAC_CLK_125M);
 723         else
 724                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 725 }
 726
 727 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 728 {
 729         struct device *dev = &bsp_priv->pdev->dev;
 730
 731         if (IS_ERR(bsp_priv->grf)) {
 732                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 733                 return;
 734         }
 735
 736         if (speed == 10) {
 737                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 738                              RK3399_GMAC_RMII_CLK_2_5M |
 739                              RK3399_GMAC_SPEED_10M);
 740         } else if (speed == 100) {
 741                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 742                              RK3399_GMAC_RMII_CLK_25M |
 743                              RK3399_GMAC_SPEED_100M);
 744         } else {
 745                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 746         }
 747 }
 748
 749 static const struct rk_gmac_ops rk3399_ops = {
 750         .set_to_rgmii = rk3399_set_to_rgmii,
 751         .set_to_rmii = rk3399_set_to_rmii,
 752         .set_rgmii_speed = rk3399_set_rgmii_speed,
 753         .set_rmii_speed = rk3399_set_rmii_speed,
 754 };
 755
 756 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 757 {
 758         struct device *dev = &bsp_priv->pdev->dev;
 759
 760         bsp_priv->clk_enabled = false;
 761
 762         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
 763         if (IS_ERR(bsp_priv->mac_clk_rx))
 764                 dev_err(dev, "cannot get clock %s\n",
 765                         "mac_clk_rx");
 766
 767         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
 768         if (IS_ERR(bsp_priv->mac_clk_tx))
 769                 dev_err(dev, "cannot get clock %s\n",
 770                         "mac_clk_tx");
 771
 772         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
 773         if (IS_ERR(bsp_priv->aclk_mac))
 774                 dev_err(dev, "cannot get clock %s\n",
 775                         "aclk_mac");
 776
 777         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
 778         if (IS_ERR(bsp_priv->pclk_mac))
 779                 dev_err(dev, "cannot get clock %s\n",
 780                         "pclk_mac");
 781
 782         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
 783         if (IS_ERR(bsp_priv->clk_mac))
 784                 dev_err(dev, "cannot get clock %s\n",
 785                         "stmmaceth");
 786
 787         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 788                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
 789                 if (IS_ERR(bsp_priv->clk_mac_ref))
 790                         dev_err(dev, "cannot get clock %s\n",
 791                                 "clk_mac_ref");
 792
 793                 if (!bsp_priv->clock_input) {
 794                         bsp_priv->clk_mac_refout =
 795                                 devm_clk_get(dev, "clk_mac_refout");
 796                         if (IS_ERR(bsp_priv->clk_mac_refout))
 797                                 dev_err(dev, "cannot get clock %s\n",
 798                                         "clk_mac_refout");
 799                 }
 800         }
 801
 802         if (bsp_priv->clock_input) {
 803                 dev_info(dev, "clock input from PHY\n");
 804         } else {
 805                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 806                         clk_set_rate(bsp_priv->clk_mac, 50000000);
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 813 {
 814         int phy_iface = bsp_priv->phy_iface;
 815
 816         if (enable) {
 817                 if (!bsp_priv->clk_enabled) {
 818                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 819                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 820                                         clk_prepare_enable(
 821                                                 bsp_priv->mac_clk_rx);
 822
 823                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 824                                         clk_prepare_enable(
 825                                                 bsp_priv->clk_mac_ref);
 826
 827                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 828                                         clk_prepare_enable(
 829                                                 bsp_priv->clk_mac_refout);
 830                         }
 831
 832                         if (!IS_ERR(bsp_priv->aclk_mac))
 833                                 clk_prepare_enable(bsp_priv->aclk_mac);
 834
 835                         if (!IS_ERR(bsp_priv->pclk_mac))
 836                                 clk_prepare_enable(bsp_priv->pclk_mac);
 837
 838                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 839                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
 840
 841                         /**
 842                          * if (!IS_ERR(bsp_priv->clk_mac))
 843                          *      clk_prepare_enable(bsp_priv->clk_mac);
 844                          */
 845                         mdelay(5);
 846                         bsp_priv->clk_enabled = true;
 847                 }
 848         } else {
 849                 if (bsp_priv->clk_enabled) {
 850                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 851                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 852                                         clk_disable_unprepare(
 853                                                 bsp_priv->mac_clk_rx);
 854
 855                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 856                                         clk_disable_unprepare(
 857                                                 bsp_priv->clk_mac_ref);
 858
 859                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 860                                         clk_disable_unprepare(
 861                                                 bsp_priv->clk_mac_refout);
 862                         }
 863
 864                         if (!IS_ERR(bsp_priv->aclk_mac))
 865                                 clk_disable_unprepare(bsp_priv->aclk_mac);
 866
 867                         if (!IS_ERR(bsp_priv->pclk_mac))
 868                                 clk_disable_unprepare(bsp_priv->pclk_mac);
 869
 870                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 871                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
 872                         /**
 873                          * if (!IS_ERR(bsp_priv->clk_mac))
 874                          *      clk_disable_unprepare(bsp_priv->clk_mac);
 875                          */
 876                         bsp_priv->clk_enabled = false;
 877                 }
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
 884 {
 885         struct regulator *ldo = bsp_priv->regulator;
 886         int ret;
 887         struct device *dev = &bsp_priv->pdev->dev;
 888
 889         if (!ldo) {
 890                 dev_err(dev, "no regulator found\n");
 891                 return -1;
 892         }
 893
 894         if (enable) {
 895                 ret = regulator_enable(ldo);
 896                 if (ret)
 897                         dev_err(dev, "fail to enable phy-supply\n");
 898         } else {
 899                 ret = regulator_disable(ldo);
 900                 if (ret)
 901                         dev_err(dev, "fail to disable phy-supply\n");
 902         }
 903
 904         return 0;
 905 }
 906
 907 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 908                                           const struct rk_gmac_ops *ops)
 909 {
 910         struct rk_priv_data *bsp_priv;
 911         struct device *dev = &pdev->dev;
 912         int ret;
 913         const char *strings = NULL;
 914         int value;
 915
 916         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
 917         if (!bsp_priv)
 918                 return ERR_PTR(-ENOMEM);
 919
 920         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
 921         bsp_priv->ops = ops;
 922
 923         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
 924         if (IS_ERR(bsp_priv->regulator)) {
 925                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
 926                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
 927                         return ERR_PTR(-EPROBE_DEFER);
 928                 }
 929                 dev_err(dev, "no regulator found\n");
 930                 bsp_priv->regulator = NULL;
 931         }
 932
 933         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
 934         if (ret) {
 935                 dev_err(dev, "Can not read property: clock_in_out.\n");
 936                 bsp_priv->clock_input = true;
 937         } else {
 938                 dev_info(dev, "clock input or output? (%s).\n",
 939                          strings);
 940                 if (!strcmp(strings, "input"))
 941                         bsp_priv->clock_input = true;
 942                 else
 943                         bsp_priv->clock_input = false;
 944         }
 945
 946         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 947         if (ret) {
 948                 bsp_priv->tx_delay = 0x30;
 949                 dev_err(dev, "Can not read property: tx_delay.");
 950                 dev_err(dev, "set tx_delay to 0x%x\n",
 951                         bsp_priv->tx_delay);
 952         } else {
 953                 dev_info(dev, "TX delay(0x%x).\n", value);
 954                 bsp_priv->tx_delay = value;
 955         }
 956
 957         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
 958         if (ret) {
 959                 bsp_priv->rx_delay = 0x10;
 960                 dev_err(dev, "Can not read property: rx_delay.");
 961                 dev_err(dev, "set rx_delay to 0x%x\n",
 962                         bsp_priv->rx_delay);
 963         } else {
 964                 dev_info(dev, "RX delay(0x%x).\n", value);
 965                 bsp_priv->rx_delay = value;
 966         }
 967
 968         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
 969                                                         "rockchip,grf");
 970         bsp_priv->pdev = pdev;
 971
 972         gmac_clk_init(bsp_priv);
 973
 974         return bsp_priv;
 975 }
 976
 977 static int rk_gmac_init(struct platform_device *pdev, void *priv)
 978 {
 979         struct rk_priv_data *bsp_priv = priv;
 980         int ret;
 981         struct device *dev = &pdev->dev;
 982
 983         /*rmii or rgmii*/
 984         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
 985                 dev_info(dev, "init for RGMII\n");
 986                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
 987                                             bsp_priv->rx_delay);
 988         } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 989                 dev_info(dev, "init for RMII\n");
 990                 bsp_priv->ops->set_to_rmii(bsp_priv);
 991         } else {
 992                 dev_err(dev, "NO interface defined!\n");
 993         }
 994
 995         ret = phy_power_on(bsp_priv, true);
 996         if (ret)
 997                 return ret;
 998
 999         ret = gmac_clk_enable(bsp_priv, true);
1000         if (ret)
1001                 return ret;
1002
1003         pm_runtime_enable(&pdev->dev);
1004         pm_runtime_get_sync(&pdev->dev);
1005
1006         return 0;
1007 }
1008
1009 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
1010 {
1011         struct rk_priv_data *gmac = priv;
1012
1013         pm_runtime_put_sync(&pdev->dev);
1014         pm_runtime_disable(&pdev->dev);
1015
1016         phy_power_on(gmac, false);
1017         gmac_clk_enable(gmac, false);
1018 }
1019
1020 static void rk_fix_speed(void *priv, unsigned int speed)
1021 {
1022         struct rk_priv_data *bsp_priv = priv;
1023         struct device *dev = &bsp_priv->pdev->dev;
1024
1025         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
1026                 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1027         else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1028                 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1029         else
1030                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1031 }
1032
1033 void rk_get_eth_addr_vendor(void *priv, unsigned char *addr)
1034 {
1035         int ret;
1036         struct rk_priv_data *bsp_priv = priv;
1037         struct device *dev = &bsp_priv->pdev->dev;
1038
1039         ret = rk_vendor_read(LAN_MAC_ID, addr, 6);
1040         if (ret != 6 || is_zero_ether_addr(addr)) {
1041                 dev_err(dev, "%s: rk_vendor_read eth mac address failed (%d)",
1042                                         __func__, ret);
1043                 random_ether_addr(addr);
1044                 dev_err(dev, "%s: generate random eth mac address: %02x:%02x:%02x:%02x:%02x:%02x",
1045                                         __func__, addr[0], addr[1], addr[2],
1046                                         addr[3], addr[4], addr[5]);
1047                 ret = rk_vendor_write(LAN_MAC_ID, addr, 6);
1048                 if (ret != 0)
1049                         dev_err(dev, "%s: rk_vendor_write eth mac address failed (%d)",
1050                                         __func__, ret);
1051         } else {
1052                 dev_dbg(dev, "%s: rk_vendor_read eth mac address: %02x:%02x:%02x:%02x:%02x:%02x",
1053                                         __func__, addr[0], addr[1], addr[2],
1054                                         addr[3], addr[4], addr[5]);
1055         }
1056 }
1057
1058 static int rk_gmac_probe(struct platform_device *pdev)
1059 {
1060         struct plat_stmmacenet_data *plat_dat;
1061         struct stmmac_resources stmmac_res;
1062         const struct rk_gmac_ops *data;
1063         int ret;
1064
1065         data = of_device_get_match_data(&pdev->dev);
1066         if (!data) {
1067                 dev_err(&pdev->dev, "no of match data provided\n");
1068                 return -EINVAL;
1069         }
1070
1071         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1072         if (ret)
1073                 return ret;
1074
1075         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1076         if (IS_ERR(plat_dat))
1077                 return PTR_ERR(plat_dat);
1078
1079         plat_dat->has_gmac = true;
1080         plat_dat->init = rk_gmac_init;
1081         plat_dat->exit = rk_gmac_exit;
1082         plat_dat->fix_mac_speed = rk_fix_speed;
1083         plat_dat->get_eth_addr = rk_get_eth_addr_vendor;
1084
1085         plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
1086         if (IS_ERR(plat_dat->bsp_priv))
1087                 return PTR_ERR(plat_dat->bsp_priv);
1088
1089         ret = rk_gmac_init(pdev, plat_dat->bsp_priv);
1090         if (ret)
1091                 return ret;
1092
1093         return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1094 }
1095
1096 static const struct of_device_id rk_gmac_dwmac_match[] = {
1097         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1098         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1099         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1100         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1101         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1102         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1103         { }
1104 };
1105 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1106
1107 static struct platform_driver rk_gmac_dwmac_driver = {
1108         .probe  = rk_gmac_probe,
1109         .remove = stmmac_pltfr_remove,
1110         .driver = {
1111                 .name           = "rk_gmac-dwmac",
1112                 .pm             = &stmmac_pltfr_pm_ops,
1113                 .of_match_table = rk_gmac_dwmac_match,
1114         },
1115 };
1116 module_platform_driver(rk_gmac_dwmac_driver);
1117
1118 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1119 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1120 MODULE_LICENSE("GPL");