drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & host->align_mask);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (host->align_sz - (addr & host->align_mask)) &
 518                          host->align_mask;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += host->align_sz;
 533                         align_addr += host->align_sz;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 if (len) {
 544                         /* tran, valid */
 545                         sdhci_adma_write_desc(host, desc, addr, len,
 546                                               ADMA2_TRAN_VALID);
 547                         desc += host->desc_sz;
 548                 }
 549
 550                 /*
 551                  * If this triggers then we have a calculation bug
 552                  * somewhere. :/
 553                  */
 554                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 555         }
 556
 557         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 558                 /*
 559                 * Mark the last descriptor as the terminating descriptor
 560                 */
 561                 if (desc != host->adma_table) {
 562                         desc -= host->desc_sz;
 563                         sdhci_adma_mark_end(desc);
 564                 }
 565         } else {
 566                 /*
 567                 * Add a terminating entry.
 568                 */
 569
 570                 /* nop, end, valid */
 571                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 572         }
 573
 574         /*
 575          * Resync align buffer as we might have changed it.
 576          */
 577         if (data->flags & MMC_DATA_WRITE) {
 578                 dma_sync_single_for_device(mmc_dev(host->mmc),
 579                         host->align_addr, host->align_buffer_sz, direction);
 580         }
 581
 582         return 0;
 583
 584 unmap_align:
 585         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 586                 host->align_buffer_sz, direction);
 587 fail:
 588         return -EINVAL;
 589 }
 590
 591 static void sdhci_adma_table_post(struct sdhci_host *host,
 592         struct mmc_data *data)
 593 {
 594         int direction;
 595
 596         struct scatterlist *sg;
 597         int i, size;
 598         void *align;
 599         char *buffer;
 600         unsigned long flags;
 601         bool has_unaligned;
 602
 603         if (data->flags & MMC_DATA_READ)
 604                 direction = DMA_FROM_DEVICE;
 605         else
 606                 direction = DMA_TO_DEVICE;
 607
 608         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 609                 host->align_buffer_sz, direction);
 610
 611         /* Do a quick scan of the SG list for any unaligned mappings */
 612         has_unaligned = false;
 613         for_each_sg(data->sg, sg, host->sg_count, i)
 614                 if (sg_dma_address(sg) & host->align_mask) {
 615                         has_unaligned = true;
 616                         break;
 617                 }
 618
 619         if (has_unaligned && data->flags & MMC_DATA_READ) {
 620                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 621                         data->sg_len, direction);
 622
 623                 align = host->align_buffer;
 624
 625                 for_each_sg(data->sg, sg, host->sg_count, i) {
 626                         if (sg_dma_address(sg) & host->align_mask) {
 627                                 size = host->align_sz -
 628                                        (sg_dma_address(sg) & host->align_mask);
 629
 630                                 buffer = sdhci_kmap_atomic(sg, &flags);
 631                                 memcpy(buffer, align, size);
 632                                 sdhci_kunmap_atomic(buffer, &flags);
 633
 634                                 align += host->align_sz;
 635                         }
 636                 }
 637         }
 638
 639         if (data->host_cookie == COOKIE_MAPPED) {
 640                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 641                         data->sg_len, direction);
 642                 data->host_cookie = COOKIE_UNMAPPED;
 643         }
 644 }
 645
 646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 647 {
 648         u8 count;
 649         struct mmc_data *data = cmd->data;
 650         unsigned target_timeout, current_timeout;
 651
 652         /*
 653          * If the host controller provides us with an incorrect timeout
 654          * value, just skip the check and use 0xE.  The hardware may take
 655          * longer to time out, but that's much better than having a too-short
 656          * timeout value.
 657          */
 658         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 659                 return 0xE;
 660
 661         /* Unspecified timeout, assume max */
 662         if (!data && !cmd->busy_timeout)
 663                 return 0xE;
 664
 665         /* timeout in us */
 666         if (!data)
 667                 target_timeout = cmd->busy_timeout * 1000;
 668         else {
 669                 target_timeout = data->timeout_ns / 1000;
 670                 if (host->clock)
 671                         target_timeout += data->timeout_clks / host->clock;
 672         }
 673
 674         /*
 675          * Figure out needed cycles.
 676          * We do this in steps in order to fit inside a 32 bit int.
 677          * The first step is the minimum timeout, which will have a
 678          * minimum resolution of 6 bits:
 679          * (1) 2^13*1000 > 2^22,
 680          * (2) host->timeout_clk < 2^16
 681          *     =>
 682          *     (1) / (2) > 2^6
 683          */
 684         count = 0;
 685         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 686         while (current_timeout < target_timeout) {
 687                 count++;
 688                 current_timeout <<= 1;
 689                 if (count >= 0xF)
 690                         break;
 691         }
 692
 693         if (count >= 0xF) {
 694                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 695                     mmc_hostname(host->mmc), count, cmd->opcode);
 696                 count = 0xE;
 697         }
 698
 699         return count;
 700 }
 701
 702 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 703 {
 704         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 705         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 706
 707         if (host->flags & SDHCI_REQ_USE_DMA)
 708                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 709         else
 710                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 711
 712         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 713         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 714 }
 715
 716 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 717 {
 718         u8 count;
 719
 720         if (host->ops->set_timeout) {
 721                 host->ops->set_timeout(host, cmd);
 722         } else {
 723                 count = sdhci_calc_timeout(host, cmd);
 724                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 725         }
 726 }
 727
 728 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 729 {
 730         u8 ctrl;
 731         struct mmc_data *data = cmd->data;
 732         int ret;
 733
 734         WARN_ON(host->data);
 735
 736         if (data || (cmd->flags & MMC_RSP_BUSY))
 737                 sdhci_set_timeout(host, cmd);
 738
 739         if (!data)
 740                 return;
 741
 742         /* Sanity checks */
 743         BUG_ON(data->blksz * data->blocks > 524288);
 744         BUG_ON(data->blksz > host->mmc->max_blk_size);
 745         BUG_ON(data->blocks > 65535);
 746
 747         host->data = data;
 748         host->data_early = 0;
 749         host->data->bytes_xfered = 0;
 750
 751         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 752                 host->flags |= SDHCI_REQ_USE_DMA;
 753
 754         /*
 755          * FIXME: This doesn't account for merging when mapping the
 756          * scatterlist.
 757          */
 758         if (host->flags & SDHCI_REQ_USE_DMA) {
 759                 int broken, i;
 760                 struct scatterlist *sg;
 761
 762                 broken = 0;
 763                 if (host->flags & SDHCI_USE_ADMA) {
 764                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 765                                 broken = 1;
 766                 } else {
 767                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 768                                 broken = 1;
 769                 }
 770
 771                 if (unlikely(broken)) {
 772                         for_each_sg(data->sg, sg, data->sg_len, i) {
 773                                 if (sg->length & 0x3) {
 774                                         DBG("Reverting to PIO because of "
 775                                                 "transfer size (%d)\n",
 776                                                 sg->length);
 777                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         }
 783
 784         /*
 785          * The assumption here being that alignment is the same after
 786          * translation to device address space.
 787          */
 788         if (host->flags & SDHCI_REQ_USE_DMA) {
 789                 int broken, i;
 790                 struct scatterlist *sg;
 791
 792                 broken = 0;
 793                 if (host->flags & SDHCI_USE_ADMA) {
 794                         /*
 795                          * As we use 3 byte chunks to work around
 796                          * alignment problems, we need to check this
 797                          * quirk.
 798                          */
 799                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 800                                 broken = 1;
 801                 } else {
 802                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 803                                 broken = 1;
 804                 }
 805
 806                 if (unlikely(broken)) {
 807                         for_each_sg(data->sg, sg, data->sg_len, i) {
 808                                 if (sg->offset & 0x3) {
 809                                         DBG("Reverting to PIO because of "
 810                                                 "bad alignment\n");
 811                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 812                                         break;
 813                                 }
 814                         }
 815                 }
 816         }
 817
 818         if (host->flags & SDHCI_REQ_USE_DMA) {
 819                 if (host->flags & SDHCI_USE_ADMA) {
 820                         ret = sdhci_adma_table_pre(host, data);
 821                         if (ret) {
 822                                 /*
 823                                  * This only happens when someone fed
 824                                  * us an invalid request.
 825                                  */
 826                                 WARN_ON(1);
 827                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 828                         } else {
 829                                 sdhci_writel(host, host->adma_addr,
 830                                         SDHCI_ADMA_ADDRESS);
 831                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 832                                         sdhci_writel(host,
 833                                                      (u64)host->adma_addr >> 32,
 834                                                      SDHCI_ADMA_ADDRESS_HI);
 835                         }
 836                 } else {
 837                         int sg_cnt;
 838
 839                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 840                         if (sg_cnt <= 0) {
 841                                 /*
 842                                  * This only happens when someone fed
 843                                  * us an invalid request.
 844                                  */
 845                                 WARN_ON(1);
 846                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 847                         } else {
 848                                 WARN_ON(sg_cnt != 1);
 849                                 sdhci_writel(host, sg_dma_address(data->sg),
 850                                         SDHCI_DMA_ADDRESS);
 851                         }
 852                 }
 853         }
 854
 855         /*
 856          * Always adjust the DMA selection as some controllers
 857          * (e.g. JMicron) can't do PIO properly when the selection
 858          * is ADMA.
 859          */
 860         if (host->version >= SDHCI_SPEC_200) {
 861                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 862                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 863                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 864                         (host->flags & SDHCI_USE_ADMA)) {
 865                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 866                                 ctrl |= SDHCI_CTRL_ADMA64;
 867                         else
 868                                 ctrl |= SDHCI_CTRL_ADMA32;
 869                 } else {
 870                         ctrl |= SDHCI_CTRL_SDMA;
 871                 }
 872                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 873         }
 874
 875         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 876                 int flags;
 877
 878                 flags = SG_MITER_ATOMIC;
 879                 if (host->data->flags & MMC_DATA_READ)
 880                         flags |= SG_MITER_TO_SG;
 881                 else
 882                         flags |= SG_MITER_FROM_SG;
 883                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 884                 host->blocks = data->blocks;
 885         }
 886
 887         sdhci_set_transfer_irqs(host);
 888
 889         /* Set the DMA boundary value and block size */
 890         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 891                 data->blksz), SDHCI_BLOCK_SIZE);
 892         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 893 }
 894
 895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 896         struct mmc_command *cmd)
 897 {
 898         u16 mode = 0;
 899         struct mmc_data *data = cmd->data;
 900
 901         if (data == NULL) {
 902                 if (host->quirks2 &
 903                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 904                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 905                 } else {
 906                 /* clear Auto CMD settings for no data CMDs */
 907                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 908                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 909                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 910                 }
 911                 return;
 912         }
 913
 914         WARN_ON(!host->data);
 915
 916         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 917                 mode = SDHCI_TRNS_BLK_CNT_EN;
 918
 919         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 920                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 921                 /*
 922                  * If we are sending CMD23, CMD12 never gets sent
 923                  * on successful completion (so no Auto-CMD12).
 924                  */
 925                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 926                     (cmd->opcode != SD_IO_RW_EXTENDED))
 927                         mode |= SDHCI_TRNS_AUTO_CMD12;
 928                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 929                         mode |= SDHCI_TRNS_AUTO_CMD23;
 930                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 931                 }
 932         }
 933
 934         if (data->flags & MMC_DATA_READ)
 935                 mode |= SDHCI_TRNS_READ;
 936         if (host->flags & SDHCI_REQ_USE_DMA)
 937                 mode |= SDHCI_TRNS_DMA;
 938
 939         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 940 }
 941
 942 static void sdhci_finish_data(struct sdhci_host *host)
 943 {
 944         struct mmc_data *data;
 945
 946         BUG_ON(!host->data);
 947
 948         data = host->data;
 949         host->data = NULL;
 950
 951         if (host->flags & SDHCI_REQ_USE_DMA) {
 952                 if (host->flags & SDHCI_USE_ADMA)
 953                         sdhci_adma_table_post(host, data);
 954                 else {
 955                         if (data->host_cookie == COOKIE_MAPPED) {
 956                                 dma_unmap_sg(mmc_dev(host->mmc),
 957                                         data->sg, data->sg_len,
 958                                         (data->flags & MMC_DATA_READ) ?
 959                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 960                                 data->host_cookie = COOKIE_UNMAPPED;
 961                         }
 962                 }
 963         }
 964
 965         /*
 966          * The specification states that the block count register must
 967          * be updated, but it does not specify at what point in the
 968          * data flow. That makes the register entirely useless to read
 969          * back so we have to assume that nothing made it to the card
 970          * in the event of an error.
 971          */
 972         if (data->error)
 973                 data->bytes_xfered = 0;
 974         else
 975                 data->bytes_xfered = data->blksz * data->blocks;
 976
 977         /*
 978          * Need to send CMD12 if -
 979          * a) open-ended multiblock transfer (no CMD23)
 980          * b) error in multiblock transfer
 981          */
 982         if (data->stop &&
 983             (data->error ||
 984              !host->mrq->sbc)) {
 985
 986                 /*
 987                  * The controller needs a reset of internal state machines
 988                  * upon error conditions.
 989                  */
 990                 if (data->error) {
 991                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 992                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 993                 }
 994
 995                 sdhci_send_command(host, data->stop);
 996         } else
 997                 tasklet_schedule(&host->finish_tasklet);
 998 }
 999
1000 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1001 {
1002         int flags;
1003         u32 mask;
1004         unsigned long timeout;
1005
1006         WARN_ON(host->cmd);
1007
1008         /* Wait max 10 ms */
1009         timeout = 10;
1010
1011         mask = SDHCI_CMD_INHIBIT;
1012         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1013                 mask |= SDHCI_DATA_INHIBIT;
1014
1015         /* We shouldn't wait for data inihibit for stop commands, even
1016            though they might use busy signaling */
1017         if (host->mrq->data && (cmd == host->mrq->data->stop))
1018                 mask &= ~SDHCI_DATA_INHIBIT;
1019
1020         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1021                 if (timeout == 0) {
1022                         pr_err("%s: Controller never released "
1023                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1024                         sdhci_dumpregs(host);
1025                         cmd->error = -EIO;
1026                         tasklet_schedule(&host->finish_tasklet);
1027                         return;
1028                 }
1029                 timeout--;
1030                 mdelay(1);
1031         }
1032
1033         timeout = jiffies;
1034         if (!cmd->data && cmd->busy_timeout > 9000)
1035                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1036         else
1037                 timeout += 10 * HZ;
1038         mod_timer(&host->timer, timeout);
1039
1040         host->cmd = cmd;
1041         host->busy_handle = 0;
1042
1043         sdhci_prepare_data(host, cmd);
1044
1045         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1046
1047         sdhci_set_transfer_mode(host, cmd);
1048
1049         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1050                 pr_err("%s: Unsupported response type!\n",
1051                         mmc_hostname(host->mmc));
1052                 cmd->error = -EINVAL;
1053                 tasklet_schedule(&host->finish_tasklet);
1054                 return;
1055         }
1056
1057         if (!(cmd->flags & MMC_RSP_PRESENT))
1058                 flags = SDHCI_CMD_RESP_NONE;
1059         else if (cmd->flags & MMC_RSP_136)
1060                 flags = SDHCI_CMD_RESP_LONG;
1061         else if (cmd->flags & MMC_RSP_BUSY)
1062                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1063         else
1064                 flags = SDHCI_CMD_RESP_SHORT;
1065
1066         if (cmd->flags & MMC_RSP_CRC)
1067                 flags |= SDHCI_CMD_CRC;
1068         if (cmd->flags & MMC_RSP_OPCODE)
1069                 flags |= SDHCI_CMD_INDEX;
1070
1071         /* CMD19 is special in that the Data Present Select should be set */
1072         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1073             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1074                 flags |= SDHCI_CMD_DATA;
1075
1076         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1077 }
1078 EXPORT_SYMBOL_GPL(sdhci_send_command);
1079
1080 static void sdhci_finish_command(struct sdhci_host *host)
1081 {
1082         int i;
1083
1084         BUG_ON(host->cmd == NULL);
1085
1086         if (host->cmd->flags & MMC_RSP_PRESENT) {
1087                 if (host->cmd->flags & MMC_RSP_136) {
1088                         /* CRC is stripped so we need to do some shifting. */
1089                         for (i = 0;i < 4;i++) {
1090                                 host->cmd->resp[i] = sdhci_readl(host,
1091                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1092                                 if (i != 3)
1093                                         host->cmd->resp[i] |=
1094                                                 sdhci_readb(host,
1095                                                 SDHCI_RESPONSE + (3-i)*4-1);
1096                         }
1097                 } else {
1098                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1099                 }
1100         }
1101
1102         host->cmd->error = 0;
1103
1104         /* Finished CMD23, now send actual command. */
1105         if (host->cmd == host->mrq->sbc) {
1106                 host->cmd = NULL;
1107                 sdhci_send_command(host, host->mrq->cmd);
1108         } else {
1109
1110                 /* Processed actual command. */
1111                 if (host->data && host->data_early)
1112                         sdhci_finish_data(host);
1113
1114                 if (!host->cmd->data)
1115                         tasklet_schedule(&host->finish_tasklet);
1116
1117                 host->cmd = NULL;
1118         }
1119 }
1120
1121 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1122 {
1123         u16 preset = 0;
1124
1125         switch (host->timing) {
1126         case MMC_TIMING_UHS_SDR12:
1127                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1128                 break;
1129         case MMC_TIMING_UHS_SDR25:
1130                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1131                 break;
1132         case MMC_TIMING_UHS_SDR50:
1133                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1134                 break;
1135         case MMC_TIMING_UHS_SDR104:
1136         case MMC_TIMING_MMC_HS200:
1137                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1138                 break;
1139         case MMC_TIMING_UHS_DDR50:
1140         case MMC_TIMING_MMC_DDR52:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1142                 break;
1143         case MMC_TIMING_MMC_HS400:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1145                 break;
1146         default:
1147                 pr_warn("%s: Invalid UHS-I mode selected\n",
1148                         mmc_hostname(host->mmc));
1149                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1150                 break;
1151         }
1152         return preset;
1153 }
1154
1155 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1156 {
1157         int div = 0; /* Initialized for compiler warning */
1158         int real_div = div, clk_mul = 1;
1159         u16 clk = 0;
1160         unsigned long timeout;
1161         bool switch_base_clk = false;
1162
1163         host->mmc->actual_clock = 0;
1164
1165         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1166         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1167                 mdelay(1);
1168
1169         if (clock == 0)
1170                 return;
1171
1172         if (host->version >= SDHCI_SPEC_300) {
1173                 if (host->preset_enabled) {
1174                         u16 pre_val;
1175
1176                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1177                         pre_val = sdhci_get_preset_value(host);
1178                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1179                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1180                         if (host->clk_mul &&
1181                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1182                                 clk = SDHCI_PROG_CLOCK_MODE;
1183                                 real_div = div + 1;
1184                                 clk_mul = host->clk_mul;
1185                         } else {
1186                                 real_div = max_t(int, 1, div << 1);
1187                         }
1188                         goto clock_set;
1189                 }
1190
1191                 /*
1192                  * Check if the Host Controller supports Programmable Clock
1193                  * Mode.
1194                  */
1195                 if (host->clk_mul) {
1196                         for (div = 1; div <= 1024; div++) {
1197                                 if ((host->max_clk * host->clk_mul / div)
1198                                         <= clock)
1199                                         break;
1200                         }
1201                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1202                                 /*
1203                                  * Set Programmable Clock Mode in the Clock
1204                                  * Control register.
1205                                  */
1206                                 clk = SDHCI_PROG_CLOCK_MODE;
1207                                 real_div = div;
1208                                 clk_mul = host->clk_mul;
1209                                 div--;
1210                         } else {
1211                                 /*
1212                                  * Divisor can be too small to reach clock
1213                                  * speed requirement. Then use the base clock.
1214                                  */
1215                                 switch_base_clk = true;
1216                         }
1217                 }
1218
1219                 if (!host->clk_mul || switch_base_clk) {
1220                         /* Version 3.00 divisors must be a multiple of 2. */
1221                         if (host->max_clk <= clock)
1222                                 div = 1;
1223                         else {
1224                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1225                                      div += 2) {
1226                                         if ((host->max_clk / div) <= clock)
1227                                                 break;
1228                                 }
1229                         }
1230                         real_div = div;
1231                         div >>= 1;
1232                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1233                                 && !div && host->max_clk <= 25000000)
1234                                 div = 1;
1235                 }
1236         } else {
1237                 /* Version 2.00 divisors must be a power of 2. */
1238                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1239                         if ((host->max_clk / div) <= clock)
1240                                 break;
1241                 }
1242                 real_div = div;
1243                 div >>= 1;
1244         }
1245
1246 clock_set:
1247         if (real_div)
1248                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1249         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1250         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1251                 << SDHCI_DIVIDER_HI_SHIFT;
1252         clk |= SDHCI_CLOCK_INT_EN;
1253         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1254
1255         /* Wait max 20 ms */
1256         timeout = 20;
1257         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1258                 & SDHCI_CLOCK_INT_STABLE)) {
1259                 if (timeout == 0) {
1260                         pr_err("%s: Internal clock never "
1261                                 "stabilised.\n", mmc_hostname(host->mmc));
1262                         sdhci_dumpregs(host);
1263                         return;
1264                 }
1265                 timeout--;
1266                 mdelay(1);
1267         }
1268
1269         clk |= SDHCI_CLOCK_CARD_EN;
1270         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1271 }
1272 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1273
1274 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1275                             unsigned short vdd)
1276 {
1277         struct mmc_host *mmc = host->mmc;
1278         u8 pwr = 0;
1279
1280         if (!IS_ERR(mmc->supply.vmmc)) {
1281                 spin_unlock_irq(&host->lock);
1282                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1283                 spin_lock_irq(&host->lock);
1284
1285                 if (mode != MMC_POWER_OFF)
1286                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1287                 else
1288                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1289
1290                 return;
1291         }
1292
1293         if (mode != MMC_POWER_OFF) {
1294                 switch (1 << vdd) {
1295                 case MMC_VDD_165_195:
1296                         pwr = SDHCI_POWER_180;
1297                         break;
1298                 case MMC_VDD_29_30:
1299                 case MMC_VDD_30_31:
1300                         pwr = SDHCI_POWER_300;
1301                         break;
1302                 case MMC_VDD_32_33:
1303                 case MMC_VDD_33_34:
1304                         pwr = SDHCI_POWER_330;
1305                         break;
1306                 default:
1307                         BUG();
1308                 }
1309         }
1310
1311         if (host->pwr == pwr)
1312                 return;
1313
1314         host->pwr = pwr;
1315
1316         if (pwr == 0) {
1317                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1318                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1319                         sdhci_runtime_pm_bus_off(host);
1320                 vdd = 0;
1321         } else {
1322                 /*
1323                  * Spec says that we should clear the power reg before setting
1324                  * a new value. Some controllers don't seem to like this though.
1325                  */
1326                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1327                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1328
1329                 /*
1330                  * At least the Marvell CaFe chip gets confused if we set the
1331                  * voltage and set turn on power at the same time, so set the
1332                  * voltage first.
1333                  */
1334                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1335                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1336
1337                 pwr |= SDHCI_POWER_ON;
1338
1339                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1340
1341                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1342                         sdhci_runtime_pm_bus_on(host);
1343
1344                 /*
1345                  * Some controllers need an extra 10ms delay of 10ms before
1346                  * they can apply clock after applying power
1347                  */
1348                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1349                         mdelay(10);
1350         }
1351 }
1352
1353 /*****************************************************************************\
1354  *                                                                           *
1355  * MMC callbacks                                                             *
1356  *                                                                           *
1357 \*****************************************************************************/
1358
1359 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1360 {
1361         struct sdhci_host *host;
1362         int present;
1363         unsigned long flags;
1364
1365         host = mmc_priv(mmc);
1366
1367         sdhci_runtime_pm_get(host);
1368
1369         /* Firstly check card presence */
1370         present = mmc->ops->get_cd(mmc);
1371
1372         spin_lock_irqsave(&host->lock, flags);
1373
1374         WARN_ON(host->mrq != NULL);
1375
1376 #ifndef SDHCI_USE_LEDS_CLASS
1377         sdhci_activate_led(host);
1378 #endif
1379
1380         /*
1381          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1382          * requests if Auto-CMD12 is enabled.
1383          */
1384         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1385                 if (mrq->stop) {
1386                         mrq->data->stop = NULL;
1387                         mrq->stop = NULL;
1388                 }
1389         }
1390
1391         host->mrq = mrq;
1392
1393         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1394                 host->mrq->cmd->error = -ENOMEDIUM;
1395                 tasklet_schedule(&host->finish_tasklet);
1396         } else {
1397                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1398                         sdhci_send_command(host, mrq->sbc);
1399                 else
1400                         sdhci_send_command(host, mrq->cmd);
1401         }
1402
1403         mmiowb();
1404         spin_unlock_irqrestore(&host->lock, flags);
1405 }
1406
1407 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1408 {
1409         u8 ctrl;
1410
1411         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1412         if (width == MMC_BUS_WIDTH_8) {
1413                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1414                 if (host->version >= SDHCI_SPEC_300)
1415                         ctrl |= SDHCI_CTRL_8BITBUS;
1416         } else {
1417                 if (host->version >= SDHCI_SPEC_300)
1418                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1419                 if (width == MMC_BUS_WIDTH_4)
1420                         ctrl |= SDHCI_CTRL_4BITBUS;
1421                 else
1422                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1423         }
1424         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1425 }
1426 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1427
1428 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1429 {
1430         u16 ctrl_2;
1431
1432         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1433         /* Select Bus Speed Mode for host */
1434         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1435         if ((timing == MMC_TIMING_MMC_HS200) ||
1436             (timing == MMC_TIMING_UHS_SDR104))
1437                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1438         else if (timing == MMC_TIMING_UHS_SDR12)
1439                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1440         else if (timing == MMC_TIMING_UHS_SDR25)
1441                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1442         else if (timing == MMC_TIMING_UHS_SDR50)
1443                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1444         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1445                  (timing == MMC_TIMING_MMC_DDR52))
1446                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1447         else if (timing == MMC_TIMING_MMC_HS400)
1448                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1449         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1450 }
1451 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1452
1453 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1454 {
1455         unsigned long flags;
1456         u8 ctrl;
1457         struct mmc_host *mmc = host->mmc;
1458
1459         spin_lock_irqsave(&host->lock, flags);
1460
1461         if (host->flags & SDHCI_DEVICE_DEAD) {
1462                 spin_unlock_irqrestore(&host->lock, flags);
1463                 if (!IS_ERR(mmc->supply.vmmc) &&
1464                     ios->power_mode == MMC_POWER_OFF)
1465                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1466                 return;
1467         }
1468
1469         /*
1470          * Reset the chip on each power off.
1471          * Should clear out any weird states.
1472          */
1473         if (ios->power_mode == MMC_POWER_OFF) {
1474                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1475                 sdhci_reinit(host);
1476         }
1477
1478         if (host->version >= SDHCI_SPEC_300 &&
1479                 (ios->power_mode == MMC_POWER_UP) &&
1480                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1481                 sdhci_enable_preset_value(host, false);
1482
1483         if (!ios->clock || ios->clock != host->clock) {
1484                 host->ops->set_clock(host, ios->clock);
1485                 host->clock = ios->clock;
1486
1487                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1488                     host->clock) {
1489                         host->timeout_clk = host->mmc->actual_clock ?
1490                                                 host->mmc->actual_clock / 1000 :
1491                                                 host->clock / 1000;
1492                         host->mmc->max_busy_timeout =
1493                                 host->ops->get_max_timeout_count ?
1494                                 host->ops->get_max_timeout_count(host) :
1495                                 1 << 27;
1496                         host->mmc->max_busy_timeout /= host->timeout_clk;
1497                 }
1498         }
1499
1500         sdhci_set_power(host, ios->power_mode, ios->vdd);
1501
1502         if (host->ops->platform_send_init_74_clocks)
1503                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1504
1505         host->ops->set_bus_width(host, ios->bus_width);
1506
1507         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1508
1509         if ((ios->timing == MMC_TIMING_SD_HS ||
1510              ios->timing == MMC_TIMING_MMC_HS)
1511             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1512                 ctrl |= SDHCI_CTRL_HISPD;
1513         else
1514                 ctrl &= ~SDHCI_CTRL_HISPD;
1515
1516         if (host->version >= SDHCI_SPEC_300) {
1517                 u16 clk, ctrl_2;
1518
1519                 /* In case of UHS-I modes, set High Speed Enable */
1520                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1521                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1522                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1523                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1524                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1525                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1526                     (ios->timing == MMC_TIMING_UHS_SDR25))
1527                         ctrl |= SDHCI_CTRL_HISPD;
1528
1529                 if (!host->preset_enabled) {
1530                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1531                         /*
1532                          * We only need to set Driver Strength if the
1533                          * preset value enable is not set.
1534                          */
1535                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1536                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1537                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1538                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1539                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1540                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1541                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1542                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1543                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1544                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1545                         else {
1546                                 pr_warn("%s: invalid driver type, default to "
1547                                         "driver type B\n", mmc_hostname(mmc));
1548                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1549                         }
1550
1551                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1552                 } else {
1553                         /*
1554                          * According to SDHC Spec v3.00, if the Preset Value
1555                          * Enable in the Host Control 2 register is set, we
1556                          * need to reset SD Clock Enable before changing High
1557                          * Speed Enable to avoid generating clock gliches.
1558                          */
1559
1560                         /* Reset SD Clock Enable */
1561                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1562                         clk &= ~SDHCI_CLOCK_CARD_EN;
1563                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1564
1565                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1566
1567                         /* Re-enable SD Clock */
1568                         host->ops->set_clock(host, host->clock);
1569                 }
1570
1571                 /* Reset SD Clock Enable */
1572                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1573                 clk &= ~SDHCI_CLOCK_CARD_EN;
1574                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1575
1576                 host->ops->set_uhs_signaling(host, ios->timing);
1577                 host->timing = ios->timing;
1578
1579                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1580                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1581                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1582                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1583                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1584                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1585                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1586                         u16 preset;
1587
1588                         sdhci_enable_preset_value(host, true);
1589                         preset = sdhci_get_preset_value(host);
1590                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1591                                 >> SDHCI_PRESET_DRV_SHIFT;
1592                 }
1593
1594                 /* Re-enable SD Clock */
1595                 host->ops->set_clock(host, host->clock);
1596         } else
1597                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1598
1599         /*
1600          * Some (ENE) controllers go apeshit on some ios operation,
1601          * signalling timeout and CRC errors even on CMD0. Resetting
1602          * it on each ios seems to solve the problem.
1603          */
1604         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1605                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1606
1607         mmiowb();
1608         spin_unlock_irqrestore(&host->lock, flags);
1609 }
1610
1611 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1612 {
1613         struct sdhci_host *host = mmc_priv(mmc);
1614
1615         sdhci_runtime_pm_get(host);
1616         sdhci_do_set_ios(host, ios);
1617         sdhci_runtime_pm_put(host);
1618 }
1619
1620 static int sdhci_do_get_cd(struct sdhci_host *host)
1621 {
1622         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1623
1624         if (host->flags & SDHCI_DEVICE_DEAD)
1625                 return 0;
1626
1627         /* If nonremovable, assume that the card is always present. */
1628         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1629                 return 1;
1630
1631         /*
1632          * Try slot gpio detect, if defined it take precedence
1633          * over build in controller functionality
1634          */
1635         if (!IS_ERR_VALUE(gpio_cd))
1636                 return !!gpio_cd;
1637
1638         /* If polling, assume that the card is always present. */
1639         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1640                 return 1;
1641
1642         /* Host native card detect */
1643         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1644 }
1645
1646 static int sdhci_get_cd(struct mmc_host *mmc)
1647 {
1648         struct sdhci_host *host = mmc_priv(mmc);
1649         int ret;
1650
1651         sdhci_runtime_pm_get(host);
1652         ret = sdhci_do_get_cd(host);
1653         sdhci_runtime_pm_put(host);
1654         return ret;
1655 }
1656
1657 static int sdhci_check_ro(struct sdhci_host *host)
1658 {
1659         unsigned long flags;
1660         int is_readonly;
1661
1662         spin_lock_irqsave(&host->lock, flags);
1663
1664         if (host->flags & SDHCI_DEVICE_DEAD)
1665                 is_readonly = 0;
1666         else if (host->ops->get_ro)
1667                 is_readonly = host->ops->get_ro(host);
1668         else
1669                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1670                                 & SDHCI_WRITE_PROTECT);
1671
1672         spin_unlock_irqrestore(&host->lock, flags);
1673
1674         /* This quirk needs to be replaced by a callback-function later */
1675         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1676                 !is_readonly : is_readonly;
1677 }
1678
1679 #define SAMPLE_COUNT    5
1680
1681 static int sdhci_do_get_ro(struct sdhci_host *host)
1682 {
1683         int i, ro_count;
1684
1685         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1686                 return sdhci_check_ro(host);
1687
1688         ro_count = 0;
1689         for (i = 0; i < SAMPLE_COUNT; i++) {
1690                 if (sdhci_check_ro(host)) {
1691                         if (++ro_count > SAMPLE_COUNT / 2)
1692                                 return 1;
1693                 }
1694                 msleep(30);
1695         }
1696         return 0;
1697 }
1698
1699 static void sdhci_hw_reset(struct mmc_host *mmc)
1700 {
1701         struct sdhci_host *host = mmc_priv(mmc);
1702
1703         if (host->ops && host->ops->hw_reset)
1704                 host->ops->hw_reset(host);
1705 }
1706
1707 static int sdhci_get_ro(struct mmc_host *mmc)
1708 {
1709         struct sdhci_host *host = mmc_priv(mmc);
1710         int ret;
1711
1712         sdhci_runtime_pm_get(host);
1713         ret = sdhci_do_get_ro(host);
1714         sdhci_runtime_pm_put(host);
1715         return ret;
1716 }
1717
1718 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1719 {
1720         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1721                 if (enable)
1722                         host->ier |= SDHCI_INT_CARD_INT;
1723                 else
1724                         host->ier &= ~SDHCI_INT_CARD_INT;
1725
1726                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1727                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1728                 mmiowb();
1729         }
1730 }
1731
1732 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1733 {
1734         struct sdhci_host *host = mmc_priv(mmc);
1735         unsigned long flags;
1736
1737         sdhci_runtime_pm_get(host);
1738
1739         spin_lock_irqsave(&host->lock, flags);
1740         if (enable)
1741                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1742         else
1743                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1744
1745         sdhci_enable_sdio_irq_nolock(host, enable);
1746         spin_unlock_irqrestore(&host->lock, flags);
1747
1748         sdhci_runtime_pm_put(host);
1749 }
1750
1751 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1752                                                 struct mmc_ios *ios)
1753 {
1754         struct mmc_host *mmc = host->mmc;
1755         u16 ctrl;
1756         int ret;
1757
1758         /*
1759          * Signal Voltage Switching is only applicable for Host Controllers
1760          * v3.00 and above.
1761          */
1762         if (host->version < SDHCI_SPEC_300)
1763                 return 0;
1764
1765         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1766
1767         switch (ios->signal_voltage) {
1768         case MMC_SIGNAL_VOLTAGE_330:
1769                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1770                 ctrl &= ~SDHCI_CTRL_VDD_180;
1771                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1772
1773                 if (!IS_ERR(mmc->supply.vqmmc)) {
1774                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1775                                                     3600000);
1776                         if (ret) {
1777                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1778                                         mmc_hostname(mmc));
1779                                 return -EIO;
1780                         }
1781                 }
1782                 /* Wait for 5ms */
1783                 usleep_range(5000, 5500);
1784
1785                 /* 3.3V regulator output should be stable within 5 ms */
1786                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1787                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1788                         return 0;
1789
1790                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1791                         mmc_hostname(mmc));
1792
1793                 return -EAGAIN;
1794         case MMC_SIGNAL_VOLTAGE_180:
1795                 if (!IS_ERR(mmc->supply.vqmmc)) {
1796                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1797                                         1700000, 1950000);
1798                         if (ret) {
1799                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1800                                         mmc_hostname(mmc));
1801                                 return -EIO;
1802                         }
1803                 }
1804
1805                 /*
1806                  * Enable 1.8V Signal Enable in the Host Control2
1807                  * register
1808                  */
1809                 ctrl |= SDHCI_CTRL_VDD_180;
1810                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1811
1812                 /* Some controller need to do more when switching */
1813                 if (host->ops->voltage_switch)
1814                         host->ops->voltage_switch(host);
1815
1816                 /* 1.8V regulator output should be stable within 5 ms */
1817                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1818                 if (ctrl & SDHCI_CTRL_VDD_180)
1819                         return 0;
1820
1821                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1822                         mmc_hostname(mmc));
1823
1824                 return -EAGAIN;
1825         case MMC_SIGNAL_VOLTAGE_120:
1826                 if (!IS_ERR(mmc->supply.vqmmc)) {
1827                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1828                                                     1300000);
1829                         if (ret) {
1830                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1831                                         mmc_hostname(mmc));
1832                                 return -EIO;
1833                         }
1834                 }
1835                 return 0;
1836         default:
1837                 /* No signal voltage switch required */
1838                 return 0;
1839         }
1840 }
1841
1842 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1843         struct mmc_ios *ios)
1844 {
1845         struct sdhci_host *host = mmc_priv(mmc);
1846         int err;
1847
1848         if (host->version < SDHCI_SPEC_300)
1849                 return 0;
1850         sdhci_runtime_pm_get(host);
1851         err = sdhci_do_start_signal_voltage_switch(host, ios);
1852         sdhci_runtime_pm_put(host);
1853         return err;
1854 }
1855
1856 static int sdhci_card_busy(struct mmc_host *mmc)
1857 {
1858         struct sdhci_host *host = mmc_priv(mmc);
1859         u32 present_state;
1860
1861         sdhci_runtime_pm_get(host);
1862         /* Check whether DAT[3:0] is 0000 */
1863         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1864         sdhci_runtime_pm_put(host);
1865
1866         return !(present_state & SDHCI_DATA_LVL_MASK);
1867 }
1868
1869 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1870 {
1871         struct sdhci_host *host = mmc_priv(mmc);
1872         unsigned long flags;
1873
1874         spin_lock_irqsave(&host->lock, flags);
1875         host->flags |= SDHCI_HS400_TUNING;
1876         spin_unlock_irqrestore(&host->lock, flags);
1877
1878         return 0;
1879 }
1880
1881 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1882 {
1883         struct sdhci_host *host = mmc_priv(mmc);
1884         u16 ctrl;
1885         int tuning_loop_counter = MAX_TUNING_LOOP;
1886         int err = 0;
1887         unsigned long flags;
1888         unsigned int tuning_count = 0;
1889         bool hs400_tuning;
1890
1891         sdhci_runtime_pm_get(host);
1892         spin_lock_irqsave(&host->lock, flags);
1893
1894         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1895         host->flags &= ~SDHCI_HS400_TUNING;
1896
1897         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1898                 tuning_count = host->tuning_count;
1899
1900         /*
1901          * The Host Controller needs tuning in case of SDR104 and DDR50
1902          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1903          * the Capabilities register.
1904          * If the Host Controller supports the HS200 mode then the
1905          * tuning function has to be executed.
1906          */
1907         switch (host->timing) {
1908         /* HS400 tuning is done in HS200 mode */
1909         case MMC_TIMING_MMC_HS400:
1910                 err = -EINVAL;
1911                 goto out_unlock;
1912
1913         case MMC_TIMING_MMC_HS200:
1914                 /*
1915                  * Periodic re-tuning for HS400 is not expected to be needed, so
1916                  * disable it here.
1917                  */
1918                 if (hs400_tuning)
1919                         tuning_count = 0;
1920                 break;
1921
1922         case MMC_TIMING_UHS_SDR104:
1923         case MMC_TIMING_UHS_DDR50:
1924                 break;
1925
1926         case MMC_TIMING_UHS_SDR50:
1927                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1928                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1929                         break;
1930                 /* FALLTHROUGH */
1931
1932         default:
1933                 goto out_unlock;
1934         }
1935
1936         if (host->ops->platform_execute_tuning) {
1937                 spin_unlock_irqrestore(&host->lock, flags);
1938                 err = host->ops->platform_execute_tuning(host, opcode);
1939                 sdhci_runtime_pm_put(host);
1940                 return err;
1941         }
1942
1943         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1944         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1945         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1946                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1947         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1948
1949         /*
1950          * As per the Host Controller spec v3.00, tuning command
1951          * generates Buffer Read Ready interrupt, so enable that.
1952          *
1953          * Note: The spec clearly says that when tuning sequence
1954          * is being performed, the controller does not generate
1955          * interrupts other than Buffer Read Ready interrupt. But
1956          * to make sure we don't hit a controller bug, we _only_
1957          * enable Buffer Read Ready interrupt here.
1958          */
1959         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1960         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1961
1962         /*
1963          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1964          * of loops reaches 40 times or a timeout of 150ms occurs.
1965          */
1966         do {
1967                 struct mmc_command cmd = {0};
1968                 struct mmc_request mrq = {NULL};
1969
1970                 cmd.opcode = opcode;
1971                 cmd.arg = 0;
1972                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1973                 cmd.retries = 0;
1974                 cmd.data = NULL;
1975                 cmd.error = 0;
1976
1977                 if (tuning_loop_counter-- == 0)
1978                         break;
1979
1980                 mrq.cmd = &cmd;
1981                 host->mrq = &mrq;
1982
1983                 /*
1984                  * In response to CMD19, the card sends 64 bytes of tuning
1985                  * block to the Host Controller. So we set the block size
1986                  * to 64 here.
1987                  */
1988                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1989                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1990                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1991                                              SDHCI_BLOCK_SIZE);
1992                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1993                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1994                                              SDHCI_BLOCK_SIZE);
1995                 } else {
1996                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1997                                      SDHCI_BLOCK_SIZE);
1998                 }
1999
2000                 /*
2001                  * The tuning block is sent by the card to the host controller.
2002                  * So we set the TRNS_READ bit in the Transfer Mode register.
2003                  * This also takes care of setting DMA Enable and Multi Block
2004                  * Select in the same register to 0.
2005                  */
2006                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2007
2008                 sdhci_send_command(host, &cmd);
2009
2010                 host->cmd = NULL;
2011                 host->mrq = NULL;
2012
2013                 spin_unlock_irqrestore(&host->lock, flags);
2014                 /* Wait for Buffer Read Ready interrupt */
2015                 wait_event_interruptible_timeout(host->buf_ready_int,
2016                                         (host->tuning_done == 1),
2017                                         msecs_to_jiffies(50));
2018                 spin_lock_irqsave(&host->lock, flags);
2019
2020                 if (!host->tuning_done) {
2021                         pr_info(DRIVER_NAME ": Timeout waiting for "
2022                                 "Buffer Read Ready interrupt during tuning "
2023                                 "procedure, falling back to fixed sampling "
2024                                 "clock\n");
2025                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2026                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2027                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2028                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2029
2030                         err = -EIO;
2031                         goto out;
2032                 }
2033
2034                 host->tuning_done = 0;
2035
2036                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2037
2038                 /* eMMC spec does not require a delay between tuning cycles */
2039                 if (opcode == MMC_SEND_TUNING_BLOCK)
2040                         mdelay(1);
2041         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2042
2043         /*
2044          * The Host Driver has exhausted the maximum number of loops allowed,
2045          * so use fixed sampling frequency.
2046          */
2047         if (tuning_loop_counter < 0) {
2048                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2049                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2050         }
2051         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2052                 pr_info(DRIVER_NAME ": Tuning procedure"
2053                         " failed, falling back to fixed sampling"
2054                         " clock\n");
2055                 err = -EIO;
2056         }
2057
2058 out:
2059         if (tuning_count) {
2060                 /*
2061                  * In case tuning fails, host controllers which support
2062                  * re-tuning can try tuning again at a later time, when the
2063                  * re-tuning timer expires.  So for these controllers, we
2064                  * return 0. Since there might be other controllers who do not
2065                  * have this capability, we return error for them.
2066                  */
2067                 err = 0;
2068         }
2069
2070         host->mmc->retune_period = err ? 0 : tuning_count;
2071
2072         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2073         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2074 out_unlock:
2075         spin_unlock_irqrestore(&host->lock, flags);
2076         sdhci_runtime_pm_put(host);
2077
2078         return err;
2079 }
2080
2081 static int sdhci_select_drive_strength(struct mmc_card *card,
2082                                        unsigned int max_dtr, int host_drv,
2083                                        int card_drv, int *drv_type)
2084 {
2085         struct sdhci_host *host = mmc_priv(card->host);
2086
2087         if (!host->ops->select_drive_strength)
2088                 return 0;
2089
2090         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2091                                                 card_drv, drv_type);
2092 }
2093
2094 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2095 {
2096         /* Host Controller v3.00 defines preset value registers */
2097         if (host->version < SDHCI_SPEC_300)
2098                 return;
2099
2100         /*
2101          * We only enable or disable Preset Value if they are not already
2102          * enabled or disabled respectively. Otherwise, we bail out.
2103          */
2104         if (host->preset_enabled != enable) {
2105                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2106
2107                 if (enable)
2108                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2109                 else
2110                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2111
2112                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2113
2114                 if (enable)
2115                         host->flags |= SDHCI_PV_ENABLED;
2116                 else
2117                         host->flags &= ~SDHCI_PV_ENABLED;
2118
2119                 host->preset_enabled = enable;
2120         }
2121 }
2122
2123 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2124                                 int err)
2125 {
2126         struct sdhci_host *host = mmc_priv(mmc);
2127         struct mmc_data *data = mrq->data;
2128
2129         if (host->flags & SDHCI_REQ_USE_DMA) {
2130                 if (data->host_cookie == COOKIE_GIVEN ||
2131                                 data->host_cookie == COOKIE_MAPPED)
2132                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2133                                          data->flags & MMC_DATA_WRITE ?
2134                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2135                 data->host_cookie = COOKIE_UNMAPPED;
2136         }
2137 }
2138
2139 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2140                                        struct mmc_data *data)
2141 {
2142         int sg_count;
2143
2144         if (data->host_cookie == COOKIE_MAPPED) {
2145                 data->host_cookie = COOKIE_GIVEN;
2146                 return data->sg_count;
2147         }
2148
2149         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2150
2151         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2152                                 data->flags & MMC_DATA_WRITE ?
2153                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2154
2155         if (sg_count == 0)
2156                 return -ENOSPC;
2157
2158         data->sg_count = sg_count;
2159         data->host_cookie = COOKIE_MAPPED;
2160
2161         return sg_count;
2162 }
2163
2164 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2165                                bool is_first_req)
2166 {
2167         struct sdhci_host *host = mmc_priv(mmc);
2168
2169         mrq->data->host_cookie = COOKIE_UNMAPPED;
2170
2171         if (host->flags & SDHCI_REQ_USE_DMA)
2172                 sdhci_pre_dma_transfer(host, mrq->data);
2173 }
2174
2175 static void sdhci_card_event(struct mmc_host *mmc)
2176 {
2177         struct sdhci_host *host = mmc_priv(mmc);
2178         unsigned long flags;
2179         int present;
2180
2181         /* First check if client has provided their own card event */
2182         if (host->ops->card_event)
2183                 host->ops->card_event(host);
2184
2185         present = sdhci_do_get_cd(host);
2186
2187         spin_lock_irqsave(&host->lock, flags);
2188
2189         /* Check host->mrq first in case we are runtime suspended */
2190         if (host->mrq && !present) {
2191                 pr_err("%s: Card removed during transfer!\n",
2192                         mmc_hostname(host->mmc));
2193                 pr_err("%s: Resetting controller.\n",
2194                         mmc_hostname(host->mmc));
2195
2196                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2197                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2198
2199                 host->mrq->cmd->error = -ENOMEDIUM;
2200                 tasklet_schedule(&host->finish_tasklet);
2201         }
2202
2203         spin_unlock_irqrestore(&host->lock, flags);
2204 }
2205
2206 static const struct mmc_host_ops sdhci_ops = {
2207         .request        = sdhci_request,
2208         .post_req       = sdhci_post_req,
2209         .pre_req        = sdhci_pre_req,
2210         .set_ios        = sdhci_set_ios,
2211         .get_cd         = sdhci_get_cd,
2212         .get_ro         = sdhci_get_ro,
2213         .hw_reset       = sdhci_hw_reset,
2214         .enable_sdio_irq = sdhci_enable_sdio_irq,
2215         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2216         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2217         .execute_tuning                 = sdhci_execute_tuning,
2218         .select_drive_strength          = sdhci_select_drive_strength,
2219         .card_event                     = sdhci_card_event,
2220         .card_busy      = sdhci_card_busy,
2221 };
2222
2223 /*****************************************************************************\
2224  *                                                                           *
2225  * Tasklets                                                                  *
2226  *                                                                           *
2227 \*****************************************************************************/
2228
2229 static void sdhci_tasklet_finish(unsigned long param)
2230 {
2231         struct sdhci_host *host;
2232         unsigned long flags;
2233         struct mmc_request *mrq;
2234
2235         host = (struct sdhci_host*)param;
2236
2237         spin_lock_irqsave(&host->lock, flags);
2238
2239         /*
2240          * If this tasklet gets rescheduled while running, it will
2241          * be run again afterwards but without any active request.
2242          */
2243         if (!host->mrq) {
2244                 spin_unlock_irqrestore(&host->lock, flags);
2245                 return;
2246         }
2247
2248         del_timer(&host->timer);
2249
2250         mrq = host->mrq;
2251
2252         /*
2253          * The controller needs a reset of internal state machines
2254          * upon error conditions.
2255          */
2256         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2257             ((mrq->cmd && mrq->cmd->error) ||
2258              (mrq->sbc && mrq->sbc->error) ||
2259              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2260                             (mrq->data->stop && mrq->data->stop->error))) ||
2261              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2262
2263                 /* Some controllers need this kick or reset won't work here */
2264                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2265                         /* This is to force an update */
2266                         host->ops->set_clock(host, host->clock);
2267
2268                 /* Spec says we should do both at the same time, but Ricoh
2269                    controllers do not like that. */
2270                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2271                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2272         }
2273
2274         host->mrq = NULL;
2275         host->cmd = NULL;
2276         host->data = NULL;
2277
2278 #ifndef SDHCI_USE_LEDS_CLASS
2279         sdhci_deactivate_led(host);
2280 #endif
2281
2282         mmiowb();
2283         spin_unlock_irqrestore(&host->lock, flags);
2284
2285         mmc_request_done(host->mmc, mrq);
2286         sdhci_runtime_pm_put(host);
2287 }
2288
2289 static void sdhci_timeout_timer(unsigned long data)
2290 {
2291         struct sdhci_host *host;
2292         unsigned long flags;
2293
2294         host = (struct sdhci_host*)data;
2295
2296         spin_lock_irqsave(&host->lock, flags);
2297
2298         if (host->mrq) {
2299                 pr_err("%s: Timeout waiting for hardware "
2300                         "interrupt.\n", mmc_hostname(host->mmc));
2301                 sdhci_dumpregs(host);
2302
2303                 if (host->data) {
2304                         host->data->error = -ETIMEDOUT;
2305                         sdhci_finish_data(host);
2306                 } else {
2307                         if (host->cmd)
2308                                 host->cmd->error = -ETIMEDOUT;
2309                         else
2310                                 host->mrq->cmd->error = -ETIMEDOUT;
2311
2312                         tasklet_schedule(&host->finish_tasklet);
2313                 }
2314         }
2315
2316         mmiowb();
2317         spin_unlock_irqrestore(&host->lock, flags);
2318 }
2319
2320 /*****************************************************************************\
2321  *                                                                           *
2322  * Interrupt handling                                                        *
2323  *                                                                           *
2324 \*****************************************************************************/
2325
2326 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2327 {
2328         BUG_ON(intmask == 0);
2329
2330         if (!host->cmd) {
2331                 pr_err("%s: Got command interrupt 0x%08x even "
2332                         "though no command operation was in progress.\n",
2333                         mmc_hostname(host->mmc), (unsigned)intmask);
2334                 sdhci_dumpregs(host);
2335                 return;
2336         }
2337
2338         if (intmask & SDHCI_INT_TIMEOUT)
2339                 host->cmd->error = -ETIMEDOUT;
2340         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2341                         SDHCI_INT_INDEX))
2342                 host->cmd->error = -EILSEQ;
2343
2344         if (host->cmd->error) {
2345                 tasklet_schedule(&host->finish_tasklet);
2346                 return;
2347         }
2348
2349         /*
2350          * The host can send and interrupt when the busy state has
2351          * ended, allowing us to wait without wasting CPU cycles.
2352          * Unfortunately this is overloaded on the "data complete"
2353          * interrupt, so we need to take some care when handling
2354          * it.
2355          *
2356          * Note: The 1.0 specification is a bit ambiguous about this
2357          *       feature so there might be some problems with older
2358          *       controllers.
2359          */
2360         if (host->cmd->flags & MMC_RSP_BUSY) {
2361                 if (host->cmd->data)
2362                         DBG("Cannot wait for busy signal when also "
2363                                 "doing a data transfer");
2364                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2365                                 && !host->busy_handle) {
2366                         /* Mark that command complete before busy is ended */
2367                         host->busy_handle = 1;
2368                         return;
2369                 }
2370
2371                 /* The controller does not support the end-of-busy IRQ,
2372                  * fall through and take the SDHCI_INT_RESPONSE */
2373         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2374                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2375                 *mask &= ~SDHCI_INT_DATA_END;
2376         }
2377
2378         if (intmask & SDHCI_INT_RESPONSE)
2379                 sdhci_finish_command(host);
2380 }
2381
2382 #ifdef CONFIG_MMC_DEBUG
2383 static void sdhci_adma_show_error(struct sdhci_host *host)
2384 {
2385         const char *name = mmc_hostname(host->mmc);
2386         void *desc = host->adma_table;
2387
2388         sdhci_dumpregs(host);
2389
2390         while (true) {
2391                 struct sdhci_adma2_64_desc *dma_desc = desc;
2392
2393                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2394                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2395                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2396                             le32_to_cpu(dma_desc->addr_lo),
2397                             le16_to_cpu(dma_desc->len),
2398                             le16_to_cpu(dma_desc->cmd));
2399                 else
2400                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2401                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2402                             le16_to_cpu(dma_desc->len),
2403                             le16_to_cpu(dma_desc->cmd));
2404
2405                 desc += host->desc_sz;
2406
2407                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2408                         break;
2409         }
2410 }
2411 #else
2412 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2413 #endif
2414
2415 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2416 {
2417         u32 command;
2418         BUG_ON(intmask == 0);
2419
2420         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2421         if (intmask & SDHCI_INT_DATA_AVAIL) {
2422                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2423                 if (command == MMC_SEND_TUNING_BLOCK ||
2424                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2425                         host->tuning_done = 1;
2426                         wake_up(&host->buf_ready_int);
2427                         return;
2428                 }
2429         }
2430
2431         if (!host->data) {
2432                 /*
2433                  * The "data complete" interrupt is also used to
2434                  * indicate that a busy state has ended. See comment
2435                  * above in sdhci_cmd_irq().
2436                  */
2437                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2438                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2439                                 host->cmd->error = -ETIMEDOUT;
2440                                 tasklet_schedule(&host->finish_tasklet);
2441                                 return;
2442                         }
2443                         if (intmask & SDHCI_INT_DATA_END) {
2444                                 /*
2445                                  * Some cards handle busy-end interrupt
2446                                  * before the command completed, so make
2447                                  * sure we do things in the proper order.
2448                                  */
2449                                 if (host->busy_handle)
2450                                         sdhci_finish_command(host);
2451                                 else
2452                                         host->busy_handle = 1;
2453                                 return;
2454                         }
2455                 }
2456
2457                 pr_err("%s: Got data interrupt 0x%08x even "
2458                         "though no data operation was in progress.\n",
2459                         mmc_hostname(host->mmc), (unsigned)intmask);
2460                 sdhci_dumpregs(host);
2461
2462                 return;
2463         }
2464
2465         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2466                 host->data->error = -ETIMEDOUT;
2467         else if (intmask & SDHCI_INT_DATA_END_BIT)
2468                 host->data->error = -EILSEQ;
2469         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2470                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2471                         != MMC_BUS_TEST_R)
2472                 host->data->error = -EILSEQ;
2473         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2474                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2475                 sdhci_adma_show_error(host);
2476                 host->data->error = -EIO;
2477                 if (host->ops->adma_workaround)
2478                         host->ops->adma_workaround(host, intmask);
2479         }
2480
2481         if (host->data->error)
2482                 sdhci_finish_data(host);
2483         else {
2484                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2485                         sdhci_transfer_pio(host);
2486
2487                 /*
2488                  * We currently don't do anything fancy with DMA
2489                  * boundaries, but as we can't disable the feature
2490                  * we need to at least restart the transfer.
2491                  *
2492                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2493                  * should return a valid address to continue from, but as
2494                  * some controllers are faulty, don't trust them.
2495                  */
2496                 if (intmask & SDHCI_INT_DMA_END) {
2497                         u32 dmastart, dmanow;
2498                         dmastart = sg_dma_address(host->data->sg);
2499                         dmanow = dmastart + host->data->bytes_xfered;
2500                         /*
2501                          * Force update to the next DMA block boundary.
2502                          */
2503                         dmanow = (dmanow &
2504                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2505                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2506                         host->data->bytes_xfered = dmanow - dmastart;
2507                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2508                                 " next 0x%08x\n",
2509                                 mmc_hostname(host->mmc), dmastart,
2510                                 host->data->bytes_xfered, dmanow);
2511                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2512                 }
2513
2514                 if (intmask & SDHCI_INT_DATA_END) {
2515                         if (host->cmd) {
2516                                 /*
2517                                  * Data managed to finish before the
2518                                  * command completed. Make sure we do
2519                                  * things in the proper order.
2520                                  */
2521                                 host->data_early = 1;
2522                         } else {
2523                                 sdhci_finish_data(host);
2524                         }
2525                 }
2526         }
2527 }
2528
2529 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2530 {
2531         irqreturn_t result = IRQ_NONE;
2532         struct sdhci_host *host = dev_id;
2533         u32 intmask, mask, unexpected = 0;
2534         int max_loops = 16;
2535
2536         spin_lock(&host->lock);
2537
2538         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2539                 spin_unlock(&host->lock);
2540                 return IRQ_NONE;
2541         }
2542
2543         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2544         if (!intmask || intmask == 0xffffffff) {
2545                 result = IRQ_NONE;
2546                 goto out;
2547         }
2548
2549         do {
2550                 /* Clear selected interrupts. */
2551                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2552                                   SDHCI_INT_BUS_POWER);
2553                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2554
2555                 DBG("*** %s got interrupt: 0x%08x\n",
2556                         mmc_hostname(host->mmc), intmask);
2557
2558                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2559                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2560                                       SDHCI_CARD_PRESENT;
2561
2562                         /*
2563                          * There is a observation on i.mx esdhc.  INSERT
2564                          * bit will be immediately set again when it gets
2565                          * cleared, if a card is inserted.  We have to mask
2566                          * the irq to prevent interrupt storm which will
2567                          * freeze the system.  And the REMOVE gets the
2568                          * same situation.
2569                          *
2570                          * More testing are needed here to ensure it works
2571                          * for other platforms though.
2572                          */
2573                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2574                                        SDHCI_INT_CARD_REMOVE);
2575                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2576                                                SDHCI_INT_CARD_INSERT;
2577                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2578                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2579
2580                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2581                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2582
2583                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2584                                                        SDHCI_INT_CARD_REMOVE);
2585                         result = IRQ_WAKE_THREAD;
2586                 }
2587
2588                 if (intmask & SDHCI_INT_CMD_MASK)
2589                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2590                                       &intmask);
2591
2592                 if (intmask & SDHCI_INT_DATA_MASK)
2593                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2594
2595                 if (intmask & SDHCI_INT_BUS_POWER)
2596                         pr_err("%s: Card is consuming too much power!\n",
2597                                 mmc_hostname(host->mmc));
2598
2599                 if (intmask & SDHCI_INT_CARD_INT) {
2600                         sdhci_enable_sdio_irq_nolock(host, false);
2601                         host->thread_isr |= SDHCI_INT_CARD_INT;
2602                         result = IRQ_WAKE_THREAD;
2603                 }
2604
2605                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2606                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2607                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2608                              SDHCI_INT_CARD_INT);
2609
2610                 if (intmask) {
2611                         unexpected |= intmask;
2612                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2613                 }
2614
2615                 if (result == IRQ_NONE)
2616                         result = IRQ_HANDLED;
2617
2618                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2619         } while (intmask && --max_loops);
2620 out:
2621         spin_unlock(&host->lock);
2622
2623         if (unexpected) {
2624                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2625                            mmc_hostname(host->mmc), unexpected);
2626                 sdhci_dumpregs(host);
2627         }
2628
2629         return result;
2630 }
2631
2632 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2633 {
2634         struct sdhci_host *host = dev_id;
2635         unsigned long flags;
2636         u32 isr;
2637
2638         spin_lock_irqsave(&host->lock, flags);
2639         isr = host->thread_isr;
2640         host->thread_isr = 0;
2641         spin_unlock_irqrestore(&host->lock, flags);
2642
2643         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2644                 sdhci_card_event(host->mmc);
2645                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2646         }
2647
2648         if (isr & SDHCI_INT_CARD_INT) {
2649                 sdio_run_irqs(host->mmc);
2650
2651                 spin_lock_irqsave(&host->lock, flags);
2652                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2653                         sdhci_enable_sdio_irq_nolock(host, true);
2654                 spin_unlock_irqrestore(&host->lock, flags);
2655         }
2656
2657         return isr ? IRQ_HANDLED : IRQ_NONE;
2658 }
2659
2660 /*****************************************************************************\
2661  *                                                                           *
2662  * Suspend/resume                                                            *
2663  *                                                                           *
2664 \*****************************************************************************/
2665
2666 #ifdef CONFIG_PM
2667 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2668 {
2669         u8 val;
2670         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2671                         | SDHCI_WAKE_ON_INT;
2672
2673         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2674         val |= mask ;
2675         /* Avoid fake wake up */
2676         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2677                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2678         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2679 }
2680 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2681
2682 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2683 {
2684         u8 val;
2685         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2686                         | SDHCI_WAKE_ON_INT;
2687
2688         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2689         val &= ~mask;
2690         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2691 }
2692
2693 int sdhci_suspend_host(struct sdhci_host *host)
2694 {
2695         sdhci_disable_card_detection(host);
2696
2697         mmc_retune_timer_stop(host->mmc);
2698         mmc_retune_needed(host->mmc);
2699
2700         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2701                 host->ier = 0;
2702                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2703                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2704                 free_irq(host->irq, host);
2705         } else {
2706                 sdhci_enable_irq_wakeups(host);
2707                 enable_irq_wake(host->irq);
2708         }
2709         return 0;
2710 }
2711
2712 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2713
2714 int sdhci_resume_host(struct sdhci_host *host)
2715 {
2716         int ret = 0;
2717
2718         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2719                 if (host->ops->enable_dma)
2720                         host->ops->enable_dma(host);
2721         }
2722
2723         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2724             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2725                 /* Card keeps power but host controller does not */
2726                 sdhci_init(host, 0);
2727                 host->pwr = 0;
2728                 host->clock = 0;
2729                 sdhci_do_set_ios(host, &host->mmc->ios);
2730         } else {
2731                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2732                 mmiowb();
2733         }
2734
2735         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2736                 ret = request_threaded_irq(host->irq, sdhci_irq,
2737                                            sdhci_thread_irq, IRQF_SHARED,
2738                                            mmc_hostname(host->mmc), host);
2739                 if (ret)
2740                         return ret;
2741         } else {
2742                 sdhci_disable_irq_wakeups(host);
2743                 disable_irq_wake(host->irq);
2744         }
2745
2746         sdhci_enable_card_detection(host);
2747
2748         return ret;
2749 }
2750
2751 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2752
2753 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2754 {
2755         return pm_runtime_get_sync(host->mmc->parent);
2756 }
2757
2758 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2759 {
2760         pm_runtime_mark_last_busy(host->mmc->parent);
2761         return pm_runtime_put_autosuspend(host->mmc->parent);
2762 }
2763
2764 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2765 {
2766         if (host->bus_on)
2767                 return;
2768         host->bus_on = true;
2769         pm_runtime_get_noresume(host->mmc->parent);
2770 }
2771
2772 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2773 {
2774         if (!host->bus_on)
2775                 return;
2776         host->bus_on = false;
2777         pm_runtime_put_noidle(host->mmc->parent);
2778 }
2779
2780 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2781 {
2782         unsigned long flags;
2783
2784         mmc_retune_timer_stop(host->mmc);
2785         mmc_retune_needed(host->mmc);
2786
2787         spin_lock_irqsave(&host->lock, flags);
2788         host->ier &= SDHCI_INT_CARD_INT;
2789         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2790         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2791         spin_unlock_irqrestore(&host->lock, flags);
2792
2793         synchronize_hardirq(host->irq);
2794
2795         spin_lock_irqsave(&host->lock, flags);
2796         host->runtime_suspended = true;
2797         spin_unlock_irqrestore(&host->lock, flags);
2798
2799         return 0;
2800 }
2801 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2802
2803 int sdhci_runtime_resume_host(struct sdhci_host *host)
2804 {
2805         unsigned long flags;
2806         int host_flags = host->flags;
2807
2808         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2809                 if (host->ops->enable_dma)
2810                         host->ops->enable_dma(host);
2811         }
2812
2813         sdhci_init(host, 0);
2814
2815         /* Force clock and power re-program */
2816         host->pwr = 0;
2817         host->clock = 0;
2818         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2819         sdhci_do_set_ios(host, &host->mmc->ios);
2820
2821         if ((host_flags & SDHCI_PV_ENABLED) &&
2822                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2823                 spin_lock_irqsave(&host->lock, flags);
2824                 sdhci_enable_preset_value(host, true);
2825                 spin_unlock_irqrestore(&host->lock, flags);
2826         }
2827
2828         spin_lock_irqsave(&host->lock, flags);
2829
2830         host->runtime_suspended = false;
2831
2832         /* Enable SDIO IRQ */
2833         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2834                 sdhci_enable_sdio_irq_nolock(host, true);
2835
2836         /* Enable Card Detection */
2837         sdhci_enable_card_detection(host);
2838
2839         spin_unlock_irqrestore(&host->lock, flags);
2840
2841         return 0;
2842 }
2843 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2844
2845 #endif /* CONFIG_PM */
2846
2847 /*****************************************************************************\
2848  *                                                                           *
2849  * Device allocation/registration                                            *
2850  *                                                                           *
2851 \*****************************************************************************/
2852
2853 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2854         size_t priv_size)
2855 {
2856         struct mmc_host *mmc;
2857         struct sdhci_host *host;
2858
2859         WARN_ON(dev == NULL);
2860
2861         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2862         if (!mmc)
2863                 return ERR_PTR(-ENOMEM);
2864
2865         host = mmc_priv(mmc);
2866         host->mmc = mmc;
2867         host->mmc_host_ops = sdhci_ops;
2868         mmc->ops = &host->mmc_host_ops;
2869
2870         return host;
2871 }
2872
2873 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2874
2875 int sdhci_add_host(struct sdhci_host *host)
2876 {
2877         struct mmc_host *mmc;
2878         u32 caps[2] = {0, 0};
2879         u32 max_current_caps;
2880         unsigned int ocr_avail;
2881         unsigned int override_timeout_clk;
2882         u32 max_clk;
2883         int ret;
2884
2885         WARN_ON(host == NULL);
2886         if (host == NULL)
2887                 return -EINVAL;
2888
2889         mmc = host->mmc;
2890
2891         if (debug_quirks)
2892                 host->quirks = debug_quirks;
2893         if (debug_quirks2)
2894                 host->quirks2 = debug_quirks2;
2895
2896         override_timeout_clk = host->timeout_clk;
2897
2898         sdhci_do_reset(host, SDHCI_RESET_ALL);
2899
2900         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2901         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2902                                 >> SDHCI_SPEC_VER_SHIFT;
2903         if (host->version > SDHCI_SPEC_300) {
2904                 pr_err("%s: Unknown controller version (%d). "
2905                         "You may experience problems.\n", mmc_hostname(mmc),
2906                         host->version);
2907         }
2908
2909         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2910                 sdhci_readl(host, SDHCI_CAPABILITIES);
2911
2912         if (host->version >= SDHCI_SPEC_300)
2913                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2914                         host->caps1 :
2915                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2916
2917         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2918                 host->flags |= SDHCI_USE_SDMA;
2919         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2920                 DBG("Controller doesn't have SDMA capability\n");
2921         else
2922                 host->flags |= SDHCI_USE_SDMA;
2923
2924         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2925                 (host->flags & SDHCI_USE_SDMA)) {
2926                 DBG("Disabling DMA as it is marked broken\n");
2927                 host->flags &= ~SDHCI_USE_SDMA;
2928         }
2929
2930         if ((host->version >= SDHCI_SPEC_200) &&
2931                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2932                 host->flags |= SDHCI_USE_ADMA;
2933
2934         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2935                 (host->flags & SDHCI_USE_ADMA)) {
2936                 DBG("Disabling ADMA as it is marked broken\n");
2937                 host->flags &= ~SDHCI_USE_ADMA;
2938         }
2939
2940         /*
2941          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2942          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2943          * that during the first call to ->enable_dma().  Similarly
2944          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2945          * implement.
2946          */
2947         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2948                 host->flags |= SDHCI_USE_64_BIT_DMA;
2949
2950         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2951                 if (host->ops->enable_dma) {
2952                         if (host->ops->enable_dma(host)) {
2953                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2954                                         mmc_hostname(mmc));
2955                                 host->flags &=
2956                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2957                         }
2958                 }
2959         }
2960
2961         /* SDMA does not support 64-bit DMA */
2962         if (host->flags & SDHCI_USE_64_BIT_DMA)
2963                 host->flags &= ~SDHCI_USE_SDMA;
2964
2965         if (host->flags & SDHCI_USE_ADMA) {
2966                 /*
2967                  * The DMA descriptor table size is calculated as the maximum
2968                  * number of segments times 2, to allow for an alignment
2969                  * descriptor for each segment, plus 1 for a nop end descriptor,
2970                  * all multipled by the descriptor size.
2971                  */
2972                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2973                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2974                                               SDHCI_ADMA2_64_DESC_SZ;
2975                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2976                                                 SDHCI_ADMA2_64_ALIGN;
2977                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2978                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2979                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2980                 } else {
2981                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2982                                               SDHCI_ADMA2_32_DESC_SZ;
2983                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2984                                                 SDHCI_ADMA2_32_ALIGN;
2985                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2986                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2987                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2988                 }
2989                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2990                                                       host->adma_table_sz,
2991                                                       &host->adma_addr,
2992                                                       GFP_KERNEL);
2993                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2994                 if (!host->adma_table || !host->align_buffer) {
2995                         if (host->adma_table)
2996                                 dma_free_coherent(mmc_dev(mmc),
2997                                                   host->adma_table_sz,
2998                                                   host->adma_table,
2999                                                   host->adma_addr);
3000                         kfree(host->align_buffer);
3001                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3002                                 mmc_hostname(mmc));
3003                         host->flags &= ~SDHCI_USE_ADMA;
3004                         host->adma_table = NULL;
3005                         host->align_buffer = NULL;
3006                 } else if (host->adma_addr & host->align_mask) {
3007                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3008                                 mmc_hostname(mmc));
3009                         host->flags &= ~SDHCI_USE_ADMA;
3010                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3011                                           host->adma_table, host->adma_addr);
3012                         kfree(host->align_buffer);
3013                         host->adma_table = NULL;
3014                         host->align_buffer = NULL;
3015                 }
3016         }
3017
3018         /*
3019          * If we use DMA, then it's up to the caller to set the DMA
3020          * mask, but PIO does not need the hw shim so we set a new
3021          * mask here in that case.
3022          */
3023         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3024                 host->dma_mask = DMA_BIT_MASK(64);
3025                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3026         }
3027
3028         if (host->version >= SDHCI_SPEC_300)
3029                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3030                         >> SDHCI_CLOCK_BASE_SHIFT;
3031         else
3032                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3033                         >> SDHCI_CLOCK_BASE_SHIFT;
3034
3035         host->max_clk *= 1000000;
3036         if (host->max_clk == 0 || host->quirks &
3037                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3038                 if (!host->ops->get_max_clock) {
3039                         pr_err("%s: Hardware doesn't specify base clock "
3040                                "frequency.\n", mmc_hostname(mmc));
3041                         return -ENODEV;
3042                 }
3043                 host->max_clk = host->ops->get_max_clock(host);
3044         }
3045
3046         /*
3047          * In case of Host Controller v3.00, find out whether clock
3048          * multiplier is supported.
3049          */
3050         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3051                         SDHCI_CLOCK_MUL_SHIFT;
3052
3053         /*
3054          * In case the value in Clock Multiplier is 0, then programmable
3055          * clock mode is not supported, otherwise the actual clock
3056          * multiplier is one more than the value of Clock Multiplier
3057          * in the Capabilities Register.
3058          */
3059         if (host->clk_mul)
3060                 host->clk_mul += 1;
3061
3062         /*
3063          * Set host parameters.
3064          */
3065         max_clk = host->max_clk;
3066
3067         if (host->ops->get_min_clock)
3068                 mmc->f_min = host->ops->get_min_clock(host);
3069         else if (host->version >= SDHCI_SPEC_300) {
3070                 if (host->clk_mul) {
3071                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3072                         max_clk = host->max_clk * host->clk_mul;
3073                 } else
3074                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3075         } else
3076                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3077
3078         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3079                 mmc->f_max = max_clk;
3080
3081         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3082                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3083                                         SDHCI_TIMEOUT_CLK_SHIFT;
3084                 if (host->timeout_clk == 0) {
3085                         if (host->ops->get_timeout_clock) {
3086                                 host->timeout_clk =
3087                                         host->ops->get_timeout_clock(host);
3088                         } else {
3089                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3090                                         mmc_hostname(mmc));
3091                                 return -ENODEV;
3092                         }
3093                 }
3094
3095                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3096                         host->timeout_clk *= 1000;
3097
3098                 if (override_timeout_clk)
3099                         host->timeout_clk = override_timeout_clk;
3100
3101                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3102                         host->ops->get_max_timeout_count(host) : 1 << 27;
3103                 mmc->max_busy_timeout /= host->timeout_clk;
3104         }
3105
3106         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3107         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3108
3109         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3110                 host->flags |= SDHCI_AUTO_CMD12;
3111
3112         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3113         if ((host->version >= SDHCI_SPEC_300) &&
3114             ((host->flags & SDHCI_USE_ADMA) ||
3115              !(host->flags & SDHCI_USE_SDMA)) &&
3116              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3117                 host->flags |= SDHCI_AUTO_CMD23;
3118                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3119         } else {
3120                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3121         }
3122
3123         /*
3124          * A controller may support 8-bit width, but the board itself
3125          * might not have the pins brought out.  Boards that support
3126          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3127          * their platform code before calling sdhci_add_host(), and we
3128          * won't assume 8-bit width for hosts without that CAP.
3129          */
3130         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3131                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3132
3133         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3134                 mmc->caps &= ~MMC_CAP_CMD23;
3135
3136         if (caps[0] & SDHCI_CAN_DO_HISPD)
3137                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3138
3139         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3140             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3141             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3142                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3143
3144         /* If there are external regulators, get them */
3145         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3146                 return -EPROBE_DEFER;
3147
3148         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3149         if (!IS_ERR(mmc->supply.vqmmc)) {
3150                 ret = regulator_enable(mmc->supply.vqmmc);
3151                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3152                                                     1950000))
3153                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3154                                         SDHCI_SUPPORT_SDR50 |
3155                                         SDHCI_SUPPORT_DDR50);
3156                 if (ret) {
3157                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3158                                 mmc_hostname(mmc), ret);
3159                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3160                 }
3161         }
3162
3163         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3164                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3165                        SDHCI_SUPPORT_DDR50);
3166
3167         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3168         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3169                        SDHCI_SUPPORT_DDR50))
3170                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3171
3172         /* SDR104 supports also implies SDR50 support */
3173         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3174                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3175                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3176                  * field can be promoted to support HS200.
3177                  */
3178                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3179                         mmc->caps2 |= MMC_CAP2_HS200;
3180         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3181                 mmc->caps |= MMC_CAP_UHS_SDR50;
3182
3183         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3184             (caps[1] & SDHCI_SUPPORT_HS400))
3185                 mmc->caps2 |= MMC_CAP2_HS400;
3186
3187         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3188             (IS_ERR(mmc->supply.vqmmc) ||
3189              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3190                                              1300000)))
3191                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3192
3193         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3194                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3195                 mmc->caps |= MMC_CAP_UHS_DDR50;
3196
3197         /* Does the host need tuning for SDR50? */
3198         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3199                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3200
3201         /* Does the host need tuning for SDR104 / HS200? */
3202         if (mmc->caps2 & MMC_CAP2_HS200)
3203                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3204
3205         /* Driver Type(s) (A, C, D) supported by the host */
3206         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3207                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3208         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3209                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3210         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3211                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3212
3213         /* Initial value for re-tuning timer count */
3214         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3215                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3216
3217         /*
3218          * In case Re-tuning Timer is not disabled, the actual value of
3219          * re-tuning timer will be 2 ^ (n - 1).
3220          */
3221         if (host->tuning_count)
3222                 host->tuning_count = 1 << (host->tuning_count - 1);
3223
3224         /* Re-tuning mode supported by the Host Controller */
3225         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3226                              SDHCI_RETUNING_MODE_SHIFT;
3227
3228         ocr_avail = 0;
3229
3230         /*
3231          * According to SD Host Controller spec v3.00, if the Host System
3232          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3233          * the value is meaningful only if Voltage Support in the Capabilities
3234          * register is set. The actual current value is 4 times the register
3235          * value.
3236          */
3237         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3238         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3239                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3240                 if (curr > 0) {
3241
3242                         /* convert to SDHCI_MAX_CURRENT format */
3243                         curr = curr/1000;  /* convert to mA */
3244                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3245
3246                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3247                         max_current_caps =
3248                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3249                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3250                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3251                 }
3252         }
3253
3254         if (caps[0] & SDHCI_CAN_VDD_330) {
3255                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3256
3257                 mmc->max_current_330 = ((max_current_caps &
3258                                    SDHCI_MAX_CURRENT_330_MASK) >>
3259                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3260                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3261         }
3262         if (caps[0] & SDHCI_CAN_VDD_300) {
3263                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3264
3265                 mmc->max_current_300 = ((max_current_caps &
3266                                    SDHCI_MAX_CURRENT_300_MASK) >>
3267                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3268                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3269         }
3270         if (caps[0] & SDHCI_CAN_VDD_180) {
3271                 ocr_avail |= MMC_VDD_165_195;
3272
3273                 mmc->max_current_180 = ((max_current_caps &
3274                                    SDHCI_MAX_CURRENT_180_MASK) >>
3275                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3276                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3277         }
3278
3279         /* If OCR set by host, use it instead. */
3280         if (host->ocr_mask)
3281                 ocr_avail = host->ocr_mask;
3282
3283         /* If OCR set by external regulators, give it highest prio. */
3284         if (mmc->ocr_avail)
3285                 ocr_avail = mmc->ocr_avail;
3286
3287         mmc->ocr_avail = ocr_avail;
3288         mmc->ocr_avail_sdio = ocr_avail;
3289         if (host->ocr_avail_sdio)
3290                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3291         mmc->ocr_avail_sd = ocr_avail;
3292         if (host->ocr_avail_sd)
3293                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3294         else /* normal SD controllers don't support 1.8V */
3295                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3296         mmc->ocr_avail_mmc = ocr_avail;
3297         if (host->ocr_avail_mmc)
3298                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3299
3300         if (mmc->ocr_avail == 0) {
3301                 pr_err("%s: Hardware doesn't report any "
3302                         "support voltages.\n", mmc_hostname(mmc));
3303                 return -ENODEV;
3304         }
3305
3306         spin_lock_init(&host->lock);
3307
3308         /*
3309          * Maximum number of segments. Depends on if the hardware
3310          * can do scatter/gather or not.
3311          */
3312         if (host->flags & SDHCI_USE_ADMA)
3313                 mmc->max_segs = SDHCI_MAX_SEGS;
3314         else if (host->flags & SDHCI_USE_SDMA)
3315                 mmc->max_segs = 1;
3316         else /* PIO */
3317                 mmc->max_segs = SDHCI_MAX_SEGS;
3318
3319         /*
3320          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3321          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3322          * is less anyway.
3323          */
3324         mmc->max_req_size = 524288;
3325
3326         /*
3327          * Maximum segment size. Could be one segment with the maximum number
3328          * of bytes. When doing hardware scatter/gather, each entry cannot
3329          * be larger than 64 KiB though.
3330          */
3331         if (host->flags & SDHCI_USE_ADMA) {
3332                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3333                         mmc->max_seg_size = 65535;
3334                 else
3335                         mmc->max_seg_size = 65536;
3336         } else {
3337                 mmc->max_seg_size = mmc->max_req_size;
3338         }
3339
3340         /*
3341          * Maximum block size. This varies from controller to controller and
3342          * is specified in the capabilities register.
3343          */
3344         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3345                 mmc->max_blk_size = 2;
3346         } else {
3347                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3348                                 SDHCI_MAX_BLOCK_SHIFT;
3349                 if (mmc->max_blk_size >= 3) {
3350                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3351                                 mmc_hostname(mmc));
3352                         mmc->max_blk_size = 0;
3353                 }
3354         }
3355
3356         mmc->max_blk_size = 512 << mmc->max_blk_size;
3357
3358         /*
3359          * Maximum block count.
3360          */
3361         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3362
3363         /*
3364          * Init tasklets.
3365          */
3366         tasklet_init(&host->finish_tasklet,
3367                 sdhci_tasklet_finish, (unsigned long)host);
3368
3369         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3370
3371         init_waitqueue_head(&host->buf_ready_int);
3372
3373         sdhci_init(host, 0);
3374
3375         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3376                                    IRQF_SHARED, mmc_hostname(mmc), host);
3377         if (ret) {
3378                 pr_err("%s: Failed to request IRQ %d: %d\n",
3379                        mmc_hostname(mmc), host->irq, ret);
3380                 goto untasklet;
3381         }
3382
3383 #ifdef CONFIG_MMC_DEBUG
3384         sdhci_dumpregs(host);
3385 #endif
3386
3387 #ifdef SDHCI_USE_LEDS_CLASS
3388         snprintf(host->led_name, sizeof(host->led_name),
3389                 "%s::", mmc_hostname(mmc));
3390         host->led.name = host->led_name;
3391         host->led.brightness = LED_OFF;
3392         host->led.default_trigger = mmc_hostname(mmc);
3393         host->led.brightness_set = sdhci_led_control;
3394
3395         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3396         if (ret) {
3397                 pr_err("%s: Failed to register LED device: %d\n",
3398                        mmc_hostname(mmc), ret);
3399                 goto reset;
3400         }
3401 #endif
3402
3403         mmiowb();
3404
3405         mmc_add_host(mmc);
3406
3407         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3408                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3409                 (host->flags & SDHCI_USE_ADMA) ?
3410                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3411                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3412
3413         sdhci_enable_card_detection(host);
3414
3415         return 0;
3416
3417 #ifdef SDHCI_USE_LEDS_CLASS
3418 reset:
3419         sdhci_do_reset(host, SDHCI_RESET_ALL);
3420         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3421         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3422         free_irq(host->irq, host);
3423 #endif
3424 untasklet:
3425         tasklet_kill(&host->finish_tasklet);
3426
3427         return ret;
3428 }
3429
3430 EXPORT_SYMBOL_GPL(sdhci_add_host);
3431
3432 void sdhci_remove_host(struct sdhci_host *host, int dead)
3433 {
3434         struct mmc_host *mmc = host->mmc;
3435         unsigned long flags;
3436
3437         if (dead) {
3438                 spin_lock_irqsave(&host->lock, flags);
3439
3440                 host->flags |= SDHCI_DEVICE_DEAD;
3441
3442                 if (host->mrq) {
3443                         pr_err("%s: Controller removed during "
3444                                 " transfer!\n", mmc_hostname(mmc));
3445
3446                         host->mrq->cmd->error = -ENOMEDIUM;
3447                         tasklet_schedule(&host->finish_tasklet);
3448                 }
3449
3450                 spin_unlock_irqrestore(&host->lock, flags);
3451         }
3452
3453         sdhci_disable_card_detection(host);
3454
3455         mmc_remove_host(mmc);
3456
3457 #ifdef SDHCI_USE_LEDS_CLASS
3458         led_classdev_unregister(&host->led);
3459 #endif
3460
3461         if (!dead)
3462                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3463
3464         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3465         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3466         free_irq(host->irq, host);
3467
3468         del_timer_sync(&host->timer);
3469
3470         tasklet_kill(&host->finish_tasklet);
3471
3472         if (!IS_ERR(mmc->supply.vqmmc))
3473                 regulator_disable(mmc->supply.vqmmc);
3474
3475         if (host->adma_table)
3476                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3477                                   host->adma_table, host->adma_addr);
3478         kfree(host->align_buffer);
3479
3480         host->adma_table = NULL;
3481         host->align_buffer = NULL;
3482 }
3483
3484 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3485
3486 void sdhci_free_host(struct sdhci_host *host)
3487 {
3488         mmc_free_host(host->mmc);
3489 }
3490
3491 EXPORT_SYMBOL_GPL(sdhci_free_host);
3492
3493 /*****************************************************************************\
3494  *                                                                           *
3495  * Driver init/exit                                                          *
3496  *                                                                           *
3497 \*****************************************************************************/
3498
3499 static int __init sdhci_drv_init(void)
3500 {
3501         pr_info(DRIVER_NAME
3502                 ": Secure Digital Host Controller Interface driver\n");
3503         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3504
3505         return 0;
3506 }
3507
3508 static void __exit sdhci_drv_exit(void)
3509 {
3510 }
3511
3512 module_init(sdhci_drv_init);
3513 module_exit(sdhci_drv_exit);
3514
3515 module_param(debug_quirks, uint, 0444);
3516 module_param(debug_quirks2, uint, 0444);
3517
3518 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3519 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3520 MODULE_LICENSE("GPL");
3521
3522 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3523 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");