drivers/mfd/wm831x-irq.c

   1 /*
   2  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
   3  *
   4  * Copyright 2009 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irqdomain.h>
  22
  23 #include <linux/mfd/wm831x/core.h>
  24 #include <linux/mfd/wm831x/pdata.h>
  25 #include <linux/mfd/wm831x/gpio.h>
  26 #include <linux/mfd/wm831x/irq.h>
  27
  28 #include <linux/delay.h>
  29
  30 struct wm831x_irq_data {
  31         int primary;
  32         int reg;
  33         int mask;
  34 };
  35
  36 static struct wm831x_irq_data wm831x_irqs[] = {
  37         [WM831X_IRQ_TEMP_THW] = {
  38                 .primary = WM831X_TEMP_INT,
  39                 .reg = 1,
  40                 .mask = WM831X_TEMP_THW_EINT,
  41         },
  42         [WM831X_IRQ_GPIO_1] = {
  43                 .primary = WM831X_GP_INT,
  44                 .reg = 5,
  45                 .mask = WM831X_GP1_EINT,
  46         },
  47         [WM831X_IRQ_GPIO_2] = {
  48                 .primary = WM831X_GP_INT,
  49                 .reg = 5,
  50                 .mask = WM831X_GP2_EINT,
  51         },
  52         [WM831X_IRQ_GPIO_3] = {
  53                 .primary = WM831X_GP_INT,
  54                 .reg = 5,
  55                 .mask = WM831X_GP3_EINT,
  56         },
  57         [WM831X_IRQ_GPIO_4] = {
  58                 .primary = WM831X_GP_INT,
  59                 .reg = 5,
  60                 .mask = WM831X_GP4_EINT,
  61         },
  62         [WM831X_IRQ_GPIO_5] = {
  63                 .primary = WM831X_GP_INT,
  64                 .reg = 5,
  65                 .mask = WM831X_GP5_EINT,
  66         },
  67         [WM831X_IRQ_GPIO_6] = {
  68                 .primary = WM831X_GP_INT,
  69                 .reg = 5,
  70                 .mask = WM831X_GP6_EINT,
  71         },
  72         [WM831X_IRQ_GPIO_7] = {
  73                 .primary = WM831X_GP_INT,
  74                 .reg = 5,
  75                 .mask = WM831X_GP7_EINT,
  76         },
  77         [WM831X_IRQ_GPIO_8] = {
  78                 .primary = WM831X_GP_INT,
  79                 .reg = 5,
  80                 .mask = WM831X_GP8_EINT,
  81         },
  82         [WM831X_IRQ_GPIO_9] = {
  83                 .primary = WM831X_GP_INT,
  84                 .reg = 5,
  85                 .mask = WM831X_GP9_EINT,
  86         },
  87         [WM831X_IRQ_GPIO_10] = {
  88                 .primary = WM831X_GP_INT,
  89                 .reg = 5,
  90                 .mask = WM831X_GP10_EINT,
  91         },
  92         [WM831X_IRQ_GPIO_11] = {
  93                 .primary = WM831X_GP_INT,
  94                 .reg = 5,
  95                 .mask = WM831X_GP11_EINT,
  96         },
  97         [WM831X_IRQ_GPIO_12] = {
  98                 .primary = WM831X_GP_INT,
  99                 .reg = 5,
 100                 .mask = WM831X_GP12_EINT,
 101         },
 102         [WM831X_IRQ_GPIO_13] = {
 103                 .primary = WM831X_GP_INT,
 104                 .reg = 5,
 105                 .mask = WM831X_GP13_EINT,
 106         },
 107         [WM831X_IRQ_GPIO_14] = {
 108                 .primary = WM831X_GP_INT,
 109                 .reg = 5,
 110                 .mask = WM831X_GP14_EINT,
 111         },
 112         [WM831X_IRQ_GPIO_15] = {
 113                 .primary = WM831X_GP_INT,
 114                 .reg = 5,
 115                 .mask = WM831X_GP15_EINT,
 116         },
 117         [WM831X_IRQ_GPIO_16] = {
 118                 .primary = WM831X_GP_INT,
 119                 .reg = 5,
 120                 .mask = WM831X_GP16_EINT,
 121         },
 122         [WM831X_IRQ_ON] = {
 123                 .primary = WM831X_ON_PIN_INT,
 124                 .reg = 1,
 125                 .mask = WM831X_ON_PIN_EINT,
 126         },
 127         [WM831X_IRQ_PPM_SYSLO] = {
 128                 .primary = WM831X_PPM_INT,
 129                 .reg = 1,
 130                 .mask = WM831X_PPM_SYSLO_EINT,
 131         },
 132         [WM831X_IRQ_PPM_PWR_SRC] = {
 133                 .primary = WM831X_PPM_INT,
 134                 .reg = 1,
 135                 .mask = WM831X_PPM_PWR_SRC_EINT,
 136         },
 137         [WM831X_IRQ_PPM_USB_CURR] = {
 138                 .primary = WM831X_PPM_INT,
 139                 .reg = 1,
 140                 .mask = WM831X_PPM_USB_CURR_EINT,
 141         },
 142         [WM831X_IRQ_WDOG_TO] = {
 143                 .primary = WM831X_WDOG_INT,
 144                 .reg = 1,
 145                 .mask = WM831X_WDOG_TO_EINT,
 146         },
 147         [WM831X_IRQ_RTC_PER] = {
 148                 .primary = WM831X_RTC_INT,
 149                 .reg = 1,
 150                 .mask = WM831X_RTC_PER_EINT,
 151         },
 152         [WM831X_IRQ_RTC_ALM] = {
 153                 .primary = WM831X_RTC_INT,
 154                 .reg = 1,
 155                 .mask = WM831X_RTC_ALM_EINT,
 156         },
 157         [WM831X_IRQ_CHG_BATT_HOT] = {
 158                 .primary = WM831X_CHG_INT,
 159                 .reg = 2,
 160                 .mask = WM831X_CHG_BATT_HOT_EINT,
 161         },
 162         [WM831X_IRQ_CHG_BATT_COLD] = {
 163                 .primary = WM831X_CHG_INT,
 164                 .reg = 2,
 165                 .mask = WM831X_CHG_BATT_COLD_EINT,
 166         },
 167         [WM831X_IRQ_CHG_BATT_FAIL] = {
 168                 .primary = WM831X_CHG_INT,
 169                 .reg = 2,
 170                 .mask = WM831X_CHG_BATT_FAIL_EINT,
 171         },
 172         [WM831X_IRQ_CHG_OV] = {
 173                 .primary = WM831X_CHG_INT,
 174                 .reg = 2,
 175                 .mask = WM831X_CHG_OV_EINT,
 176         },
 177         [WM831X_IRQ_CHG_END] = {
 178                 .primary = WM831X_CHG_INT,
 179                 .reg = 2,
 180                 .mask = WM831X_CHG_END_EINT,
 181         },
 182         [WM831X_IRQ_CHG_TO] = {
 183                 .primary = WM831X_CHG_INT,
 184                 .reg = 2,
 185                 .mask = WM831X_CHG_TO_EINT,
 186         },
 187         [WM831X_IRQ_CHG_MODE] = {
 188                 .primary = WM831X_CHG_INT,
 189                 .reg = 2,
 190                 .mask = WM831X_CHG_MODE_EINT,
 191         },
 192         [WM831X_IRQ_CHG_START] = {
 193                 .primary = WM831X_CHG_INT,
 194                 .reg = 2,
 195                 .mask = WM831X_CHG_START_EINT,
 196         },
 197         [WM831X_IRQ_TCHDATA] = {
 198                 .primary = WM831X_TCHDATA_INT,
 199                 .reg = 1,
 200                 .mask = WM831X_TCHDATA_EINT,
 201         },
 202         [WM831X_IRQ_TCHPD] = {
 203                 .primary = WM831X_TCHPD_INT,
 204                 .reg = 1,
 205                 .mask = WM831X_TCHPD_EINT,
 206         },
 207         [WM831X_IRQ_AUXADC_DATA] = {
 208                 .primary = WM831X_AUXADC_INT,
 209                 .reg = 1,
 210                 .mask = WM831X_AUXADC_DATA_EINT,
 211         },
 212         [WM831X_IRQ_AUXADC_DCOMP1] = {
 213                 .primary = WM831X_AUXADC_INT,
 214                 .reg = 1,
 215                 .mask = WM831X_AUXADC_DCOMP1_EINT,
 216         },
 217         [WM831X_IRQ_AUXADC_DCOMP2] = {
 218                 .primary = WM831X_AUXADC_INT,
 219                 .reg = 1,
 220                 .mask = WM831X_AUXADC_DCOMP2_EINT,
 221         },
 222         [WM831X_IRQ_AUXADC_DCOMP3] = {
 223                 .primary = WM831X_AUXADC_INT,
 224                 .reg = 1,
 225                 .mask = WM831X_AUXADC_DCOMP3_EINT,
 226         },
 227         [WM831X_IRQ_AUXADC_DCOMP4] = {
 228                 .primary = WM831X_AUXADC_INT,
 229                 .reg = 1,
 230                 .mask = WM831X_AUXADC_DCOMP4_EINT,
 231         },
 232         [WM831X_IRQ_CS1] = {
 233                 .primary = WM831X_CS_INT,
 234                 .reg = 2,
 235                 .mask = WM831X_CS1_EINT,
 236         },
 237         [WM831X_IRQ_CS2] = {
 238                 .primary = WM831X_CS_INT,
 239                 .reg = 2,
 240                 .mask = WM831X_CS2_EINT,
 241         },
 242         [WM831X_IRQ_HC_DC1] = {
 243                 .primary = WM831X_HC_INT,
 244                 .reg = 4,
 245                 .mask = WM831X_HC_DC1_EINT,
 246         },
 247         [WM831X_IRQ_HC_DC2] = {
 248                 .primary = WM831X_HC_INT,
 249                 .reg = 4,
 250                 .mask = WM831X_HC_DC2_EINT,
 251         },
 252         [WM831X_IRQ_UV_LDO1] = {
 253                 .primary = WM831X_UV_INT,
 254                 .reg = 3,
 255                 .mask = WM831X_UV_LDO1_EINT,
 256         },
 257         [WM831X_IRQ_UV_LDO2] = {
 258                 .primary = WM831X_UV_INT,
 259                 .reg = 3,
 260                 .mask = WM831X_UV_LDO2_EINT,
 261         },
 262         [WM831X_IRQ_UV_LDO3] = {
 263                 .primary = WM831X_UV_INT,
 264                 .reg = 3,
 265                 .mask = WM831X_UV_LDO3_EINT,
 266         },
 267         [WM831X_IRQ_UV_LDO4] = {
 268                 .primary = WM831X_UV_INT,
 269                 .reg = 3,
 270                 .mask = WM831X_UV_LDO4_EINT,
 271         },
 272         [WM831X_IRQ_UV_LDO5] = {
 273                 .primary = WM831X_UV_INT,
 274                 .reg = 3,
 275                 .mask = WM831X_UV_LDO5_EINT,
 276         },
 277         [WM831X_IRQ_UV_LDO6] = {
 278                 .primary = WM831X_UV_INT,
 279                 .reg = 3,
 280                 .mask = WM831X_UV_LDO6_EINT,
 281         },
 282         [WM831X_IRQ_UV_LDO7] = {
 283                 .primary = WM831X_UV_INT,
 284                 .reg = 3,
 285                 .mask = WM831X_UV_LDO7_EINT,
 286         },
 287         [WM831X_IRQ_UV_LDO8] = {
 288                 .primary = WM831X_UV_INT,
 289                 .reg = 3,
 290                 .mask = WM831X_UV_LDO8_EINT,
 291         },
 292         [WM831X_IRQ_UV_LDO9] = {
 293                 .primary = WM831X_UV_INT,
 294                 .reg = 3,
 295                 .mask = WM831X_UV_LDO9_EINT,
 296         },
 297         [WM831X_IRQ_UV_LDO10] = {
 298                 .primary = WM831X_UV_INT,
 299                 .reg = 3,
 300                 .mask = WM831X_UV_LDO10_EINT,
 301         },
 302         [WM831X_IRQ_UV_DC1] = {
 303                 .primary = WM831X_UV_INT,
 304                 .reg = 4,
 305                 .mask = WM831X_UV_DC1_EINT,
 306         },
 307         [WM831X_IRQ_UV_DC2] = {
 308                 .primary = WM831X_UV_INT,
 309                 .reg = 4,
 310                 .mask = WM831X_UV_DC2_EINT,
 311         },
 312         [WM831X_IRQ_UV_DC3] = {
 313                 .primary = WM831X_UV_INT,
 314                 .reg = 4,
 315                 .mask = WM831X_UV_DC3_EINT,
 316         },
 317         [WM831X_IRQ_UV_DC4] = {
 318                 .primary = WM831X_UV_INT,
 319                 .reg = 4,
 320                 .mask = WM831X_UV_DC4_EINT,
 321         },
 322 };
 323
 324 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
 325 {
 326         return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
 327 }
 328
 329 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
 330                                                         int irq)
 331 {
 332         return &wm831x_irqs[irq];
 333 }
 334
 335 static void wm831x_irq_lock(struct irq_data *data)
 336 {
 337         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 338
 339         mutex_lock(&wm831x->irq_lock);
 340 }
 341
 342 static void wm831x_irq_sync_unlock(struct irq_data *data)
 343 {
 344         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 345         int i;
 346
 347         for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
 348                 if (wm831x->gpio_update[i]) {
 349                         wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
 350                                         WM831X_GPN_INT_MODE | WM831X_GPN_POL,
 351                                         wm831x->gpio_update[i]);
 352                         wm831x->gpio_update[i] = 0;
 353                 }
 354         }
 355
 356         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 357                 /* If there's been a change in the mask write it back
 358                  * to the hardware. */
 359                 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
 360                         dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
 361                                 WM831X_INTERRUPT_STATUS_1_MASK + i,
 362                                 wm831x->irq_masks_cur[i]);
 363
 364                         wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
 365                         wm831x_reg_write(wm831x,
 366                                          WM831X_INTERRUPT_STATUS_1_MASK + i,
 367                                          wm831x->irq_masks_cur[i]);
 368                 }
 369         }
 370
 371         mutex_unlock(&wm831x->irq_lock);
 372 }
 373
 374 static void wm831x_irq_enable(struct irq_data *data)
 375 {
 376         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 377         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 378                                                              data->hwirq);
 379
 380         wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 381 }
 382
 383 static void wm831x_irq_disable(struct irq_data *data)
 384 {
 385         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 386         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 387                                                              data->hwirq);
 388
 389         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 390 }
 391
 392 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
 393 {
 394         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 395         int irq;
 396
 397         irq = data->hwirq;
 398
 399         if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
 400                 /* Ignore internal-only IRQs */
 401                 if (irq >= 0 && irq < WM831X_NUM_IRQS)
 402                         return 0;
 403                 else
 404                         return -EINVAL;
 405         }
 406
 407         /* Rebase the IRQ into the GPIO range so we've got a sensible array
 408          * index.
 409          */
 410         irq -= WM831X_IRQ_GPIO_1;
 411
 412         /* We set the high bit to flag that we need an update; don't
 413          * do the update here as we can be called with the bus lock
 414          * held.
 415          */
 416         wm831x->gpio_level_low[irq] = false;
 417         wm831x->gpio_level_high[irq] = false;
 418         switch (type) {
 419         case IRQ_TYPE_EDGE_BOTH:
 420                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
 421                 break;
 422         case IRQ_TYPE_EDGE_RISING:
 423                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
 424                 break;
 425         case IRQ_TYPE_EDGE_FALLING:
 426                 wm831x->gpio_update[irq] = 0x10000;
 427                 break;
 428         case IRQ_TYPE_LEVEL_HIGH:
 429                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
 430                 wm831x->gpio_level_high[irq] = true;
 431                 break;
 432         case IRQ_TYPE_LEVEL_LOW:
 433                 wm831x->gpio_update[irq] = 0x10000;
 434                 wm831x->gpio_level_low[irq] = true;
 435                 break;
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static struct irq_chip wm831x_irq_chip = {
 444         .name                   = "wm831x",
 445         .irq_bus_lock           = wm831x_irq_lock,
 446         .irq_bus_sync_unlock    = wm831x_irq_sync_unlock,
 447         .irq_disable            = wm831x_irq_disable,
 448         .irq_enable             = wm831x_irq_enable,
 449         .irq_set_type           = wm831x_irq_set_type,
 450 };
 451
 452 /* The processing of the primary interrupt occurs in a thread so that
 453  * we can interact with the device over I2C or SPI. */
 454 static irqreturn_t wm831x_irq_thread(int irq, void *data)
 455 {
 456         struct wm831x *wm831x = data;
 457         unsigned int i;
 458         int primary, status_addr, ret;
 459         int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
 460         int read[WM831X_NUM_IRQ_REGS] = { 0 };
 461         int *status;
 462
 463         primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
 464         if (primary < 0) {
 465                 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
 466                         primary);
 467                 goto out;
 468         }
 469
 470         /* The touch interrupts are visible in the primary register as
 471          * an optimisation; open code this to avoid complicating the
 472          * main handling loop and so we can also skip iterating the
 473          * descriptors.
 474          */
 475         if (primary & WM831X_TCHPD_INT)
 476                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
 477                                                    WM831X_IRQ_TCHPD));
 478         if (primary & WM831X_TCHDATA_INT)
 479                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
 480                                                    WM831X_IRQ_TCHDATA));
 481         primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
 482
 483         for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
 484                 int offset = wm831x_irqs[i].reg - 1;
 485
 486                 if (!(primary & wm831x_irqs[i].primary))
 487                         continue;
 488
 489                 status = &status_regs[offset];
 490
 491                 /* Hopefully there should only be one register to read
 492                  * each time otherwise we ought to do a block read. */
 493                 if (!read[offset]) {
 494                         status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
 495
 496                         *status = wm831x_reg_read(wm831x, status_addr);
 497                         if (*status < 0) {
 498                                 dev_err(wm831x->dev,
 499                                         "Failed to read IRQ status: %d\n",
 500                                         *status);
 501                                 goto out;
 502                         }
 503
 504                         read[offset] = 1;
 505
 506                         /* Ignore any bits that we don't think are masked */
 507                         *status &= ~wm831x->irq_masks_cur[offset];
 508
 509                         /* Acknowledge now so we don't miss
 510                          * notifications while we handle.
 511                          */
 512                         wm831x_reg_write(wm831x, status_addr, *status);
 513                 }
 514
 515                 if (*status & wm831x_irqs[i].mask)
 516                         handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
 517                                                            i));
 518
 519                 /* Simulate an edge triggered IRQ by polling the input
 520                  * status.  This is sucky but improves interoperability.
 521                  */
 522                 if (primary == WM831X_GP_INT &&
 523                     wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
 524                         ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
 525                         while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
 526                                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
 527                                                                    i));
 528                                 ret = wm831x_reg_read(wm831x,
 529                                                       WM831X_GPIO_LEVEL);
 530                         }
 531                 }
 532
 533                 if (primary == WM831X_GP_INT &&
 534                     wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
 535                         ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
 536                         while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
 537                                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
 538                                                                    i));
 539                                 ret = wm831x_reg_read(wm831x,
 540                                                       WM831X_GPIO_LEVEL);
 541                         }
 542                 }
 543         }
 544
 545 out:
 546         return IRQ_HANDLED;
 547 }
 548
 549 static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
 550                           irq_hw_number_t hw)
 551 {
 552         irq_set_chip_data(virq, h->host_data);
 553         irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
 554         irq_set_nested_thread(virq, 1);
 555         irq_set_noprobe(virq);
 556
 557         return 0;
 558 }
 559
 560 static const struct irq_domain_ops wm831x_irq_domain_ops = {
 561         .map    = wm831x_irq_map,
 562         .xlate  = irq_domain_xlate_twocell,
 563 };
 564
 565 int wm831x_irq_init(struct wm831x *wm831x, int irq)
 566 {
 567         struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
 568         struct irq_domain *domain;
 569         int i, ret, irq_base;
 570
 571         mutex_init(&wm831x->irq_lock);
 572
 573         /* Mask the individual interrupt sources */
 574         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 575                 wm831x->irq_masks_cur[i] = 0xffff;
 576                 wm831x->irq_masks_cache[i] = 0xffff;
 577                 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
 578                                  0xffff);
 579         }
 580
 581         /* Try to dynamically allocate IRQs if no base is specified */
 582         if (pdata && pdata->irq_base) {
 583                 irq_base = irq_alloc_descs(pdata->irq_base, 0,
 584                                            WM831X_NUM_IRQS, 0);
 585                 if (irq_base < 0) {
 586                         dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
 587                                  irq_base);
 588                         irq_base = 0;
 589                 }
 590         } else {
 591                 irq_base = 0;
 592         }
 593
 594         if (irq_base)
 595                 domain = irq_domain_add_legacy(wm831x->dev->of_node,
 596                                                ARRAY_SIZE(wm831x_irqs),
 597                                                irq_base, 0,
 598                                                &wm831x_irq_domain_ops,
 599                                                wm831x);
 600         else
 601                 domain = irq_domain_add_linear(wm831x->dev->of_node,
 602                                                ARRAY_SIZE(wm831x_irqs),
 603                                                &wm831x_irq_domain_ops,
 604                                                wm831x);
 605
 606         if (!domain) {
 607                 dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
 608                 return -EINVAL;
 609         }
 610
 611         if (pdata && pdata->irq_cmos)
 612                 i = 0;
 613         else
 614                 i = WM831X_IRQ_OD;
 615
 616         wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 617                         WM831X_IRQ_OD, i);
 618
 619         wm831x->irq = irq;
 620         wm831x->irq_domain = domain;
 621
 622         if (irq) {
 623                 /* Try to flag /IRQ as a wake source; there are a number of
 624                  * unconditional wake sources in the PMIC so this isn't
 625                  * conditional but we don't actually care *too* much if it
 626                  * fails.
 627                  */
 628                 ret = enable_irq_wake(irq);
 629                 if (ret != 0) {
 630                         dev_warn(wm831x->dev,
 631                                  "Can't enable IRQ as wake source: %d\n",
 632                                  ret);
 633                 }
 634
 635                 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
 636                                            IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 637                                            "wm831x", wm831x);
 638                 if (ret != 0) {
 639                         dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 640                                 irq, ret);
 641                         return ret;
 642                 }
 643         } else {
 644                 dev_warn(wm831x->dev,
 645                          "No interrupt specified - functionality limited\n");
 646         }
 647
 648         /* Enable top level interrupts, we mask at secondary level */
 649         wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
 650
 651         return 0;
 652 }
 653
 654 void wm831x_irq_exit(struct wm831x *wm831x)
 655 {
 656         if (wm831x->irq)
 657                 free_irq(wm831x->irq, wm831x);
 658 }