mfd: add driver for fusb302 Type-C PD
[firefly-linux-kernel-4.4.55.git] / drivers / mfd / fusb302.c
1 /*
2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3  * Author: Zain Wang <zain.wang@rock-chips.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * Some ideas are from chrome ec and fairchild GPL fusb302 driver.
10  */
11
12 #include <linux/delay.h>
13 #include <linux/extcon.h>
14 #include <linux/gpio.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_gpio.h>
18 #include <linux/regmap.h>
19
20 #include "fusb302.h"
21
22 #define FUSB302_MAX_REG         (FUSB_REG_FIFO + 50)
23 #define FUSB_MS_TO_NS(x)        ((s64)x * 1000 * 1000)
24
25 #define FUSB_MODE_DRP           0
26 #define FUSB_MODE_UFP           1
27 #define FUSB_MODE_DFP           2
28 #define FUSB_MODE_ASS           3
29
30 #define TYPEC_CC_VOLT_OPEN      0
31 #define TYPEC_CC_VOLT_RA        1
32 #define TYPEC_CC_VOLT_RD        2
33 #define TYPEC_CC_VOLT_RP        3
34
35 #define EVENT_CC                BIT(0)
36 #define EVENT_RX                BIT(1)
37 #define EVENT_TX                BIT(2)
38 #define EVENT_REC_RESET         BIT(3)
39 #define EVENT_WORK_CONTINUE     BIT(5)
40 #define EVENT_TIMER_MUX         BIT(6)
41 #define EVENT_TIMER_STATE       BIT(7)
42 #define FLAG_EVENT              (EVENT_RX | EVENT_TIMER_MUX | \
43                                  EVENT_TIMER_STATE)
44
45 #define PIN_MAP_A               BIT(0)
46 #define PIN_MAP_B               BIT(1)
47 #define PIN_MAP_C               BIT(2)
48 #define PIN_MAP_D               BIT(3)
49 #define PIN_MAP_E               BIT(4)
50 #define PIN_MAP_F               BIT(5)
51
52 static u8 fusb30x_port_used;
53 static struct fusb30x_chip *fusb30x_port_info[256];
54
55 static bool is_write_reg(struct device *dev, unsigned int reg)
56 {
57         if (reg >= FUSB_REG_FIFO)
58                 return true;
59         else
60                 return ((reg < (FUSB_REG_CONTROL4 + 1)) && (reg > 0x01)) ?
61                         true : false;
62 }
63
64 static bool is_volatile_reg(struct device *dev, unsigned int reg)
65 {
66         if (reg > FUSB_REG_CONTROL4)
67                 return true;
68
69         switch (reg) {
70         case FUSB_REG_CONTROL0:
71         case FUSB_REG_CONTROL1:
72         case FUSB_REG_CONTROL3:
73         case FUSB_REG_RESET:
74                 return true;
75         }
76         return false;
77 }
78
79 struct regmap_config fusb302_regmap_config = {
80         .reg_bits = 8,
81         .val_bits = 8,
82         .writeable_reg = is_write_reg,
83         .volatile_reg = is_volatile_reg,
84         .max_register = FUSB302_MAX_REG,
85         .cache_type = REGCACHE_RBTREE,
86 };
87
88 static void dump_notify_info(struct fusb30x_chip *chip)
89 {
90         dev_dbg(chip->dev, "port        %d\n", chip->port_num);
91         dev_dbg(chip->dev, "orientation %d\n", chip->notify.orientation);
92         dev_dbg(chip->dev, "power_role  %d\n", chip->notify.power_role);
93         dev_dbg(chip->dev, "data_role   %d\n", chip->notify.data_role);
94         dev_dbg(chip->dev, "cc          %d\n", chip->notify.is_cc_connected);
95         dev_dbg(chip->dev, "pd          %d\n", chip->notify.is_pd_connected);
96         dev_dbg(chip->dev, "enter_mode  %d\n", chip->notify.is_enter_mode);
97         dev_dbg(chip->dev, "pin support %d\n",
98                 chip->notify.pin_assignment_support);
99         dev_dbg(chip->dev, "pin def     %d\n", chip->notify.pin_assignment_def);
100         dev_dbg(chip->dev, "attention   %d\n", chip->notify.attention);
101 }
102
103 static const unsigned int fusb302_cable[] = {
104         EXTCON_USB,
105         EXTCON_USB_HOST,
106         EXTCON_CHG_USB_SDP,
107         EXTCON_CHG_USB_CDP,
108         EXTCON_CHG_USB_DCP,
109         EXTCON_CHG_USB_SLOW,
110         EXTCON_DISP_DP,
111         EXTCON_NONE,
112 };
113
114 void fusb_irq_disable(struct fusb30x_chip *chip)
115 {
116         unsigned long irqflags = 0;
117
118         spin_lock_irqsave(&chip->irq_lock, irqflags);
119         if (chip->enable_irq) {
120                 disable_irq_nosync(chip->gpio_int_irq);
121                 chip->enable_irq = 0;
122         } else {
123                 dev_warn(chip->dev, "irq have already disabled\n");
124         }
125         spin_unlock_irqrestore(&chip->irq_lock, irqflags);
126 }
127
128 void fusb_irq_enable(struct fusb30x_chip *chip)
129 {
130         unsigned long irqflags = 0;
131
132         spin_lock_irqsave(&chip->irq_lock, irqflags);
133         if (!chip->enable_irq) {
134                 enable_irq(chip->gpio_int_irq);
135                 chip->enable_irq = 1;
136         }
137         spin_unlock_irqrestore(&chip->irq_lock, irqflags);
138 }
139
140 static void platform_fusb_notify(struct fusb30x_chip *chip)
141 {
142         bool plugged = 0, flip = 0, dfp = 0, ufp = 0, dp = 0;
143         union extcon_property_value property;
144
145         if (chip->notify.is_cc_connected)
146                 chip->notify.orientation = chip->cc_polarity + 1;
147
148         /* avoid notify repeated */
149         if (memcmp(&chip->notify, &chip->notify_cmp,
150                    sizeof(struct notify_info))) {
151                 dump_notify_info(chip);
152                 chip->notify.attention = 0;
153                 memcpy(&chip->notify_cmp, &chip->notify,
154                        sizeof(struct notify_info));
155
156                 plugged = chip->notify.is_cc_connected ||
157                           chip->notify.is_pd_connected;
158                 flip = chip->notify.orientation ?
159                        (chip->notify.orientation - 1) : 0;
160                 dp = chip->notify.is_enter_mode;
161
162                 if (dp)
163                         dfp = (chip->notify.pin_assignment_def &
164                                 (PIN_MAP_B | PIN_MAP_D | PIN_MAP_F)) ? 1 : 0;
165                 else if (chip->notify.data_role)
166                         dfp = 1;
167                 else if (plugged)
168                         ufp = 1;
169
170                 property.intval = flip;
171                 extcon_set_property(chip->extcon, EXTCON_USB,
172                                     EXTCON_PROP_USB_TYPEC_POLARITY, property);
173                 extcon_set_property(chip->extcon, EXTCON_USB_HOST,
174                                     EXTCON_PROP_USB_TYPEC_POLARITY, property);
175                 extcon_set_property(chip->extcon, EXTCON_DISP_DP,
176                                     EXTCON_PROP_USB_TYPEC_POLARITY, property);
177                 extcon_set_state(chip->extcon, EXTCON_USB, ufp);
178                 extcon_set_state(chip->extcon, EXTCON_USB_HOST, dfp);
179                 extcon_set_state(chip->extcon, EXTCON_DISP_DP, dp);
180                 extcon_sync(chip->extcon, EXTCON_USB);
181                 extcon_sync(chip->extcon, EXTCON_USB_HOST);
182                 extcon_sync(chip->extcon, EXTCON_DISP_DP);
183         }
184 }
185
186 static bool platform_get_device_irq_state(struct fusb30x_chip *chip)
187 {
188         return !gpiod_get_value(chip->gpio_int);
189 }
190
191 static void fusb_timer_start(struct hrtimer *timer, int ms)
192 {
193         ktime_t ktime;
194
195         ktime = ktime_set(0, FUSB_MS_TO_NS(ms));
196         hrtimer_start(timer, ktime, HRTIMER_MODE_REL);
197 }
198
199 static void platform_set_vbus_lvl_enable(struct fusb30x_chip *chip, int vbus_5v,
200                                          int vbus_other)
201 {
202         if (chip->gpio_vbus_5v)
203                 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_5v);
204
205         if (chip->gpio_vbus_other)
206                 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_other);
207 }
208
209 static void set_state(struct fusb30x_chip *chip, enum connection_state state)
210 {
211         dev_dbg(chip->dev, "port %d, state %d\n", chip->port_num, state);
212         if (!state)
213                 dev_info(chip->dev, "PD disabled\n");
214         chip->conn_state = state;
215         chip->sub_state = 0;
216         chip->val_tmp = 0;
217         chip->work_continue = 1;
218 }
219
220 static int tcpm_get_message(struct fusb30x_chip *chip)
221 {
222         u8 buf[32];
223         int len;
224
225         regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, 3);
226         chip->rec_head = (buf[1] & 0xff) | ((buf[2] << 8) & 0xff00);
227
228         len = PD_HEADER_CNT(chip->rec_head) << 2;
229         regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, len + 4);
230
231         memcpy(chip->rec_load, buf, len);
232
233         return 0;
234 }
235
236 static void fusb302_flush_rx_fifo(struct fusb30x_chip *chip)
237 {
238         tcpm_get_message(chip);
239 }
240
241 static int tcpm_get_cc(struct fusb30x_chip *chip, int *CC1, int *CC2)
242 {
243         u8 val;
244         int *CC_MEASURE;
245         u8 store;
246
247         *CC1 = TYPEC_CC_VOLT_OPEN;
248         *CC2 = TYPEC_CC_VOLT_OPEN;
249
250         if (chip->cc_state & 0x01)
251                 CC_MEASURE = CC1;
252         else
253                 CC_MEASURE = CC2;
254
255         if (chip->cc_state & 0x04) {
256                 regmap_read(chip->regmap, FUSB_REG_SWITCHES0, (u32 *)(&store));
257
258                 /* measure cc1 first */
259                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
260                                    SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
261                                    SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
262                                    SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
263                                    SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
264                                    SWITCHES0_MEAS_CC1);
265                 usleep_range(250, 300);
266
267                 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
268                 val &= STATUS0_BC_LVL;
269                 if (val)
270                         *CC1 = val;
271
272                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
273                                    SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
274                                    SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
275                                    SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
276                                    SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
277                                    SWITCHES0_MEAS_CC2);
278                 usleep_range(250, 300);
279
280                 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
281                 val &= STATUS0_BC_LVL;
282                 if (val)
283                         *CC2 = val;
284
285                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
286                                    SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
287                                    store);
288         } else {
289                 if (chip->cc_state & 0x01) {
290                         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
291                                            SWITCHES0_MEAS_CC1 |
292                                            SWITCHES0_MEAS_CC2 |
293                                            SWITCHES0_PU_EN1 |
294                                            SWITCHES0_PU_EN2 |
295                                            SWITCHES0_PDWN1 |
296                                            SWITCHES0_PDWN2,
297                                            SWITCHES0_MEAS_CC1 |
298                                            SWITCHES0_PU_EN1);
299                 } else {
300                         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
301                                            SWITCHES0_MEAS_CC1 |
302                                            SWITCHES0_MEAS_CC2 |
303                                            SWITCHES0_PU_EN1 |
304                                            SWITCHES0_PU_EN2 |
305                                            SWITCHES0_PDWN1 |
306                                            SWITCHES0_PDWN2,
307                                            SWITCHES0_MEAS_CC2 |
308                                            SWITCHES0_PU_EN2);
309                 }
310
311                 regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x26 << 2);
312                 usleep_range(250, 300);
313
314                 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
315
316                 if (val & STATUS0_COMP) {
317                         *CC_MEASURE = TYPEC_CC_VOLT_OPEN;
318                 } else {
319                         regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x05 << 2);
320                         usleep_range(250, 300);
321
322                         regmap_read(chip->regmap, FUSB_REG_STATUS0,
323                                     (u32 *)(&val));
324
325                         if (val & STATUS0_COMP)
326                                 *CC_MEASURE = TYPEC_CC_VOLT_RA;
327                         else
328                                 *CC_MEASURE = TYPEC_CC_VOLT_RD;
329                 }
330         }
331         return 0;
332 }
333
334 static int tcpm_set_cc(struct fusb30x_chip *chip, int mode)
335 {
336         u8 val = 0, mask;
337
338         val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
339                  SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
340
341         mask = ~val;
342
343         switch (mode) {
344         case FUSB_MODE_DFP:
345                 if (chip->togdone_pullup)
346                         val |= SWITCHES0_PU_EN2;
347                 else
348                         val |= SWITCHES0_PU_EN1;
349                 break;
350         case FUSB_MODE_UFP:
351                 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
352                 break;
353         case FUSB_MODE_DRP:
354                 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
355                 break;
356         case FUSB_MODE_ASS:
357                 break;
358         }
359
360         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, mask, val);
361         return 0;
362 }
363
364 static int tcpm_set_rx_enable(struct fusb30x_chip *chip, int enable)
365 {
366         u8 val = 0;
367
368         if (enable) {
369                 if (chip->cc_polarity)
370                         val |= SWITCHES0_MEAS_CC2;
371                 else
372                         val |= SWITCHES0_MEAS_CC1;
373                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
374                                    SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
375                                    val);
376                 fusb302_flush_rx_fifo(chip);
377                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
378                                    SWITCHES1_AUTO_CRC, SWITCHES1_AUTO_CRC);
379         } else {
380                 /*
381                  * bit of a hack here.
382                  * when this function is called to disable rx (enable=0)
383                  * using it as an indication of detach (gulp!)
384                  * to reset our knowledge of where
385                  * the toggle state machine landed.
386                  */
387                 chip->togdone_pullup = 0;
388
389 #ifdef  FUSB_HAVE_DRP
390                 tcpm_set_cc(chip, FUSB_MODE_DRP);
391                 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
392                                    CONTROL2_TOG_RD_ONLY,
393                                    CONTROL2_TOG_RD_ONLY);
394 #endif
395                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
396                                    SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
397                                    0);
398                 regmap_update_bits(chip->regmap,
399                                    FUSB_REG_SWITCHES1, SWITCHES1_AUTO_CRC, 0);
400         }
401
402         return 0;
403 }
404
405 static int tcpm_set_msg_header(struct fusb30x_chip *chip)
406 {
407         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
408                            SWITCHES1_POWERROLE | SWITCHES1_DATAROLE,
409                            (chip->notify.power_role << 7) |
410                            (chip->notify.data_role << 4));
411         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
412                            SWITCHES1_SPECREV, 2 << 5);
413         return 0;
414 }
415
416 static int tcpm_set_polarity(struct fusb30x_chip *chip, bool polarity)
417 {
418         u8 val = 0;
419
420 #ifdef FUSB_VCONN_SUPPORT
421         if (chip->vconn_enabled) {
422                 if (polarity)
423                         val |= SWITCHES0_VCONN_CC1;
424                 else
425                         val |= SWITCHES0_VCONN_CC2;
426         }
427 #endif
428
429         if (polarity)
430                 val |= SWITCHES0_MEAS_CC2;
431         else
432                 val |= SWITCHES0_MEAS_CC1;
433
434         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
435                            SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2 |
436                            SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
437                            val);
438
439         val = 0;
440         if (polarity)
441                 val |= SWITCHES1_TXCC2;
442         else
443                 val |= SWITCHES1_TXCC1;
444         regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
445                            SWITCHES1_TXCC1 | SWITCHES1_TXCC2,
446                            val);
447
448         chip->cc_polarity = polarity;
449
450         return 0;
451 }
452
453 static int tcpm_set_vconn(struct fusb30x_chip *chip, int enable)
454 {
455         u8 val = 0;
456
457         if (enable) {
458                 tcpm_set_polarity(chip, chip->cc_polarity);
459         } else {
460                 val &= ~(SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2);
461                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
462                                    SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2,
463                                    val);
464         }
465         chip->vconn_enabled = enable;
466         return 0;
467 }
468
469 static void fusb302_pd_reset(struct fusb30x_chip *chip)
470 {
471         regmap_write(chip->regmap, FUSB_REG_RESET, RESET_PD_RESET);
472         regmap_reinit_cache(chip->regmap, &fusb302_regmap_config);
473 }
474
475 static void tcpm_init(struct fusb30x_chip *chip)
476 {
477         u8 val;
478
479         regmap_read(chip->regmap, FUSB_REG_DEVICEID, (u32 *)(&chip->chip_id));
480         platform_set_vbus_lvl_enable(chip, 0, 0);
481         chip->notify.is_cc_connected = 0;
482         chip->cc_state = 0;
483
484         /* restore default settings */
485         regmap_update_bits(chip->regmap, FUSB_REG_RESET, RESET_SW_RESET,
486                            RESET_SW_RESET);
487         fusb302_pd_reset(chip);
488         /* set auto_retry and number of retries */
489         regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
490                            CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES,
491                            CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES),
492
493         /* set interrupts */
494         val = 0xff;
495         val &= ~(MASK_M_BC_LVL | MASK_M_COLLISION | MASK_M_ALERT |
496                  MASK_M_VBUSOK);
497         regmap_write(chip->regmap, FUSB_REG_MASK, val);
498
499         val = 0xff;
500         val &= ~(MASKA_M_TOGDONE | MASKA_M_RETRYFAIL | MASKA_M_HARDSENT |
501                  MASKA_M_TXSENT | MASKA_M_HARDRST);
502         regmap_write(chip->regmap, FUSB_REG_MASKA, val);
503
504         val = 0xff;
505         val = ~MASKB_M_GCRCSEND;
506         regmap_write(chip->regmap, FUSB_REG_MASKB, val);
507
508 #ifdef  FUSB_HAVE_DRP
509                 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
510                                    CONTROL2_MODE | CONTROL2_TOGGLE,
511                                    (1 << 1) | CONTROL2_TOGGLE);
512
513                 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
514                                    CONTROL2_TOG_RD_ONLY,
515                                    CONTROL2_TOG_RD_ONLY);
516 #endif
517         /* Interrupts Enable */
518         regmap_update_bits(chip->regmap, FUSB_REG_CONTROL0, CONTROL0_INT_MASK,
519                            ~CONTROL0_INT_MASK);
520
521         tcpm_set_polarity(chip, 0);
522         tcpm_set_vconn(chip, 0);
523
524         regmap_write(chip->regmap, FUSB_REG_POWER, 0xf);
525 }
526
527 static void pd_execute_hard_reset(struct fusb30x_chip *chip)
528 {
529         chip->msg_id = 0;
530         chip->vdm_state = 0;
531         if (chip->notify.power_role)
532                 set_state(chip, policy_src_transition_default);
533         else
534                 set_state(chip, policy_snk_transition_default);
535 }
536
537 static void tcpc_alert(struct fusb30x_chip *chip, int *evt)
538 {
539         int interrupt, interrupta, interruptb;
540         u32 val;
541
542         regmap_read(chip->regmap, FUSB_REG_INTERRUPT, &interrupt);
543         regmap_read(chip->regmap, FUSB_REG_INTERRUPTA, &interrupta);
544         regmap_read(chip->regmap, FUSB_REG_INTERRUPTB, &interruptb);
545
546         if (interrupt & INTERRUPT_BC_LVL) {
547                 if (chip->notify.is_cc_connected)
548                         *evt |= EVENT_CC;
549         }
550
551         if (interrupt & INTERRUPT_VBUSOK) {
552                 if (chip->notify.is_cc_connected)
553                         *evt |= EVENT_CC;
554         }
555
556         if (interrupta & INTERRUPTA_TOGDONE) {
557                 *evt |= EVENT_CC;
558                 regmap_read(chip->regmap, FUSB_REG_STATUS1A, &val);
559                 chip->cc_state = ((u8)val >> 3) & 0x07;
560
561                 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
562                                    CONTROL2_TOGGLE,
563                                    0);
564
565                 val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
566                          SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
567
568                 if (chip->cc_state | 0x01)
569                         val |= SWITCHES0_PU_EN1;
570                 else
571                         val |= SWITCHES0_PU_EN2;
572
573                 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
574                                    SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
575                                    SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
576                                    val);
577         }
578
579         if (interrupta & INTERRUPTA_TXSENT) {
580                 *evt |= EVENT_TX;
581                 fusb302_flush_rx_fifo(chip);
582                 chip->tx_state = tx_success;
583         }
584
585         if (interruptb & INTERRUPTB_GCRCSENT)
586                 *evt |= EVENT_RX;
587
588         if (interrupta & INTERRUPTA_HARDRST) {
589                 fusb302_pd_reset(chip);
590                 pd_execute_hard_reset(chip);
591                 *evt |= EVENT_REC_RESET;
592         }
593
594         if (interrupta & INTERRUPTA_RETRYFAIL) {
595                 *evt |= EVENT_TX;
596                 chip->tx_state = tx_failed;
597         }
598
599         if (interrupta & INTERRUPTA_HARDSENT) {
600                 chip->tx_state = tx_success;
601                 chip->timer_state = T_DISABLED;
602                 *evt |= EVENT_TX;
603         }
604 }
605
606 static void mux_alert(struct fusb30x_chip *chip, int *evt)
607 {
608         if (!chip->timer_mux) {
609                 *evt |= EVENT_TIMER_MUX;
610                 chip->timer_mux = T_DISABLED;
611         }
612
613         if (!chip->timer_state) {
614                 *evt |= EVENT_TIMER_STATE;
615                 chip->timer_state = T_DISABLED;
616         }
617
618         if (chip->work_continue) {
619                 *evt |= EVENT_WORK_CONTINUE;
620                 chip->work_continue = 0;
621         }
622 }
623
624 static void set_state_unattached(struct fusb30x_chip *chip)
625 {
626         dev_info(chip->dev, "connection has disconnected\n");
627         tcpm_init(chip);
628         tcpm_set_rx_enable(chip, 0);
629         chip->conn_state = unattached;
630         tcpm_set_cc(chip, FUSB_MODE_DRP);
631
632         /* claer notify_info */
633         memset(&chip->notify, 0, sizeof(struct notify_info));
634         platform_fusb_notify(chip);
635
636         msleep(100);
637 }
638
639 static int tcpm_check_vbus(struct fusb30x_chip *chip)
640 {
641         u8 val;
642
643         /* Read status register */
644         regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)&val);
645
646         return (val & STATUS0_VBUSOK) ? 1 : 0;
647 }
648
649 static void set_mesg(struct fusb30x_chip *chip, int cmd, int is_DMT)
650 {
651         int i;
652         struct PD_CAP_INFO *pd_cap_info = &chip->pd_cap_info;
653
654         chip->send_head = ((chip->msg_id & 0x7) << 9) |
655                          ((chip->notify.power_role & 0x1) << 8) |
656                          (1 << 6) |
657                          ((chip->notify.data_role & 0x1) << 5);
658
659         if (is_DMT) {
660                 switch (cmd) {
661                 case DMT_SOURCECAPABILITIES:
662                         chip->send_head |= ((chip->n_caps_used & 0x3) << 12) | (cmd & 0xf);
663
664                         for (i = 0; i < chip->n_caps_used; i++) {
665                                 chip->send_load[i] = (pd_cap_info->supply_type << 30) |
666                                                     (pd_cap_info->dual_role_power << 29) |
667                                                     (pd_cap_info->usb_suspend_support << 28) |
668                                                     (pd_cap_info->externally_powered << 27) |
669                                                     (pd_cap_info->usb_communications_cap << 26) |
670                                                     (pd_cap_info->data_role_swap << 25) |
671                                                     (pd_cap_info->peak_current << 20) |
672                                                     (chip->source_power_supply[i] << 10) |
673                                                     (chip->source_max_current[i]);
674                         }
675                         break;
676                 case DMT_REQUEST:
677                         chip->send_head |= ((1 << 12) | (cmd & 0xf));
678                         /* send request with FVRDO */
679                         chip->send_load[0] = (chip->pos_power << 28) |
680                                             (0 << 27) |
681                                             (1 << 26) |
682                                             (0 << 25) |
683                                             (0 << 24);
684
685                         switch (CAP_POWER_TYPE(chip->rec_load[chip->pos_power - 1])) {
686                         case 0:
687                                 /* Fixed Supply */
688                                 chip->send_load[0] |= ((CAP_FPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
689                                 chip->send_load[0] |= (CAP_FPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
690                                 break;
691                         case 1:
692                                 /* Battery */
693                                 chip->send_load[0] |= ((CAP_VPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
694                                 chip->send_load[0] |= (CAP_VPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
695                                 break;
696                         default:
697                                 /* not meet battery caps */
698                                 break;
699                         }
700                         break;
701                 case DMT_SINKCAPABILITIES:
702                         break;
703                 case DMT_VENDERDEFINED:
704                         break;
705                 default:
706                         break;
707                 }
708         } else {
709                 chip->send_head |= (cmd & 0xf);
710         }
711 }
712
713 static void set_vdm_mesg(struct fusb30x_chip *chip, int cmd, int type, int mode)
714 {
715         chip->send_head = (chip->msg_id & 0x7) << 9;
716         chip->send_head |= (chip->notify.power_role & 0x1) << 8;
717
718         chip->send_head = ((chip->msg_id & 0x7) << 9) |
719                          ((chip->notify.power_role & 0x1) << 8) |
720                          (1 << 6) |
721                          ((chip->notify.data_role & 0x1) << 5) |
722                          (DMT_VENDERDEFINED & 0xf);
723
724         chip->send_load[0] = (1 << 15) |
725                             (0 << 13) |
726                             (type << 6) |
727                             (cmd);
728
729         switch (cmd) {
730         case VDM_DISCOVERY_ID:
731         case VDM_DISCOVERY_SVIDS:
732         case VDM_ATTENTION:
733                 chip->send_load[0] |= (0xff00 << 16);
734                 chip->send_head |= (1 << 12);
735                 break;
736         case VDM_DISCOVERY_MODES:
737                 chip->send_load[0] |=
738                         (chip->vdm_svid[chip->val_tmp >> 1] << 16);
739                 chip->send_head |= (1 << 12);
740                 break;
741         case VDM_ENTER_MODE:
742                 chip->send_head |= (1 << 12);
743                 chip->send_load[0] |= (mode << 8) | (0xff01 << 16);
744                 break;
745         case VDM_EXIT_MODE:
746                 chip->send_head |= (1 << 12);
747                 chip->send_load[0] |= (0x0f << 8) | (0xff01 << 16);
748                 break;
749         case VDM_DP_STATUS_UPDATE:
750                 chip->send_head |= (2 << 12);
751                 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
752                 chip->send_load[1] = 5;
753                 break;
754         case VDM_DP_CONFIG:
755                 chip->send_head |= (2 << 12);
756                 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
757                 chip->send_load[1] = (chip->notify.pin_assignment_def << 8) |
758                                     (1 << 2) | 2;
759                 break;
760         default:
761                 break;
762         }
763 }
764
765 static enum tx_state policy_send_hardrst(struct fusb30x_chip *chip, int evt)
766 {
767         switch (chip->tx_state) {
768         case 0:
769                 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
770                                    CONTROL3_SEND_HARDRESET,
771                                    CONTROL3_SEND_HARDRESET);
772                 chip->tx_state = tx_busy;
773                 chip->timer_state = T_BMC_TIMEOUT;
774                 fusb_timer_start(&chip->timer_state_machine,
775                                  chip->timer_state);
776                 break;
777         default:
778                 if (evt & EVENT_TIMER_STATE)
779                         chip->tx_state = tx_success;
780                 break;
781         }
782         return chip->tx_state;
783 }
784
785 static enum tx_state policy_send_data(struct fusb30x_chip *chip)
786 {
787         u8 senddata[40];
788         int pos = 0;
789         u8 len;
790
791         switch (chip->tx_state) {
792         case 0:
793                 senddata[pos++] = FUSB_TKN_SYNC1;
794                 senddata[pos++] = FUSB_TKN_SYNC1;
795                 senddata[pos++] = FUSB_TKN_SYNC1;
796                 senddata[pos++] = FUSB_TKN_SYNC2;
797
798                 len = PD_HEADER_CNT(chip->send_head) << 2;
799                 senddata[pos++] = FUSB_TKN_PACKSYM | ((len + 2) & 0x1f);
800
801                 senddata[pos++] = chip->send_head & 0xff;
802                 senddata[pos++] = (chip->send_head >> 8) & 0xff;
803
804                 memcpy(&senddata[pos], chip->send_load, len);
805                 pos += len;
806
807                 senddata[pos++] = FUSB_TKN_JAMCRC;
808                 senddata[pos++] = FUSB_TKN_EOP;
809                 senddata[pos++] = FUSB_TKN_TXOFF;
810                 senddata[pos++] = FUSB_TKN_TXON;
811
812                 regmap_raw_write(chip->regmap, FUSB_REG_FIFO, senddata, pos);
813                 chip->tx_state = tx_busy;
814                 break;
815
816         default:
817                 /* wait Tx result */
818                 break;
819         }
820
821         return chip->tx_state;
822 }
823
824 static void process_vdm_msg(struct fusb30x_chip *chip)
825 {
826         u32 vdm_header = chip->rec_load[0];
827         int i;
828         u32 tmp;
829
830         /* can't procee unstructed vdm msg */
831         if (!GET_VDMHEAD_STRUCT_TYPE(vdm_header))
832                 return;
833
834         switch (GET_VDMHEAD_CMD_TYPE(vdm_header)) {
835         case VDM_TYPE_INIT:
836                 switch (GET_VDMHEAD_CMD(vdm_header)) {
837                 case VDM_ATTENTION:
838                         dev_info(chip->dev, "attention, dp_status %x\n",
839                                  chip->rec_load[1]);
840                         chip->notify.attention = 1;
841                         chip->vdm_state = 6;
842                         break;
843                 default:
844                         dev_warn(chip->dev, "rec unknown init vdm msg\n");
845                         break;
846                 }
847                 break;
848         case VDM_TYPE_ACK:
849                 switch (GET_VDMHEAD_CMD(vdm_header)) {
850                 case VDM_DISCOVERY_ID:
851                         chip->vdm_id = chip->rec_load[1];
852                         break;
853                 case VDM_DISCOVERY_SVIDS:
854                         for (i = 0; i < 6; i++) {
855                                 tmp = (chip->rec_load[i + 1] >> 16) &
856                                       0x0000ffff;
857                                 if (tmp) {
858                                         chip->vdm_svid[i * 2] = tmp;
859                                         chip->vdm_svid_num++;
860                                 } else {
861                                         break;
862                                 }
863
864                                 tmp = (chip->rec_load[i + 1] & 0x0000ffff);
865                                 if (tmp) {
866                                         chip->vdm_svid[i * 2 + 1] = tmp;
867                                         chip->vdm_svid_num++;
868                                 } else {
869                                         break;
870                                 }
871                         }
872                         break;
873                 case VDM_DISCOVERY_MODES:
874                         /* indicate there are some vdo modes */
875                         if (PD_HEADER_CNT(chip->rec_head) > 1) {
876                                 /*
877                                  * store mode config,
878                                  * enter first mode default
879                                  */
880                                 if (!((chip->rec_load[1] >> 8) & 0x3f)) {
881                                         chip->val_tmp |= 1;
882                                         break;
883                                 }
884                                 chip->notify.pin_assignment_support = 0;
885                                 chip->notify.pin_assignment_def = 0;
886                                 chip->notify.pin_assignment_support =
887                                         (chip->rec_load[1] >> 8) & 0x3f;
888                                 tmp = chip->notify.pin_assignment_support;
889                                 for (i = 0; i < 6; i++) {
890                                         if (!(tmp & 0x20))
891                                                 tmp = tmp << 1;
892                                         else
893                                                 break;
894                                 }
895                                 chip->notify.pin_assignment_def = 0x20 >> i;
896                                 chip->val_tmp |= 1;
897                         }
898                         break;
899                 case VDM_ENTER_MODE:
900                         chip->val_tmp = 1;
901                         break;
902                 case VDM_DP_STATUS_UPDATE:
903                         dev_dbg(chip->dev, "dp_status 0x%x\n",
904                                 chip->rec_load[1]);
905                         chip->val_tmp = 1;
906                         break;
907                 case VDM_DP_CONFIG:
908                         chip->val_tmp = 1;
909                         dev_info(chip->dev,
910                                  "DP config successful, pin_assignment 0x%x\n",
911                                  chip->notify.pin_assignment_def);
912                         chip->notify.is_enter_mode = 1;
913                         break;
914                 default:
915                         break;
916                 }
917                 break;
918         case VDM_TYPE_NACK:
919                         dev_warn(chip->dev, "REC NACK for 0x%x\n",
920                                  GET_VDMHEAD_CMD(vdm_header));
921                         /* disable vdm */
922                         chip->vdm_state = 0xff;
923                 break;
924         }
925 }
926
927 static int vdm_send_discoveryid(struct fusb30x_chip *chip, int evt)
928 {
929         int tmp;
930
931         switch (chip->vdm_send_state) {
932         case 0:
933                 set_vdm_mesg(chip, VDM_DISCOVERY_ID, VDM_TYPE_INIT, 0);
934                 chip->vdm_id = 0;
935                 chip->tx_state = 0;
936                 chip->vdm_send_state++;
937         case 1:
938                 tmp = policy_send_data(chip);
939                 if (tmp == tx_success) {
940                         chip->vdm_send_state++;
941                         chip->timer_state = T_SENDER_RESPONSE;
942                         fusb_timer_start(&chip->timer_state_machine,
943                                          chip->timer_state);
944                 } else if (tmp == tx_failed) {
945                         dev_warn(chip->dev, "VDM_DISCOVERY_ID send failed\n");
946                         /* disable auto_vdm_machine */
947                         chip->vdm_state = 0xff;
948                 }
949
950                 if (chip->vdm_send_state != 2)
951                         break;
952         default:
953                 if (evt & EVENT_TIMER_STATE) {
954                         dev_warn(chip->dev, "VDM_DISCOVERY_ID time out\n");
955                         chip->vdm_state = 0xff;
956                         chip->work_continue = 1;
957                 }
958
959                 if (!chip->vdm_id)
960                         break;
961                 chip->vdm_send_state = 0;
962                 return 0;
963         }
964         return -EINPROGRESS;
965 }
966
967 static int vdm_send_discoverysvid(struct fusb30x_chip *chip, int evt)
968 {
969         int tmp;
970
971         switch (chip->vdm_send_state) {
972         case 0:
973                 set_vdm_mesg(chip, VDM_DISCOVERY_SVIDS, VDM_TYPE_INIT, 0);
974                 memset(chip->vdm_svid, 0, 12);
975                 chip->vdm_svid_num = 0;
976                 chip->tx_state = 0;
977                 chip->vdm_send_state++;
978         case 1:
979                 tmp = policy_send_data(chip);
980                 if (tmp == tx_success) {
981                         chip->vdm_send_state++;
982                         chip->timer_state = T_SENDER_RESPONSE;
983                         fusb_timer_start(&chip->timer_state_machine,
984                                          chip->timer_state);
985                 } else if (tmp == tx_failed) {
986                         dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS send failed\n");
987                         /* disable auto_vdm_machine */
988                         chip->vdm_state = 0xff;
989                 }
990
991                 if (chip->vdm_send_state != 2)
992                         break;
993         default:
994                 if (evt & EVENT_TIMER_STATE) {
995                         dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS time out\n");
996                         chip->vdm_state = 0xff;
997                         chip->work_continue = 1;
998                 }
999
1000                 if (!chip->vdm_svid_num)
1001                         break;
1002                 chip->vdm_send_state = 0;
1003                 return 0;
1004         }
1005         return -EINPROGRESS;
1006 }
1007
1008 static int vdm_send_discoverymodes(struct fusb30x_chip *chip, int evt)
1009 {
1010         int tmp;
1011
1012         if ((chip->val_tmp >> 1) != chip->vdm_svid_num) {
1013                 switch (chip->vdm_send_state) {
1014                 case 0:
1015                         set_vdm_mesg(chip, VDM_DISCOVERY_MODES,
1016                                      VDM_TYPE_INIT, 0);
1017                         chip->tx_state = 0;
1018                         chip->vdm_send_state++;
1019                 case 1:
1020                         tmp = policy_send_data(chip);
1021                         if (tmp == tx_success) {
1022                                 chip->vdm_send_state++;
1023                                 chip->timer_state = T_SENDER_RESPONSE;
1024                                 fusb_timer_start(&chip->timer_state_machine,
1025                                                  chip->timer_state);
1026                         } else if (tmp == tx_failed) {
1027                                 dev_warn(chip->dev,
1028                                          "VDM_DISCOVERY_MODES send failed\n");
1029                                 chip->vdm_state = 0xff;
1030                         }
1031
1032                         if (chip->vdm_send_state != 2)
1033                                 break;
1034                 default:
1035                         if (evt & EVENT_TIMER_STATE) {
1036                                 dev_warn(chip->dev,
1037                                          "VDM_DISCOVERY_MODES time out\n");
1038                                 chip->vdm_state = 0xff;
1039                                 chip->work_continue = 1;
1040                         }
1041
1042                         if (!(chip->val_tmp & 1))
1043                                 break;
1044                         chip->val_tmp &= 0xfe;
1045                         chip->val_tmp += 2;
1046                         chip->vdm_send_state = 0;
1047                         chip->work_continue = 1;
1048                         break;
1049                 }
1050         } else {
1051                 chip->val_tmp = 0;
1052                 return 0;
1053         }
1054
1055         return -EINPROGRESS;
1056 }
1057
1058 static int vdm_send_entermode(struct fusb30x_chip *chip, int evt)
1059 {
1060         int tmp;
1061
1062         switch (chip->vdm_send_state) {
1063         case 0:
1064                 set_vdm_mesg(chip, VDM_ENTER_MODE, VDM_TYPE_INIT, 1);
1065                 chip->tx_state = 0;
1066                 chip->vdm_send_state++;
1067                 chip->notify.is_enter_mode = 0;
1068         case 1:
1069                 tmp = policy_send_data(chip);
1070                 if (tmp == tx_success) {
1071                         chip->vdm_send_state++;
1072                         chip->timer_state = T_SENDER_RESPONSE;
1073                         fusb_timer_start(&chip->timer_state_machine,
1074                                          chip->timer_state);
1075                 } else if (tmp == tx_failed) {
1076                         dev_warn(chip->dev, "VDM_ENTER_MODE send failed\n");
1077                         /* disable auto_vdm_machine */
1078                         chip->vdm_state = 0xff;
1079                 }
1080
1081                 if (chip->vdm_send_state != 2)
1082                         break;
1083         default:
1084                 if (evt & EVENT_TIMER_STATE) {
1085                         dev_warn(chip->dev, "VDM_ENTER_MODE time out\n");
1086                         chip->vdm_state = 0xff;
1087                         chip->work_continue = 1;
1088                 }
1089
1090                 if (!chip->val_tmp)
1091                         break;
1092                 chip->val_tmp = 0;
1093                 chip->vdm_send_state = 0;
1094                 return 0;
1095         }
1096         return -EINPROGRESS;
1097 }
1098
1099 static int vdm_send_getdpstatus(struct fusb30x_chip *chip, int evt)
1100 {
1101         int tmp;
1102
1103         switch (chip->vdm_send_state) {
1104         case 0:
1105                 set_vdm_mesg(chip, VDM_DP_STATUS_UPDATE, VDM_TYPE_INIT, 1);
1106                 chip->tx_state = 0;
1107                 chip->vdm_send_state++;
1108         case 1:
1109                 tmp = policy_send_data(chip);
1110                 if (tmp == tx_success) {
1111                         chip->vdm_send_state++;
1112                         chip->timer_state = T_SENDER_RESPONSE;
1113                         fusb_timer_start(&chip->timer_state_machine,
1114                                          chip->timer_state);
1115                 } else if (tmp == tx_failed) {
1116                         dev_warn(chip->dev,
1117                                  "VDM_DP_STATUS_UPDATE send failed\n");
1118                         /* disable auto_vdm_machine */
1119                         chip->vdm_state = 0xff;
1120                 }
1121
1122                 if (chip->vdm_send_state != 2)
1123                         break;
1124         default:
1125                 if (evt & EVENT_TIMER_STATE) {
1126                         dev_warn(chip->dev, "VDM_DP_STATUS_UPDATE time out\n");
1127                         chip->vdm_state = 0xff;
1128                         chip->work_continue = 1;
1129                 }
1130
1131                 if (!chip->val_tmp)
1132                         break;
1133                 chip->val_tmp = 0;
1134                 chip->vdm_send_state = 0;
1135                 return 0;
1136         }
1137         return -EINPROGRESS;
1138 }
1139
1140 static int vdm_send_dpconfig(struct fusb30x_chip *chip, int evt)
1141 {
1142         int tmp;
1143
1144         switch (chip->vdm_send_state) {
1145         case 0:
1146                 set_vdm_mesg(chip, VDM_DP_CONFIG, VDM_TYPE_INIT, 0);
1147                 chip->tx_state = 0;
1148                 chip->vdm_send_state++;
1149         case 1:
1150                 tmp = policy_send_data(chip);
1151                 if (tmp == tx_success) {
1152                         chip->vdm_send_state++;
1153                         chip->timer_state = T_SENDER_RESPONSE;
1154                         fusb_timer_start(&chip->timer_state_machine,
1155                                          chip->timer_state);
1156                 } else if (tmp == tx_failed) {
1157                         dev_warn(chip->dev, "vdm_send_dpconfig send failed\n");
1158                         /* disable auto_vdm_machine */
1159                         chip->vdm_state = 0xff;
1160                 }
1161
1162                 if (chip->vdm_send_state != 2)
1163                         break;
1164         default:
1165                 if (evt & EVENT_TIMER_STATE) {
1166                         dev_warn(chip->dev, "vdm_send_dpconfig time out\n");
1167                         chip->vdm_state = 0xff;
1168                         chip->work_continue = 1;
1169                 }
1170
1171                 if (!chip->val_tmp)
1172                         break;
1173                 chip->val_tmp = 0;
1174                 chip->vdm_send_state = 0;
1175                 return 0;
1176         }
1177         return -EINPROGRESS;
1178 }
1179
1180 static void auto_vdm_machine(struct fusb30x_chip *chip, int evt)
1181 {
1182         switch (chip->vdm_state) {
1183         case 0:
1184                 if (vdm_send_discoveryid(chip, evt))
1185                         break;
1186                 chip->vdm_state++;
1187                 /* without break */
1188         case 1:
1189                 if (vdm_send_discoverysvid(chip, evt))
1190                         break;
1191                 chip->vdm_state++;
1192                 /* without break */
1193         case 2:
1194                 if (vdm_send_discoverymodes(chip, evt))
1195                         break;
1196                 chip->vdm_state++;
1197                 /* without break */
1198         case 3:
1199                 if (vdm_send_entermode(chip, evt))
1200                         break;
1201                 chip->vdm_state++;
1202                 /* without break */
1203         case 4:
1204                 if (vdm_send_dpconfig(chip, evt))
1205                         break;
1206                 chip->vdm_state = 6;
1207                 /* without break */
1208         case 5:
1209                 if (vdm_send_getdpstatus(chip, evt))
1210                         break;
1211                 chip->vdm_state++;
1212                 /* without break */
1213         default:
1214                 platform_fusb_notify(chip);
1215                 break;
1216         }
1217 }
1218
1219 static void fusb_state_disabled(struct fusb30x_chip *chip, int evt)
1220 {
1221         platform_fusb_notify(chip);
1222 }
1223
1224 static void fusb_state_unattached(struct fusb30x_chip *chip, int evt)
1225 {
1226         chip->notify.is_cc_connected = 0;
1227         if ((evt & EVENT_CC) && chip->cc_state) {
1228                 if (chip->cc_state & 0x04)
1229                         set_state(chip, attach_wait_sink);
1230                 else
1231                         set_state(chip, attach_wait_source);
1232
1233                 tcpm_get_cc(chip, &chip->cc1, &chip->cc2);
1234                 chip->debounce_cnt = 0;
1235                 chip->timer_mux = 2;
1236                 fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux);
1237         }
1238 }
1239
1240 static void fusb_state_attach_wait_sink(struct fusb30x_chip *chip, int evt)
1241 {
1242         int cc1, cc2;
1243
1244         if (evt & EVENT_TIMER_MUX) {
1245                 tcpm_get_cc(chip, &cc1, &cc2);
1246
1247                 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1248                         chip->debounce_cnt++;
1249                 } else {
1250                         chip->cc1 = cc1;
1251                         chip->cc2 = cc2;
1252                         chip->debounce_cnt = 0;
1253                 }
1254
1255                 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1256                         if ((chip->cc1 != chip->cc2) &&
1257                             ((!chip->cc1) || (!chip->cc2))) {
1258                                 set_state(chip, attached_sink);
1259                         } else {
1260                                 set_state_unattached(chip);
1261                         }
1262                         return;
1263                 }
1264
1265                 chip->timer_mux = 2;
1266                 fusb_timer_start(&chip->timer_mux_machine,
1267                                  chip->timer_mux);
1268         }
1269 }
1270
1271 static void fusb_state_attach_wait_source(struct fusb30x_chip *chip, int evt)
1272 {
1273         int cc1, cc2;
1274
1275         if (evt & EVENT_TIMER_MUX) {
1276                 tcpm_get_cc(chip, &cc1, &cc2);
1277
1278                 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1279                         chip->debounce_cnt++;
1280                         tcpm_set_polarity(chip, !(chip->cc_state & 0x01));
1281                         platform_set_vbus_lvl_enable(chip, 1, 0);
1282                         tcpm_set_vconn(chip, 1);
1283                 } else {
1284                         chip->cc1 = cc1;
1285                         chip->cc2 = cc2;
1286                         chip->debounce_cnt = 0;
1287                 }
1288
1289                 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1290                         if (((!chip->cc1) || (!chip->cc2)) &&
1291                             ((chip->cc1 == TYPEC_CC_VOLT_RD) ||
1292                              (chip->cc2 == TYPEC_CC_VOLT_RD))) {
1293                                 set_state(chip, attached_source);
1294                         } else {
1295                                 set_state_unattached(chip);
1296                         }
1297
1298                         return;
1299                 }
1300
1301                 chip->timer_mux = 2;
1302                 fusb_timer_start(&chip->timer_mux_machine,
1303                                  chip->timer_mux);
1304         }
1305 }
1306
1307 static void fusb_state_attached_source(struct fusb30x_chip *chip, int evt)
1308 {
1309         chip->notify.is_cc_connected = 1;
1310         if (chip->cc_state & 0x01)
1311                 chip->cc_polarity = 0;
1312         else
1313                 chip->cc_polarity = 1;
1314
1315         chip->notify.power_role = 1;
1316         chip->notify.data_role = 1;
1317         chip->hardrst_count = 0;
1318         set_state(chip, policy_src_startup);
1319         dev_info(chip->dev, "CC connected in %d as DFP\n", chip->cc_polarity);
1320 }
1321
1322 static void fusb_state_attached_sink(struct fusb30x_chip *chip, int evt)
1323 {
1324         chip->notify.is_cc_connected = 1;
1325         if (chip->cc_state & 0x01)
1326                 chip->cc_polarity = 0;
1327         else
1328                 chip->cc_polarity = 1;
1329
1330         chip->notify.power_role = 0;
1331         chip->notify.data_role = 0;
1332         chip->hardrst_count = 0;
1333         set_state(chip, policy_snk_startup);
1334         dev_info(chip->dev, "CC connected in %d as UFP\n", chip->cc_polarity);
1335 }
1336
1337 static void fusb_state_src_startup(struct fusb30x_chip *chip, int evt)
1338 {
1339         chip->caps_counter = 0;
1340         chip->notify.is_pd_connected = 0;
1341         chip->msg_id = 0;
1342         chip->vdm_state = 0;
1343         chip->vdm_substate = 0;
1344         chip->vdm_send_state = 0;
1345         chip->val_tmp = 0;
1346
1347         memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1348
1349         tcpm_set_msg_header(chip);
1350         tcpm_set_polarity(chip, chip->cc_polarity);
1351         tcpm_set_rx_enable(chip, 1);
1352
1353         set_state(chip, policy_src_send_caps);
1354 }
1355
1356 static void fusb_state_src_discovery(struct fusb30x_chip *chip, int evt)
1357 {
1358         switch (chip->sub_state) {
1359         case 0:
1360                 chip->caps_counter++;
1361
1362                 if (chip->caps_counter < N_CAPS_COUNT) {
1363                         chip->timer_state = T_TYPEC_SEND_SOURCECAP;
1364                         fusb_timer_start(&chip->timer_state_machine,
1365                                          chip->timer_state);
1366                         chip->sub_state = 1;
1367                 } else {
1368                         set_state(chip, disabled);
1369                 }
1370                 break;
1371         default:
1372                 if (evt & EVENT_TIMER_STATE) {
1373                         set_state(chip, policy_src_send_caps);
1374                 } else if ((evt & EVENT_TIMER_MUX) &&
1375                            (chip->hardrst_count > N_HARDRESET_COUNT)) {
1376                         if (chip->notify.is_pd_connected)
1377                                 set_state(chip, error_recovery);
1378                         else
1379                                 set_state(chip, disabled);
1380                 }
1381                 break;
1382         }
1383 }
1384
1385 static void fusb_state_src_send_caps(struct fusb30x_chip *chip, int evt)
1386 {
1387         u32 tmp;
1388
1389         switch (chip->sub_state) {
1390         case 0:
1391                 set_mesg(chip, DMT_SOURCECAPABILITIES, DATAMESSAGE);
1392                 chip->sub_state = 1;
1393                 chip->tx_state = tx_idle;
1394                 /* without break */
1395         case 1:
1396                 tmp = policy_send_data(chip);
1397
1398                 if (tmp == tx_success) {
1399                         chip->hardrst_count = 0;
1400                         chip->caps_counter = 0;
1401                         chip->timer_state = T_SENDER_RESPONSE;
1402                         fusb_timer_start(&chip->timer_state_machine,
1403                                          chip->timer_state);
1404                         chip->timer_mux = T_DISABLED;
1405                         chip->sub_state++;
1406                 } else if (tmp == tx_failed) {
1407                         set_state(chip, policy_src_discovery);
1408                         break;
1409                 }
1410
1411                 if (!(evt & FLAG_EVENT))
1412                         break;
1413         default:
1414                 if (evt & EVENT_RX) {
1415                         if ((PD_HEADER_CNT(chip->rec_head) == 1) &&
1416                             (PD_HEADER_TYPE(chip->rec_head) == DMT_REQUEST)) {
1417                                 set_state(chip, policy_src_negotiate_cap);
1418                         } else {
1419                                 set_state(chip, policy_src_send_softrst);
1420                         }
1421                 } else if (evt & EVENT_TIMER_STATE) {
1422                         if (chip->hardrst_count <= N_HARDRESET_COUNT)
1423                                 set_state(chip, policy_src_send_hardrst);
1424                         else
1425                                 set_state(chip, disabled);
1426                 } else if (evt & EVENT_TIMER_MUX) {
1427                         if (chip->notify.is_pd_connected)
1428                                 set_state(chip, disabled);
1429                         else
1430                                 set_state(chip, error_recovery);
1431                 }
1432                 break;
1433         }
1434 }
1435
1436 static void fusb_state_src_negotiate_cap(struct fusb30x_chip *chip, int evt)
1437 {
1438         u32 tmp;
1439
1440         /* base on evb1 */
1441         tmp = (chip->rec_load[0] >> 28) & 0x07;
1442         if (tmp > chip->n_caps_used)
1443                 set_state(chip, policy_src_cap_response);
1444         else
1445                 set_state(chip, policy_src_transition_supply);
1446 }
1447
1448 static void fusb_state_src_transition_supply(struct fusb30x_chip *chip,
1449                                              int evt)
1450 {
1451         u32 tmp;
1452
1453         switch (chip->sub_state) {
1454         case 0:
1455                 set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE);
1456                 chip->tx_state = tx_idle;
1457                 chip->sub_state++;
1458                 /* without break */
1459         case 1:
1460                 tmp = policy_send_data(chip);
1461                 if (tmp == tx_success) {
1462                         chip->timer_state = T_SRC_TRANSITION;
1463                         chip->sub_state++;
1464                         fusb_timer_start(&chip->timer_state_machine,
1465                                          chip->timer_state);
1466                 } else if (tmp == tx_failed) {
1467                         set_state(chip, policy_src_send_softrst);
1468                 }
1469                 break;
1470         case 2:
1471                 if (evt & EVENT_TIMER_STATE) {
1472                         chip->notify.is_pd_connected = 1;
1473                         platform_set_vbus_lvl_enable(chip, 1, 0);
1474                         set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE);
1475                         chip->tx_state = tx_idle;
1476                         chip->sub_state++;
1477                         chip->work_continue = 1;
1478                 }
1479                 break;
1480         default:
1481                 tmp = policy_send_data(chip);
1482                 if (tmp == tx_success) {
1483                         dev_info(chip->dev,
1484                                  "PD connected as DFP, supporting 5V\n");
1485                         set_state(chip, policy_src_ready);
1486                 } else if (tmp == tx_failed) {
1487                         set_state(chip, policy_src_send_softrst);
1488                 }
1489                 break;
1490         }
1491 }
1492
1493 static void fusb_state_src_cap_response(struct fusb30x_chip *chip, int evt)
1494 {
1495         u32 tmp;
1496
1497         switch (chip->sub_state) {
1498         case 0:
1499                 set_mesg(chip, CMT_REJECT, CONTROLMESSAGE);
1500                 chip->tx_state = tx_idle;
1501                 chip->sub_state++;
1502                 /* without break */
1503         default:
1504                 tmp = policy_send_data(chip);
1505                 if (tmp == tx_success) {
1506                         if (chip->notify.is_pd_connected) {
1507                                 dev_info(chip->dev,
1508                                          "PD connected as DFP, supporting 5V\n");
1509                                 set_state(chip, policy_src_ready);
1510                         } else {
1511                                 set_state(chip, policy_src_send_hardrst);
1512                         }
1513                 } else if (tmp == tx_failed) {
1514                         set_state(chip, policy_src_send_softrst);
1515                 }
1516                 break;
1517         }
1518 }
1519
1520 static void fusb_state_src_transition_default(struct fusb30x_chip *chip,
1521                                               int evt)
1522 {
1523         switch (chip->sub_state) {
1524         case 0:
1525                 chip->notify.is_pd_connected = 0;
1526                 platform_set_vbus_lvl_enable(chip, 0, 0);
1527                 if (chip->notify.data_role)
1528                         regmap_update_bits(chip->regmap,
1529                                            FUSB_REG_SWITCHES1,
1530                                            SWITCHES1_DATAROLE,
1531                                            SWITCHES1_DATAROLE);
1532                 else
1533                         regmap_update_bits(chip->regmap,
1534                                            FUSB_REG_SWITCHES1,
1535                                            SWITCHES1_DATAROLE,
1536                                            0);
1537
1538                 chip->timer_state = T_SRC_RECOVER;
1539                 fusb_timer_start(&chip->timer_state_machine,
1540                                  chip->timer_state);
1541                 chip->sub_state++;
1542                 break;
1543         default:
1544                 if (evt & EVENT_TIMER_STATE) {
1545                         platform_set_vbus_lvl_enable(chip, 1, 0);
1546                         chip->timer_mux = T_NO_RESPONSE;
1547                         fusb_timer_start(&chip->timer_mux_machine,
1548                                          chip->timer_mux);
1549                         set_state(chip, policy_src_startup);
1550                         dev_dbg(chip->dev, "reset over-> src startup\n");
1551                 }
1552                 break;
1553         }
1554 }
1555
1556 static void fusb_state_src_ready(struct fusb30x_chip *chip, int evt)
1557 {
1558         if (evt & EVENT_RX) {
1559                 if ((PD_HEADER_CNT(chip->rec_head)) &&
1560                     (PD_HEADER_TYPE(chip->rec_head) == DMT_VENDERDEFINED)) {
1561                         process_vdm_msg(chip);
1562                         chip->work_continue = 1;
1563                         chip->timer_state = T_DISABLED;
1564                 }
1565         }
1566
1567         /* TODO: swap function would be added here later on*/
1568
1569         if (!chip->partner_cap[0])
1570                 set_state(chip, policy_src_get_sink_caps);
1571         else
1572                 auto_vdm_machine(chip, evt);
1573 }
1574
1575 static void fusb_state_src_get_sink_cap(struct fusb30x_chip *chip, int evt)
1576 {
1577         u32 tmp;
1578
1579         switch (chip->sub_state) {
1580         case 0:
1581                 set_mesg(chip, CMT_GETSINKCAP, CONTROLMESSAGE);
1582                 chip->tx_state = tx_idle;
1583                 chip->sub_state++;
1584                 /* without break */
1585         case 1:
1586                 tmp = policy_send_data(chip);
1587                 if (tmp == tx_success) {
1588                         chip->timer_state = T_SENDER_RESPONSE;
1589                         chip->sub_state++;
1590                         fusb_timer_start(&chip->timer_state_machine,
1591                                          chip->timer_state);
1592                 } else if (tmp == tx_failed) {
1593                         set_state(chip, policy_src_send_softrst);
1594                 }
1595
1596                 if (!(evt & FLAG_EVENT))
1597                         break;
1598         default:
1599                 if (evt & EVENT_RX) {
1600                         if ((PD_HEADER_CNT(chip->rec_head)) &&
1601                             (PD_HEADER_TYPE(chip->rec_head) ==
1602                              DMT_SINKCAPABILITIES)) {
1603                                 for (tmp = 0;
1604                                      tmp < PD_HEADER_CNT(chip->rec_head);
1605                                      tmp++) {
1606                                         chip->partner_cap[tmp] =
1607                                                 chip->rec_load[tmp];
1608                                 }
1609                                 set_state(chip, policy_src_ready);
1610                         } else {
1611                                 chip->partner_cap[0] = 0xffffffff;
1612                                 set_state(chip, policy_src_ready);
1613                         }
1614                 } else if (evt & EVENT_TIMER_STATE) {
1615                         dev_warn(chip->dev, "Get sink cap time out\n");
1616                         chip->partner_cap[0] = 0xffffffff;
1617                         set_state(chip, policy_src_ready);
1618                 }
1619         }
1620 }
1621
1622 static void fusb_state_src_send_hardreset(struct fusb30x_chip *chip, int evt)
1623 {
1624         u32 tmp;
1625
1626         switch (chip->sub_state) {
1627         case 0:
1628                 chip->tx_state = tx_idle;
1629                 chip->sub_state++;
1630                 /* without break */
1631         default:
1632                 tmp = policy_send_hardrst(chip, evt);
1633                 if (tmp == tx_success) {
1634                         chip->hardrst_count++;
1635                         set_state(chip, policy_src_transition_default);
1636                 } else if (tmp == tx_failed) {
1637                         /* can't reach here */
1638                         set_state(chip, error_recovery);
1639                 }
1640                 break;
1641         }
1642 }
1643
1644 static void fusb_state_src_send_softreset(struct fusb30x_chip *chip, int evt)
1645 {
1646         u32 tmp;
1647
1648         switch (chip->sub_state) {
1649         case 0:
1650                 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1651                 chip->tx_state = tx_idle;
1652                 chip->sub_state++;
1653                 /* without break */
1654         case 1:
1655                 tmp = policy_send_data(chip);
1656                 if (tmp == tx_success) {
1657                         chip->timer_state = T_SENDER_RESPONSE;
1658                         chip->sub_state++;
1659                         fusb_timer_start(&chip->timer_state_machine,
1660                                          chip->timer_state);
1661                 } else if (tmp == tx_failed) {
1662                         set_state(chip, policy_src_send_hardrst);
1663                 }
1664
1665                 if (!(evt & FLAG_EVENT))
1666                         break;
1667         default:
1668                 if (evt & EVENT_RX) {
1669                         if ((!PD_HEADER_CNT(chip->rec_head)) &&
1670                             (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1671                                 set_state(chip, policy_src_send_caps);
1672                 } else if (evt & EVENT_TIMER_STATE) {
1673                         set_state(chip, policy_src_send_hardrst);
1674                 }
1675                 break;
1676         }
1677 }
1678
1679 static void fusb_state_snk_startup(struct fusb30x_chip *chip, int evt)
1680 {
1681         chip->notify.is_pd_connected = 0;
1682         chip->msg_id = 0;
1683         chip->vdm_state = 0;
1684         chip->vdm_substate = 0;
1685         chip->vdm_send_state = 0;
1686         chip->val_tmp = 0;
1687         chip->pos_power = 0;
1688
1689         memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1690
1691         tcpm_set_msg_header(chip);
1692         tcpm_set_polarity(chip, chip->cc_polarity);
1693         tcpm_set_rx_enable(chip, 1);
1694         set_state(chip, policy_snk_discovery);
1695 }
1696
1697 static void fusb_state_snk_discovery(struct fusb30x_chip *chip, int evt)
1698 {
1699         set_state(chip, policy_snk_wait_caps);
1700         chip->timer_state = T_TYPEC_SINK_WAIT_CAP;
1701         fusb_timer_start(&chip->timer_state_machine,
1702                          chip->timer_state);
1703 }
1704
1705 static void fusb_state_snk_wait_caps(struct fusb30x_chip *chip, int evt)
1706 {
1707         if (evt & EVENT_RX) {
1708                 if (PD_HEADER_CNT(chip->rec_head) &&
1709                     PD_HEADER_TYPE(chip->rec_head) == DMT_SOURCECAPABILITIES) {
1710                         chip->timer_mux = T_DISABLED;
1711                         set_state(chip, policy_snk_evaluate_caps);
1712                 }
1713         } else if (evt & EVENT_TIMER_STATE) {
1714                 if (chip->hardrst_count <= N_HARDRESET_COUNT)
1715                         set_state(chip, policy_snk_send_hardrst);
1716                 else
1717                         set_state(chip, disabled);
1718         } else if ((evt & EVENT_TIMER_MUX) &&
1719                    (chip->hardrst_count > N_HARDRESET_COUNT)) {
1720                 if (chip->notify.is_pd_connected)
1721                         set_state(chip, error_recovery);
1722                 else
1723                         set_state(chip, disabled);
1724         }
1725 }
1726
1727 static void fusb_state_snk_evaluate_caps(struct fusb30x_chip *chip, int evt)
1728 {
1729         u32 tmp;
1730
1731         chip->hardrst_count = 0;
1732         chip->pos_power = 0;
1733
1734         for (tmp = 0; tmp < PD_HEADER_CNT(chip->rec_head); tmp++) {
1735                 switch (CAP_POWER_TYPE(chip->rec_load[tmp])) {
1736                 case 0:
1737                         /* Fixed Supply */
1738                         if (CAP_FPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1739                                 chip->pos_power = tmp + 1;
1740                         break;
1741                 case 1:
1742                         /* Battery */
1743                         if (CAP_VPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1744                                 chip->pos_power = tmp + 1;
1745                         break;
1746                 default:
1747                         /* not meet battery caps */
1748                         break;
1749                 }
1750         }
1751
1752         if ((!chip->pos_power) || (chip->pos_power > 7)) {
1753                 chip->pos_power = 0;
1754                 set_state(chip, policy_snk_wait_caps);
1755         } else {
1756                 set_state(chip, policy_snk_select_cap);
1757         }
1758 }
1759
1760 static void fusb_state_snk_select_cap(struct fusb30x_chip *chip, int evt)
1761 {
1762         u32 tmp;
1763
1764         switch (chip->sub_state) {
1765         case 0:
1766                 set_mesg(chip, DMT_REQUEST, DATAMESSAGE);
1767                 chip->sub_state = 1;
1768                 chip->tx_state = tx_idle;
1769                 /* without break */
1770         case 1:
1771                 tmp = policy_send_data(chip);
1772
1773                 if (tmp == tx_success) {
1774                         chip->timer_state = T_SENDER_RESPONSE;
1775                         fusb_timer_start(&chip->timer_state_machine,
1776                                          chip->timer_state);
1777                         chip->sub_state++;
1778                 } else if (tmp == tx_failed) {
1779                         set_state(chip, policy_snk_discovery);
1780                         break;
1781                 }
1782
1783                 if (!(evt & FLAG_EVENT))
1784                         break;
1785         default:
1786                 if (evt & EVENT_RX) {
1787                         if (!PD_HEADER_CNT(chip->rec_head)) {
1788                                 switch (PD_HEADER_TYPE(chip->rec_head)) {
1789                                 case CMT_ACCEPT:
1790                                         set_state(chip,
1791                                                   policy_snk_transition_sink);
1792                                         chip->timer_state = T_PS_TRANSITION;
1793                                         fusb_timer_start(&chip->timer_state_machine,
1794                                                          chip->timer_state);
1795                                         break;
1796                                 case CMT_WAIT:
1797                                 case CMT_REJECT:
1798                                         if (chip->notify.is_pd_connected) {
1799                                                 dev_info(chip->dev,
1800                                                          "PD connected as UFP, fetching 5V\n");
1801                                                 set_state(chip,
1802                                                           policy_snk_ready);
1803                                         } else {
1804                                                 set_state(chip,
1805                                                           policy_snk_wait_caps);
1806                                                 /*
1807                                                  * make sure don't send
1808                                                  * hard reset to prevent
1809                                                  * infinite loop
1810                                                  */
1811                                                 chip->hardrst_count =
1812                                                         N_HARDRESET_COUNT + 1;
1813                                         }
1814                                         break;
1815                                 default:
1816                                         break;
1817                                 }
1818                         }
1819                 } else if (evt & EVENT_TIMER_STATE) {
1820                         set_state(chip, policy_snk_send_hardrst);
1821                 }
1822                 break;
1823         }
1824 }
1825
1826 static void fusb_state_snk_transition_sink(struct fusb30x_chip *chip, int evt)
1827 {
1828         if (evt & EVENT_RX) {
1829                 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1830                     (PD_HEADER_TYPE(chip->rec_head) == CMT_PS_RDY)) {
1831                         chip->notify.is_pd_connected = 1;
1832                         dev_info(chip->dev,
1833                                  "PD connected as UFP, fetching 5V\n");
1834                         set_state(chip, policy_snk_ready);
1835                 } else if ((PD_HEADER_CNT(chip->rec_head)) &&
1836                            (PD_HEADER_TYPE(chip->rec_head) ==
1837                             DMT_SOURCECAPABILITIES)) {
1838                         set_state(chip, policy_snk_evaluate_caps);
1839                 }
1840         } else if (evt & EVENT_TIMER_STATE) {
1841                 set_state(chip, policy_snk_send_hardrst);
1842         }
1843 }
1844
1845 static void fusb_state_snk_transition_default(struct fusb30x_chip *chip,
1846                                               int evt)
1847 {
1848         switch (chip->sub_state) {
1849         case 0:
1850                 chip->notify.is_pd_connected = 0;
1851                 chip->timer_mux = T_NO_RESPONSE;
1852                 fusb_timer_start(&chip->timer_mux_machine,
1853                                  chip->timer_mux);
1854                 chip->timer_state = T_PS_HARD_RESET_MAX + T_SAFE_0V;
1855                 fusb_timer_start(&chip->timer_state_machine,
1856                                  chip->timer_state);
1857                 if (chip->notify.data_role)
1858                         tcpm_set_msg_header(chip);
1859
1860                 chip->sub_state++;
1861         case 1:
1862                 if (!tcpm_check_vbus(chip)) {
1863                         chip->sub_state++;
1864                         chip->timer_state = T_SRC_RECOVER_MAX + T_SRC_TURN_ON;
1865                         fusb_timer_start(&chip->timer_state_machine,
1866                                          chip->timer_state);
1867                 } else if (evt & EVENT_TIMER_STATE) {
1868                         set_state(chip, policy_snk_startup);
1869                 }
1870                 break;
1871         default:
1872                 if (tcpm_check_vbus(chip)) {
1873                         chip->timer_state = T_DISABLED;
1874                         set_state(chip, policy_snk_startup);
1875                 } else if (evt & EVENT_TIMER_STATE) {
1876                         set_state(chip, policy_snk_startup);
1877                 }
1878                 break;
1879         }
1880 }
1881
1882 static void fusb_state_snk_ready(struct fusb30x_chip *chip, int evt)
1883 {
1884         /* TODO: snk_ready_function would be added later on*/
1885         platform_fusb_notify(chip);
1886 }
1887
1888 static void fusb_state_snk_send_hardreset(struct fusb30x_chip *chip, int evt)
1889 {
1890         u32 tmp;
1891
1892         switch (chip->sub_state) {
1893         case 0:
1894                 chip->tx_state = tx_idle;
1895                 chip->sub_state++;
1896         default:
1897                 tmp = policy_send_hardrst(chip, evt);
1898                 if (tmp == tx_success) {
1899                         chip->hardrst_count++;
1900                         set_state(chip, policy_snk_transition_default);
1901                 } else if (tmp == tx_failed) {
1902                         set_state(chip, error_recovery);
1903                 }
1904                 break;
1905         }
1906 }
1907
1908 static void fusb_state_snk_send_softreset(struct fusb30x_chip *chip, int evt)
1909 {
1910         u32 tmp;
1911
1912         switch (chip->sub_state) {
1913         case 0:
1914                 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1915                 chip->tx_state = tx_idle;
1916                 chip->sub_state++;
1917         case 1:
1918                 tmp = policy_send_data(chip);
1919                 if (tmp == tx_success) {
1920                         chip->timer_state = T_SENDER_RESPONSE;
1921                         chip->sub_state++;
1922                         fusb_timer_start(&chip->timer_state_machine,
1923                                          chip->timer_state);
1924                 } else if (tmp == tx_failed) {
1925                         /* can't reach here */
1926                         set_state(chip, policy_snk_send_hardrst);
1927                 }
1928
1929                 if (!(evt & FLAG_EVENT))
1930                         break;
1931         default:
1932                 if (evt & EVENT_RX) {
1933                         if ((!PD_HEADER_CNT(chip->rec_head)) &&
1934                             (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1935                                 set_state(chip, policy_snk_wait_caps);
1936                 } else if (evt & EVENT_TIMER_STATE) {
1937                         set_state(chip, policy_snk_send_hardrst);
1938                 }
1939                 break;
1940         }
1941 }
1942
1943 static void state_machine_typec(struct fusb30x_chip *chip)
1944 {
1945         int evt = 0;
1946         int cc1, cc2;
1947
1948         tcpc_alert(chip, &evt);
1949         mux_alert(chip, &evt);
1950         if (!evt)
1951                 goto BACK;
1952
1953         if (chip->notify.is_cc_connected) {
1954                 if (evt & EVENT_CC) {
1955                         if ((chip->cc_state & 0x04) &&
1956                             (chip->conn_state !=
1957                              policy_snk_transition_default)) {
1958                                 if (!tcpm_check_vbus(chip))
1959                                         set_state_unattached(chip);
1960                         } else if (chip->conn_state !=
1961                                    policy_src_transition_default) {
1962                                 tcpm_get_cc(chip, &cc1, &cc2);
1963                                 if (!(chip->cc_state & 0x01))
1964                                         cc1 = cc2;
1965                                 if (cc1 == TYPEC_CC_VOLT_OPEN)
1966                                         set_state_unattached(chip);
1967                         }
1968                 }
1969         }
1970
1971         if (evt & EVENT_RX) {
1972                 tcpm_get_message(chip);
1973                 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1974                     (PD_HEADER_TYPE(chip->rec_head) == CMT_SOFTRESET)) {
1975                         if (chip->notify.power_role)
1976                                 set_state(chip, policy_src_send_softrst);
1977                         else
1978                                 set_state(chip, policy_snk_send_softrst);
1979                 }
1980         }
1981
1982         if (evt & EVENT_TX) {
1983                 if (chip->tx_state == tx_success)
1984                         chip->msg_id++;
1985         }
1986         switch (chip->conn_state) {
1987         case disabled:
1988                 fusb_state_disabled(chip, evt);
1989                 break;
1990         case error_recovery:
1991                 set_state_unattached(chip);
1992                 break;
1993         case unattached:
1994                 fusb_state_unattached(chip, evt);
1995                 break;
1996         case attach_wait_sink:
1997                 fusb_state_attach_wait_sink(chip, evt);
1998                 break;
1999         case attach_wait_source:
2000                 fusb_state_attach_wait_source(chip, evt);
2001                 break;
2002         case attached_source:
2003                 fusb_state_attached_source(chip, evt);
2004                 break;
2005         case attached_sink:
2006                 fusb_state_attached_sink(chip, evt);
2007                 break;
2008
2009         /* POWER DELIVERY */
2010         case policy_src_startup:
2011                 fusb_state_src_startup(chip, evt);
2012                 break;
2013         case policy_src_discovery:
2014                 fusb_state_src_discovery(chip, evt);
2015                 break;
2016         case policy_src_send_caps:
2017                 fusb_state_src_send_caps(chip, evt);
2018                 if (chip->conn_state != policy_src_negotiate_cap)
2019                         break;
2020         case policy_src_negotiate_cap:
2021                 fusb_state_src_negotiate_cap(chip, evt);
2022
2023         case policy_src_transition_supply:
2024                 fusb_state_src_transition_supply(chip, evt);
2025                 break;
2026         case policy_src_cap_response:
2027                 fusb_state_src_cap_response(chip, evt);
2028                 break;
2029         case policy_src_transition_default:
2030                 fusb_state_src_transition_default(chip, evt);
2031                 break;
2032         case policy_src_ready:
2033                 fusb_state_src_ready(chip, evt);
2034                 break;
2035         case policy_src_get_sink_caps:
2036                 fusb_state_src_get_sink_cap(chip, evt);
2037                 break;
2038         case policy_src_send_hardrst:
2039                 fusb_state_src_send_hardreset(chip, evt);
2040                 break;
2041         case policy_src_send_softrst:
2042                 fusb_state_src_send_softreset(chip, evt);
2043                 break;
2044
2045         /* UFP */
2046         case policy_snk_startup:
2047                 fusb_state_snk_startup(chip, evt);
2048                 break;
2049         case policy_snk_discovery:
2050                 fusb_state_snk_discovery(chip, evt);
2051                 break;
2052         case policy_snk_wait_caps:
2053                 fusb_state_snk_wait_caps(chip, evt);
2054                 break;
2055         case policy_snk_evaluate_caps:
2056                 fusb_state_snk_evaluate_caps(chip, evt);
2057                 /* without break */
2058         case policy_snk_select_cap:
2059                 fusb_state_snk_select_cap(chip, evt);
2060                 break;
2061         case policy_snk_transition_sink:
2062                 fusb_state_snk_transition_sink(chip, evt);
2063                 break;
2064         case policy_snk_transition_default:
2065                 fusb_state_snk_transition_default(chip, evt);
2066                 break;
2067         case policy_snk_ready:
2068                 fusb_state_snk_ready(chip, evt);
2069                 break;
2070         case policy_snk_send_hardrst:
2071                 fusb_state_snk_send_hardreset(chip, evt);
2072                 break;
2073         case policy_snk_send_softrst:
2074                 fusb_state_snk_send_softreset(chip, evt);
2075                 break;
2076
2077         default:
2078                 break;
2079         }
2080
2081 BACK:
2082         if (chip->work_continue) {
2083                 queue_work(chip->fusb30x_wq, &chip->work);
2084                 return;
2085         }
2086
2087         if (!platform_get_device_irq_state(chip))
2088                 fusb_irq_enable(chip);
2089         else
2090                 queue_work(chip->fusb30x_wq, &chip->work);
2091 }
2092
2093 static irqreturn_t cc_interrupt_handler(int irq, void *dev_id)
2094 {
2095         struct fusb30x_chip *chip = dev_id;
2096
2097         queue_work(chip->fusb30x_wq, &chip->work);
2098         fusb_irq_disable(chip);
2099         return IRQ_HANDLED;
2100 }
2101
2102 static int fusb_initialize_gpio(struct fusb30x_chip *chip)
2103 {
2104         chip->gpio_int = devm_gpiod_get_optional(chip->dev, "int-n", GPIOD_IN);
2105         if (IS_ERR(chip->gpio_int))
2106                 return PTR_ERR(chip->gpio_int);
2107
2108         /* some board support vbus with other ways */
2109         chip->gpio_vbus_5v = devm_gpiod_get_optional(chip->dev, "vbus-5v",
2110                                                      GPIOD_OUT_LOW);
2111         if (IS_ERR(chip->gpio_vbus_5v))
2112                 dev_warn(chip->dev,
2113                          "Could not get named GPIO for VBus5V!\n");
2114         else
2115                 gpiod_set_raw_value(chip->gpio_vbus_5v, 0);
2116
2117         chip->gpio_vbus_other = devm_gpiod_get_optional(chip->dev,
2118                                                         "vbus-other",
2119                                                         GPIOD_OUT_LOW);
2120         if (IS_ERR(chip->gpio_vbus_other))
2121                 dev_warn(chip->dev,
2122                          "Could not get named GPIO for VBusOther!\n");
2123         else
2124                 gpiod_set_raw_value(chip->gpio_vbus_other, 0);
2125
2126         return 0;
2127 }
2128
2129 static enum hrtimer_restart fusb_timer_handler(struct hrtimer *timer)
2130 {
2131         int i;
2132
2133         for (i = 0; i < fusb30x_port_used; i++) {
2134                 if (timer == &fusb30x_port_info[i]->timer_state_machine) {
2135                         if (fusb30x_port_info[i]->timer_state != T_DISABLED)
2136                                 fusb30x_port_info[i]->timer_state = 0;
2137                         break;
2138                 }
2139
2140                 if (timer == &fusb30x_port_info[i]->timer_mux_machine) {
2141                         if (fusb30x_port_info[i]->timer_mux != T_DISABLED)
2142                                 fusb30x_port_info[i]->timer_mux = 0;
2143                         break;
2144                 }
2145         }
2146
2147         if (i != fusb30x_port_used)
2148                 queue_work(fusb30x_port_info[i]->fusb30x_wq,
2149                            &fusb30x_port_info[i]->work);
2150
2151         return HRTIMER_NORESTART;
2152 }
2153
2154 static void fusb_initialize_timer(struct fusb30x_chip *chip)
2155 {
2156         hrtimer_init(&chip->timer_state_machine, CLOCK_MONOTONIC,
2157                      HRTIMER_MODE_REL);
2158         chip->timer_state_machine.function = fusb_timer_handler;
2159
2160         hrtimer_init(&chip->timer_mux_machine, CLOCK_MONOTONIC,
2161                      HRTIMER_MODE_REL);
2162         chip->timer_mux_machine.function = fusb_timer_handler;
2163
2164         chip->timer_state = T_DISABLED;
2165         chip->timer_mux = T_DISABLED;
2166 }
2167
2168 static void fusb302_work_func(struct work_struct *work)
2169 {
2170         struct fusb30x_chip *chip;
2171
2172         chip = container_of(work, struct fusb30x_chip, work);
2173         state_machine_typec(chip);
2174 }
2175
2176 static int fusb30x_probe(struct i2c_client *client,
2177                          const struct i2c_device_id *id)
2178 {
2179         struct fusb30x_chip *chip;
2180         struct PD_CAP_INFO *pd_cap_info;
2181         int ret;
2182
2183         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
2184         if (!chip)
2185                 return -ENOMEM;
2186
2187         if (fusb30x_port_used == 0xff)
2188                 return -1;
2189
2190         chip->port_num = fusb30x_port_used++;
2191         fusb30x_port_info[chip->port_num] = chip;
2192
2193         chip->dev = &client->dev;
2194         chip->regmap = devm_regmap_init_i2c(client, &fusb302_regmap_config);
2195         if (IS_ERR(chip->regmap)) {
2196                 dev_err(&client->dev, "Failed to allocate regmap!\n");
2197                 return PTR_ERR(chip->regmap);
2198         }
2199
2200         ret = fusb_initialize_gpio(chip);
2201         if (ret)
2202                 return ret;
2203
2204         fusb_initialize_timer(chip);
2205
2206         chip->fusb30x_wq = create_workqueue("fusb302_wq");
2207         INIT_WORK(&chip->work, fusb302_work_func);
2208
2209         tcpm_init(chip);
2210         tcpm_set_rx_enable(chip, 0);
2211         chip->conn_state = unattached;
2212         tcpm_set_cc(chip, FUSB_MODE_DRP);
2213
2214         chip->n_caps_used = 1;
2215         chip->source_power_supply[0] = 0x64;
2216         chip->source_max_current[0] = 0x96;
2217
2218         /*
2219          * these two variable should be 1 if support DRP,
2220          * but now we do not support swap,
2221          * it will be blanked in future
2222          */
2223         pd_cap_info = &chip->pd_cap_info;
2224         pd_cap_info->dual_role_power = 0;
2225         pd_cap_info->data_role_swap = 0;
2226
2227         pd_cap_info->externally_powered = 1;
2228         pd_cap_info->usb_suspend_support = 0;
2229         pd_cap_info->usb_communications_cap = 0;
2230         pd_cap_info->supply_type = 0;
2231         pd_cap_info->peak_current = 0;
2232
2233         chip->extcon = devm_extcon_dev_allocate(&client->dev, fusb302_cable);
2234         if (IS_ERR(chip->extcon)) {
2235                 dev_err(&client->dev, "allocat extcon failed\n");
2236                 return PTR_ERR(chip->extcon);
2237         }
2238
2239         ret = devm_extcon_dev_register(&client->dev, chip->extcon);
2240         if (ret) {
2241                 dev_err(&client->dev, "failed to register extcon: %d\n",
2242                         ret);
2243                 return ret;
2244         }
2245
2246         ret = extcon_set_property_capability(chip->extcon, EXTCON_USB,
2247                                              EXTCON_PROP_USB_TYPEC_POLARITY);
2248         if (ret) {
2249                 dev_err(&client->dev,
2250                         "failed to set USB property capability: %d\n",
2251                         ret);
2252                 return ret;
2253         }
2254
2255         ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST,
2256                                              EXTCON_PROP_USB_TYPEC_POLARITY);
2257         if (ret) {
2258                 dev_err(&client->dev,
2259                         "failed to set USB_HOST property capability: %d\n",
2260                         ret);
2261                 return ret;
2262         }
2263
2264         ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP,
2265                                              EXTCON_PROP_USB_TYPEC_POLARITY);
2266         if (ret) {
2267                 dev_err(&client->dev,
2268                         "failed to set DISP_DP property capability: %d\n",
2269                         ret);
2270                 return ret;
2271         }
2272
2273         i2c_set_clientdata(client, chip);
2274
2275         spin_lock_init(&chip->irq_lock);
2276         chip->enable_irq = 1;
2277
2278         chip->gpio_int_irq = gpiod_to_irq(chip->gpio_int);
2279         if (chip->gpio_int_irq < 0) {
2280                 dev_err(&client->dev,
2281                         "Unable to request IRQ for INT_N GPIO! %d\n",
2282                         ret);
2283                 ret = chip->gpio_int_irq;
2284                 goto IRQ_ERR;
2285         }
2286
2287         ret = devm_request_threaded_irq(&client->dev,
2288                                         chip->gpio_int_irq,
2289                                         NULL,
2290                                         cc_interrupt_handler,
2291                                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2292                                         client->name,
2293                                         chip);
2294         if (ret) {
2295                 dev_err(&client->dev, "irq request failed\n");
2296                 goto IRQ_ERR;
2297         }
2298
2299         dev_info(chip->dev, "port %d probe success\n", chip->port_num);
2300
2301         return 0;
2302
2303 IRQ_ERR:
2304         destroy_workqueue(chip->fusb30x_wq);
2305         return ret;
2306 }
2307
2308 static int fusb30x_remove(struct i2c_client *client)
2309 {
2310         struct fusb30x_chip *chip = i2c_get_clientdata(client);
2311
2312         destroy_workqueue(chip->fusb30x_wq);
2313         return 0;
2314 }
2315
2316 static const struct of_device_id fusb30x_dt_match[] = {
2317         { .compatible = FUSB30X_I2C_DEVICETREE_NAME },
2318         {},
2319 };
2320 MODULE_DEVICE_TABLE(of, fusb30x_dt_match);
2321
2322 static const struct i2c_device_id fusb30x_i2c_device_id[] = {
2323         { FUSB30X_I2C_DRIVER_NAME, 0 },
2324         {}
2325 };
2326 MODULE_DEVICE_TABLE(i2c, fusb30x_i2c_device_id);
2327
2328 static struct i2c_driver fusb30x_driver = {
2329         .driver = {
2330                 .name = FUSB30X_I2C_DRIVER_NAME,
2331                 .of_match_table = of_match_ptr(fusb30x_dt_match),
2332         },
2333         .probe = fusb30x_probe,
2334         .remove = fusb30x_remove,
2335         .id_table = fusb30x_i2c_device_id,
2336 };
2337
2338 module_i2c_driver(fusb30x_driver);
2339
2340 MODULE_LICENSE("GPL");
2341 MODULE_AUTHOR("zain wang <zain.wang@rock-chips.com>");
2342 MODULE_DESCRIPTION("fusb302 typec pd driver");