2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Zain Wang <zain.wang@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * Some ideas are from chrome ec and fairchild GPL fusb302 driver.
12 #include <linux/delay.h>
13 #include <linux/extcon.h>
14 #include <linux/gpio.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_gpio.h>
18 #include <linux/regmap.h>
22 #define FUSB302_MAX_REG (FUSB_REG_FIFO + 50)
23 #define FUSB_MS_TO_NS(x) ((s64)x * 1000 * 1000)
25 #define FUSB_MODE_DRP 0
26 #define FUSB_MODE_UFP 1
27 #define FUSB_MODE_DFP 2
28 #define FUSB_MODE_ASS 3
30 #define TYPEC_CC_VOLT_OPEN 0
31 #define TYPEC_CC_VOLT_RA 1
32 #define TYPEC_CC_VOLT_RD 2
33 #define TYPEC_CC_VOLT_RP 3
35 #define EVENT_CC BIT(0)
36 #define EVENT_RX BIT(1)
37 #define EVENT_TX BIT(2)
38 #define EVENT_REC_RESET BIT(3)
39 #define EVENT_WORK_CONTINUE BIT(5)
40 #define EVENT_TIMER_MUX BIT(6)
41 #define EVENT_TIMER_STATE BIT(7)
42 #define FLAG_EVENT (EVENT_RX | EVENT_TIMER_MUX | \
45 #define PIN_MAP_A BIT(0)
46 #define PIN_MAP_B BIT(1)
47 #define PIN_MAP_C BIT(2)
48 #define PIN_MAP_D BIT(3)
49 #define PIN_MAP_E BIT(4)
50 #define PIN_MAP_F BIT(5)
52 static u8 fusb30x_port_used;
53 static struct fusb30x_chip *fusb30x_port_info[256];
55 static bool is_write_reg(struct device *dev, unsigned int reg)
57 if (reg >= FUSB_REG_FIFO)
60 return ((reg < (FUSB_REG_CONTROL4 + 1)) && (reg > 0x01)) ?
64 static bool is_volatile_reg(struct device *dev, unsigned int reg)
66 if (reg > FUSB_REG_CONTROL4)
70 case FUSB_REG_CONTROL0:
71 case FUSB_REG_CONTROL1:
72 case FUSB_REG_CONTROL3:
79 struct regmap_config fusb302_regmap_config = {
82 .writeable_reg = is_write_reg,
83 .volatile_reg = is_volatile_reg,
84 .max_register = FUSB302_MAX_REG,
85 .cache_type = REGCACHE_RBTREE,
88 static void dump_notify_info(struct fusb30x_chip *chip)
90 dev_dbg(chip->dev, "port %d\n", chip->port_num);
91 dev_dbg(chip->dev, "orientation %d\n", chip->notify.orientation);
92 dev_dbg(chip->dev, "power_role %d\n", chip->notify.power_role);
93 dev_dbg(chip->dev, "data_role %d\n", chip->notify.data_role);
94 dev_dbg(chip->dev, "cc %d\n", chip->notify.is_cc_connected);
95 dev_dbg(chip->dev, "pd %d\n", chip->notify.is_pd_connected);
96 dev_dbg(chip->dev, "enter_mode %d\n", chip->notify.is_enter_mode);
97 dev_dbg(chip->dev, "pin support %d\n",
98 chip->notify.pin_assignment_support);
99 dev_dbg(chip->dev, "pin def %d\n", chip->notify.pin_assignment_def);
100 dev_dbg(chip->dev, "attention %d\n", chip->notify.attention);
103 static const unsigned int fusb302_cable[] = {
114 void fusb_irq_disable(struct fusb30x_chip *chip)
116 unsigned long irqflags = 0;
118 spin_lock_irqsave(&chip->irq_lock, irqflags);
119 if (chip->enable_irq) {
120 disable_irq_nosync(chip->gpio_int_irq);
121 chip->enable_irq = 0;
123 dev_warn(chip->dev, "irq have already disabled\n");
125 spin_unlock_irqrestore(&chip->irq_lock, irqflags);
128 void fusb_irq_enable(struct fusb30x_chip *chip)
130 unsigned long irqflags = 0;
132 spin_lock_irqsave(&chip->irq_lock, irqflags);
133 if (!chip->enable_irq) {
134 enable_irq(chip->gpio_int_irq);
135 chip->enable_irq = 1;
137 spin_unlock_irqrestore(&chip->irq_lock, irqflags);
140 static void platform_fusb_notify(struct fusb30x_chip *chip)
142 bool plugged = 0, flip = 0, dfp = 0, ufp = 0, dp = 0;
143 union extcon_property_value property;
145 if (chip->notify.is_cc_connected)
146 chip->notify.orientation = chip->cc_polarity + 1;
148 /* avoid notify repeated */
149 if (memcmp(&chip->notify, &chip->notify_cmp,
150 sizeof(struct notify_info))) {
151 dump_notify_info(chip);
152 chip->notify.attention = 0;
153 memcpy(&chip->notify_cmp, &chip->notify,
154 sizeof(struct notify_info));
156 plugged = chip->notify.is_cc_connected ||
157 chip->notify.is_pd_connected;
158 flip = chip->notify.orientation ?
159 (chip->notify.orientation - 1) : 0;
160 dp = chip->notify.is_enter_mode;
163 dfp = (chip->notify.pin_assignment_def &
164 (PIN_MAP_B | PIN_MAP_D | PIN_MAP_F)) ? 1 : 0;
165 else if (chip->notify.data_role)
170 property.intval = flip;
171 extcon_set_property(chip->extcon, EXTCON_USB,
172 EXTCON_PROP_USB_TYPEC_POLARITY, property);
173 extcon_set_property(chip->extcon, EXTCON_USB_HOST,
174 EXTCON_PROP_USB_TYPEC_POLARITY, property);
175 extcon_set_property(chip->extcon, EXTCON_DISP_DP,
176 EXTCON_PROP_USB_TYPEC_POLARITY, property);
177 extcon_set_state(chip->extcon, EXTCON_USB, ufp);
178 extcon_set_state(chip->extcon, EXTCON_USB_HOST, dfp);
179 extcon_set_state(chip->extcon, EXTCON_DISP_DP, dp);
180 extcon_sync(chip->extcon, EXTCON_USB);
181 extcon_sync(chip->extcon, EXTCON_USB_HOST);
182 extcon_sync(chip->extcon, EXTCON_DISP_DP);
186 static bool platform_get_device_irq_state(struct fusb30x_chip *chip)
188 return !gpiod_get_value(chip->gpio_int);
191 static void fusb_timer_start(struct hrtimer *timer, int ms)
195 ktime = ktime_set(0, FUSB_MS_TO_NS(ms));
196 hrtimer_start(timer, ktime, HRTIMER_MODE_REL);
199 static void platform_set_vbus_lvl_enable(struct fusb30x_chip *chip, int vbus_5v,
202 if (chip->gpio_vbus_5v)
203 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_5v);
205 if (chip->gpio_vbus_other)
206 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_other);
209 static void set_state(struct fusb30x_chip *chip, enum connection_state state)
211 dev_dbg(chip->dev, "port %d, state %d\n", chip->port_num, state);
213 dev_info(chip->dev, "PD disabled\n");
214 chip->conn_state = state;
217 chip->work_continue = 1;
220 static int tcpm_get_message(struct fusb30x_chip *chip)
225 regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, 3);
226 chip->rec_head = (buf[1] & 0xff) | ((buf[2] << 8) & 0xff00);
228 len = PD_HEADER_CNT(chip->rec_head) << 2;
229 regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, len + 4);
231 memcpy(chip->rec_load, buf, len);
236 static void fusb302_flush_rx_fifo(struct fusb30x_chip *chip)
238 tcpm_get_message(chip);
241 static int tcpm_get_cc(struct fusb30x_chip *chip, int *CC1, int *CC2)
247 *CC1 = TYPEC_CC_VOLT_OPEN;
248 *CC2 = TYPEC_CC_VOLT_OPEN;
250 if (chip->cc_state & 0x01)
255 if (chip->cc_state & 0x04) {
256 regmap_read(chip->regmap, FUSB_REG_SWITCHES0, (u32 *)(&store));
258 /* measure cc1 first */
259 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
260 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
261 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
262 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
263 SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
265 usleep_range(250, 300);
267 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
268 val &= STATUS0_BC_LVL;
272 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
273 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
274 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
275 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
276 SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
278 usleep_range(250, 300);
280 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
281 val &= STATUS0_BC_LVL;
285 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
286 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
289 if (chip->cc_state & 0x01) {
290 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
300 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
311 regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x26 << 2);
312 usleep_range(250, 300);
314 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)(&val));
316 if (val & STATUS0_COMP) {
317 *CC_MEASURE = TYPEC_CC_VOLT_OPEN;
319 regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x05 << 2);
320 usleep_range(250, 300);
322 regmap_read(chip->regmap, FUSB_REG_STATUS0,
325 if (val & STATUS0_COMP)
326 *CC_MEASURE = TYPEC_CC_VOLT_RA;
328 *CC_MEASURE = TYPEC_CC_VOLT_RD;
334 static int tcpm_set_cc(struct fusb30x_chip *chip, int mode)
338 val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
339 SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
345 if (chip->togdone_pullup)
346 val |= SWITCHES0_PU_EN2;
348 val |= SWITCHES0_PU_EN1;
351 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
354 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
360 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, mask, val);
364 static int tcpm_set_rx_enable(struct fusb30x_chip *chip, int enable)
369 if (chip->cc_polarity)
370 val |= SWITCHES0_MEAS_CC2;
372 val |= SWITCHES0_MEAS_CC1;
373 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
374 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
376 fusb302_flush_rx_fifo(chip);
377 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
378 SWITCHES1_AUTO_CRC, SWITCHES1_AUTO_CRC);
381 * bit of a hack here.
382 * when this function is called to disable rx (enable=0)
383 * using it as an indication of detach (gulp!)
384 * to reset our knowledge of where
385 * the toggle state machine landed.
387 chip->togdone_pullup = 0;
390 tcpm_set_cc(chip, FUSB_MODE_DRP);
391 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
392 CONTROL2_TOG_RD_ONLY,
393 CONTROL2_TOG_RD_ONLY);
395 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
396 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
398 regmap_update_bits(chip->regmap,
399 FUSB_REG_SWITCHES1, SWITCHES1_AUTO_CRC, 0);
405 static int tcpm_set_msg_header(struct fusb30x_chip *chip)
407 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
408 SWITCHES1_POWERROLE | SWITCHES1_DATAROLE,
409 (chip->notify.power_role << 7) |
410 (chip->notify.data_role << 4));
411 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
412 SWITCHES1_SPECREV, 2 << 5);
416 static int tcpm_set_polarity(struct fusb30x_chip *chip, bool polarity)
420 #ifdef FUSB_VCONN_SUPPORT
421 if (chip->vconn_enabled) {
423 val |= SWITCHES0_VCONN_CC1;
425 val |= SWITCHES0_VCONN_CC2;
430 val |= SWITCHES0_MEAS_CC2;
432 val |= SWITCHES0_MEAS_CC1;
434 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
435 SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2 |
436 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
441 val |= SWITCHES1_TXCC2;
443 val |= SWITCHES1_TXCC1;
444 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
445 SWITCHES1_TXCC1 | SWITCHES1_TXCC2,
448 chip->cc_polarity = polarity;
453 static int tcpm_set_vconn(struct fusb30x_chip *chip, int enable)
458 tcpm_set_polarity(chip, chip->cc_polarity);
460 val &= ~(SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2);
461 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
462 SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2,
465 chip->vconn_enabled = enable;
469 static void fusb302_pd_reset(struct fusb30x_chip *chip)
471 regmap_write(chip->regmap, FUSB_REG_RESET, RESET_PD_RESET);
472 regmap_reinit_cache(chip->regmap, &fusb302_regmap_config);
475 static void tcpm_init(struct fusb30x_chip *chip)
479 regmap_read(chip->regmap, FUSB_REG_DEVICEID, (u32 *)(&chip->chip_id));
480 platform_set_vbus_lvl_enable(chip, 0, 0);
481 chip->notify.is_cc_connected = 0;
484 /* restore default settings */
485 regmap_update_bits(chip->regmap, FUSB_REG_RESET, RESET_SW_RESET,
487 fusb302_pd_reset(chip);
488 /* set auto_retry and number of retries */
489 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
490 CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES,
491 CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES),
495 val &= ~(MASK_M_BC_LVL | MASK_M_COLLISION | MASK_M_ALERT |
497 regmap_write(chip->regmap, FUSB_REG_MASK, val);
500 val &= ~(MASKA_M_TOGDONE | MASKA_M_RETRYFAIL | MASKA_M_HARDSENT |
501 MASKA_M_TXSENT | MASKA_M_HARDRST);
502 regmap_write(chip->regmap, FUSB_REG_MASKA, val);
505 val = ~MASKB_M_GCRCSEND;
506 regmap_write(chip->regmap, FUSB_REG_MASKB, val);
509 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
510 CONTROL2_MODE | CONTROL2_TOGGLE,
511 (1 << 1) | CONTROL2_TOGGLE);
513 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
514 CONTROL2_TOG_RD_ONLY,
515 CONTROL2_TOG_RD_ONLY);
517 /* Interrupts Enable */
518 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL0, CONTROL0_INT_MASK,
521 tcpm_set_polarity(chip, 0);
522 tcpm_set_vconn(chip, 0);
524 regmap_write(chip->regmap, FUSB_REG_POWER, 0xf);
527 static void pd_execute_hard_reset(struct fusb30x_chip *chip)
531 if (chip->notify.power_role)
532 set_state(chip, policy_src_transition_default);
534 set_state(chip, policy_snk_transition_default);
537 static void tcpc_alert(struct fusb30x_chip *chip, int *evt)
539 int interrupt, interrupta, interruptb;
542 regmap_read(chip->regmap, FUSB_REG_INTERRUPT, &interrupt);
543 regmap_read(chip->regmap, FUSB_REG_INTERRUPTA, &interrupta);
544 regmap_read(chip->regmap, FUSB_REG_INTERRUPTB, &interruptb);
546 if (interrupt & INTERRUPT_BC_LVL) {
547 if (chip->notify.is_cc_connected)
551 if (interrupt & INTERRUPT_VBUSOK) {
552 if (chip->notify.is_cc_connected)
556 if (interrupta & INTERRUPTA_TOGDONE) {
558 regmap_read(chip->regmap, FUSB_REG_STATUS1A, &val);
559 chip->cc_state = ((u8)val >> 3) & 0x07;
561 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
565 val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
566 SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
568 if (chip->cc_state | 0x01)
569 val |= SWITCHES0_PU_EN1;
571 val |= SWITCHES0_PU_EN2;
573 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
574 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
575 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
579 if (interrupta & INTERRUPTA_TXSENT) {
581 fusb302_flush_rx_fifo(chip);
582 chip->tx_state = tx_success;
585 if (interruptb & INTERRUPTB_GCRCSENT)
588 if (interrupta & INTERRUPTA_HARDRST) {
589 fusb302_pd_reset(chip);
590 pd_execute_hard_reset(chip);
591 *evt |= EVENT_REC_RESET;
594 if (interrupta & INTERRUPTA_RETRYFAIL) {
596 chip->tx_state = tx_failed;
599 if (interrupta & INTERRUPTA_HARDSENT) {
600 chip->tx_state = tx_success;
601 chip->timer_state = T_DISABLED;
606 static void mux_alert(struct fusb30x_chip *chip, int *evt)
608 if (!chip->timer_mux) {
609 *evt |= EVENT_TIMER_MUX;
610 chip->timer_mux = T_DISABLED;
613 if (!chip->timer_state) {
614 *evt |= EVENT_TIMER_STATE;
615 chip->timer_state = T_DISABLED;
618 if (chip->work_continue) {
619 *evt |= EVENT_WORK_CONTINUE;
620 chip->work_continue = 0;
624 static void set_state_unattached(struct fusb30x_chip *chip)
626 dev_info(chip->dev, "connection has disconnected\n");
628 tcpm_set_rx_enable(chip, 0);
629 chip->conn_state = unattached;
630 tcpm_set_cc(chip, FUSB_MODE_DRP);
632 /* claer notify_info */
633 memset(&chip->notify, 0, sizeof(struct notify_info));
634 platform_fusb_notify(chip);
639 static int tcpm_check_vbus(struct fusb30x_chip *chip)
643 /* Read status register */
644 regmap_read(chip->regmap, FUSB_REG_STATUS0, (u32 *)&val);
646 return (val & STATUS0_VBUSOK) ? 1 : 0;
649 static void set_mesg(struct fusb30x_chip *chip, int cmd, int is_DMT)
652 struct PD_CAP_INFO *pd_cap_info = &chip->pd_cap_info;
654 chip->send_head = ((chip->msg_id & 0x7) << 9) |
655 ((chip->notify.power_role & 0x1) << 8) |
657 ((chip->notify.data_role & 0x1) << 5);
661 case DMT_SOURCECAPABILITIES:
662 chip->send_head |= ((chip->n_caps_used & 0x3) << 12) | (cmd & 0xf);
664 for (i = 0; i < chip->n_caps_used; i++) {
665 chip->send_load[i] = (pd_cap_info->supply_type << 30) |
666 (pd_cap_info->dual_role_power << 29) |
667 (pd_cap_info->usb_suspend_support << 28) |
668 (pd_cap_info->externally_powered << 27) |
669 (pd_cap_info->usb_communications_cap << 26) |
670 (pd_cap_info->data_role_swap << 25) |
671 (pd_cap_info->peak_current << 20) |
672 (chip->source_power_supply[i] << 10) |
673 (chip->source_max_current[i]);
677 chip->send_head |= ((1 << 12) | (cmd & 0xf));
678 /* send request with FVRDO */
679 chip->send_load[0] = (chip->pos_power << 28) |
685 switch (CAP_POWER_TYPE(chip->rec_load[chip->pos_power - 1])) {
688 chip->send_load[0] |= ((CAP_FPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
689 chip->send_load[0] |= (CAP_FPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
693 chip->send_load[0] |= ((CAP_VPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
694 chip->send_load[0] |= (CAP_VPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
697 /* not meet battery caps */
701 case DMT_SINKCAPABILITIES:
703 case DMT_VENDERDEFINED:
709 chip->send_head |= (cmd & 0xf);
713 static void set_vdm_mesg(struct fusb30x_chip *chip, int cmd, int type, int mode)
715 chip->send_head = (chip->msg_id & 0x7) << 9;
716 chip->send_head |= (chip->notify.power_role & 0x1) << 8;
718 chip->send_head = ((chip->msg_id & 0x7) << 9) |
719 ((chip->notify.power_role & 0x1) << 8) |
721 ((chip->notify.data_role & 0x1) << 5) |
722 (DMT_VENDERDEFINED & 0xf);
724 chip->send_load[0] = (1 << 15) |
730 case VDM_DISCOVERY_ID:
731 case VDM_DISCOVERY_SVIDS:
733 chip->send_load[0] |= (0xff00 << 16);
734 chip->send_head |= (1 << 12);
736 case VDM_DISCOVERY_MODES:
737 chip->send_load[0] |=
738 (chip->vdm_svid[chip->val_tmp >> 1] << 16);
739 chip->send_head |= (1 << 12);
742 chip->send_head |= (1 << 12);
743 chip->send_load[0] |= (mode << 8) | (0xff01 << 16);
746 chip->send_head |= (1 << 12);
747 chip->send_load[0] |= (0x0f << 8) | (0xff01 << 16);
749 case VDM_DP_STATUS_UPDATE:
750 chip->send_head |= (2 << 12);
751 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
752 chip->send_load[1] = 5;
755 chip->send_head |= (2 << 12);
756 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
757 chip->send_load[1] = (chip->notify.pin_assignment_def << 8) |
765 static enum tx_state policy_send_hardrst(struct fusb30x_chip *chip, int evt)
767 switch (chip->tx_state) {
769 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
770 CONTROL3_SEND_HARDRESET,
771 CONTROL3_SEND_HARDRESET);
772 chip->tx_state = tx_busy;
773 chip->timer_state = T_BMC_TIMEOUT;
774 fusb_timer_start(&chip->timer_state_machine,
778 if (evt & EVENT_TIMER_STATE)
779 chip->tx_state = tx_success;
782 return chip->tx_state;
785 static enum tx_state policy_send_data(struct fusb30x_chip *chip)
791 switch (chip->tx_state) {
793 senddata[pos++] = FUSB_TKN_SYNC1;
794 senddata[pos++] = FUSB_TKN_SYNC1;
795 senddata[pos++] = FUSB_TKN_SYNC1;
796 senddata[pos++] = FUSB_TKN_SYNC2;
798 len = PD_HEADER_CNT(chip->send_head) << 2;
799 senddata[pos++] = FUSB_TKN_PACKSYM | ((len + 2) & 0x1f);
801 senddata[pos++] = chip->send_head & 0xff;
802 senddata[pos++] = (chip->send_head >> 8) & 0xff;
804 memcpy(&senddata[pos], chip->send_load, len);
807 senddata[pos++] = FUSB_TKN_JAMCRC;
808 senddata[pos++] = FUSB_TKN_EOP;
809 senddata[pos++] = FUSB_TKN_TXOFF;
810 senddata[pos++] = FUSB_TKN_TXON;
812 regmap_raw_write(chip->regmap, FUSB_REG_FIFO, senddata, pos);
813 chip->tx_state = tx_busy;
821 return chip->tx_state;
824 static void process_vdm_msg(struct fusb30x_chip *chip)
826 u32 vdm_header = chip->rec_load[0];
830 /* can't procee unstructed vdm msg */
831 if (!GET_VDMHEAD_STRUCT_TYPE(vdm_header))
834 switch (GET_VDMHEAD_CMD_TYPE(vdm_header)) {
836 switch (GET_VDMHEAD_CMD(vdm_header)) {
838 dev_info(chip->dev, "attention, dp_status %x\n",
840 chip->notify.attention = 1;
844 dev_warn(chip->dev, "rec unknown init vdm msg\n");
849 switch (GET_VDMHEAD_CMD(vdm_header)) {
850 case VDM_DISCOVERY_ID:
851 chip->vdm_id = chip->rec_load[1];
853 case VDM_DISCOVERY_SVIDS:
854 for (i = 0; i < 6; i++) {
855 tmp = (chip->rec_load[i + 1] >> 16) &
858 chip->vdm_svid[i * 2] = tmp;
859 chip->vdm_svid_num++;
864 tmp = (chip->rec_load[i + 1] & 0x0000ffff);
866 chip->vdm_svid[i * 2 + 1] = tmp;
867 chip->vdm_svid_num++;
873 case VDM_DISCOVERY_MODES:
874 /* indicate there are some vdo modes */
875 if (PD_HEADER_CNT(chip->rec_head) > 1) {
878 * enter first mode default
880 if (!((chip->rec_load[1] >> 8) & 0x3f)) {
884 chip->notify.pin_assignment_support = 0;
885 chip->notify.pin_assignment_def = 0;
886 chip->notify.pin_assignment_support =
887 (chip->rec_load[1] >> 8) & 0x3f;
888 tmp = chip->notify.pin_assignment_support;
889 for (i = 0; i < 6; i++) {
895 chip->notify.pin_assignment_def = 0x20 >> i;
902 case VDM_DP_STATUS_UPDATE:
903 dev_dbg(chip->dev, "dp_status 0x%x\n",
910 "DP config successful, pin_assignment 0x%x\n",
911 chip->notify.pin_assignment_def);
912 chip->notify.is_enter_mode = 1;
919 dev_warn(chip->dev, "REC NACK for 0x%x\n",
920 GET_VDMHEAD_CMD(vdm_header));
922 chip->vdm_state = 0xff;
927 static int vdm_send_discoveryid(struct fusb30x_chip *chip, int evt)
931 switch (chip->vdm_send_state) {
933 set_vdm_mesg(chip, VDM_DISCOVERY_ID, VDM_TYPE_INIT, 0);
936 chip->vdm_send_state++;
938 tmp = policy_send_data(chip);
939 if (tmp == tx_success) {
940 chip->vdm_send_state++;
941 chip->timer_state = T_SENDER_RESPONSE;
942 fusb_timer_start(&chip->timer_state_machine,
944 } else if (tmp == tx_failed) {
945 dev_warn(chip->dev, "VDM_DISCOVERY_ID send failed\n");
946 /* disable auto_vdm_machine */
947 chip->vdm_state = 0xff;
950 if (chip->vdm_send_state != 2)
953 if (evt & EVENT_TIMER_STATE) {
954 dev_warn(chip->dev, "VDM_DISCOVERY_ID time out\n");
955 chip->vdm_state = 0xff;
956 chip->work_continue = 1;
961 chip->vdm_send_state = 0;
967 static int vdm_send_discoverysvid(struct fusb30x_chip *chip, int evt)
971 switch (chip->vdm_send_state) {
973 set_vdm_mesg(chip, VDM_DISCOVERY_SVIDS, VDM_TYPE_INIT, 0);
974 memset(chip->vdm_svid, 0, 12);
975 chip->vdm_svid_num = 0;
977 chip->vdm_send_state++;
979 tmp = policy_send_data(chip);
980 if (tmp == tx_success) {
981 chip->vdm_send_state++;
982 chip->timer_state = T_SENDER_RESPONSE;
983 fusb_timer_start(&chip->timer_state_machine,
985 } else if (tmp == tx_failed) {
986 dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS send failed\n");
987 /* disable auto_vdm_machine */
988 chip->vdm_state = 0xff;
991 if (chip->vdm_send_state != 2)
994 if (evt & EVENT_TIMER_STATE) {
995 dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS time out\n");
996 chip->vdm_state = 0xff;
997 chip->work_continue = 1;
1000 if (!chip->vdm_svid_num)
1002 chip->vdm_send_state = 0;
1005 return -EINPROGRESS;
1008 static int vdm_send_discoverymodes(struct fusb30x_chip *chip, int evt)
1012 if ((chip->val_tmp >> 1) != chip->vdm_svid_num) {
1013 switch (chip->vdm_send_state) {
1015 set_vdm_mesg(chip, VDM_DISCOVERY_MODES,
1018 chip->vdm_send_state++;
1020 tmp = policy_send_data(chip);
1021 if (tmp == tx_success) {
1022 chip->vdm_send_state++;
1023 chip->timer_state = T_SENDER_RESPONSE;
1024 fusb_timer_start(&chip->timer_state_machine,
1026 } else if (tmp == tx_failed) {
1028 "VDM_DISCOVERY_MODES send failed\n");
1029 chip->vdm_state = 0xff;
1032 if (chip->vdm_send_state != 2)
1035 if (evt & EVENT_TIMER_STATE) {
1037 "VDM_DISCOVERY_MODES time out\n");
1038 chip->vdm_state = 0xff;
1039 chip->work_continue = 1;
1042 if (!(chip->val_tmp & 1))
1044 chip->val_tmp &= 0xfe;
1046 chip->vdm_send_state = 0;
1047 chip->work_continue = 1;
1055 return -EINPROGRESS;
1058 static int vdm_send_entermode(struct fusb30x_chip *chip, int evt)
1062 switch (chip->vdm_send_state) {
1064 set_vdm_mesg(chip, VDM_ENTER_MODE, VDM_TYPE_INIT, 1);
1066 chip->vdm_send_state++;
1067 chip->notify.is_enter_mode = 0;
1069 tmp = policy_send_data(chip);
1070 if (tmp == tx_success) {
1071 chip->vdm_send_state++;
1072 chip->timer_state = T_SENDER_RESPONSE;
1073 fusb_timer_start(&chip->timer_state_machine,
1075 } else if (tmp == tx_failed) {
1076 dev_warn(chip->dev, "VDM_ENTER_MODE send failed\n");
1077 /* disable auto_vdm_machine */
1078 chip->vdm_state = 0xff;
1081 if (chip->vdm_send_state != 2)
1084 if (evt & EVENT_TIMER_STATE) {
1085 dev_warn(chip->dev, "VDM_ENTER_MODE time out\n");
1086 chip->vdm_state = 0xff;
1087 chip->work_continue = 1;
1093 chip->vdm_send_state = 0;
1096 return -EINPROGRESS;
1099 static int vdm_send_getdpstatus(struct fusb30x_chip *chip, int evt)
1103 switch (chip->vdm_send_state) {
1105 set_vdm_mesg(chip, VDM_DP_STATUS_UPDATE, VDM_TYPE_INIT, 1);
1107 chip->vdm_send_state++;
1109 tmp = policy_send_data(chip);
1110 if (tmp == tx_success) {
1111 chip->vdm_send_state++;
1112 chip->timer_state = T_SENDER_RESPONSE;
1113 fusb_timer_start(&chip->timer_state_machine,
1115 } else if (tmp == tx_failed) {
1117 "VDM_DP_STATUS_UPDATE send failed\n");
1118 /* disable auto_vdm_machine */
1119 chip->vdm_state = 0xff;
1122 if (chip->vdm_send_state != 2)
1125 if (evt & EVENT_TIMER_STATE) {
1126 dev_warn(chip->dev, "VDM_DP_STATUS_UPDATE time out\n");
1127 chip->vdm_state = 0xff;
1128 chip->work_continue = 1;
1134 chip->vdm_send_state = 0;
1137 return -EINPROGRESS;
1140 static int vdm_send_dpconfig(struct fusb30x_chip *chip, int evt)
1144 switch (chip->vdm_send_state) {
1146 set_vdm_mesg(chip, VDM_DP_CONFIG, VDM_TYPE_INIT, 0);
1148 chip->vdm_send_state++;
1150 tmp = policy_send_data(chip);
1151 if (tmp == tx_success) {
1152 chip->vdm_send_state++;
1153 chip->timer_state = T_SENDER_RESPONSE;
1154 fusb_timer_start(&chip->timer_state_machine,
1156 } else if (tmp == tx_failed) {
1157 dev_warn(chip->dev, "vdm_send_dpconfig send failed\n");
1158 /* disable auto_vdm_machine */
1159 chip->vdm_state = 0xff;
1162 if (chip->vdm_send_state != 2)
1165 if (evt & EVENT_TIMER_STATE) {
1166 dev_warn(chip->dev, "vdm_send_dpconfig time out\n");
1167 chip->vdm_state = 0xff;
1168 chip->work_continue = 1;
1174 chip->vdm_send_state = 0;
1177 return -EINPROGRESS;
1180 static void auto_vdm_machine(struct fusb30x_chip *chip, int evt)
1182 switch (chip->vdm_state) {
1184 if (vdm_send_discoveryid(chip, evt))
1189 if (vdm_send_discoverysvid(chip, evt))
1194 if (vdm_send_discoverymodes(chip, evt))
1199 if (vdm_send_entermode(chip, evt))
1204 if (vdm_send_dpconfig(chip, evt))
1206 chip->vdm_state = 6;
1209 if (vdm_send_getdpstatus(chip, evt))
1214 platform_fusb_notify(chip);
1219 static void fusb_state_disabled(struct fusb30x_chip *chip, int evt)
1221 platform_fusb_notify(chip);
1224 static void fusb_state_unattached(struct fusb30x_chip *chip, int evt)
1226 chip->notify.is_cc_connected = 0;
1227 if ((evt & EVENT_CC) && chip->cc_state) {
1228 if (chip->cc_state & 0x04)
1229 set_state(chip, attach_wait_sink);
1231 set_state(chip, attach_wait_source);
1233 tcpm_get_cc(chip, &chip->cc1, &chip->cc2);
1234 chip->debounce_cnt = 0;
1235 chip->timer_mux = 2;
1236 fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux);
1240 static void fusb_state_attach_wait_sink(struct fusb30x_chip *chip, int evt)
1244 if (evt & EVENT_TIMER_MUX) {
1245 tcpm_get_cc(chip, &cc1, &cc2);
1247 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1248 chip->debounce_cnt++;
1252 chip->debounce_cnt = 0;
1255 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1256 if ((chip->cc1 != chip->cc2) &&
1257 ((!chip->cc1) || (!chip->cc2))) {
1258 set_state(chip, attached_sink);
1260 set_state_unattached(chip);
1265 chip->timer_mux = 2;
1266 fusb_timer_start(&chip->timer_mux_machine,
1271 static void fusb_state_attach_wait_source(struct fusb30x_chip *chip, int evt)
1275 if (evt & EVENT_TIMER_MUX) {
1276 tcpm_get_cc(chip, &cc1, &cc2);
1278 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1279 chip->debounce_cnt++;
1280 tcpm_set_polarity(chip, !(chip->cc_state & 0x01));
1281 platform_set_vbus_lvl_enable(chip, 1, 0);
1282 tcpm_set_vconn(chip, 1);
1286 chip->debounce_cnt = 0;
1289 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1290 if (((!chip->cc1) || (!chip->cc2)) &&
1291 ((chip->cc1 == TYPEC_CC_VOLT_RD) ||
1292 (chip->cc2 == TYPEC_CC_VOLT_RD))) {
1293 set_state(chip, attached_source);
1295 set_state_unattached(chip);
1301 chip->timer_mux = 2;
1302 fusb_timer_start(&chip->timer_mux_machine,
1307 static void fusb_state_attached_source(struct fusb30x_chip *chip, int evt)
1309 chip->notify.is_cc_connected = 1;
1310 if (chip->cc_state & 0x01)
1311 chip->cc_polarity = 0;
1313 chip->cc_polarity = 1;
1315 chip->notify.power_role = 1;
1316 chip->notify.data_role = 1;
1317 chip->hardrst_count = 0;
1318 set_state(chip, policy_src_startup);
1319 dev_info(chip->dev, "CC connected in %d as DFP\n", chip->cc_polarity);
1322 static void fusb_state_attached_sink(struct fusb30x_chip *chip, int evt)
1324 chip->notify.is_cc_connected = 1;
1325 if (chip->cc_state & 0x01)
1326 chip->cc_polarity = 0;
1328 chip->cc_polarity = 1;
1330 chip->notify.power_role = 0;
1331 chip->notify.data_role = 0;
1332 chip->hardrst_count = 0;
1333 set_state(chip, policy_snk_startup);
1334 dev_info(chip->dev, "CC connected in %d as UFP\n", chip->cc_polarity);
1337 static void fusb_state_src_startup(struct fusb30x_chip *chip, int evt)
1339 chip->caps_counter = 0;
1340 chip->notify.is_pd_connected = 0;
1342 chip->vdm_state = 0;
1343 chip->vdm_substate = 0;
1344 chip->vdm_send_state = 0;
1347 memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1349 tcpm_set_msg_header(chip);
1350 tcpm_set_polarity(chip, chip->cc_polarity);
1351 tcpm_set_rx_enable(chip, 1);
1353 set_state(chip, policy_src_send_caps);
1356 static void fusb_state_src_discovery(struct fusb30x_chip *chip, int evt)
1358 switch (chip->sub_state) {
1360 chip->caps_counter++;
1362 if (chip->caps_counter < N_CAPS_COUNT) {
1363 chip->timer_state = T_TYPEC_SEND_SOURCECAP;
1364 fusb_timer_start(&chip->timer_state_machine,
1366 chip->sub_state = 1;
1368 set_state(chip, disabled);
1372 if (evt & EVENT_TIMER_STATE) {
1373 set_state(chip, policy_src_send_caps);
1374 } else if ((evt & EVENT_TIMER_MUX) &&
1375 (chip->hardrst_count > N_HARDRESET_COUNT)) {
1376 if (chip->notify.is_pd_connected)
1377 set_state(chip, error_recovery);
1379 set_state(chip, disabled);
1385 static void fusb_state_src_send_caps(struct fusb30x_chip *chip, int evt)
1389 switch (chip->sub_state) {
1391 set_mesg(chip, DMT_SOURCECAPABILITIES, DATAMESSAGE);
1392 chip->sub_state = 1;
1393 chip->tx_state = tx_idle;
1396 tmp = policy_send_data(chip);
1398 if (tmp == tx_success) {
1399 chip->hardrst_count = 0;
1400 chip->caps_counter = 0;
1401 chip->timer_state = T_SENDER_RESPONSE;
1402 fusb_timer_start(&chip->timer_state_machine,
1404 chip->timer_mux = T_DISABLED;
1406 } else if (tmp == tx_failed) {
1407 set_state(chip, policy_src_discovery);
1411 if (!(evt & FLAG_EVENT))
1414 if (evt & EVENT_RX) {
1415 if ((PD_HEADER_CNT(chip->rec_head) == 1) &&
1416 (PD_HEADER_TYPE(chip->rec_head) == DMT_REQUEST)) {
1417 set_state(chip, policy_src_negotiate_cap);
1419 set_state(chip, policy_src_send_softrst);
1421 } else if (evt & EVENT_TIMER_STATE) {
1422 if (chip->hardrst_count <= N_HARDRESET_COUNT)
1423 set_state(chip, policy_src_send_hardrst);
1425 set_state(chip, disabled);
1426 } else if (evt & EVENT_TIMER_MUX) {
1427 if (chip->notify.is_pd_connected)
1428 set_state(chip, disabled);
1430 set_state(chip, error_recovery);
1436 static void fusb_state_src_negotiate_cap(struct fusb30x_chip *chip, int evt)
1441 tmp = (chip->rec_load[0] >> 28) & 0x07;
1442 if (tmp > chip->n_caps_used)
1443 set_state(chip, policy_src_cap_response);
1445 set_state(chip, policy_src_transition_supply);
1448 static void fusb_state_src_transition_supply(struct fusb30x_chip *chip,
1453 switch (chip->sub_state) {
1455 set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE);
1456 chip->tx_state = tx_idle;
1460 tmp = policy_send_data(chip);
1461 if (tmp == tx_success) {
1462 chip->timer_state = T_SRC_TRANSITION;
1464 fusb_timer_start(&chip->timer_state_machine,
1466 } else if (tmp == tx_failed) {
1467 set_state(chip, policy_src_send_softrst);
1471 if (evt & EVENT_TIMER_STATE) {
1472 chip->notify.is_pd_connected = 1;
1473 platform_set_vbus_lvl_enable(chip, 1, 0);
1474 set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE);
1475 chip->tx_state = tx_idle;
1477 chip->work_continue = 1;
1481 tmp = policy_send_data(chip);
1482 if (tmp == tx_success) {
1484 "PD connected as DFP, supporting 5V\n");
1485 set_state(chip, policy_src_ready);
1486 } else if (tmp == tx_failed) {
1487 set_state(chip, policy_src_send_softrst);
1493 static void fusb_state_src_cap_response(struct fusb30x_chip *chip, int evt)
1497 switch (chip->sub_state) {
1499 set_mesg(chip, CMT_REJECT, CONTROLMESSAGE);
1500 chip->tx_state = tx_idle;
1504 tmp = policy_send_data(chip);
1505 if (tmp == tx_success) {
1506 if (chip->notify.is_pd_connected) {
1508 "PD connected as DFP, supporting 5V\n");
1509 set_state(chip, policy_src_ready);
1511 set_state(chip, policy_src_send_hardrst);
1513 } else if (tmp == tx_failed) {
1514 set_state(chip, policy_src_send_softrst);
1520 static void fusb_state_src_transition_default(struct fusb30x_chip *chip,
1523 switch (chip->sub_state) {
1525 chip->notify.is_pd_connected = 0;
1526 platform_set_vbus_lvl_enable(chip, 0, 0);
1527 if (chip->notify.data_role)
1528 regmap_update_bits(chip->regmap,
1531 SWITCHES1_DATAROLE);
1533 regmap_update_bits(chip->regmap,
1538 chip->timer_state = T_SRC_RECOVER;
1539 fusb_timer_start(&chip->timer_state_machine,
1544 if (evt & EVENT_TIMER_STATE) {
1545 platform_set_vbus_lvl_enable(chip, 1, 0);
1546 chip->timer_mux = T_NO_RESPONSE;
1547 fusb_timer_start(&chip->timer_mux_machine,
1549 set_state(chip, policy_src_startup);
1550 dev_dbg(chip->dev, "reset over-> src startup\n");
1556 static void fusb_state_src_ready(struct fusb30x_chip *chip, int evt)
1558 if (evt & EVENT_RX) {
1559 if ((PD_HEADER_CNT(chip->rec_head)) &&
1560 (PD_HEADER_TYPE(chip->rec_head) == DMT_VENDERDEFINED)) {
1561 process_vdm_msg(chip);
1562 chip->work_continue = 1;
1563 chip->timer_state = T_DISABLED;
1567 /* TODO: swap function would be added here later on*/
1569 if (!chip->partner_cap[0])
1570 set_state(chip, policy_src_get_sink_caps);
1572 auto_vdm_machine(chip, evt);
1575 static void fusb_state_src_get_sink_cap(struct fusb30x_chip *chip, int evt)
1579 switch (chip->sub_state) {
1581 set_mesg(chip, CMT_GETSINKCAP, CONTROLMESSAGE);
1582 chip->tx_state = tx_idle;
1586 tmp = policy_send_data(chip);
1587 if (tmp == tx_success) {
1588 chip->timer_state = T_SENDER_RESPONSE;
1590 fusb_timer_start(&chip->timer_state_machine,
1592 } else if (tmp == tx_failed) {
1593 set_state(chip, policy_src_send_softrst);
1596 if (!(evt & FLAG_EVENT))
1599 if (evt & EVENT_RX) {
1600 if ((PD_HEADER_CNT(chip->rec_head)) &&
1601 (PD_HEADER_TYPE(chip->rec_head) ==
1602 DMT_SINKCAPABILITIES)) {
1604 tmp < PD_HEADER_CNT(chip->rec_head);
1606 chip->partner_cap[tmp] =
1607 chip->rec_load[tmp];
1609 set_state(chip, policy_src_ready);
1611 chip->partner_cap[0] = 0xffffffff;
1612 set_state(chip, policy_src_ready);
1614 } else if (evt & EVENT_TIMER_STATE) {
1615 dev_warn(chip->dev, "Get sink cap time out\n");
1616 chip->partner_cap[0] = 0xffffffff;
1617 set_state(chip, policy_src_ready);
1622 static void fusb_state_src_send_hardreset(struct fusb30x_chip *chip, int evt)
1626 switch (chip->sub_state) {
1628 chip->tx_state = tx_idle;
1632 tmp = policy_send_hardrst(chip, evt);
1633 if (tmp == tx_success) {
1634 chip->hardrst_count++;
1635 set_state(chip, policy_src_transition_default);
1636 } else if (tmp == tx_failed) {
1637 /* can't reach here */
1638 set_state(chip, error_recovery);
1644 static void fusb_state_src_send_softreset(struct fusb30x_chip *chip, int evt)
1648 switch (chip->sub_state) {
1650 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1651 chip->tx_state = tx_idle;
1655 tmp = policy_send_data(chip);
1656 if (tmp == tx_success) {
1657 chip->timer_state = T_SENDER_RESPONSE;
1659 fusb_timer_start(&chip->timer_state_machine,
1661 } else if (tmp == tx_failed) {
1662 set_state(chip, policy_src_send_hardrst);
1665 if (!(evt & FLAG_EVENT))
1668 if (evt & EVENT_RX) {
1669 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1670 (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1671 set_state(chip, policy_src_send_caps);
1672 } else if (evt & EVENT_TIMER_STATE) {
1673 set_state(chip, policy_src_send_hardrst);
1679 static void fusb_state_snk_startup(struct fusb30x_chip *chip, int evt)
1681 chip->notify.is_pd_connected = 0;
1683 chip->vdm_state = 0;
1684 chip->vdm_substate = 0;
1685 chip->vdm_send_state = 0;
1687 chip->pos_power = 0;
1689 memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1691 tcpm_set_msg_header(chip);
1692 tcpm_set_polarity(chip, chip->cc_polarity);
1693 tcpm_set_rx_enable(chip, 1);
1694 set_state(chip, policy_snk_discovery);
1697 static void fusb_state_snk_discovery(struct fusb30x_chip *chip, int evt)
1699 set_state(chip, policy_snk_wait_caps);
1700 chip->timer_state = T_TYPEC_SINK_WAIT_CAP;
1701 fusb_timer_start(&chip->timer_state_machine,
1705 static void fusb_state_snk_wait_caps(struct fusb30x_chip *chip, int evt)
1707 if (evt & EVENT_RX) {
1708 if (PD_HEADER_CNT(chip->rec_head) &&
1709 PD_HEADER_TYPE(chip->rec_head) == DMT_SOURCECAPABILITIES) {
1710 chip->timer_mux = T_DISABLED;
1711 set_state(chip, policy_snk_evaluate_caps);
1713 } else if (evt & EVENT_TIMER_STATE) {
1714 if (chip->hardrst_count <= N_HARDRESET_COUNT)
1715 set_state(chip, policy_snk_send_hardrst);
1717 set_state(chip, disabled);
1718 } else if ((evt & EVENT_TIMER_MUX) &&
1719 (chip->hardrst_count > N_HARDRESET_COUNT)) {
1720 if (chip->notify.is_pd_connected)
1721 set_state(chip, error_recovery);
1723 set_state(chip, disabled);
1727 static void fusb_state_snk_evaluate_caps(struct fusb30x_chip *chip, int evt)
1731 chip->hardrst_count = 0;
1732 chip->pos_power = 0;
1734 for (tmp = 0; tmp < PD_HEADER_CNT(chip->rec_head); tmp++) {
1735 switch (CAP_POWER_TYPE(chip->rec_load[tmp])) {
1738 if (CAP_FPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1739 chip->pos_power = tmp + 1;
1743 if (CAP_VPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1744 chip->pos_power = tmp + 1;
1747 /* not meet battery caps */
1752 if ((!chip->pos_power) || (chip->pos_power > 7)) {
1753 chip->pos_power = 0;
1754 set_state(chip, policy_snk_wait_caps);
1756 set_state(chip, policy_snk_select_cap);
1760 static void fusb_state_snk_select_cap(struct fusb30x_chip *chip, int evt)
1764 switch (chip->sub_state) {
1766 set_mesg(chip, DMT_REQUEST, DATAMESSAGE);
1767 chip->sub_state = 1;
1768 chip->tx_state = tx_idle;
1771 tmp = policy_send_data(chip);
1773 if (tmp == tx_success) {
1774 chip->timer_state = T_SENDER_RESPONSE;
1775 fusb_timer_start(&chip->timer_state_machine,
1778 } else if (tmp == tx_failed) {
1779 set_state(chip, policy_snk_discovery);
1783 if (!(evt & FLAG_EVENT))
1786 if (evt & EVENT_RX) {
1787 if (!PD_HEADER_CNT(chip->rec_head)) {
1788 switch (PD_HEADER_TYPE(chip->rec_head)) {
1791 policy_snk_transition_sink);
1792 chip->timer_state = T_PS_TRANSITION;
1793 fusb_timer_start(&chip->timer_state_machine,
1798 if (chip->notify.is_pd_connected) {
1800 "PD connected as UFP, fetching 5V\n");
1805 policy_snk_wait_caps);
1807 * make sure don't send
1808 * hard reset to prevent
1811 chip->hardrst_count =
1812 N_HARDRESET_COUNT + 1;
1819 } else if (evt & EVENT_TIMER_STATE) {
1820 set_state(chip, policy_snk_send_hardrst);
1826 static void fusb_state_snk_transition_sink(struct fusb30x_chip *chip, int evt)
1828 if (evt & EVENT_RX) {
1829 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1830 (PD_HEADER_TYPE(chip->rec_head) == CMT_PS_RDY)) {
1831 chip->notify.is_pd_connected = 1;
1833 "PD connected as UFP, fetching 5V\n");
1834 set_state(chip, policy_snk_ready);
1835 } else if ((PD_HEADER_CNT(chip->rec_head)) &&
1836 (PD_HEADER_TYPE(chip->rec_head) ==
1837 DMT_SOURCECAPABILITIES)) {
1838 set_state(chip, policy_snk_evaluate_caps);
1840 } else if (evt & EVENT_TIMER_STATE) {
1841 set_state(chip, policy_snk_send_hardrst);
1845 static void fusb_state_snk_transition_default(struct fusb30x_chip *chip,
1848 switch (chip->sub_state) {
1850 chip->notify.is_pd_connected = 0;
1851 chip->timer_mux = T_NO_RESPONSE;
1852 fusb_timer_start(&chip->timer_mux_machine,
1854 chip->timer_state = T_PS_HARD_RESET_MAX + T_SAFE_0V;
1855 fusb_timer_start(&chip->timer_state_machine,
1857 if (chip->notify.data_role)
1858 tcpm_set_msg_header(chip);
1862 if (!tcpm_check_vbus(chip)) {
1864 chip->timer_state = T_SRC_RECOVER_MAX + T_SRC_TURN_ON;
1865 fusb_timer_start(&chip->timer_state_machine,
1867 } else if (evt & EVENT_TIMER_STATE) {
1868 set_state(chip, policy_snk_startup);
1872 if (tcpm_check_vbus(chip)) {
1873 chip->timer_state = T_DISABLED;
1874 set_state(chip, policy_snk_startup);
1875 } else if (evt & EVENT_TIMER_STATE) {
1876 set_state(chip, policy_snk_startup);
1882 static void fusb_state_snk_ready(struct fusb30x_chip *chip, int evt)
1884 /* TODO: snk_ready_function would be added later on*/
1885 platform_fusb_notify(chip);
1888 static void fusb_state_snk_send_hardreset(struct fusb30x_chip *chip, int evt)
1892 switch (chip->sub_state) {
1894 chip->tx_state = tx_idle;
1897 tmp = policy_send_hardrst(chip, evt);
1898 if (tmp == tx_success) {
1899 chip->hardrst_count++;
1900 set_state(chip, policy_snk_transition_default);
1901 } else if (tmp == tx_failed) {
1902 set_state(chip, error_recovery);
1908 static void fusb_state_snk_send_softreset(struct fusb30x_chip *chip, int evt)
1912 switch (chip->sub_state) {
1914 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1915 chip->tx_state = tx_idle;
1918 tmp = policy_send_data(chip);
1919 if (tmp == tx_success) {
1920 chip->timer_state = T_SENDER_RESPONSE;
1922 fusb_timer_start(&chip->timer_state_machine,
1924 } else if (tmp == tx_failed) {
1925 /* can't reach here */
1926 set_state(chip, policy_snk_send_hardrst);
1929 if (!(evt & FLAG_EVENT))
1932 if (evt & EVENT_RX) {
1933 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1934 (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1935 set_state(chip, policy_snk_wait_caps);
1936 } else if (evt & EVENT_TIMER_STATE) {
1937 set_state(chip, policy_snk_send_hardrst);
1943 static void state_machine_typec(struct fusb30x_chip *chip)
1948 tcpc_alert(chip, &evt);
1949 mux_alert(chip, &evt);
1953 if (chip->notify.is_cc_connected) {
1954 if (evt & EVENT_CC) {
1955 if ((chip->cc_state & 0x04) &&
1956 (chip->conn_state !=
1957 policy_snk_transition_default)) {
1958 if (!tcpm_check_vbus(chip))
1959 set_state_unattached(chip);
1960 } else if (chip->conn_state !=
1961 policy_src_transition_default) {
1962 tcpm_get_cc(chip, &cc1, &cc2);
1963 if (!(chip->cc_state & 0x01))
1965 if (cc1 == TYPEC_CC_VOLT_OPEN)
1966 set_state_unattached(chip);
1971 if (evt & EVENT_RX) {
1972 tcpm_get_message(chip);
1973 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1974 (PD_HEADER_TYPE(chip->rec_head) == CMT_SOFTRESET)) {
1975 if (chip->notify.power_role)
1976 set_state(chip, policy_src_send_softrst);
1978 set_state(chip, policy_snk_send_softrst);
1982 if (evt & EVENT_TX) {
1983 if (chip->tx_state == tx_success)
1986 switch (chip->conn_state) {
1988 fusb_state_disabled(chip, evt);
1990 case error_recovery:
1991 set_state_unattached(chip);
1994 fusb_state_unattached(chip, evt);
1996 case attach_wait_sink:
1997 fusb_state_attach_wait_sink(chip, evt);
1999 case attach_wait_source:
2000 fusb_state_attach_wait_source(chip, evt);
2002 case attached_source:
2003 fusb_state_attached_source(chip, evt);
2006 fusb_state_attached_sink(chip, evt);
2009 /* POWER DELIVERY */
2010 case policy_src_startup:
2011 fusb_state_src_startup(chip, evt);
2013 case policy_src_discovery:
2014 fusb_state_src_discovery(chip, evt);
2016 case policy_src_send_caps:
2017 fusb_state_src_send_caps(chip, evt);
2018 if (chip->conn_state != policy_src_negotiate_cap)
2020 case policy_src_negotiate_cap:
2021 fusb_state_src_negotiate_cap(chip, evt);
2023 case policy_src_transition_supply:
2024 fusb_state_src_transition_supply(chip, evt);
2026 case policy_src_cap_response:
2027 fusb_state_src_cap_response(chip, evt);
2029 case policy_src_transition_default:
2030 fusb_state_src_transition_default(chip, evt);
2032 case policy_src_ready:
2033 fusb_state_src_ready(chip, evt);
2035 case policy_src_get_sink_caps:
2036 fusb_state_src_get_sink_cap(chip, evt);
2038 case policy_src_send_hardrst:
2039 fusb_state_src_send_hardreset(chip, evt);
2041 case policy_src_send_softrst:
2042 fusb_state_src_send_softreset(chip, evt);
2046 case policy_snk_startup:
2047 fusb_state_snk_startup(chip, evt);
2049 case policy_snk_discovery:
2050 fusb_state_snk_discovery(chip, evt);
2052 case policy_snk_wait_caps:
2053 fusb_state_snk_wait_caps(chip, evt);
2055 case policy_snk_evaluate_caps:
2056 fusb_state_snk_evaluate_caps(chip, evt);
2058 case policy_snk_select_cap:
2059 fusb_state_snk_select_cap(chip, evt);
2061 case policy_snk_transition_sink:
2062 fusb_state_snk_transition_sink(chip, evt);
2064 case policy_snk_transition_default:
2065 fusb_state_snk_transition_default(chip, evt);
2067 case policy_snk_ready:
2068 fusb_state_snk_ready(chip, evt);
2070 case policy_snk_send_hardrst:
2071 fusb_state_snk_send_hardreset(chip, evt);
2073 case policy_snk_send_softrst:
2074 fusb_state_snk_send_softreset(chip, evt);
2082 if (chip->work_continue) {
2083 queue_work(chip->fusb30x_wq, &chip->work);
2087 if (!platform_get_device_irq_state(chip))
2088 fusb_irq_enable(chip);
2090 queue_work(chip->fusb30x_wq, &chip->work);
2093 static irqreturn_t cc_interrupt_handler(int irq, void *dev_id)
2095 struct fusb30x_chip *chip = dev_id;
2097 queue_work(chip->fusb30x_wq, &chip->work);
2098 fusb_irq_disable(chip);
2102 static int fusb_initialize_gpio(struct fusb30x_chip *chip)
2104 chip->gpio_int = devm_gpiod_get_optional(chip->dev, "int-n", GPIOD_IN);
2105 if (IS_ERR(chip->gpio_int))
2106 return PTR_ERR(chip->gpio_int);
2108 /* some board support vbus with other ways */
2109 chip->gpio_vbus_5v = devm_gpiod_get_optional(chip->dev, "vbus-5v",
2111 if (IS_ERR(chip->gpio_vbus_5v))
2113 "Could not get named GPIO for VBus5V!\n");
2115 gpiod_set_raw_value(chip->gpio_vbus_5v, 0);
2117 chip->gpio_vbus_other = devm_gpiod_get_optional(chip->dev,
2120 if (IS_ERR(chip->gpio_vbus_other))
2122 "Could not get named GPIO for VBusOther!\n");
2124 gpiod_set_raw_value(chip->gpio_vbus_other, 0);
2129 static enum hrtimer_restart fusb_timer_handler(struct hrtimer *timer)
2133 for (i = 0; i < fusb30x_port_used; i++) {
2134 if (timer == &fusb30x_port_info[i]->timer_state_machine) {
2135 if (fusb30x_port_info[i]->timer_state != T_DISABLED)
2136 fusb30x_port_info[i]->timer_state = 0;
2140 if (timer == &fusb30x_port_info[i]->timer_mux_machine) {
2141 if (fusb30x_port_info[i]->timer_mux != T_DISABLED)
2142 fusb30x_port_info[i]->timer_mux = 0;
2147 if (i != fusb30x_port_used)
2148 queue_work(fusb30x_port_info[i]->fusb30x_wq,
2149 &fusb30x_port_info[i]->work);
2151 return HRTIMER_NORESTART;
2154 static void fusb_initialize_timer(struct fusb30x_chip *chip)
2156 hrtimer_init(&chip->timer_state_machine, CLOCK_MONOTONIC,
2158 chip->timer_state_machine.function = fusb_timer_handler;
2160 hrtimer_init(&chip->timer_mux_machine, CLOCK_MONOTONIC,
2162 chip->timer_mux_machine.function = fusb_timer_handler;
2164 chip->timer_state = T_DISABLED;
2165 chip->timer_mux = T_DISABLED;
2168 static void fusb302_work_func(struct work_struct *work)
2170 struct fusb30x_chip *chip;
2172 chip = container_of(work, struct fusb30x_chip, work);
2173 state_machine_typec(chip);
2176 static int fusb30x_probe(struct i2c_client *client,
2177 const struct i2c_device_id *id)
2179 struct fusb30x_chip *chip;
2180 struct PD_CAP_INFO *pd_cap_info;
2183 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
2187 if (fusb30x_port_used == 0xff)
2190 chip->port_num = fusb30x_port_used++;
2191 fusb30x_port_info[chip->port_num] = chip;
2193 chip->dev = &client->dev;
2194 chip->regmap = devm_regmap_init_i2c(client, &fusb302_regmap_config);
2195 if (IS_ERR(chip->regmap)) {
2196 dev_err(&client->dev, "Failed to allocate regmap!\n");
2197 return PTR_ERR(chip->regmap);
2200 ret = fusb_initialize_gpio(chip);
2204 fusb_initialize_timer(chip);
2206 chip->fusb30x_wq = create_workqueue("fusb302_wq");
2207 INIT_WORK(&chip->work, fusb302_work_func);
2210 tcpm_set_rx_enable(chip, 0);
2211 chip->conn_state = unattached;
2212 tcpm_set_cc(chip, FUSB_MODE_DRP);
2214 chip->n_caps_used = 1;
2215 chip->source_power_supply[0] = 0x64;
2216 chip->source_max_current[0] = 0x96;
2219 * these two variable should be 1 if support DRP,
2220 * but now we do not support swap,
2221 * it will be blanked in future
2223 pd_cap_info = &chip->pd_cap_info;
2224 pd_cap_info->dual_role_power = 0;
2225 pd_cap_info->data_role_swap = 0;
2227 pd_cap_info->externally_powered = 1;
2228 pd_cap_info->usb_suspend_support = 0;
2229 pd_cap_info->usb_communications_cap = 0;
2230 pd_cap_info->supply_type = 0;
2231 pd_cap_info->peak_current = 0;
2233 chip->extcon = devm_extcon_dev_allocate(&client->dev, fusb302_cable);
2234 if (IS_ERR(chip->extcon)) {
2235 dev_err(&client->dev, "allocat extcon failed\n");
2236 return PTR_ERR(chip->extcon);
2239 ret = devm_extcon_dev_register(&client->dev, chip->extcon);
2241 dev_err(&client->dev, "failed to register extcon: %d\n",
2246 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB,
2247 EXTCON_PROP_USB_TYPEC_POLARITY);
2249 dev_err(&client->dev,
2250 "failed to set USB property capability: %d\n",
2255 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST,
2256 EXTCON_PROP_USB_TYPEC_POLARITY);
2258 dev_err(&client->dev,
2259 "failed to set USB_HOST property capability: %d\n",
2264 ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP,
2265 EXTCON_PROP_USB_TYPEC_POLARITY);
2267 dev_err(&client->dev,
2268 "failed to set DISP_DP property capability: %d\n",
2273 i2c_set_clientdata(client, chip);
2275 spin_lock_init(&chip->irq_lock);
2276 chip->enable_irq = 1;
2278 chip->gpio_int_irq = gpiod_to_irq(chip->gpio_int);
2279 if (chip->gpio_int_irq < 0) {
2280 dev_err(&client->dev,
2281 "Unable to request IRQ for INT_N GPIO! %d\n",
2283 ret = chip->gpio_int_irq;
2287 ret = devm_request_threaded_irq(&client->dev,
2290 cc_interrupt_handler,
2291 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2295 dev_err(&client->dev, "irq request failed\n");
2299 dev_info(chip->dev, "port %d probe success\n", chip->port_num);
2304 destroy_workqueue(chip->fusb30x_wq);
2308 static int fusb30x_remove(struct i2c_client *client)
2310 struct fusb30x_chip *chip = i2c_get_clientdata(client);
2312 destroy_workqueue(chip->fusb30x_wq);
2316 static const struct of_device_id fusb30x_dt_match[] = {
2317 { .compatible = FUSB30X_I2C_DEVICETREE_NAME },
2320 MODULE_DEVICE_TABLE(of, fusb30x_dt_match);
2322 static const struct i2c_device_id fusb30x_i2c_device_id[] = {
2323 { FUSB30X_I2C_DRIVER_NAME, 0 },
2326 MODULE_DEVICE_TABLE(i2c, fusb30x_i2c_device_id);
2328 static struct i2c_driver fusb30x_driver = {
2330 .name = FUSB30X_I2C_DRIVER_NAME,
2331 .of_match_table = of_match_ptr(fusb30x_dt_match),
2333 .probe = fusb30x_probe,
2334 .remove = fusb30x_remove,
2335 .id_table = fusb30x_i2c_device_id,
2338 module_i2c_driver(fusb30x_driver);
2340 MODULE_LICENSE("GPL");
2341 MODULE_AUTHOR("zain wang <zain.wang@rock-chips.com>");
2342 MODULE_DESCRIPTION("fusb302 typec pd driver");