drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  76                 REG_SET(x, name, win->offset, win->ext->name, v, true)
  77 #define VOP_SCL_SET(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  79 #define VOP_SCL_SET_EXT(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  81
  82 #define VOP_CTRL_SET(x, name, v) \
  83                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  84
  85 #define VOP_INTR_GET(vop, name) \
  86                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  87
  88 #define VOP_INTR_SET(vop, name, mask, v) \
  89                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  90                              mask, v, false)
  91
  92 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  93         do { \
  94                 int i, reg = 0, mask = 0; \
  95                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  96                         if (vop->data->intr->intrs[i] & type) { \
  97                                 reg |= (v) << i; \
  98                                 mask |= 1 << i; \
  99                         } \
 100                 } \
 101                 VOP_INTR_SET(vop, name, mask, reg); \
 102         } while (0)
 103 #define VOP_INTR_GET_TYPE(vop, name, type) \
 104                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 105
 106 #define VOP_CTRL_GET(x, name) \
 107                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 108
 109 #define VOP_WIN_GET(x, win, name) \
 110                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 111
 112 #define VOP_WIN_NAME(win, name) \
 113                 (vop_get_win_phy(win, &win->phy->name)->name)
 114
 115 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 116                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 117
 118 #define to_vop(x) container_of(x, struct vop, crtc)
 119 #define to_vop_win(x) container_of(x, struct vop_win, base)
 120 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 121
 122 struct vop_zpos {
 123         int win_id;
 124         int zpos;
 125 };
 126
 127 struct vop_plane_state {
 128         struct drm_plane_state base;
 129         int format;
 130         int zpos;
 131         struct drm_rect src;
 132         struct drm_rect dest;
 133         dma_addr_t yrgb_mst;
 134         dma_addr_t uv_mst;
 135         const uint32_t *y2r_table;
 136         const uint32_t *r2r_table;
 137         const uint32_t *r2y_table;
 138         bool enable;
 139 };
 140
 141 struct vop_win {
 142         struct vop_win *parent;
 143         struct drm_plane base;
 144
 145         int win_id;
 146         int area_id;
 147         uint32_t offset;
 148         enum drm_plane_type type;
 149         const struct vop_win_phy *phy;
 150         const struct vop_csc *csc;
 151         const uint32_t *data_formats;
 152         uint32_t nformats;
 153         struct vop *vop;
 154
 155         struct drm_property *rotation_prop;
 156         struct vop_plane_state state;
 157 };
 158
 159 struct vop {
 160         struct drm_crtc crtc;
 161         struct device *dev;
 162         struct drm_device *drm_dev;
 163         struct drm_property *plane_zpos_prop;
 164         struct drm_property *plane_feature_prop;
 165         struct drm_property *feature_prop;
 166         bool is_iommu_enabled;
 167         bool is_iommu_needed;
 168         bool is_enabled;
 169
 170         /* mutex vsync_ work */
 171         struct mutex vsync_mutex;
 172         bool vsync_work_pending;
 173         struct completion dsp_hold_completion;
 174         struct completion wait_update_complete;
 175         struct drm_pending_vblank_event *event;
 176
 177         const struct vop_data *data;
 178         int num_wins;
 179
 180         uint32_t *regsbak;
 181         void __iomem *regs;
 182
 183         /* physical map length of vop register */
 184         uint32_t len;
 185
 186         /* one time only one process allowed to config the register */
 187         spinlock_t reg_lock;
 188         /* lock vop irq reg */
 189         spinlock_t irq_lock;
 190
 191         unsigned int irq;
 192
 193         /* vop AHP clk */
 194         struct clk *hclk;
 195         /* vop dclk */
 196         struct clk *dclk;
 197         /* vop share memory frequency */
 198         struct clk *aclk;
 199
 200         /* vop dclk reset */
 201         struct reset_control *dclk_rst;
 202
 203         struct vop_win win[];
 204 };
 205
 206 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 207 {
 208         writel(v, vop->regs + offset);
 209         vop->regsbak[offset >> 2] = v;
 210 }
 211
 212 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 213 {
 214         return readl(vop->regs + offset);
 215 }
 216
 217 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 218                                     const struct vop_reg *reg)
 219 {
 220         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 221 }
 222
 223 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 224                                   uint32_t mask, uint32_t shift, uint32_t v,
 225                                   bool write_mask, bool relaxed)
 226 {
 227         if (!mask)
 228                 return;
 229
 230         if (write_mask) {
 231                 v = ((v & mask) << shift) | (mask << (shift + 16));
 232         } else {
 233                 uint32_t cached_val = vop->regsbak[offset >> 2];
 234
 235                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 236                 vop->regsbak[offset >> 2] = v;
 237         }
 238
 239         if (relaxed)
 240                 writel_relaxed(v, vop->regs + offset);
 241         else
 242                 writel(v, vop->regs + offset);
 243 }
 244
 245 static inline const struct vop_win_phy *
 246 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 247 {
 248         if (!reg->mask && win->parent)
 249                 return win->parent->phy;
 250
 251         return win->phy;
 252 }
 253
 254 static inline uint32_t vop_get_intr_type(struct vop *vop,
 255                                          const struct vop_reg *reg, int type)
 256 {
 257         uint32_t i, ret = 0;
 258         uint32_t regs = vop_read_reg(vop, 0, reg);
 259
 260         for (i = 0; i < vop->data->intr->nintrs; i++) {
 261                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 262                         ret |= vop->data->intr->intrs[i];
 263         }
 264
 265         return ret;
 266 }
 267
 268 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 269 {
 270         int i;
 271
 272         if (!table)
 273                 return;
 274
 275         for (i = 0; i < 8; i++)
 276                 vop_writel(vop, offset + i * 4, table[i]);
 277 }
 278
 279 static inline void vop_cfg_done(struct vop *vop)
 280 {
 281         VOP_CTRL_SET(vop, cfg_done, 1);
 282 }
 283
 284 static bool vop_is_allwin_disabled(struct vop *vop)
 285 {
 286         int i;
 287
 288         for (i = 0; i < vop->num_wins; i++) {
 289                 struct vop_win *win = &vop->win[i];
 290
 291                 if (VOP_WIN_GET(vop, win, enable) != 0)
 292                         return false;
 293         }
 294
 295         return true;
 296 }
 297
 298 static bool vop_is_cfg_done_complete(struct vop *vop)
 299 {
 300         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 301 }
 302
 303 static bool has_rb_swapped(uint32_t format)
 304 {
 305         switch (format) {
 306         case DRM_FORMAT_XBGR8888:
 307         case DRM_FORMAT_ABGR8888:
 308         case DRM_FORMAT_BGR888:
 309         case DRM_FORMAT_BGR565:
 310                 return true;
 311         default:
 312                 return false;
 313         }
 314 }
 315
 316 static enum vop_data_format vop_convert_format(uint32_t format)
 317 {
 318         switch (format) {
 319         case DRM_FORMAT_XRGB8888:
 320         case DRM_FORMAT_ARGB8888:
 321         case DRM_FORMAT_XBGR8888:
 322         case DRM_FORMAT_ABGR8888:
 323                 return VOP_FMT_ARGB8888;
 324         case DRM_FORMAT_RGB888:
 325         case DRM_FORMAT_BGR888:
 326                 return VOP_FMT_RGB888;
 327         case DRM_FORMAT_RGB565:
 328         case DRM_FORMAT_BGR565:
 329                 return VOP_FMT_RGB565;
 330         case DRM_FORMAT_NV12:
 331         case DRM_FORMAT_NV12_10:
 332                 return VOP_FMT_YUV420SP;
 333         case DRM_FORMAT_NV16:
 334         case DRM_FORMAT_NV16_10:
 335                 return VOP_FMT_YUV422SP;
 336         case DRM_FORMAT_NV24:
 337         case DRM_FORMAT_NV24_10:
 338                 return VOP_FMT_YUV444SP;
 339         default:
 340                 DRM_ERROR("unsupport format[%08x]\n", format);
 341                 return -EINVAL;
 342         }
 343 }
 344
 345 static bool is_yuv_support(uint32_t format)
 346 {
 347         switch (format) {
 348         case DRM_FORMAT_NV12:
 349         case DRM_FORMAT_NV12_10:
 350         case DRM_FORMAT_NV16:
 351         case DRM_FORMAT_NV16_10:
 352         case DRM_FORMAT_NV24:
 353         case DRM_FORMAT_NV24_10:
 354                 return true;
 355         default:
 356                 return false;
 357         }
 358 }
 359
 360 static bool is_yuv_10bit(uint32_t format)
 361 {
 362         switch (format) {
 363         case DRM_FORMAT_NV12_10:
 364         case DRM_FORMAT_NV16_10:
 365         case DRM_FORMAT_NV24_10:
 366                 return true;
 367         default:
 368                 return false;
 369         }
 370 }
 371
 372 static bool is_alpha_support(uint32_t format)
 373 {
 374         switch (format) {
 375         case DRM_FORMAT_ARGB8888:
 376         case DRM_FORMAT_ABGR8888:
 377                 return true;
 378         default:
 379                 return false;
 380         }
 381 }
 382
 383 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 384                                   uint32_t dst, bool is_horizontal,
 385                                   int vsu_mode, int *vskiplines)
 386 {
 387         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 388
 389         if (is_horizontal) {
 390                 if (mode == SCALE_UP)
 391                         val = GET_SCL_FT_BIC(src, dst);
 392                 else if (mode == SCALE_DOWN)
 393                         val = GET_SCL_FT_BILI_DN(src, dst);
 394         } else {
 395                 if (mode == SCALE_UP) {
 396                         if (vsu_mode == SCALE_UP_BIL)
 397                                 val = GET_SCL_FT_BILI_UP(src, dst);
 398                         else
 399                                 val = GET_SCL_FT_BIC(src, dst);
 400                 } else if (mode == SCALE_DOWN) {
 401                         if (vskiplines) {
 402                                 *vskiplines = scl_get_vskiplines(src, dst);
 403                                 val = scl_get_bili_dn_vskip(src, dst,
 404                                                             *vskiplines);
 405                         } else {
 406                                 val = GET_SCL_FT_BILI_DN(src, dst);
 407                         }
 408                 }
 409         }
 410
 411         return val;
 412 }
 413
 414 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 415                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 416                                 uint32_t dst_h, uint32_t pixel_format)
 417 {
 418         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 419         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 420         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 421         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 422         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 423         bool is_yuv = is_yuv_support(pixel_format);
 424         uint16_t cbcr_src_w = src_w / hsub;
 425         uint16_t cbcr_src_h = src_h / vsub;
 426         uint16_t vsu_mode;
 427         uint16_t lb_mode;
 428         uint32_t val;
 429         int vskiplines = 0;
 430
 431         if (!win->phy->scl)
 432                 return;
 433
 434         if (dst_w > 3840) {
 435                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 436                 return;
 437         }
 438
 439         if (!win->phy->scl->ext) {
 440                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 441                             scl_cal_scale2(src_w, dst_w));
 442                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 443                             scl_cal_scale2(src_h, dst_h));
 444                 if (is_yuv) {
 445                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 446                                     scl_cal_scale2(cbcr_src_w, dst_w));
 447                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 448                                     scl_cal_scale2(cbcr_src_h, dst_h));
 449                 }
 450                 return;
 451         }
 452
 453         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 454         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 455
 456         if (is_yuv) {
 457                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 458                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 459                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 460                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 461                 else
 462                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 463         } else {
 464                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 465                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 466                 else
 467                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 468         }
 469
 470         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 471         if (lb_mode == LB_RGB_3840X2) {
 472                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 473                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 474                         return;
 475                 }
 476                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 477                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 478                         return;
 479                 }
 480                 vsu_mode = SCALE_UP_BIL;
 481         } else if (lb_mode == LB_RGB_2560X4) {
 482                 vsu_mode = SCALE_UP_BIL;
 483         } else {
 484                 vsu_mode = SCALE_UP_BIC;
 485         }
 486
 487         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 488                                 true, 0, NULL);
 489         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 490         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 491                                 false, vsu_mode, &vskiplines);
 492         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 493
 494         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 495         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 496
 497         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 498         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 499         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 500         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 501         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 502         if (is_yuv) {
 503                 vskiplines = 0;
 504
 505                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 506                                         dst_w, true, 0, NULL);
 507                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 508                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 509                                         dst_h, false, vsu_mode, &vskiplines);
 510                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 511
 512                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 513                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 514                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 515                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 516                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 517                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 518                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 519         }
 520 }
 521
 522 /*
 523  * rk3399 colorspace path:
 524  *      Input        Win csc                     Output
 525  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 526  *    RGB        --> R2Y                  __/
 527  *
 528  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 529  *    RGB        --> 709To2020->R2Y       __/
 530  *
 531  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 532  *    RGB        --> R2Y                  __/
 533  *
 534  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 535  *    RGB        --> 709To2020->R2Y       __/
 536  *
 537  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 538  *    RGB        --> R2Y                  __/
 539  *
 540  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 541  *    RGB        --> R2Y(601)             __/
 542  *
 543  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 544  *    RGB        --> bypass               __/
 545  *
 546  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 547  *
 548  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 549  *
 550  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 551  *
 552  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 553  */
 554 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 555                          bool is_input_yuv, bool is_output_yuv,
 556                          int input_csc, int output_csc,
 557                          const uint32_t **y2r_table,
 558                          const uint32_t **r2r_table,
 559                          const uint32_t **r2y_table)
 560 {
 561         *y2r_table = NULL;
 562         *r2r_table = NULL;
 563         *r2y_table = NULL;
 564
 565         if (is_output_yuv) {
 566                 if (output_csc == CSC_BT2020) {
 567                         if (is_input_yuv) {
 568                                 if (input_csc == CSC_BT2020)
 569                                         return 0;
 570                                 *y2r_table = csc_table->y2r_bt709;
 571                         }
 572                         if (input_csc != CSC_BT2020)
 573                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 574                         *r2y_table = csc_table->r2y_bt2020;
 575                 } else {
 576                         if (is_input_yuv && input_csc == CSC_BT2020)
 577                                 *y2r_table = csc_table->y2r_bt2020;
 578                         if (input_csc == CSC_BT2020)
 579                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 580                         if (!is_input_yuv || y2r_table) {
 581                                 if (output_csc == CSC_BT709)
 582                                         *r2y_table = csc_table->r2y_bt709;
 583                                 else
 584                                         *r2y_table = csc_table->r2y_bt601;
 585                         }
 586                 }
 587
 588         } else {
 589                 if (!is_input_yuv)
 590                         return 0;
 591
 592                 /*
 593                  * is possible use bt2020 on rgb mode?
 594                  */
 595                 if (WARN_ON(output_csc == CSC_BT2020))
 596                         return -EINVAL;
 597
 598                 if (input_csc == CSC_BT2020)
 599                         *y2r_table = csc_table->y2r_bt2020;
 600                 else if (input_csc == CSC_BT709)
 601                         *y2r_table = csc_table->y2r_bt709;
 602                 else
 603                         *y2r_table = csc_table->y2r_bt601;
 604
 605                 if (input_csc == CSC_BT2020)
 606                         /*
 607                          * We don't have bt601 to bt709 table, force use bt709.
 608                          */
 609                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 610         }
 611
 612         return 0;
 613 }
 614
 615 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 616                                 struct drm_crtc_state *crtc_state)
 617 {
 618         struct vop *vop = to_vop(crtc);
 619         struct drm_atomic_state *state = crtc_state->state;
 620         const struct vop_csc_table *csc_table = vop->data->csc_table;
 621         struct drm_plane_state *pstate;
 622         struct drm_plane *plane;
 623         bool is_yuv;
 624         int ret;
 625
 626         if (!csc_table)
 627                 return 0;
 628
 629         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 630                 struct vop_plane_state *vop_plane_state;
 631
 632                 pstate = drm_atomic_get_plane_state(state, plane);
 633                 if (IS_ERR(pstate))
 634                         return PTR_ERR(pstate);
 635                 vop_plane_state = to_vop_plane_state(pstate);
 636
 637                 if (!pstate->fb)
 638                         continue;
 639                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 640
 641                 /*
 642                  * TODO: force set input and output csc mode.
 643                  */
 644                 ret = vop_csc_setup(csc_table, is_yuv, false,
 645                                     CSC_BT709, CSC_BT709,
 646                                     &vop_plane_state->y2r_table,
 647                                     &vop_plane_state->r2r_table,
 648                                     &vop_plane_state->r2y_table);
 649                 if (ret)
 650                         return ret;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 657 {
 658         unsigned long flags;
 659
 660         spin_lock_irqsave(&vop->irq_lock, flags);
 661
 662         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 663
 664         spin_unlock_irqrestore(&vop->irq_lock, flags);
 665 }
 666
 667 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 668 {
 669         unsigned long flags;
 670
 671         spin_lock_irqsave(&vop->irq_lock, flags);
 672
 673         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 674
 675         spin_unlock_irqrestore(&vop->irq_lock, flags);
 676 }
 677
 678 static void vop_enable(struct drm_crtc *crtc)
 679 {
 680         struct vop *vop = to_vop(crtc);
 681         int ret, i;
 682
 683         ret = clk_prepare_enable(vop->hclk);
 684         if (ret < 0) {
 685                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 686                 return;
 687         }
 688
 689         ret = clk_prepare_enable(vop->dclk);
 690         if (ret < 0) {
 691                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 692                 goto err_disable_hclk;
 693         }
 694
 695         ret = clk_prepare_enable(vop->aclk);
 696         if (ret < 0) {
 697                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 698                 goto err_disable_dclk;
 699         }
 700
 701         ret = pm_runtime_get_sync(vop->dev);
 702         if (ret < 0) {
 703                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 704                 return;
 705         }
 706
 707         memcpy(vop->regsbak, vop->regs, vop->len);
 708
 709         VOP_CTRL_SET(vop, global_regdone_en, 1);
 710         VOP_CTRL_SET(vop, dsp_blank, 0);
 711
 712         for (i = 0; i < vop->num_wins; i++) {
 713                 struct vop_win *win = &vop->win[i];
 714
 715                 VOP_WIN_SET(vop, win, gate, 1);
 716         }
 717         vop->is_enabled = true;
 718
 719         spin_lock(&vop->reg_lock);
 720
 721         VOP_CTRL_SET(vop, standby, 0);
 722
 723         spin_unlock(&vop->reg_lock);
 724
 725         enable_irq(vop->irq);
 726
 727         drm_crtc_vblank_on(crtc);
 728
 729         return;
 730
 731 err_disable_dclk:
 732         clk_disable_unprepare(vop->dclk);
 733 err_disable_hclk:
 734         clk_disable_unprepare(vop->hclk);
 735 }
 736
 737 static void vop_crtc_disable(struct drm_crtc *crtc)
 738 {
 739         struct vop *vop = to_vop(crtc);
 740         int i;
 741
 742         /*
 743          * We need to make sure that all windows are disabled before we
 744          * disable that crtc. Otherwise we might try to scan from a destroyed
 745          * buffer later.
 746          */
 747         for (i = 0; i < vop->num_wins; i++) {
 748                 struct vop_win *win = &vop->win[i];
 749
 750                 spin_lock(&vop->reg_lock);
 751                 VOP_WIN_SET(vop, win, enable, 0);
 752                 spin_unlock(&vop->reg_lock);
 753         }
 754         VOP_CTRL_SET(vop, afbdc_en, 0);
 755         vop_cfg_done(vop);
 756
 757         drm_crtc_vblank_off(crtc);
 758
 759         /*
 760          * Vop standby will take effect at end of current frame,
 761          * if dsp hold valid irq happen, it means standby complete.
 762          *
 763          * we must wait standby complete when we want to disable aclk,
 764          * if not, memory bus maybe dead.
 765          */
 766         reinit_completion(&vop->dsp_hold_completion);
 767         vop_dsp_hold_valid_irq_enable(vop);
 768
 769         spin_lock(&vop->reg_lock);
 770
 771         VOP_CTRL_SET(vop, standby, 1);
 772
 773         spin_unlock(&vop->reg_lock);
 774
 775         wait_for_completion(&vop->dsp_hold_completion);
 776
 777         vop_dsp_hold_valid_irq_disable(vop);
 778
 779         disable_irq(vop->irq);
 780
 781         vop->is_enabled = false;
 782         if (vop->is_iommu_enabled) {
 783                 /*
 784                  * vop standby complete, so iommu detach is safe.
 785                  */
 786                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 787                 vop->is_iommu_enabled = false;
 788         }
 789
 790         pm_runtime_put(vop->dev);
 791         clk_disable_unprepare(vop->dclk);
 792         clk_disable_unprepare(vop->aclk);
 793         clk_disable_unprepare(vop->hclk);
 794 }
 795
 796 static void vop_plane_destroy(struct drm_plane *plane)
 797 {
 798         drm_plane_cleanup(plane);
 799 }
 800
 801 static int vop_plane_prepare_fb(struct drm_plane *plane,
 802                                 const struct drm_plane_state *new_state)
 803 {
 804         if (plane->state->fb)
 805                 drm_framebuffer_reference(plane->state->fb);
 806
 807         return 0;
 808 }
 809
 810 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 811                                  const struct drm_plane_state *old_state)
 812 {
 813         if (old_state->fb)
 814                 drm_framebuffer_unreference(old_state->fb);
 815 }
 816
 817 static int vop_plane_atomic_check(struct drm_plane *plane,
 818                            struct drm_plane_state *state)
 819 {
 820         struct drm_crtc *crtc = state->crtc;
 821         struct drm_framebuffer *fb = state->fb;
 822         struct vop_win *win = to_vop_win(plane);
 823         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 824         struct drm_crtc_state *crtc_state;
 825         bool visible;
 826         int ret;
 827         struct drm_rect *dest = &vop_plane_state->dest;
 828         struct drm_rect *src = &vop_plane_state->src;
 829         struct drm_rect clip;
 830         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 831                                         DRM_PLANE_HELPER_NO_SCALING;
 832         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 833                                         DRM_PLANE_HELPER_NO_SCALING;
 834         unsigned long offset;
 835         dma_addr_t dma_addr;
 836
 837         crtc = crtc ? crtc : plane->state->crtc;
 838         /*
 839          * Both crtc or plane->state->crtc can be null.
 840          */
 841         if (!crtc || !fb)
 842                 goto out_disable;
 843
 844         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 845         if (IS_ERR(crtc_state))
 846                 return PTR_ERR(crtc_state);
 847
 848         src->x1 = state->src_x;
 849         src->y1 = state->src_y;
 850         src->x2 = state->src_x + state->src_w;
 851         src->y2 = state->src_y + state->src_h;
 852         dest->x1 = state->crtc_x;
 853         dest->y1 = state->crtc_y;
 854         dest->x2 = state->crtc_x + state->crtc_w;
 855         dest->y2 = state->crtc_y + state->crtc_h;
 856
 857         clip.x1 = 0;
 858         clip.y1 = 0;
 859         clip.x2 = crtc_state->mode.hdisplay;
 860         clip.y2 = crtc_state->mode.vdisplay;
 861
 862         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 863                                             src, dest, &clip,
 864                                             min_scale,
 865                                             max_scale,
 866                                             true, true, &visible);
 867         if (ret)
 868                 return ret;
 869
 870         if (!visible)
 871                 goto out_disable;
 872
 873         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 874         if (vop_plane_state->format < 0)
 875                 return vop_plane_state->format;
 876
 877         /*
 878          * Src.x1 can be odd when do clip, but yuv plane start point
 879          * need align with 2 pixel.
 880          */
 881         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 882                 return -EINVAL;
 883
 884         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 885         if (state->rotation & BIT(DRM_REFLECT_Y))
 886                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 887         else
 888                 offset += (src->y1 >> 16) * fb->pitches[0];
 889
 890         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 891         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 892         if (is_yuv_support(fb->pixel_format)) {
 893                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 894                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 895                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
 896
 897                 offset = (src->x1 >> 16) * bpp / hsub / 8;
 898                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 899
 900                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 901                 dma_addr += offset + fb->offsets[1];
 902                 vop_plane_state->uv_mst = dma_addr;
 903         }
 904
 905         vop_plane_state->enable = true;
 906
 907         return 0;
 908
 909 out_disable:
 910         vop_plane_state->enable = false;
 911         return 0;
 912 }
 913
 914 static void vop_plane_atomic_disable(struct drm_plane *plane,
 915                                      struct drm_plane_state *old_state)
 916 {
 917         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 918         struct vop_win *win = to_vop_win(plane);
 919         struct vop *vop = to_vop(old_state->crtc);
 920
 921         if (!old_state->crtc)
 922                 return;
 923
 924         spin_lock(&vop->reg_lock);
 925
 926         VOP_WIN_SET(vop, win, enable, 0);
 927
 928         spin_unlock(&vop->reg_lock);
 929
 930         vop_plane_state->enable = false;
 931 }
 932
 933 static void vop_plane_atomic_update(struct drm_plane *plane,
 934                 struct drm_plane_state *old_state)
 935 {
 936         struct drm_plane_state *state = plane->state;
 937         struct drm_crtc *crtc = state->crtc;
 938         struct vop_win *win = to_vop_win(plane);
 939         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 940         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 941         struct vop *vop = to_vop(state->crtc);
 942         struct drm_framebuffer *fb = state->fb;
 943         unsigned int actual_w, actual_h;
 944         unsigned int dsp_stx, dsp_sty;
 945         uint32_t act_info, dsp_info, dsp_st;
 946         struct drm_rect *src = &vop_plane_state->src;
 947         struct drm_rect *dest = &vop_plane_state->dest;
 948         const uint32_t *y2r_table = vop_plane_state->y2r_table;
 949         const uint32_t *r2r_table = vop_plane_state->r2r_table;
 950         const uint32_t *r2y_table = vop_plane_state->r2y_table;
 951         int ymirror, xmirror;
 952         uint32_t val;
 953         bool rb_swap;
 954
 955         /*
 956          * can't update plane when vop is disabled.
 957          */
 958         if (!crtc)
 959                 return;
 960
 961         if (!vop_plane_state->enable) {
 962                 vop_plane_atomic_disable(plane, old_state);
 963                 return;
 964         }
 965
 966         actual_w = drm_rect_width(src) >> 16;
 967         actual_h = drm_rect_height(src) >> 16;
 968         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 969
 970         dsp_info = (drm_rect_height(dest) - 1) << 16;
 971         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 972
 973         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 974         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 975         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 976
 977         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 978         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 979
 980         spin_lock(&vop->reg_lock);
 981
 982         VOP_WIN_SET(vop, win, xmirror, xmirror);
 983         VOP_WIN_SET(vop, win, ymirror, ymirror);
 984         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 985         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 986         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 987         if (is_yuv_support(fb->pixel_format)) {
 988                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 989                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
 990         }
 991         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
 992
 993         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 994                             drm_rect_width(dest), drm_rect_height(dest),
 995                             fb->pixel_format);
 996
 997         VOP_WIN_SET(vop, win, act_info, act_info);
 998         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 999         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1000
1001         rb_swap = has_rb_swapped(fb->pixel_format);
1002         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1003
1004         if (is_alpha_support(fb->pixel_format) &&
1005             (s->dsp_layer_sel & 0x3) != win->win_id) {
1006                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1007                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1008                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1009                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1010                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1011                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1012                         SRC_FACTOR_M0(ALPHA_ONE);
1013                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1014                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1015                 VOP_WIN_SET(vop, win, alpha_en, 1);
1016         } else {
1017                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1018                 VOP_WIN_SET(vop, win, alpha_en, 0);
1019         }
1020
1021         if (win->csc) {
1022                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1023                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1024                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1025                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1026                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1027                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1028         }
1029         VOP_WIN_SET(vop, win, enable, 1);
1030         spin_unlock(&vop->reg_lock);
1031         vop->is_iommu_needed = true;
1032 }
1033
1034 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1035         .prepare_fb = vop_plane_prepare_fb,
1036         .cleanup_fb = vop_plane_cleanup_fb,
1037         .atomic_check = vop_plane_atomic_check,
1038         .atomic_update = vop_plane_atomic_update,
1039         .atomic_disable = vop_plane_atomic_disable,
1040 };
1041
1042 void vop_atomic_plane_reset(struct drm_plane *plane)
1043 {
1044         struct vop_win *win = to_vop_win(plane);
1045         struct vop_plane_state *vop_plane_state =
1046                                         to_vop_plane_state(plane->state);
1047
1048         if (plane->state && plane->state->fb)
1049                 drm_framebuffer_unreference(plane->state->fb);
1050
1051         kfree(vop_plane_state);
1052         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1053         if (!vop_plane_state)
1054                 return;
1055
1056         vop_plane_state->zpos = win->win_id;
1057         plane->state = &vop_plane_state->base;
1058         plane->state->plane = plane;
1059 }
1060
1061 struct drm_plane_state *
1062 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1063 {
1064         struct vop_plane_state *old_vop_plane_state;
1065         struct vop_plane_state *vop_plane_state;
1066
1067         if (WARN_ON(!plane->state))
1068                 return NULL;
1069
1070         old_vop_plane_state = to_vop_plane_state(plane->state);
1071         vop_plane_state = kmemdup(old_vop_plane_state,
1072                                   sizeof(*vop_plane_state), GFP_KERNEL);
1073         if (!vop_plane_state)
1074                 return NULL;
1075
1076         __drm_atomic_helper_plane_duplicate_state(plane,
1077                                                   &vop_plane_state->base);
1078
1079         return &vop_plane_state->base;
1080 }
1081
1082 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1083                                            struct drm_plane_state *state)
1084 {
1085         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1086
1087         __drm_atomic_helper_plane_destroy_state(plane, state);
1088
1089         kfree(vop_state);
1090 }
1091
1092 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1093                                          struct drm_plane_state *state,
1094                                          struct drm_property *property,
1095                                          uint64_t val)
1096 {
1097         struct vop_win *win = to_vop_win(plane);
1098         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1099
1100         if (property == win->vop->plane_zpos_prop) {
1101                 plane_state->zpos = val;
1102                 return 0;
1103         }
1104
1105         if (property == win->rotation_prop) {
1106                 state->rotation = val;
1107                 return 0;
1108         }
1109
1110         DRM_ERROR("failed to set vop plane property\n");
1111         return -EINVAL;
1112 }
1113
1114 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1115                                          const struct drm_plane_state *state,
1116                                          struct drm_property *property,
1117                                          uint64_t *val)
1118 {
1119         struct vop_win *win = to_vop_win(plane);
1120         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1121
1122         if (property == win->vop->plane_zpos_prop) {
1123                 *val = plane_state->zpos;
1124                 return 0;
1125         }
1126
1127         if (property == win->rotation_prop) {
1128                 *val = state->rotation;
1129                 return 0;
1130         }
1131
1132         DRM_ERROR("failed to get vop plane property\n");
1133         return -EINVAL;
1134 }
1135
1136 static const struct drm_plane_funcs vop_plane_funcs = {
1137         .update_plane   = drm_atomic_helper_update_plane,
1138         .disable_plane  = drm_atomic_helper_disable_plane,
1139         .destroy = vop_plane_destroy,
1140         .reset = vop_atomic_plane_reset,
1141         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1142         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1143         .atomic_set_property = vop_atomic_plane_set_property,
1144         .atomic_get_property = vop_atomic_plane_get_property,
1145 };
1146
1147 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1148 {
1149         struct vop *vop = to_vop(crtc);
1150         unsigned long flags;
1151
1152         if (!vop->is_enabled)
1153                 return -EPERM;
1154
1155         spin_lock_irqsave(&vop->irq_lock, flags);
1156
1157         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1158
1159         spin_unlock_irqrestore(&vop->irq_lock, flags);
1160
1161         return 0;
1162 }
1163
1164 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1165 {
1166         struct vop *vop = to_vop(crtc);
1167         unsigned long flags;
1168
1169         if (!vop->is_enabled)
1170                 return;
1171
1172         spin_lock_irqsave(&vop->irq_lock, flags);
1173
1174         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1175
1176         spin_unlock_irqrestore(&vop->irq_lock, flags);
1177 }
1178
1179 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1180 {
1181         struct vop *vop = to_vop(crtc);
1182
1183         reinit_completion(&vop->wait_update_complete);
1184         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1185 }
1186
1187 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1188                                            struct drm_file *file_priv)
1189 {
1190         struct drm_device *drm = crtc->dev;
1191         struct vop *vop = to_vop(crtc);
1192         struct drm_pending_vblank_event *e;
1193         unsigned long flags;
1194
1195         spin_lock_irqsave(&drm->event_lock, flags);
1196         e = vop->event;
1197         if (e && e->base.file_priv == file_priv) {
1198                 vop->event = NULL;
1199
1200                 e->base.destroy(&e->base);
1201                 file_priv->event_space += sizeof(e->event);
1202         }
1203         spin_unlock_irqrestore(&drm->event_lock, flags);
1204 }
1205
1206 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1207         .enable_vblank = vop_crtc_enable_vblank,
1208         .disable_vblank = vop_crtc_disable_vblank,
1209         .wait_for_update = vop_crtc_wait_for_update,
1210         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1211 };
1212
1213 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1214                                 const struct drm_display_mode *mode,
1215                                 struct drm_display_mode *adjusted_mode)
1216 {
1217         struct vop *vop = to_vop(crtc);
1218
1219         adjusted_mode->clock =
1220                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1221
1222         return true;
1223 }
1224
1225 static void vop_crtc_enable(struct drm_crtc *crtc)
1226 {
1227         struct vop *vop = to_vop(crtc);
1228         const struct vop_data *vop_data = vop->data;
1229         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1230         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1231         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1232         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1233         u16 htotal = adjusted_mode->crtc_htotal;
1234         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1235         u16 hact_end = hact_st + hdisplay;
1236         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1237         u16 vtotal = adjusted_mode->crtc_vtotal;
1238         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1239         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1240         u16 vact_end = vact_st + vdisplay;
1241         uint32_t val;
1242
1243         vop_enable(crtc);
1244         /*
1245          * If dclk rate is zero, mean that scanout is stop,
1246          * we don't need wait any more.
1247          */
1248         if (clk_get_rate(vop->dclk)) {
1249                 /*
1250                  * Rk3288 vop timing register is immediately, when configure
1251                  * display timing on display time, may cause tearing.
1252                  *
1253                  * Vop standby will take effect at end of current frame,
1254                  * if dsp hold valid irq happen, it means standby complete.
1255                  *
1256                  * mode set:
1257                  *    standby and wait complete --> |----
1258                  *                                  | display time
1259                  *                                  |----
1260                  *                                  |---> dsp hold irq
1261                  *     configure display timing --> |
1262                  *         standby exit             |
1263                  *                                  | new frame start.
1264                  */
1265
1266                 reinit_completion(&vop->dsp_hold_completion);
1267                 vop_dsp_hold_valid_irq_enable(vop);
1268
1269                 spin_lock(&vop->reg_lock);
1270
1271                 VOP_CTRL_SET(vop, standby, 1);
1272
1273                 spin_unlock(&vop->reg_lock);
1274
1275                 wait_for_completion(&vop->dsp_hold_completion);
1276
1277                 vop_dsp_hold_valid_irq_disable(vop);
1278         }
1279
1280         val = 0x8;
1281         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1282         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1283         VOP_CTRL_SET(vop, pin_pol, val);
1284         switch (s->output_type) {
1285         case DRM_MODE_CONNECTOR_LVDS:
1286                 VOP_CTRL_SET(vop, rgb_en, 1);
1287                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1288                 break;
1289         case DRM_MODE_CONNECTOR_eDP:
1290                 VOP_CTRL_SET(vop, edp_en, 1);
1291                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1292                 break;
1293         case DRM_MODE_CONNECTOR_HDMIA:
1294                 VOP_CTRL_SET(vop, hdmi_en, 1);
1295                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1296                 break;
1297         case DRM_MODE_CONNECTOR_DSI:
1298                 VOP_CTRL_SET(vop, mipi_en, 1);
1299                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1300                 break;
1301         default:
1302                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1303         }
1304
1305         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1306             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1307                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1308
1309         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1310
1311         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1312         val = hact_st << 16;
1313         val |= hact_end;
1314         VOP_CTRL_SET(vop, hact_st_end, val);
1315         VOP_CTRL_SET(vop, hpost_st_end, val);
1316
1317         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1318         val = vact_st << 16;
1319         val |= vact_end;
1320         VOP_CTRL_SET(vop, vact_st_end, val);
1321         VOP_CTRL_SET(vop, vpost_st_end, val);
1322         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1323                 u16 vact_st_f1 = vtotal + vact_st + 1;
1324                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1325
1326                 val = vact_st_f1 << 16 | vact_end_f1;
1327                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1328                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1329
1330                 val = vtotal << 16 | (vtotal + vsync_len);
1331                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1332                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1333                 VOP_CTRL_SET(vop, p2i_en, 1);
1334         } else {
1335                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1336                 VOP_CTRL_SET(vop, p2i_en, 0);
1337         }
1338
1339         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1340
1341         VOP_CTRL_SET(vop, standby, 0);
1342 }
1343
1344 static int vop_zpos_cmp(const void *a, const void *b)
1345 {
1346         struct vop_zpos *pa = (struct vop_zpos *)a;
1347         struct vop_zpos *pb = (struct vop_zpos *)b;
1348
1349         return pa->zpos - pb->zpos;
1350 }
1351
1352 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1353                                   struct drm_crtc_state *crtc_state)
1354 {
1355         struct vop *vop = to_vop(crtc);
1356         const struct vop_data *vop_data = vop->data;
1357         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1358         struct drm_atomic_state *state = crtc_state->state;
1359         struct drm_plane *plane;
1360         struct drm_plane_state *pstate;
1361         struct vop_plane_state *plane_state;
1362         struct vop_win *win;
1363         int afbdc_format;
1364         int i;
1365
1366         s->afbdc_en = 0;
1367
1368         for_each_plane_in_state(state, plane, pstate, i) {
1369                 struct drm_framebuffer *fb = pstate->fb;
1370                 struct drm_rect *src;
1371
1372                 win = to_vop_win(plane);
1373                 plane_state = to_vop_plane_state(pstate);
1374
1375                 if (pstate->crtc != crtc || !fb)
1376                         continue;
1377
1378                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1379                         continue;
1380
1381                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1382                         DRM_ERROR("not support afbdc\n");
1383                         return -EINVAL;
1384                 }
1385
1386                 switch (plane_state->format) {
1387                 case VOP_FMT_ARGB8888:
1388                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1389                         break;
1390                 case VOP_FMT_RGB888:
1391                         afbdc_format = AFBDC_FMT_U8U8U8;
1392                         break;
1393                 case VOP_FMT_RGB565:
1394                         afbdc_format = AFBDC_FMT_RGB565;
1395                         break;
1396                 default:
1397                         return -EINVAL;
1398                 }
1399
1400                 if (s->afbdc_en) {
1401                         DRM_ERROR("vop only support one afbc layer\n");
1402                         return -EINVAL;
1403                 }
1404
1405                 src = &plane_state->src;
1406                 if (src->x1 || src->y1 || fb->offsets[0]) {
1407                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1408                                   win->win_id);
1409                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1410                                   src->x1, src->y1, fb->offsets[0]);
1411                         return -EINVAL;
1412                 }
1413                 s->afbdc_win_format = afbdc_format;
1414                 s->afbdc_win_width = pstate->fb->width - 1;
1415                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1416                 s->afbdc_win_id = win->win_id;
1417                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1418                 s->afbdc_en = 1;
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1425                                  struct drm_crtc_state *crtc_state)
1426 {
1427         struct drm_atomic_state *state = crtc_state->state;
1428         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1429         struct vop *vop = to_vop(crtc);
1430         const struct vop_data *vop_data = vop->data;
1431         struct drm_plane *plane;
1432         struct drm_plane_state *pstate;
1433         struct vop_plane_state *plane_state;
1434         struct vop_zpos *pzpos;
1435         int dsp_layer_sel = 0;
1436         int i, j, cnt = 0, ret = 0;
1437
1438         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1439         if (ret)
1440                 return ret;
1441
1442         ret = vop_csc_atomic_check(crtc, crtc_state);
1443         if (ret)
1444                 return ret;
1445
1446         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1447         if (!pzpos)
1448                 return -ENOMEM;
1449
1450         for (i = 0; i < vop_data->win_size; i++) {
1451                 const struct vop_win_data *win_data = &vop_data->win[i];
1452                 struct vop_win *win;
1453
1454                 if (!win_data->phy)
1455                         continue;
1456
1457                 for (j = 0; j < vop->num_wins; j++) {
1458                         win = &vop->win[j];
1459
1460                         if (win->win_id == i && !win->area_id)
1461                                 break;
1462                 }
1463                 if (WARN_ON(j >= vop->num_wins)) {
1464                         ret = -EINVAL;
1465                         goto err_free_pzpos;
1466                 }
1467
1468                 plane = &win->base;
1469                 pstate = state->plane_states[drm_plane_index(plane)];
1470                 /*
1471                  * plane might not have changed, in which case take
1472                  * current state:
1473                  */
1474                 if (!pstate)
1475                         pstate = plane->state;
1476                 plane_state = to_vop_plane_state(pstate);
1477                 pzpos[cnt].zpos = plane_state->zpos;
1478                 pzpos[cnt++].win_id = win->win_id;
1479         }
1480
1481         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1482
1483         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1484                 const struct vop_win_data *win_data = &vop_data->win[i];
1485                 int shift = i * 2;
1486
1487                 if (win_data->phy) {
1488                         struct vop_zpos *zpos = &pzpos[cnt++];
1489
1490                         dsp_layer_sel |= zpos->win_id << shift;
1491                 } else {
1492                         dsp_layer_sel |= i << shift;
1493                 }
1494         }
1495
1496         s->dsp_layer_sel = dsp_layer_sel;
1497
1498 err_free_pzpos:
1499         kfree(pzpos);
1500         return ret;
1501 }
1502
1503 static void vop_cfg_update(struct drm_crtc *crtc,
1504                            struct drm_crtc_state *old_crtc_state)
1505 {
1506         struct rockchip_crtc_state *s =
1507                         to_rockchip_crtc_state(crtc->state);
1508         struct vop *vop = to_vop(crtc);
1509
1510         spin_lock(&vop->reg_lock);
1511
1512         if (s->afbdc_en) {
1513                 uint32_t pic_size;
1514
1515                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1516                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1517                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1518                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1519                 pic_size = (s->afbdc_win_width & 0xffff);
1520                 pic_size |= s->afbdc_win_height << 16;
1521                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1522         }
1523
1524         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1525         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1526         vop_cfg_done(vop);
1527
1528         spin_unlock(&vop->reg_lock);
1529 }
1530
1531 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1532                                   struct drm_crtc_state *old_crtc_state)
1533 {
1534         struct vop *vop = to_vop(crtc);
1535
1536         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1537                 int ret;
1538                 if (!vop_is_allwin_disabled(vop)) {
1539                         vop_cfg_update(crtc, old_crtc_state);
1540                         while(!vop_is_cfg_done_complete(vop));
1541                 }
1542                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1543                 if (ret) {
1544                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1545                 }
1546                 vop->is_iommu_enabled = true;
1547         }
1548
1549         vop_cfg_update(crtc, old_crtc_state);
1550 }
1551
1552 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1553                                   struct drm_crtc_state *old_crtc_state)
1554 {
1555         struct vop *vop = to_vop(crtc);
1556
1557         if (crtc->state->event) {
1558                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1559
1560                 vop->event = crtc->state->event;
1561                 crtc->state->event = NULL;
1562         }
1563 }
1564
1565 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1566         .enable = vop_crtc_enable,
1567         .disable = vop_crtc_disable,
1568         .mode_fixup = vop_crtc_mode_fixup,
1569         .atomic_check = vop_crtc_atomic_check,
1570         .atomic_flush = vop_crtc_atomic_flush,
1571         .atomic_begin = vop_crtc_atomic_begin,
1572 };
1573
1574 static void vop_crtc_destroy(struct drm_crtc *crtc)
1575 {
1576         drm_crtc_cleanup(crtc);
1577 }
1578
1579 static void vop_crtc_reset(struct drm_crtc *crtc)
1580 {
1581         if (crtc->state)
1582                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1583         kfree(crtc->state);
1584
1585         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1586         if (crtc->state)
1587                 crtc->state->crtc = crtc;
1588 }
1589
1590 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1591 {
1592         struct rockchip_crtc_state *rockchip_state;
1593
1594         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1595         if (!rockchip_state)
1596                 return NULL;
1597
1598         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1599         return &rockchip_state->base;
1600 }
1601
1602 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1603                                    struct drm_crtc_state *state)
1604 {
1605         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1606
1607         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1608         kfree(s);
1609 }
1610
1611 static const struct drm_crtc_funcs vop_crtc_funcs = {
1612         .set_config = drm_atomic_helper_set_config,
1613         .page_flip = drm_atomic_helper_page_flip,
1614         .destroy = vop_crtc_destroy,
1615         .reset = vop_crtc_reset,
1616         .atomic_duplicate_state = vop_crtc_duplicate_state,
1617         .atomic_destroy_state = vop_crtc_destroy_state,
1618 };
1619
1620 static void vop_handle_vblank(struct vop *vop)
1621 {
1622         struct drm_device *drm = vop->drm_dev;
1623         struct drm_crtc *crtc = &vop->crtc;
1624         unsigned long flags;
1625
1626         if (!vop_is_cfg_done_complete(vop))
1627                 return;
1628
1629         if (vop->event) {
1630                 spin_lock_irqsave(&drm->event_lock, flags);
1631
1632                 drm_crtc_send_vblank_event(crtc, vop->event);
1633                 drm_crtc_vblank_put(crtc);
1634                 vop->event = NULL;
1635
1636                 spin_unlock_irqrestore(&drm->event_lock, flags);
1637         }
1638         if (!completion_done(&vop->wait_update_complete))
1639                 complete(&vop->wait_update_complete);
1640 }
1641
1642 static irqreturn_t vop_isr(int irq, void *data)
1643 {
1644         struct vop *vop = data;
1645         struct drm_crtc *crtc = &vop->crtc;
1646         uint32_t active_irqs;
1647         unsigned long flags;
1648         int ret = IRQ_NONE;
1649
1650         /*
1651          * interrupt register has interrupt status, enable and clear bits, we
1652          * must hold irq_lock to avoid a race with enable/disable_vblank().
1653         */
1654         spin_lock_irqsave(&vop->irq_lock, flags);
1655
1656         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1657         /* Clear all active interrupt sources */
1658         if (active_irqs)
1659                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1660
1661         spin_unlock_irqrestore(&vop->irq_lock, flags);
1662
1663         /* This is expected for vop iommu irqs, since the irq is shared */
1664         if (!active_irqs)
1665                 return IRQ_NONE;
1666
1667         if (active_irqs & DSP_HOLD_VALID_INTR) {
1668                 complete(&vop->dsp_hold_completion);
1669                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1670                 ret = IRQ_HANDLED;
1671         }
1672
1673         if (active_irqs & FS_INTR) {
1674                 drm_crtc_handle_vblank(crtc);
1675                 vop_handle_vblank(vop);
1676                 active_irqs &= ~FS_INTR;
1677                 ret = IRQ_HANDLED;
1678         }
1679
1680         /* Unhandled irqs are spurious. */
1681         if (active_irqs)
1682                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1683
1684         return ret;
1685 }
1686
1687 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1688                           unsigned long possible_crtcs)
1689 {
1690         struct drm_plane *share = NULL;
1691         unsigned int rotations = 0;
1692         struct drm_property *prop;
1693         uint64_t feature = 0;
1694         int ret;
1695
1696         if (win->parent)
1697                 share = &win->parent->base;
1698
1699         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1700                                    possible_crtcs, &vop_plane_funcs,
1701                                    win->data_formats, win->nformats, win->type);
1702         if (ret) {
1703                 DRM_ERROR("failed to initialize plane\n");
1704                 return ret;
1705         }
1706         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1707         drm_object_attach_property(&win->base.base,
1708                                    vop->plane_zpos_prop, win->win_id);
1709
1710         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1711                 rotations |= BIT(DRM_REFLECT_X);
1712
1713         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1714                 rotations |= BIT(DRM_REFLECT_Y);
1715
1716         if (rotations) {
1717                 rotations |= BIT(DRM_ROTATE_0);
1718                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1719                                                          rotations);
1720                 if (!prop) {
1721                         DRM_ERROR("failed to create zpos property\n");
1722                         return -EINVAL;
1723                 }
1724                 drm_object_attach_property(&win->base.base, prop,
1725                                            BIT(DRM_ROTATE_0));
1726                 win->rotation_prop = prop;
1727         }
1728         if (win->phy->scl)
1729                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1730         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1731             VOP_WIN_SUPPORT(vop, win, alpha_en))
1732                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1733
1734         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1735                                    feature);
1736
1737         return 0;
1738 }
1739
1740 static int vop_create_crtc(struct vop *vop)
1741 {
1742         struct device *dev = vop->dev;
1743         struct drm_device *drm_dev = vop->drm_dev;
1744         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1745         struct drm_crtc *crtc = &vop->crtc;
1746         struct device_node *port;
1747         uint64_t feature = 0;
1748         int ret;
1749         int i;
1750
1751         /*
1752          * Create drm_plane for primary and cursor planes first, since we need
1753          * to pass them to drm_crtc_init_with_planes, which sets the
1754          * "possible_crtcs" to the newly initialized crtc.
1755          */
1756         for (i = 0; i < vop->num_wins; i++) {
1757                 struct vop_win *win = &vop->win[i];
1758
1759                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1760                     win->type != DRM_PLANE_TYPE_CURSOR)
1761                         continue;
1762
1763                 ret = vop_plane_init(vop, win, 0);
1764                 if (ret)
1765                         goto err_cleanup_planes;
1766
1767                 plane = &win->base;
1768                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1769                         primary = plane;
1770                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1771                         cursor = plane;
1772
1773         }
1774
1775         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1776                                         &vop_crtc_funcs, NULL);
1777         if (ret)
1778                 goto err_cleanup_planes;
1779
1780         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1781
1782         /*
1783          * Create drm_planes for overlay windows with possible_crtcs restricted
1784          * to the newly created crtc.
1785          */
1786         for (i = 0; i < vop->num_wins; i++) {
1787                 struct vop_win *win = &vop->win[i];
1788                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1789
1790                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1791                         continue;
1792
1793                 ret = vop_plane_init(vop, win, possible_crtcs);
1794                 if (ret)
1795                         goto err_cleanup_crtc;
1796         }
1797
1798         port = of_get_child_by_name(dev->of_node, "port");
1799         if (!port) {
1800                 DRM_ERROR("no port node found in %s\n",
1801                           dev->of_node->full_name);
1802                 ret = -ENOENT;
1803                 goto err_cleanup_crtc;
1804         }
1805
1806         init_completion(&vop->dsp_hold_completion);
1807         init_completion(&vop->wait_update_complete);
1808         crtc->port = port;
1809         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1810
1811         if (VOP_CTRL_SUPPORT(vop, afbdc_en))
1812                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
1813         drm_object_attach_property(&crtc->base, vop->feature_prop,
1814                                    feature);
1815
1816         return 0;
1817
1818 err_cleanup_crtc:
1819         drm_crtc_cleanup(crtc);
1820 err_cleanup_planes:
1821         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1822                                  head)
1823                 drm_plane_cleanup(plane);
1824         return ret;
1825 }
1826
1827 static void vop_destroy_crtc(struct vop *vop)
1828 {
1829         struct drm_crtc *crtc = &vop->crtc;
1830         struct drm_device *drm_dev = vop->drm_dev;
1831         struct drm_plane *plane, *tmp;
1832
1833         rockchip_unregister_crtc_funcs(crtc);
1834         of_node_put(crtc->port);
1835
1836         /*
1837          * We need to cleanup the planes now.  Why?
1838          *
1839          * The planes are "&vop->win[i].base".  That means the memory is
1840          * all part of the big "struct vop" chunk of memory.  That memory
1841          * was devm allocated and associated with this component.  We need to
1842          * free it ourselves before vop_unbind() finishes.
1843          */
1844         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1845                                  head)
1846                 vop_plane_destroy(plane);
1847
1848         /*
1849          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1850          * references the CRTC.
1851          */
1852         drm_crtc_cleanup(crtc);
1853 }
1854
1855 /*
1856  * Initialize the vop->win array elements.
1857  */
1858 static int vop_win_init(struct vop *vop)
1859 {
1860         const struct vop_data *vop_data = vop->data;
1861         unsigned int i, j;
1862         unsigned int num_wins = 0;
1863         struct drm_property *prop;
1864         static const struct drm_prop_enum_list props[] = {
1865                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1866                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1867         };
1868         static const struct drm_prop_enum_list crtc_props[] = {
1869                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
1870         };
1871
1872         for (i = 0; i < vop_data->win_size; i++) {
1873                 struct vop_win *vop_win = &vop->win[num_wins];
1874                 const struct vop_win_data *win_data = &vop_data->win[i];
1875
1876                 if (!win_data->phy)
1877                         continue;
1878
1879                 vop_win->phy = win_data->phy;
1880                 vop_win->csc = win_data->csc;
1881                 vop_win->offset = win_data->base;
1882                 vop_win->type = win_data->type;
1883                 vop_win->data_formats = win_data->phy->data_formats;
1884                 vop_win->nformats = win_data->phy->nformats;
1885                 vop_win->vop = vop;
1886                 vop_win->win_id = i;
1887                 vop_win->area_id = 0;
1888                 num_wins++;
1889
1890                 for (j = 0; j < win_data->area_size; j++) {
1891                         struct vop_win *vop_area = &vop->win[num_wins];
1892                         const struct vop_win_phy *area = win_data->area[j];
1893
1894                         vop_area->parent = vop_win;
1895                         vop_area->offset = vop_win->offset;
1896                         vop_area->phy = area;
1897                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1898                         vop_area->data_formats = vop_win->data_formats;
1899                         vop_area->nformats = vop_win->nformats;
1900                         vop_area->vop = vop;
1901                         vop_area->win_id = i;
1902                         vop_area->area_id = j;
1903                         num_wins++;
1904                 }
1905         }
1906
1907         vop->num_wins = num_wins;
1908
1909         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1910                                          "ZPOS", 0, vop->data->win_size);
1911         if (!prop) {
1912                 DRM_ERROR("failed to create zpos property\n");
1913                 return -EINVAL;
1914         }
1915         vop->plane_zpos_prop = prop;
1916
1917         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1918                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1919                                 props, ARRAY_SIZE(props),
1920                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1921                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1922         if (!vop->plane_feature_prop) {
1923                 DRM_ERROR("failed to create feature property\n");
1924                 return -EINVAL;
1925         }
1926
1927         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
1928                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1929                                 props, ARRAY_SIZE(crtc_props),
1930                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
1931         if (!vop->feature_prop) {
1932                 DRM_ERROR("failed to create vop feature property\n");
1933                 return -EINVAL;
1934         }
1935
1936         return 0;
1937 }
1938
1939 static int vop_bind(struct device *dev, struct device *master, void *data)
1940 {
1941         struct platform_device *pdev = to_platform_device(dev);
1942         const struct vop_data *vop_data;
1943         struct drm_device *drm_dev = data;
1944         struct vop *vop;
1945         struct resource *res;
1946         size_t alloc_size;
1947         int ret, irq, i;
1948         int num_wins = 0;
1949
1950         vop_data = of_device_get_match_data(dev);
1951         if (!vop_data)
1952                 return -ENODEV;
1953
1954         for (i = 0; i < vop_data->win_size; i++) {
1955                 const struct vop_win_data *win_data = &vop_data->win[i];
1956
1957                 num_wins += win_data->area_size + 1;
1958         }
1959
1960         /* Allocate vop struct and its vop_win array */
1961         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1962         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1963         if (!vop)
1964                 return -ENOMEM;
1965
1966         vop->dev = dev;
1967         vop->data = vop_data;
1968         vop->drm_dev = drm_dev;
1969         vop->num_wins = num_wins;
1970         dev_set_drvdata(dev, vop);
1971
1972         ret = vop_win_init(vop);
1973         if (ret)
1974                 return ret;
1975
1976         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1977         vop->len = resource_size(res);
1978         vop->regs = devm_ioremap_resource(dev, res);
1979         if (IS_ERR(vop->regs))
1980                 return PTR_ERR(vop->regs);
1981
1982         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1983         if (!vop->regsbak)
1984                 return -ENOMEM;
1985
1986         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1987         if (IS_ERR(vop->hclk)) {
1988                 dev_err(vop->dev, "failed to get hclk source\n");
1989                 return PTR_ERR(vop->hclk);
1990         }
1991         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1992         if (IS_ERR(vop->aclk)) {
1993                 dev_err(vop->dev, "failed to get aclk source\n");
1994                 return PTR_ERR(vop->aclk);
1995         }
1996         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1997         if (IS_ERR(vop->dclk)) {
1998                 dev_err(vop->dev, "failed to get dclk source\n");
1999                 return PTR_ERR(vop->dclk);
2000         }
2001
2002         irq = platform_get_irq(pdev, 0);
2003         if (irq < 0) {
2004                 dev_err(dev, "cannot find irq for vop\n");
2005                 return irq;
2006         }
2007         vop->irq = (unsigned int)irq;
2008
2009         spin_lock_init(&vop->reg_lock);
2010         spin_lock_init(&vop->irq_lock);
2011
2012         mutex_init(&vop->vsync_mutex);
2013
2014         ret = devm_request_irq(dev, vop->irq, vop_isr,
2015                                IRQF_SHARED, dev_name(dev), vop);
2016         if (ret)
2017                 return ret;
2018
2019         /* IRQ is initially disabled; it gets enabled in power_on */
2020         disable_irq(vop->irq);
2021
2022         ret = vop_create_crtc(vop);
2023         if (ret)
2024                 return ret;
2025
2026         pm_runtime_enable(&pdev->dev);
2027         return 0;
2028 }
2029
2030 static void vop_unbind(struct device *dev, struct device *master, void *data)
2031 {
2032         struct vop *vop = dev_get_drvdata(dev);
2033
2034         pm_runtime_disable(dev);
2035         vop_destroy_crtc(vop);
2036 }
2037
2038 const struct component_ops vop_component_ops = {
2039         .bind = vop_bind,
2040         .unbind = vop_unbind,
2041 };
2042 EXPORT_SYMBOL_GPL(vop_component_ops);