drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, win, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, win, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_SCL_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  77 #define VOP_SCL_SET_EXT(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  79
  80 #define VOP_CTRL_SET(x, name, v) \
  81                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  82
  83 #define VOP_INTR_GET(vop, name) \
  84                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  85
  86 #define VOP_INTR_SET(vop, name, mask, v) \
  87                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  88                              mask, v, false)
  89
  90 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  91         do { \
  92                 int i, reg = 0, mask = 0; \
  93                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  94                         if (vop->data->intr->intrs[i] & type) { \
  95                                 reg |= (v) << i; \
  96                                 mask |= 1 << i; \
  97                         } \
  98                 } \
  99                 VOP_INTR_SET(vop, name, mask, reg); \
 100         } while (0)
 101 #define VOP_INTR_GET_TYPE(vop, name, type) \
 102                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 103
 104 #define VOP_CTRL_GET(x, name) \
 105                 vop_read_reg(x, 0, vop->data->ctrl->name)
 106
 107 #define VOP_WIN_GET(x, win, name) \
 108                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 109
 110 #define VOP_WIN_NAME(win, name) \
 111                 (vop_get_win_phy(win, &win->phy->name)->name)
 112
 113 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 114                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 115
 116 #define to_vop(x) container_of(x, struct vop, crtc)
 117 #define to_vop_win(x) container_of(x, struct vop_win, base)
 118 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 119
 120 struct vop_zpos {
 121         int win_id;
 122         int zpos;
 123 };
 124
 125 struct vop_plane_state {
 126         struct drm_plane_state base;
 127         int format;
 128         int zpos;
 129         struct drm_rect src;
 130         struct drm_rect dest;
 131         dma_addr_t yrgb_mst;
 132         bool enable;
 133 };
 134
 135 struct vop_win {
 136         struct vop_win *parent;
 137         struct drm_plane base;
 138
 139         int win_id;
 140         int area_id;
 141         uint32_t offset;
 142         enum drm_plane_type type;
 143         const struct vop_win_phy *phy;
 144         const uint32_t *data_formats;
 145         uint32_t nformats;
 146         struct vop *vop;
 147
 148         struct drm_property *rotation_prop;
 149         struct vop_plane_state state;
 150 };
 151
 152 struct vop {
 153         struct drm_crtc crtc;
 154         struct device *dev;
 155         struct drm_device *drm_dev;
 156         struct drm_property *plane_zpos_prop;
 157         struct drm_property *plane_feature_prop;
 158         bool is_iommu_enabled;
 159         bool is_iommu_needed;
 160
 161         /* mutex vsync_ work */
 162         struct mutex vsync_mutex;
 163         bool vsync_work_pending;
 164         struct completion dsp_hold_completion;
 165         struct completion wait_update_complete;
 166         struct drm_pending_vblank_event *event;
 167
 168         const struct vop_data *data;
 169         int num_wins;
 170
 171         uint32_t *regsbak;
 172         void __iomem *regs;
 173
 174         /* physical map length of vop register */
 175         uint32_t len;
 176
 177         /* one time only one process allowed to config the register */
 178         spinlock_t reg_lock;
 179         /* lock vop irq reg */
 180         spinlock_t irq_lock;
 181
 182         unsigned int irq;
 183
 184         /* vop AHP clk */
 185         struct clk *hclk;
 186         /* vop dclk */
 187         struct clk *dclk;
 188         /* vop share memory frequency */
 189         struct clk *aclk;
 190
 191         /* vop dclk reset */
 192         struct reset_control *dclk_rst;
 193
 194         struct vop_win win[];
 195 };
 196
 197 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 198 {
 199         writel(v, vop->regs + offset);
 200         vop->regsbak[offset >> 2] = v;
 201 }
 202
 203 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 204 {
 205         return readl(vop->regs + offset);
 206 }
 207
 208 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 209                                     const struct vop_reg *reg)
 210 {
 211         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 212 }
 213
 214 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 215                                   uint32_t mask, uint32_t shift, uint32_t v,
 216                                   bool write_mask, bool relaxed)
 217 {
 218         if (!mask)
 219                 return;
 220
 221         if (write_mask) {
 222                 v = ((v & mask) << shift) | (mask << (shift + 16));
 223         } else {
 224                 uint32_t cached_val = vop->regsbak[offset >> 2];
 225
 226                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 227                 vop->regsbak[offset >> 2] = v;
 228         }
 229
 230         if (relaxed)
 231                 writel_relaxed(v, vop->regs + offset);
 232         else
 233                 writel(v, vop->regs + offset);
 234 }
 235
 236 static inline const struct vop_win_phy *
 237 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 238 {
 239         if (!reg->mask && win->parent)
 240                 return win->parent->phy;
 241
 242         return win->phy;
 243 }
 244
 245 static inline uint32_t vop_get_intr_type(struct vop *vop,
 246                                          const struct vop_reg *reg, int type)
 247 {
 248         uint32_t i, ret = 0;
 249         uint32_t regs = vop_read_reg(vop, 0, reg);
 250
 251         for (i = 0; i < vop->data->intr->nintrs; i++) {
 252                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 253                         ret |= vop->data->intr->intrs[i];
 254         }
 255
 256         return ret;
 257 }
 258
 259 static inline void vop_cfg_done(struct vop *vop)
 260 {
 261         VOP_CTRL_SET(vop, cfg_done, 1);
 262 }
 263
 264 static bool vop_is_allwin_disabled(struct vop *vop)
 265 {
 266         int i;
 267
 268         for (i = 0; i < vop->num_wins; i++) {
 269                 struct vop_win *win = &vop->win[i];
 270
 271                 if (VOP_WIN_GET(vop, win, enable) != 0)
 272                         return false;
 273         }
 274
 275         return true;
 276 }
 277
 278 static bool vop_win_pending_is_complete(struct vop *vop)
 279 {
 280         dma_addr_t yrgb_mst;
 281         int i;
 282
 283         for (i = 0; i < vop->num_wins; i++) {
 284                 struct vop_win *win = &vop->win[i];
 285                 struct drm_plane *plane = &win->base;
 286                 struct vop_plane_state *state =
 287                                 to_vop_plane_state(plane->state);
 288                 if (!state->enable) {
 289                         if (VOP_WIN_GET(vop, win, enable) != 0)
 290                                 return false;
 291                         continue;
 292                 }
 293                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop, win);
 294                 if (yrgb_mst != state->yrgb_mst)
 295                         return false;
 296         }
 297
 298         return true;
 299 }
 300
 301 static bool has_rb_swapped(uint32_t format)
 302 {
 303         switch (format) {
 304         case DRM_FORMAT_XBGR8888:
 305         case DRM_FORMAT_ABGR8888:
 306         case DRM_FORMAT_BGR888:
 307         case DRM_FORMAT_BGR565:
 308                 return true;
 309         default:
 310                 return false;
 311         }
 312 }
 313
 314 static enum vop_data_format vop_convert_format(uint32_t format)
 315 {
 316         switch (format) {
 317         case DRM_FORMAT_XRGB8888:
 318         case DRM_FORMAT_ARGB8888:
 319         case DRM_FORMAT_XBGR8888:
 320         case DRM_FORMAT_ABGR8888:
 321                 return VOP_FMT_ARGB8888;
 322         case DRM_FORMAT_RGB888:
 323         case DRM_FORMAT_BGR888:
 324                 return VOP_FMT_RGB888;
 325         case DRM_FORMAT_RGB565:
 326         case DRM_FORMAT_BGR565:
 327                 return VOP_FMT_RGB565;
 328         case DRM_FORMAT_NV12:
 329                 return VOP_FMT_YUV420SP;
 330         case DRM_FORMAT_NV16:
 331                 return VOP_FMT_YUV422SP;
 332         case DRM_FORMAT_NV24:
 333                 return VOP_FMT_YUV444SP;
 334         default:
 335                 DRM_ERROR("unsupport format[%08x]\n", format);
 336                 return -EINVAL;
 337         }
 338 }
 339
 340 static bool is_yuv_support(uint32_t format)
 341 {
 342         switch (format) {
 343         case DRM_FORMAT_NV12:
 344         case DRM_FORMAT_NV16:
 345         case DRM_FORMAT_NV24:
 346                 return true;
 347         default:
 348                 return false;
 349         }
 350 }
 351
 352 static bool is_alpha_support(uint32_t format)
 353 {
 354         switch (format) {
 355         case DRM_FORMAT_ARGB8888:
 356         case DRM_FORMAT_ABGR8888:
 357                 return true;
 358         default:
 359                 return false;
 360         }
 361 }
 362
 363 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 364                                   uint32_t dst, bool is_horizontal,
 365                                   int vsu_mode, int *vskiplines)
 366 {
 367         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 368
 369         if (is_horizontal) {
 370                 if (mode == SCALE_UP)
 371                         val = GET_SCL_FT_BIC(src, dst);
 372                 else if (mode == SCALE_DOWN)
 373                         val = GET_SCL_FT_BILI_DN(src, dst);
 374         } else {
 375                 if (mode == SCALE_UP) {
 376                         if (vsu_mode == SCALE_UP_BIL)
 377                                 val = GET_SCL_FT_BILI_UP(src, dst);
 378                         else
 379                                 val = GET_SCL_FT_BIC(src, dst);
 380                 } else if (mode == SCALE_DOWN) {
 381                         if (vskiplines) {
 382                                 *vskiplines = scl_get_vskiplines(src, dst);
 383                                 val = scl_get_bili_dn_vskip(src, dst,
 384                                                             *vskiplines);
 385                         } else {
 386                                 val = GET_SCL_FT_BILI_DN(src, dst);
 387                         }
 388                 }
 389         }
 390
 391         return val;
 392 }
 393
 394 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 395                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 396                                 uint32_t dst_h, uint32_t pixel_format)
 397 {
 398         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 399         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 400         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 401         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 402         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 403         bool is_yuv = is_yuv_support(pixel_format);
 404         uint16_t cbcr_src_w = src_w / hsub;
 405         uint16_t cbcr_src_h = src_h / vsub;
 406         uint16_t vsu_mode;
 407         uint16_t lb_mode;
 408         uint32_t val;
 409         int vskiplines = 0;
 410
 411         if (!win->phy->scl)
 412                 return;
 413
 414         if (dst_w > 3840) {
 415                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 416                 return;
 417         }
 418
 419         if (!win->phy->scl->ext) {
 420                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 421                             scl_cal_scale2(src_w, dst_w));
 422                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 423                             scl_cal_scale2(src_h, dst_h));
 424                 if (is_yuv) {
 425                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 426                                     scl_cal_scale2(cbcr_src_w, dst_w));
 427                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 428                                     scl_cal_scale2(cbcr_src_h, dst_h));
 429                 }
 430                 return;
 431         }
 432
 433         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 434         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 435
 436         if (is_yuv) {
 437                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 438                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 439                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 440                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 441                 else
 442                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 443         } else {
 444                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 445                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 446                 else
 447                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 448         }
 449
 450         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 451         if (lb_mode == LB_RGB_3840X2) {
 452                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 453                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 454                         return;
 455                 }
 456                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 457                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 458                         return;
 459                 }
 460                 vsu_mode = SCALE_UP_BIL;
 461         } else if (lb_mode == LB_RGB_2560X4) {
 462                 vsu_mode = SCALE_UP_BIL;
 463         } else {
 464                 vsu_mode = SCALE_UP_BIC;
 465         }
 466
 467         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 468                                 true, 0, NULL);
 469         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 470         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 471                                 false, vsu_mode, &vskiplines);
 472         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 473
 474         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 475         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 476
 477         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 478         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 479         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 480         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 481         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 482         if (is_yuv) {
 483                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 484                                         dst_w, true, 0, NULL);
 485                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 486                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 487                                         dst_h, false, vsu_mode, &vskiplines);
 488                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 489
 490                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 491                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 492                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 493                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 494                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 495                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 496                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 497         }
 498 }
 499
 500 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 501 {
 502         unsigned long flags;
 503
 504         spin_lock_irqsave(&vop->irq_lock, flags);
 505
 506         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 507
 508         spin_unlock_irqrestore(&vop->irq_lock, flags);
 509 }
 510
 511 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 512 {
 513         unsigned long flags;
 514
 515         spin_lock_irqsave(&vop->irq_lock, flags);
 516
 517         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 518
 519         spin_unlock_irqrestore(&vop->irq_lock, flags);
 520 }
 521
 522 static void vop_enable(struct drm_crtc *crtc)
 523 {
 524         struct vop *vop = to_vop(crtc);
 525         int ret, i;
 526
 527         ret = clk_prepare_enable(vop->hclk);
 528         if (ret < 0) {
 529                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 530                 return;
 531         }
 532
 533         ret = clk_prepare_enable(vop->dclk);
 534         if (ret < 0) {
 535                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 536                 goto err_disable_hclk;
 537         }
 538
 539         ret = clk_prepare_enable(vop->aclk);
 540         if (ret < 0) {
 541                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 542                 goto err_disable_dclk;
 543         }
 544
 545         ret = pm_runtime_get_sync(vop->dev);
 546         if (ret < 0) {
 547                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 548                 return;
 549         }
 550
 551         memcpy(vop->regsbak, vop->regs, vop->len);
 552
 553         VOP_CTRL_SET(vop, global_regdone_en, 1);
 554
 555         for (i = 0; i < vop->num_wins; i++) {
 556                 struct vop_win *win = &vop->win[i];
 557
 558                 VOP_WIN_SET(vop, win, gate, 1);
 559         }
 560
 561         spin_lock(&vop->reg_lock);
 562
 563         VOP_CTRL_SET(vop, standby, 0);
 564
 565         spin_unlock(&vop->reg_lock);
 566
 567         enable_irq(vop->irq);
 568
 569         drm_crtc_vblank_on(crtc);
 570
 571         return;
 572
 573 err_disable_dclk:
 574         clk_disable_unprepare(vop->dclk);
 575 err_disable_hclk:
 576         clk_disable_unprepare(vop->hclk);
 577 }
 578
 579 static void vop_crtc_disable(struct drm_crtc *crtc)
 580 {
 581         struct vop *vop = to_vop(crtc);
 582         int i;
 583
 584         /*
 585          * We need to make sure that all windows are disabled before we
 586          * disable that crtc. Otherwise we might try to scan from a destroyed
 587          * buffer later.
 588          */
 589         for (i = 0; i < vop->num_wins; i++) {
 590                 struct vop_win *win = &vop->win[i];
 591
 592                 spin_lock(&vop->reg_lock);
 593                 VOP_WIN_SET(vop, win, enable, 0);
 594                 spin_unlock(&vop->reg_lock);
 595         }
 596         vop_cfg_done(vop);
 597
 598         drm_crtc_vblank_off(crtc);
 599
 600         /*
 601          * Vop standby will take effect at end of current frame,
 602          * if dsp hold valid irq happen, it means standby complete.
 603          *
 604          * we must wait standby complete when we want to disable aclk,
 605          * if not, memory bus maybe dead.
 606          */
 607         reinit_completion(&vop->dsp_hold_completion);
 608         vop_dsp_hold_valid_irq_enable(vop);
 609
 610         spin_lock(&vop->reg_lock);
 611
 612         VOP_CTRL_SET(vop, standby, 1);
 613
 614         spin_unlock(&vop->reg_lock);
 615
 616         wait_for_completion(&vop->dsp_hold_completion);
 617
 618         vop_dsp_hold_valid_irq_disable(vop);
 619
 620         disable_irq(vop->irq);
 621
 622         if (vop->is_iommu_enabled) {
 623                 /*
 624                  * vop standby complete, so iommu detach is safe.
 625                  */
 626                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 627                 vop->is_iommu_enabled = false;
 628         }
 629
 630         pm_runtime_put(vop->dev);
 631         clk_disable_unprepare(vop->dclk);
 632         clk_disable_unprepare(vop->aclk);
 633         clk_disable_unprepare(vop->hclk);
 634 }
 635
 636 static void vop_plane_destroy(struct drm_plane *plane)
 637 {
 638         drm_plane_cleanup(plane);
 639 }
 640
 641 static int vop_plane_prepare_fb(struct drm_plane *plane,
 642                                 const struct drm_plane_state *new_state)
 643 {
 644         if (plane->state->fb)
 645                 drm_framebuffer_reference(plane->state->fb);
 646
 647         return 0;
 648 }
 649
 650 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 651                                  const struct drm_plane_state *old_state)
 652 {
 653         if (old_state->fb)
 654                 drm_framebuffer_unreference(old_state->fb);
 655 }
 656
 657 static int vop_plane_atomic_check(struct drm_plane *plane,
 658                            struct drm_plane_state *state)
 659 {
 660         struct drm_crtc *crtc = state->crtc;
 661         struct drm_framebuffer *fb = state->fb;
 662         struct vop_win *win = to_vop_win(plane);
 663         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 664         struct drm_crtc_state *crtc_state;
 665         bool visible;
 666         int ret;
 667         struct drm_rect *dest = &vop_plane_state->dest;
 668         struct drm_rect *src = &vop_plane_state->src;
 669         struct drm_rect clip;
 670         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 671                                         DRM_PLANE_HELPER_NO_SCALING;
 672         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 673                                         DRM_PLANE_HELPER_NO_SCALING;
 674
 675         crtc = crtc ? crtc : plane->state->crtc;
 676         /*
 677          * Both crtc or plane->state->crtc can be null.
 678          */
 679         if (!crtc || !fb)
 680                 goto out_disable;
 681
 682         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 683         if (IS_ERR(crtc_state))
 684                 return PTR_ERR(crtc_state);
 685
 686         src->x1 = state->src_x;
 687         src->y1 = state->src_y;
 688         src->x2 = state->src_x + state->src_w;
 689         src->y2 = state->src_y + state->src_h;
 690         dest->x1 = state->crtc_x;
 691         dest->y1 = state->crtc_y;
 692         dest->x2 = state->crtc_x + state->crtc_w;
 693         dest->y2 = state->crtc_y + state->crtc_h;
 694
 695         clip.x1 = 0;
 696         clip.y1 = 0;
 697         clip.x2 = crtc_state->mode.hdisplay;
 698         clip.y2 = crtc_state->mode.vdisplay;
 699
 700         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 701                                             src, dest, &clip,
 702                                             min_scale,
 703                                             max_scale,
 704                                             true, true, &visible);
 705         if (ret)
 706                 return ret;
 707
 708         if (!visible)
 709                 goto out_disable;
 710
 711         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 712         if (vop_plane_state->format < 0)
 713                 return vop_plane_state->format;
 714
 715         /*
 716          * Src.x1 can be odd when do clip, but yuv plane start point
 717          * need align with 2 pixel.
 718          */
 719         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 720                 return -EINVAL;
 721
 722         vop_plane_state->enable = true;
 723
 724         return 0;
 725
 726 out_disable:
 727         vop_plane_state->enable = false;
 728         return 0;
 729 }
 730
 731 static void vop_plane_atomic_disable(struct drm_plane *plane,
 732                                      struct drm_plane_state *old_state)
 733 {
 734         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 735         struct vop_win *win = to_vop_win(plane);
 736         struct vop *vop = to_vop(old_state->crtc);
 737
 738         if (!old_state->crtc)
 739                 return;
 740
 741         spin_lock(&vop->reg_lock);
 742
 743         VOP_WIN_SET(vop, win, enable, 0);
 744
 745         spin_unlock(&vop->reg_lock);
 746
 747         vop_plane_state->enable = false;
 748 }
 749
 750 static void vop_plane_atomic_update(struct drm_plane *plane,
 751                 struct drm_plane_state *old_state)
 752 {
 753         struct drm_plane_state *state = plane->state;
 754         struct drm_crtc *crtc = state->crtc;
 755         struct vop_win *win = to_vop_win(plane);
 756         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 757         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 758         struct vop *vop = to_vop(state->crtc);
 759         struct drm_framebuffer *fb = state->fb;
 760         unsigned int actual_w, actual_h;
 761         unsigned int dsp_stx, dsp_sty;
 762         uint32_t act_info, dsp_info, dsp_st;
 763         struct drm_rect *src = &vop_plane_state->src;
 764         struct drm_rect *dest = &vop_plane_state->dest;
 765         unsigned long offset;
 766         dma_addr_t dma_addr;
 767         int ymirror, xmirror;
 768         uint32_t val;
 769         bool rb_swap;
 770
 771         /*
 772          * can't update plane when vop is disabled.
 773          */
 774         if (!crtc)
 775                 return;
 776
 777         if (!vop_plane_state->enable) {
 778                 vop_plane_atomic_disable(plane, old_state);
 779                 return;
 780         }
 781
 782         actual_w = drm_rect_width(src) >> 16;
 783         actual_h = drm_rect_height(src) >> 16;
 784         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 785
 786         dsp_info = (drm_rect_height(dest) - 1) << 16;
 787         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 788
 789         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 790         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 791         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 792
 793         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 794         if (state->rotation & BIT(DRM_REFLECT_Y))
 795                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 796         else
 797                 offset += (src->y1 >> 16) * fb->pitches[0];
 798
 799         dma_addr = rockchip_fb_get_dma_addr(fb, 0, vop->dev);
 800         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 801
 802         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 803         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 804
 805         spin_lock(&vop->reg_lock);
 806
 807         VOP_WIN_SET(vop, win, xmirror, xmirror);
 808         VOP_WIN_SET(vop, win, ymirror, ymirror);
 809         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 810         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 811         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 812         if (is_yuv_support(fb->pixel_format)) {
 813                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 814                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 815                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 816
 817                 offset = (src->x1 >> 16) * bpp / hsub;
 818                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 819
 820                 dma_addr = rockchip_fb_get_dma_addr(fb, 1, vop->dev);
 821                 dma_addr += offset + fb->offsets[1];
 822                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 823                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 824         }
 825
 826         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 827                             drm_rect_width(dest), drm_rect_height(dest),
 828                             fb->pixel_format);
 829
 830         VOP_WIN_SET(vop, win, act_info, act_info);
 831         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 832         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 833
 834         rb_swap = has_rb_swapped(fb->pixel_format);
 835         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 836
 837         if (is_alpha_support(fb->pixel_format) &&
 838             (s->dsp_layer_sel & 0x3) != win->win_id) {
 839                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 840                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 841                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 842                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 843                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 844                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 845                         SRC_FACTOR_M0(ALPHA_ONE);
 846                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 847                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 848                 VOP_WIN_SET(vop, win, alpha_en, 1);
 849         } else {
 850                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 851                 VOP_WIN_SET(vop, win, alpha_en, 0);
 852         }
 853
 854         VOP_WIN_SET(vop, win, enable, 1);
 855         spin_unlock(&vop->reg_lock);
 856         vop->is_iommu_needed = true;
 857 }
 858
 859 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 860         .prepare_fb = vop_plane_prepare_fb,
 861         .cleanup_fb = vop_plane_cleanup_fb,
 862         .atomic_check = vop_plane_atomic_check,
 863         .atomic_update = vop_plane_atomic_update,
 864         .atomic_disable = vop_plane_atomic_disable,
 865 };
 866
 867 void vop_atomic_plane_reset(struct drm_plane *plane)
 868 {
 869         struct vop_win *win = to_vop_win(plane);
 870         struct vop_plane_state *vop_plane_state =
 871                                         to_vop_plane_state(plane->state);
 872
 873         if (plane->state && plane->state->fb)
 874                 drm_framebuffer_unreference(plane->state->fb);
 875
 876         kfree(vop_plane_state);
 877         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 878         if (!vop_plane_state)
 879                 return;
 880
 881         vop_plane_state->zpos = win->win_id;
 882         plane->state = &vop_plane_state->base;
 883         plane->state->plane = plane;
 884 }
 885
 886 struct drm_plane_state *
 887 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 888 {
 889         struct vop_plane_state *old_vop_plane_state;
 890         struct vop_plane_state *vop_plane_state;
 891
 892         if (WARN_ON(!plane->state))
 893                 return NULL;
 894
 895         old_vop_plane_state = to_vop_plane_state(plane->state);
 896         vop_plane_state = kmemdup(old_vop_plane_state,
 897                                   sizeof(*vop_plane_state), GFP_KERNEL);
 898         if (!vop_plane_state)
 899                 return NULL;
 900
 901         __drm_atomic_helper_plane_duplicate_state(plane,
 902                                                   &vop_plane_state->base);
 903
 904         return &vop_plane_state->base;
 905 }
 906
 907 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 908                                            struct drm_plane_state *state)
 909 {
 910         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 911
 912         __drm_atomic_helper_plane_destroy_state(plane, state);
 913
 914         kfree(vop_state);
 915 }
 916
 917 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 918                                          struct drm_plane_state *state,
 919                                          struct drm_property *property,
 920                                          uint64_t val)
 921 {
 922         struct vop_win *win = to_vop_win(plane);
 923         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 924
 925         if (property == win->vop->plane_zpos_prop) {
 926                 plane_state->zpos = val;
 927                 return 0;
 928         }
 929
 930         if (property == win->rotation_prop) {
 931                 state->rotation = val;
 932                 return 0;
 933         }
 934
 935         DRM_ERROR("failed to set vop plane property\n");
 936         return -EINVAL;
 937 }
 938
 939 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 940                                          const struct drm_plane_state *state,
 941                                          struct drm_property *property,
 942                                          uint64_t *val)
 943 {
 944         struct vop_win *win = to_vop_win(plane);
 945         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 946
 947         if (property == win->vop->plane_zpos_prop) {
 948                 *val = plane_state->zpos;
 949                 return 0;
 950         }
 951
 952         if (property == win->rotation_prop) {
 953                 *val = state->rotation;
 954                 return 0;
 955         }
 956
 957         DRM_ERROR("failed to get vop plane property\n");
 958         return -EINVAL;
 959 }
 960
 961 static const struct drm_plane_funcs vop_plane_funcs = {
 962         .update_plane   = drm_atomic_helper_update_plane,
 963         .disable_plane  = drm_atomic_helper_disable_plane,
 964         .destroy = vop_plane_destroy,
 965         .reset = vop_atomic_plane_reset,
 966         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 967         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 968         .atomic_set_property = vop_atomic_plane_set_property,
 969         .atomic_get_property = vop_atomic_plane_get_property,
 970 };
 971
 972 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 973 {
 974         struct vop *vop = to_vop(crtc);
 975         unsigned long flags;
 976
 977         spin_lock_irqsave(&vop->irq_lock, flags);
 978
 979         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 980
 981         spin_unlock_irqrestore(&vop->irq_lock, flags);
 982
 983         return 0;
 984 }
 985
 986 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 987 {
 988         struct vop *vop = to_vop(crtc);
 989         unsigned long flags;
 990
 991         spin_lock_irqsave(&vop->irq_lock, flags);
 992
 993         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 994
 995         spin_unlock_irqrestore(&vop->irq_lock, flags);
 996 }
 997
 998 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 999 {
1000         struct vop *vop = to_vop(crtc);
1001
1002         reinit_completion(&vop->wait_update_complete);
1003         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1004 }
1005
1006 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1007                                            struct drm_file *file_priv)
1008 {
1009         struct drm_device *drm = crtc->dev;
1010         struct vop *vop = to_vop(crtc);
1011         struct drm_pending_vblank_event *e;
1012         unsigned long flags;
1013
1014         spin_lock_irqsave(&drm->event_lock, flags);
1015         e = vop->event;
1016         if (e && e->base.file_priv == file_priv) {
1017                 vop->event = NULL;
1018
1019                 e->base.destroy(&e->base);
1020                 file_priv->event_space += sizeof(e->event);
1021         }
1022         spin_unlock_irqrestore(&drm->event_lock, flags);
1023 }
1024
1025 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1026         .enable_vblank = vop_crtc_enable_vblank,
1027         .disable_vblank = vop_crtc_disable_vblank,
1028         .wait_for_update = vop_crtc_wait_for_update,
1029         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1030 };
1031
1032 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1033                                 const struct drm_display_mode *mode,
1034                                 struct drm_display_mode *adjusted_mode)
1035 {
1036         struct vop *vop = to_vop(crtc);
1037
1038         adjusted_mode->clock =
1039                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1040
1041         return true;
1042 }
1043
1044 static void vop_crtc_enable(struct drm_crtc *crtc)
1045 {
1046         struct vop *vop = to_vop(crtc);
1047         const struct vop_data *vop_data = vop->data;
1048         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1049         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1050         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1051         u16 hdisplay = adjusted_mode->hdisplay;
1052         u16 htotal = adjusted_mode->htotal;
1053         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1054         u16 hact_end = hact_st + hdisplay;
1055         u16 vdisplay = adjusted_mode->vdisplay;
1056         u16 vtotal = adjusted_mode->vtotal;
1057         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1058         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1059         u16 vact_end = vact_st + vdisplay;
1060         uint32_t val;
1061
1062         vop_enable(crtc);
1063         /*
1064          * If dclk rate is zero, mean that scanout is stop,
1065          * we don't need wait any more.
1066          */
1067         if (clk_get_rate(vop->dclk)) {
1068                 /*
1069                  * Rk3288 vop timing register is immediately, when configure
1070                  * display timing on display time, may cause tearing.
1071                  *
1072                  * Vop standby will take effect at end of current frame,
1073                  * if dsp hold valid irq happen, it means standby complete.
1074                  *
1075                  * mode set:
1076                  *    standby and wait complete --> |----
1077                  *                                  | display time
1078                  *                                  |----
1079                  *                                  |---> dsp hold irq
1080                  *     configure display timing --> |
1081                  *         standby exit             |
1082                  *                                  | new frame start.
1083                  */
1084
1085                 reinit_completion(&vop->dsp_hold_completion);
1086                 vop_dsp_hold_valid_irq_enable(vop);
1087
1088                 spin_lock(&vop->reg_lock);
1089
1090                 VOP_CTRL_SET(vop, standby, 1);
1091
1092                 spin_unlock(&vop->reg_lock);
1093
1094                 wait_for_completion(&vop->dsp_hold_completion);
1095
1096                 vop_dsp_hold_valid_irq_disable(vop);
1097         }
1098
1099         val = 0x8;
1100         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1101         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1102         VOP_CTRL_SET(vop, pin_pol, val);
1103         switch (s->output_type) {
1104         case DRM_MODE_CONNECTOR_LVDS:
1105                 VOP_CTRL_SET(vop, rgb_en, 1);
1106                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1107                 break;
1108         case DRM_MODE_CONNECTOR_eDP:
1109                 VOP_CTRL_SET(vop, edp_en, 1);
1110                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1111                 break;
1112         case DRM_MODE_CONNECTOR_HDMIA:
1113                 VOP_CTRL_SET(vop, hdmi_en, 1);
1114                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1115                 break;
1116         case DRM_MODE_CONNECTOR_DSI:
1117                 VOP_CTRL_SET(vop, mipi_en, 1);
1118                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1119                 break;
1120         default:
1121                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1122         }
1123
1124         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1125             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1126                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1127
1128         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1129
1130         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1131         val = hact_st << 16;
1132         val |= hact_end;
1133         VOP_CTRL_SET(vop, hact_st_end, val);
1134         VOP_CTRL_SET(vop, hpost_st_end, val);
1135
1136         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1137         val = vact_st << 16;
1138         val |= vact_end;
1139         VOP_CTRL_SET(vop, vact_st_end, val);
1140         VOP_CTRL_SET(vop, vpost_st_end, val);
1141
1142         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1143
1144         VOP_CTRL_SET(vop, standby, 0);
1145 }
1146
1147 static int vop_zpos_cmp(const void *a, const void *b)
1148 {
1149         struct vop_zpos *pa = (struct vop_zpos *)a;
1150         struct vop_zpos *pb = (struct vop_zpos *)b;
1151
1152         return pa->zpos - pb->zpos;
1153 }
1154
1155 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1156                                  struct drm_crtc_state *crtc_state)
1157 {
1158         struct drm_atomic_state *state = crtc_state->state;
1159         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1160         struct vop *vop = to_vop(crtc);
1161         const struct vop_data *vop_data = vop->data;
1162         struct drm_plane *plane;
1163         struct drm_plane_state *pstate;
1164         struct vop_plane_state *plane_state;
1165         struct vop_zpos *pzpos;
1166         int dsp_layer_sel = 0;
1167         int i, j, cnt = 0, ret = 0;
1168
1169         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1170         if (!pzpos)
1171                 return -ENOMEM;
1172
1173         for (i = 0; i < vop_data->win_size; i++) {
1174                 const struct vop_win_data *win_data = &vop_data->win[i];
1175                 struct vop_win *win;
1176
1177                 if (!win_data->phy)
1178                         continue;
1179
1180                 for (j = 0; j < vop->num_wins; j++) {
1181                         win = &vop->win[j];
1182
1183                         if (win->win_id == i && !win->area_id)
1184                                 break;
1185                 }
1186                 if (WARN_ON(j >= vop->num_wins)) {
1187                         ret = -EINVAL;
1188                         goto err_free_pzpos;
1189                 }
1190
1191                 plane = &win->base;
1192                 pstate = state->plane_states[drm_plane_index(plane)];
1193                 /*
1194                  * plane might not have changed, in which case take
1195                  * current state:
1196                  */
1197                 if (!pstate)
1198                         pstate = plane->state;
1199                 plane_state = to_vop_plane_state(pstate);
1200                 pzpos[cnt].zpos = plane_state->zpos;
1201                 pzpos[cnt++].win_id = win->win_id;
1202         }
1203
1204         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1205
1206         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1207                 const struct vop_win_data *win_data = &vop_data->win[i];
1208                 int shift = i * 2;
1209
1210                 if (win_data->phy) {
1211                         struct vop_zpos *zpos = &pzpos[cnt++];
1212
1213                         dsp_layer_sel |= zpos->win_id << shift;
1214                 } else {
1215                         dsp_layer_sel |= i << shift;
1216                 }
1217         }
1218
1219         s->dsp_layer_sel = dsp_layer_sel;
1220
1221 err_free_pzpos:
1222         kfree(pzpos);
1223         return ret;
1224 }
1225
1226 static void vop_cfg_update(struct drm_crtc *crtc,
1227                            struct drm_crtc_state *old_crtc_state)
1228 {
1229         struct rockchip_crtc_state *s =
1230                         to_rockchip_crtc_state(crtc->state);
1231         struct vop *vop = to_vop(crtc);
1232
1233         spin_lock(&vop->reg_lock);
1234
1235         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1236         vop_cfg_done(vop);
1237
1238         spin_unlock(&vop->reg_lock);
1239 }
1240
1241 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1242                                   struct drm_crtc_state *old_crtc_state)
1243 {
1244         struct vop *vop = to_vop(crtc);
1245
1246         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1247                 int ret;
1248                 if (!vop_is_allwin_disabled(vop)) {
1249                         vop_cfg_update(crtc, old_crtc_state);
1250                         while(!vop_win_pending_is_complete(vop));
1251                 }
1252                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1253                 if (ret) {
1254                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1255                 }
1256                 vop->is_iommu_enabled = true;
1257         }
1258
1259         vop_cfg_update(crtc, old_crtc_state);
1260 }
1261
1262 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1263                                   struct drm_crtc_state *old_crtc_state)
1264 {
1265         struct vop *vop = to_vop(crtc);
1266
1267         if (crtc->state->event) {
1268                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1269
1270                 vop->event = crtc->state->event;
1271                 crtc->state->event = NULL;
1272         }
1273 }
1274
1275 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1276         .enable = vop_crtc_enable,
1277         .disable = vop_crtc_disable,
1278         .mode_fixup = vop_crtc_mode_fixup,
1279         .atomic_check = vop_crtc_atomic_check,
1280         .atomic_flush = vop_crtc_atomic_flush,
1281         .atomic_begin = vop_crtc_atomic_begin,
1282 };
1283
1284 static void vop_crtc_destroy(struct drm_crtc *crtc)
1285 {
1286         drm_crtc_cleanup(crtc);
1287 }
1288
1289 static void vop_crtc_reset(struct drm_crtc *crtc)
1290 {
1291         if (crtc->state)
1292                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1293         kfree(crtc->state);
1294
1295         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1296         if (crtc->state)
1297                 crtc->state->crtc = crtc;
1298 }
1299
1300 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1301 {
1302         struct rockchip_crtc_state *rockchip_state;
1303
1304         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1305         if (!rockchip_state)
1306                 return NULL;
1307
1308         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1309         return &rockchip_state->base;
1310 }
1311
1312 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1313                                    struct drm_crtc_state *state)
1314 {
1315         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1316
1317         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1318         kfree(s);
1319 }
1320
1321 static const struct drm_crtc_funcs vop_crtc_funcs = {
1322         .set_config = drm_atomic_helper_set_config,
1323         .page_flip = drm_atomic_helper_page_flip,
1324         .destroy = vop_crtc_destroy,
1325         .reset = vop_crtc_reset,
1326         .atomic_duplicate_state = vop_crtc_duplicate_state,
1327         .atomic_destroy_state = vop_crtc_destroy_state,
1328 };
1329
1330 static void vop_handle_vblank(struct vop *vop)
1331 {
1332         struct drm_device *drm = vop->drm_dev;
1333         struct drm_crtc *crtc = &vop->crtc;
1334         unsigned long flags;
1335
1336         if (!vop_win_pending_is_complete(vop))
1337                 return;
1338
1339         if (vop->event) {
1340                 spin_lock_irqsave(&drm->event_lock, flags);
1341
1342                 drm_crtc_send_vblank_event(crtc, vop->event);
1343                 drm_crtc_vblank_put(crtc);
1344                 vop->event = NULL;
1345
1346                 spin_unlock_irqrestore(&drm->event_lock, flags);
1347         }
1348         if (!completion_done(&vop->wait_update_complete))
1349                 complete(&vop->wait_update_complete);
1350 }
1351
1352 static irqreturn_t vop_isr(int irq, void *data)
1353 {
1354         struct vop *vop = data;
1355         struct drm_crtc *crtc = &vop->crtc;
1356         uint32_t active_irqs;
1357         unsigned long flags;
1358         int ret = IRQ_NONE;
1359
1360         /*
1361          * interrupt register has interrupt status, enable and clear bits, we
1362          * must hold irq_lock to avoid a race with enable/disable_vblank().
1363         */
1364         spin_lock_irqsave(&vop->irq_lock, flags);
1365
1366         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1367         /* Clear all active interrupt sources */
1368         if (active_irqs)
1369                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1370
1371         spin_unlock_irqrestore(&vop->irq_lock, flags);
1372
1373         /* This is expected for vop iommu irqs, since the irq is shared */
1374         if (!active_irqs)
1375                 return IRQ_NONE;
1376
1377         if (active_irqs & DSP_HOLD_VALID_INTR) {
1378                 complete(&vop->dsp_hold_completion);
1379                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1380                 ret = IRQ_HANDLED;
1381         }
1382
1383         if (active_irqs & FS_INTR) {
1384                 drm_crtc_handle_vblank(crtc);
1385                 vop_handle_vblank(vop);
1386                 active_irqs &= ~FS_INTR;
1387                 ret = IRQ_HANDLED;
1388         }
1389
1390         /* Unhandled irqs are spurious. */
1391         if (active_irqs)
1392                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1393
1394         return ret;
1395 }
1396
1397 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1398                           unsigned long possible_crtcs)
1399 {
1400         struct drm_plane *share = NULL;
1401         unsigned int rotations = 0;
1402         struct drm_property *prop;
1403         uint64_t feature = 0;
1404         int ret;
1405
1406         if (win->parent)
1407                 share = &win->parent->base;
1408
1409         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1410                                    possible_crtcs, &vop_plane_funcs,
1411                                    win->data_formats, win->nformats, win->type);
1412         if (ret) {
1413                 DRM_ERROR("failed to initialize plane\n");
1414                 return ret;
1415         }
1416         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1417         drm_object_attach_property(&win->base.base,
1418                                    vop->plane_zpos_prop, win->win_id);
1419
1420         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1421                 rotations |= BIT(DRM_REFLECT_X);
1422
1423         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1424                 rotations |= BIT(DRM_REFLECT_Y);
1425
1426         if (rotations) {
1427                 rotations |= BIT(DRM_ROTATE_0);
1428                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1429                                                          rotations);
1430                 if (!prop) {
1431                         DRM_ERROR("failed to create zpos property\n");
1432                         return -EINVAL;
1433                 }
1434                 drm_object_attach_property(&win->base.base, prop,
1435                                            BIT(DRM_ROTATE_0));
1436                 win->rotation_prop = prop;
1437         }
1438         if (win->phy->scl)
1439                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1440         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1441             VOP_WIN_SUPPORT(vop, win, alpha_en))
1442                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1443
1444         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1445                                    feature);
1446
1447         return 0;
1448 }
1449
1450 static int vop_create_crtc(struct vop *vop)
1451 {
1452         struct device *dev = vop->dev;
1453         struct drm_device *drm_dev = vop->drm_dev;
1454         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1455         struct drm_crtc *crtc = &vop->crtc;
1456         struct device_node *port;
1457         int ret;
1458         int i;
1459
1460         /*
1461          * Create drm_plane for primary and cursor planes first, since we need
1462          * to pass them to drm_crtc_init_with_planes, which sets the
1463          * "possible_crtcs" to the newly initialized crtc.
1464          */
1465         for (i = 0; i < vop->num_wins; i++) {
1466                 struct vop_win *win = &vop->win[i];
1467
1468                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1469                     win->type != DRM_PLANE_TYPE_CURSOR)
1470                         continue;
1471
1472                 ret = vop_plane_init(vop, win, 0);
1473                 if (ret)
1474                         goto err_cleanup_planes;
1475
1476                 plane = &win->base;
1477                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1478                         primary = plane;
1479                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1480                         cursor = plane;
1481
1482         }
1483
1484         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1485                                         &vop_crtc_funcs, NULL);
1486         if (ret)
1487                 goto err_cleanup_planes;
1488
1489         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1490
1491         /*
1492          * Create drm_planes for overlay windows with possible_crtcs restricted
1493          * to the newly created crtc.
1494          */
1495         for (i = 0; i < vop->num_wins; i++) {
1496                 struct vop_win *win = &vop->win[i];
1497                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1498
1499                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1500                         continue;
1501
1502                 ret = vop_plane_init(vop, win, possible_crtcs);
1503                 if (ret)
1504                         goto err_cleanup_crtc;
1505         }
1506
1507         port = of_get_child_by_name(dev->of_node, "port");
1508         if (!port) {
1509                 DRM_ERROR("no port node found in %s\n",
1510                           dev->of_node->full_name);
1511                 ret = -ENOENT;
1512                 goto err_cleanup_crtc;
1513         }
1514
1515         init_completion(&vop->dsp_hold_completion);
1516         init_completion(&vop->wait_update_complete);
1517         crtc->port = port;
1518         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1519
1520         return 0;
1521
1522 err_cleanup_crtc:
1523         drm_crtc_cleanup(crtc);
1524 err_cleanup_planes:
1525         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1526                                  head)
1527                 drm_plane_cleanup(plane);
1528         return ret;
1529 }
1530
1531 static void vop_destroy_crtc(struct vop *vop)
1532 {
1533         struct drm_crtc *crtc = &vop->crtc;
1534         struct drm_device *drm_dev = vop->drm_dev;
1535         struct drm_plane *plane, *tmp;
1536
1537         rockchip_unregister_crtc_funcs(crtc);
1538         of_node_put(crtc->port);
1539
1540         /*
1541          * We need to cleanup the planes now.  Why?
1542          *
1543          * The planes are "&vop->win[i].base".  That means the memory is
1544          * all part of the big "struct vop" chunk of memory.  That memory
1545          * was devm allocated and associated with this component.  We need to
1546          * free it ourselves before vop_unbind() finishes.
1547          */
1548         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1549                                  head)
1550                 vop_plane_destroy(plane);
1551
1552         /*
1553          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1554          * references the CRTC.
1555          */
1556         drm_crtc_cleanup(crtc);
1557 }
1558
1559 /*
1560  * Initialize the vop->win array elements.
1561  */
1562 static int vop_win_init(struct vop *vop)
1563 {
1564         const struct vop_data *vop_data = vop->data;
1565         unsigned int i, j;
1566         unsigned int num_wins = 0;
1567         struct drm_property *prop;
1568         static const struct drm_prop_enum_list props[] = {
1569                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1570                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1571         };
1572
1573         for (i = 0; i < vop_data->win_size; i++) {
1574                 struct vop_win *vop_win = &vop->win[num_wins];
1575                 const struct vop_win_data *win_data = &vop_data->win[i];
1576
1577                 if (!win_data->phy)
1578                         continue;
1579
1580                 vop_win->phy = win_data->phy;
1581                 vop_win->offset = win_data->base;
1582                 vop_win->type = win_data->type;
1583                 vop_win->data_formats = win_data->phy->data_formats;
1584                 vop_win->nformats = win_data->phy->nformats;
1585                 vop_win->vop = vop;
1586                 vop_win->win_id = i;
1587                 vop_win->area_id = 0;
1588                 num_wins++;
1589
1590                 for (j = 0; j < win_data->area_size; j++) {
1591                         struct vop_win *vop_area = &vop->win[num_wins];
1592                         const struct vop_win_phy *area = win_data->area[j];
1593
1594                         vop_area->parent = vop_win;
1595                         vop_area->offset = vop_win->offset;
1596                         vop_area->phy = area;
1597                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1598                         vop_area->data_formats = vop_win->data_formats;
1599                         vop_area->nformats = vop_win->nformats;
1600                         vop_area->vop = vop;
1601                         vop_area->win_id = i;
1602                         vop_area->area_id = j;
1603                         num_wins++;
1604                 }
1605         }
1606
1607         vop->num_wins = num_wins;
1608
1609         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1610                                          "ZPOS", 0, vop->data->win_size);
1611         if (!prop) {
1612                 DRM_ERROR("failed to create zpos property\n");
1613                 return -EINVAL;
1614         }
1615         vop->plane_zpos_prop = prop;
1616
1617         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1618                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1619                                 props, ARRAY_SIZE(props),
1620                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1621                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1622         if (!vop->plane_feature_prop) {
1623                 DRM_ERROR("failed to create feature property\n");
1624                 return -EINVAL;
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int vop_bind(struct device *dev, struct device *master, void *data)
1631 {
1632         struct platform_device *pdev = to_platform_device(dev);
1633         const struct vop_data *vop_data;
1634         struct drm_device *drm_dev = data;
1635         struct vop *vop;
1636         struct resource *res;
1637         size_t alloc_size;
1638         int ret, irq, i;
1639         int num_wins = 0;
1640
1641         vop_data = of_device_get_match_data(dev);
1642         if (!vop_data)
1643                 return -ENODEV;
1644
1645         for (i = 0; i < vop_data->win_size; i++) {
1646                 const struct vop_win_data *win_data = &vop_data->win[i];
1647
1648                 num_wins += win_data->area_size + 1;
1649         }
1650
1651         /* Allocate vop struct and its vop_win array */
1652         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1653         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1654         if (!vop)
1655                 return -ENOMEM;
1656
1657         vop->dev = dev;
1658         vop->data = vop_data;
1659         vop->drm_dev = drm_dev;
1660         vop->num_wins = num_wins;
1661         dev_set_drvdata(dev, vop);
1662
1663         ret = vop_win_init(vop);
1664         if (ret)
1665                 return ret;
1666
1667         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1668         vop->len = resource_size(res);
1669         vop->regs = devm_ioremap_resource(dev, res);
1670         if (IS_ERR(vop->regs))
1671                 return PTR_ERR(vop->regs);
1672
1673         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1674         if (!vop->regsbak)
1675                 return -ENOMEM;
1676
1677         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1678         if (IS_ERR(vop->hclk)) {
1679                 dev_err(vop->dev, "failed to get hclk source\n");
1680                 return PTR_ERR(vop->hclk);
1681         }
1682         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1683         if (IS_ERR(vop->aclk)) {
1684                 dev_err(vop->dev, "failed to get aclk source\n");
1685                 return PTR_ERR(vop->aclk);
1686         }
1687         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1688         if (IS_ERR(vop->dclk)) {
1689                 dev_err(vop->dev, "failed to get dclk source\n");
1690                 return PTR_ERR(vop->dclk);
1691         }
1692
1693         irq = platform_get_irq(pdev, 0);
1694         if (irq < 0) {
1695                 dev_err(dev, "cannot find irq for vop\n");
1696                 return irq;
1697         }
1698         vop->irq = (unsigned int)irq;
1699
1700         spin_lock_init(&vop->reg_lock);
1701         spin_lock_init(&vop->irq_lock);
1702
1703         mutex_init(&vop->vsync_mutex);
1704
1705         ret = devm_request_irq(dev, vop->irq, vop_isr,
1706                                IRQF_SHARED, dev_name(dev), vop);
1707         if (ret)
1708                 return ret;
1709
1710         /* IRQ is initially disabled; it gets enabled in power_on */
1711         disable_irq(vop->irq);
1712
1713         ret = vop_create_crtc(vop);
1714         if (ret)
1715                 return ret;
1716
1717         pm_runtime_enable(&pdev->dev);
1718         return 0;
1719 }
1720
1721 static void vop_unbind(struct device *dev, struct device *master, void *data)
1722 {
1723         struct vop *vop = dev_get_drvdata(dev);
1724
1725         pm_runtime_disable(dev);
1726         vop_destroy_crtc(vop);
1727 }
1728
1729 const struct component_ops vop_component_ops = {
1730         .bind = vop_bind,
1731         .unbind = vop_unbind,
1732 };
1733 EXPORT_SYMBOL_GPL(vop_component_ops);