2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33 #include <linux/sort.h>
34 #include <uapi/drm/rockchip_drm.h>
36 #include "rockchip_drm_drv.h"
37 #include "rockchip_drm_gem.h"
38 #include "rockchip_drm_fb.h"
39 #include "rockchip_drm_vop.h"
41 #define VOP_REG_SUPPORT(vop, reg) \
42 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
43 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
44 reg.end_minor >= VOP_MINOR(vop->data->version) && \
47 #define VOP_WIN_SUPPORT(vop, win, name) \
48 VOP_REG_SUPPORT(vop, win->phy->name)
50 #define VOP_CTRL_SUPPORT(vop, win, name) \
51 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
53 #define VOP_INTR_SUPPORT(vop, win, name) \
54 VOP_REG_SUPPORT(vop, vop->data->intr->name)
56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
57 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
61 if (VOP_REG_SUPPORT(vop, reg)) \
62 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
63 v, reg.write_mask, relaxed); \
65 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
68 #define REG_SET(x, name, off, reg, v, relaxed) \
69 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
71 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
73 #define VOP_WIN_SET(x, win, name, v) \
74 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
75 #define VOP_SCL_SET(x, win, name, v) \
76 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
77 #define VOP_SCL_SET_EXT(x, win, name, v) \
78 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
80 #define VOP_CTRL_SET(x, name, v) \
81 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
83 #define VOP_INTR_GET(vop, name) \
84 vop_read_reg(vop, 0, &vop->data->ctrl->name)
86 #define VOP_INTR_SET(vop, name, mask, v) \
87 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
90 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
92 int i, reg = 0, mask = 0; \
93 for (i = 0; i < vop->data->intr->nintrs; i++) { \
94 if (vop->data->intr->intrs[i] & type) { \
99 VOP_INTR_SET(vop, name, mask, reg); \
101 #define VOP_INTR_GET_TYPE(vop, name, type) \
102 vop_get_intr_type(vop, &vop->data->intr->name, type)
104 #define VOP_CTRL_GET(x, name) \
105 vop_read_reg(x, 0, &vop->data->ctrl->name)
107 #define VOP_WIN_GET(x, win, name) \
108 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
110 #define VOP_WIN_NAME(win, name) \
111 (vop_get_win_phy(win, &win->phy->name)->name)
113 #define VOP_WIN_GET_YRGBADDR(vop, win) \
114 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
116 #define to_vop(x) container_of(x, struct vop, crtc)
117 #define to_vop_win(x) container_of(x, struct vop_win, base)
118 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
125 struct vop_plane_state {
126 struct drm_plane_state base;
130 struct drm_rect dest;
137 struct vop_win *parent;
138 struct drm_plane base;
143 enum drm_plane_type type;
144 const struct vop_win_phy *phy;
145 const uint32_t *data_formats;
149 struct drm_property *rotation_prop;
150 struct vop_plane_state state;
154 struct drm_crtc crtc;
156 struct drm_device *drm_dev;
157 struct drm_property *plane_zpos_prop;
158 struct drm_property *plane_feature_prop;
159 bool is_iommu_enabled;
160 bool is_iommu_needed;
163 /* mutex vsync_ work */
164 struct mutex vsync_mutex;
165 bool vsync_work_pending;
166 struct completion dsp_hold_completion;
167 struct completion wait_update_complete;
168 struct drm_pending_vblank_event *event;
170 const struct vop_data *data;
176 /* physical map length of vop register */
179 /* one time only one process allowed to config the register */
181 /* lock vop irq reg */
190 /* vop share memory frequency */
194 struct reset_control *dclk_rst;
196 struct vop_win win[];
199 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
201 writel(v, vop->regs + offset);
202 vop->regsbak[offset >> 2] = v;
205 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
207 return readl(vop->regs + offset);
210 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
211 const struct vop_reg *reg)
213 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
216 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
217 uint32_t mask, uint32_t shift, uint32_t v,
218 bool write_mask, bool relaxed)
224 v = ((v & mask) << shift) | (mask << (shift + 16));
226 uint32_t cached_val = vop->regsbak[offset >> 2];
228 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
229 vop->regsbak[offset >> 2] = v;
233 writel_relaxed(v, vop->regs + offset);
235 writel(v, vop->regs + offset);
238 static inline const struct vop_win_phy *
239 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
241 if (!reg->mask && win->parent)
242 return win->parent->phy;
247 static inline uint32_t vop_get_intr_type(struct vop *vop,
248 const struct vop_reg *reg, int type)
251 uint32_t regs = vop_read_reg(vop, 0, reg);
253 for (i = 0; i < vop->data->intr->nintrs; i++) {
254 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
255 ret |= vop->data->intr->intrs[i];
261 static inline void vop_cfg_done(struct vop *vop)
263 VOP_CTRL_SET(vop, cfg_done, 1);
266 static bool vop_is_allwin_disabled(struct vop *vop)
270 for (i = 0; i < vop->num_wins; i++) {
271 struct vop_win *win = &vop->win[i];
273 if (VOP_WIN_GET(vop, win, enable) != 0)
280 static bool vop_is_cfg_done_complete(struct vop *vop)
282 return VOP_CTRL_GET(vop, cfg_done) ? false : true;
285 static bool has_rb_swapped(uint32_t format)
288 case DRM_FORMAT_XBGR8888:
289 case DRM_FORMAT_ABGR8888:
290 case DRM_FORMAT_BGR888:
291 case DRM_FORMAT_BGR565:
298 static enum vop_data_format vop_convert_format(uint32_t format)
301 case DRM_FORMAT_XRGB8888:
302 case DRM_FORMAT_ARGB8888:
303 case DRM_FORMAT_XBGR8888:
304 case DRM_FORMAT_ABGR8888:
305 return VOP_FMT_ARGB8888;
306 case DRM_FORMAT_RGB888:
307 case DRM_FORMAT_BGR888:
308 return VOP_FMT_RGB888;
309 case DRM_FORMAT_RGB565:
310 case DRM_FORMAT_BGR565:
311 return VOP_FMT_RGB565;
312 case DRM_FORMAT_NV12:
313 return VOP_FMT_YUV420SP;
314 case DRM_FORMAT_NV16:
315 return VOP_FMT_YUV422SP;
316 case DRM_FORMAT_NV24:
317 return VOP_FMT_YUV444SP;
319 DRM_ERROR("unsupport format[%08x]\n", format);
324 static bool is_yuv_support(uint32_t format)
327 case DRM_FORMAT_NV12:
328 case DRM_FORMAT_NV16:
329 case DRM_FORMAT_NV24:
336 static bool is_alpha_support(uint32_t format)
339 case DRM_FORMAT_ARGB8888:
340 case DRM_FORMAT_ABGR8888:
347 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
348 uint32_t dst, bool is_horizontal,
349 int vsu_mode, int *vskiplines)
351 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
354 if (mode == SCALE_UP)
355 val = GET_SCL_FT_BIC(src, dst);
356 else if (mode == SCALE_DOWN)
357 val = GET_SCL_FT_BILI_DN(src, dst);
359 if (mode == SCALE_UP) {
360 if (vsu_mode == SCALE_UP_BIL)
361 val = GET_SCL_FT_BILI_UP(src, dst);
363 val = GET_SCL_FT_BIC(src, dst);
364 } else if (mode == SCALE_DOWN) {
366 *vskiplines = scl_get_vskiplines(src, dst);
367 val = scl_get_bili_dn_vskip(src, dst,
370 val = GET_SCL_FT_BILI_DN(src, dst);
378 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
379 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
380 uint32_t dst_h, uint32_t pixel_format)
382 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
383 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
384 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
385 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
386 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
387 bool is_yuv = is_yuv_support(pixel_format);
388 uint16_t cbcr_src_w = src_w / hsub;
389 uint16_t cbcr_src_h = src_h / vsub;
399 DRM_ERROR("Maximum destination width (3840) exceeded\n");
403 if (!win->phy->scl->ext) {
404 VOP_SCL_SET(vop, win, scale_yrgb_x,
405 scl_cal_scale2(src_w, dst_w));
406 VOP_SCL_SET(vop, win, scale_yrgb_y,
407 scl_cal_scale2(src_h, dst_h));
409 VOP_SCL_SET(vop, win, scale_cbcr_x,
410 scl_cal_scale2(cbcr_src_w, dst_w));
411 VOP_SCL_SET(vop, win, scale_cbcr_y,
412 scl_cal_scale2(cbcr_src_h, dst_h));
417 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
418 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
421 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
422 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
423 if (cbcr_hor_scl_mode == SCALE_DOWN)
424 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
426 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
428 if (yrgb_hor_scl_mode == SCALE_DOWN)
429 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
431 lb_mode = scl_vop_cal_lb_mode(src_w, false);
434 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
435 if (lb_mode == LB_RGB_3840X2) {
436 if (yrgb_ver_scl_mode != SCALE_NONE) {
437 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
440 if (cbcr_ver_scl_mode != SCALE_NONE) {
441 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
444 vsu_mode = SCALE_UP_BIL;
445 } else if (lb_mode == LB_RGB_2560X4) {
446 vsu_mode = SCALE_UP_BIL;
448 vsu_mode = SCALE_UP_BIC;
451 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
453 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
454 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
455 false, vsu_mode, &vskiplines);
456 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
458 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
459 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
461 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
462 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
463 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
464 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
465 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
467 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
468 dst_w, true, 0, NULL);
469 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
470 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
471 dst_h, false, vsu_mode, &vskiplines);
472 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
474 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
475 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
476 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
477 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
478 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
479 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
480 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
484 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
488 spin_lock_irqsave(&vop->irq_lock, flags);
490 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
492 spin_unlock_irqrestore(&vop->irq_lock, flags);
495 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
499 spin_lock_irqsave(&vop->irq_lock, flags);
501 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
503 spin_unlock_irqrestore(&vop->irq_lock, flags);
506 static void vop_enable(struct drm_crtc *crtc)
508 struct vop *vop = to_vop(crtc);
511 ret = clk_prepare_enable(vop->hclk);
513 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
517 ret = clk_prepare_enable(vop->dclk);
519 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
520 goto err_disable_hclk;
523 ret = clk_prepare_enable(vop->aclk);
525 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
526 goto err_disable_dclk;
529 ret = pm_runtime_get_sync(vop->dev);
531 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
535 memcpy(vop->regsbak, vop->regs, vop->len);
537 VOP_CTRL_SET(vop, global_regdone_en, 1);
538 VOP_CTRL_SET(vop, dsp_blank, 0);
540 for (i = 0; i < vop->num_wins; i++) {
541 struct vop_win *win = &vop->win[i];
543 VOP_WIN_SET(vop, win, gate, 1);
545 vop->is_enabled = true;
547 spin_lock(&vop->reg_lock);
549 VOP_CTRL_SET(vop, standby, 0);
551 spin_unlock(&vop->reg_lock);
553 enable_irq(vop->irq);
555 drm_crtc_vblank_on(crtc);
560 clk_disable_unprepare(vop->dclk);
562 clk_disable_unprepare(vop->hclk);
565 static void vop_crtc_disable(struct drm_crtc *crtc)
567 struct vop *vop = to_vop(crtc);
571 * We need to make sure that all windows are disabled before we
572 * disable that crtc. Otherwise we might try to scan from a destroyed
575 for (i = 0; i < vop->num_wins; i++) {
576 struct vop_win *win = &vop->win[i];
578 spin_lock(&vop->reg_lock);
579 VOP_WIN_SET(vop, win, enable, 0);
580 spin_unlock(&vop->reg_lock);
584 drm_crtc_vblank_off(crtc);
587 * Vop standby will take effect at end of current frame,
588 * if dsp hold valid irq happen, it means standby complete.
590 * we must wait standby complete when we want to disable aclk,
591 * if not, memory bus maybe dead.
593 reinit_completion(&vop->dsp_hold_completion);
594 vop_dsp_hold_valid_irq_enable(vop);
596 spin_lock(&vop->reg_lock);
598 VOP_CTRL_SET(vop, standby, 1);
600 spin_unlock(&vop->reg_lock);
602 wait_for_completion(&vop->dsp_hold_completion);
604 vop_dsp_hold_valid_irq_disable(vop);
606 disable_irq(vop->irq);
608 vop->is_enabled = false;
609 if (vop->is_iommu_enabled) {
611 * vop standby complete, so iommu detach is safe.
613 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
614 vop->is_iommu_enabled = false;
617 pm_runtime_put(vop->dev);
618 clk_disable_unprepare(vop->dclk);
619 clk_disable_unprepare(vop->aclk);
620 clk_disable_unprepare(vop->hclk);
623 static void vop_plane_destroy(struct drm_plane *plane)
625 drm_plane_cleanup(plane);
628 static int vop_plane_prepare_fb(struct drm_plane *plane,
629 const struct drm_plane_state *new_state)
631 if (plane->state->fb)
632 drm_framebuffer_reference(plane->state->fb);
637 static void vop_plane_cleanup_fb(struct drm_plane *plane,
638 const struct drm_plane_state *old_state)
641 drm_framebuffer_unreference(old_state->fb);
644 static int vop_plane_atomic_check(struct drm_plane *plane,
645 struct drm_plane_state *state)
647 struct drm_crtc *crtc = state->crtc;
648 struct drm_framebuffer *fb = state->fb;
649 struct vop_win *win = to_vop_win(plane);
650 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
651 struct drm_crtc_state *crtc_state;
654 struct drm_rect *dest = &vop_plane_state->dest;
655 struct drm_rect *src = &vop_plane_state->src;
656 struct drm_rect clip;
657 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
658 DRM_PLANE_HELPER_NO_SCALING;
659 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
660 DRM_PLANE_HELPER_NO_SCALING;
661 unsigned long offset;
664 crtc = crtc ? crtc : plane->state->crtc;
666 * Both crtc or plane->state->crtc can be null.
671 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
672 if (IS_ERR(crtc_state))
673 return PTR_ERR(crtc_state);
675 src->x1 = state->src_x;
676 src->y1 = state->src_y;
677 src->x2 = state->src_x + state->src_w;
678 src->y2 = state->src_y + state->src_h;
679 dest->x1 = state->crtc_x;
680 dest->y1 = state->crtc_y;
681 dest->x2 = state->crtc_x + state->crtc_w;
682 dest->y2 = state->crtc_y + state->crtc_h;
686 clip.x2 = crtc_state->mode.hdisplay;
687 clip.y2 = crtc_state->mode.vdisplay;
689 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
693 true, true, &visible);
700 vop_plane_state->format = vop_convert_format(fb->pixel_format);
701 if (vop_plane_state->format < 0)
702 return vop_plane_state->format;
705 * Src.x1 can be odd when do clip, but yuv plane start point
706 * need align with 2 pixel.
708 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
711 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
712 if (state->rotation & BIT(DRM_REFLECT_Y))
713 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
715 offset += (src->y1 >> 16) * fb->pitches[0];
717 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
718 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
719 if (is_yuv_support(fb->pixel_format)) {
720 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
721 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
722 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
724 offset = (src->x1 >> 16) * bpp / hsub;
725 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
727 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
728 dma_addr += offset + fb->offsets[1];
729 vop_plane_state->uv_mst = dma_addr;
732 vop_plane_state->enable = true;
737 vop_plane_state->enable = false;
741 static void vop_plane_atomic_disable(struct drm_plane *plane,
742 struct drm_plane_state *old_state)
744 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
745 struct vop_win *win = to_vop_win(plane);
746 struct vop *vop = to_vop(old_state->crtc);
748 if (!old_state->crtc)
751 spin_lock(&vop->reg_lock);
753 VOP_WIN_SET(vop, win, enable, 0);
755 spin_unlock(&vop->reg_lock);
757 vop_plane_state->enable = false;
760 static void vop_plane_atomic_update(struct drm_plane *plane,
761 struct drm_plane_state *old_state)
763 struct drm_plane_state *state = plane->state;
764 struct drm_crtc *crtc = state->crtc;
765 struct vop_win *win = to_vop_win(plane);
766 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
767 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
768 struct vop *vop = to_vop(state->crtc);
769 struct drm_framebuffer *fb = state->fb;
770 unsigned int actual_w, actual_h;
771 unsigned int dsp_stx, dsp_sty;
772 uint32_t act_info, dsp_info, dsp_st;
773 struct drm_rect *src = &vop_plane_state->src;
774 struct drm_rect *dest = &vop_plane_state->dest;
775 int ymirror, xmirror;
780 * can't update plane when vop is disabled.
785 if (!vop_plane_state->enable) {
786 vop_plane_atomic_disable(plane, old_state);
790 actual_w = drm_rect_width(src) >> 16;
791 actual_h = drm_rect_height(src) >> 16;
792 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
794 dsp_info = (drm_rect_height(dest) - 1) << 16;
795 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
797 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
798 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
799 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
801 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
802 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
804 spin_lock(&vop->reg_lock);
806 VOP_WIN_SET(vop, win, xmirror, xmirror);
807 VOP_WIN_SET(vop, win, ymirror, ymirror);
808 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
809 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
810 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
811 if (is_yuv_support(fb->pixel_format)) {
812 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
813 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
816 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
817 drm_rect_width(dest), drm_rect_height(dest),
820 VOP_WIN_SET(vop, win, act_info, act_info);
821 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
822 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
824 rb_swap = has_rb_swapped(fb->pixel_format);
825 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
827 if (is_alpha_support(fb->pixel_format) &&
828 (s->dsp_layer_sel & 0x3) != win->win_id) {
829 VOP_WIN_SET(vop, win, dst_alpha_ctl,
830 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
831 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
832 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
833 SRC_BLEND_M0(ALPHA_PER_PIX) |
834 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
835 SRC_FACTOR_M0(ALPHA_ONE);
836 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
837 VOP_WIN_SET(vop, win, alpha_mode, 1);
838 VOP_WIN_SET(vop, win, alpha_en, 1);
840 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
841 VOP_WIN_SET(vop, win, alpha_en, 0);
844 VOP_WIN_SET(vop, win, enable, 1);
845 spin_unlock(&vop->reg_lock);
846 vop->is_iommu_needed = true;
849 static const struct drm_plane_helper_funcs plane_helper_funcs = {
850 .prepare_fb = vop_plane_prepare_fb,
851 .cleanup_fb = vop_plane_cleanup_fb,
852 .atomic_check = vop_plane_atomic_check,
853 .atomic_update = vop_plane_atomic_update,
854 .atomic_disable = vop_plane_atomic_disable,
857 void vop_atomic_plane_reset(struct drm_plane *plane)
859 struct vop_win *win = to_vop_win(plane);
860 struct vop_plane_state *vop_plane_state =
861 to_vop_plane_state(plane->state);
863 if (plane->state && plane->state->fb)
864 drm_framebuffer_unreference(plane->state->fb);
866 kfree(vop_plane_state);
867 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
868 if (!vop_plane_state)
871 vop_plane_state->zpos = win->win_id;
872 plane->state = &vop_plane_state->base;
873 plane->state->plane = plane;
876 struct drm_plane_state *
877 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
879 struct vop_plane_state *old_vop_plane_state;
880 struct vop_plane_state *vop_plane_state;
882 if (WARN_ON(!plane->state))
885 old_vop_plane_state = to_vop_plane_state(plane->state);
886 vop_plane_state = kmemdup(old_vop_plane_state,
887 sizeof(*vop_plane_state), GFP_KERNEL);
888 if (!vop_plane_state)
891 __drm_atomic_helper_plane_duplicate_state(plane,
892 &vop_plane_state->base);
894 return &vop_plane_state->base;
897 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
898 struct drm_plane_state *state)
900 struct vop_plane_state *vop_state = to_vop_plane_state(state);
902 __drm_atomic_helper_plane_destroy_state(plane, state);
907 static int vop_atomic_plane_set_property(struct drm_plane *plane,
908 struct drm_plane_state *state,
909 struct drm_property *property,
912 struct vop_win *win = to_vop_win(plane);
913 struct vop_plane_state *plane_state = to_vop_plane_state(state);
915 if (property == win->vop->plane_zpos_prop) {
916 plane_state->zpos = val;
920 if (property == win->rotation_prop) {
921 state->rotation = val;
925 DRM_ERROR("failed to set vop plane property\n");
929 static int vop_atomic_plane_get_property(struct drm_plane *plane,
930 const struct drm_plane_state *state,
931 struct drm_property *property,
934 struct vop_win *win = to_vop_win(plane);
935 struct vop_plane_state *plane_state = to_vop_plane_state(state);
937 if (property == win->vop->plane_zpos_prop) {
938 *val = plane_state->zpos;
942 if (property == win->rotation_prop) {
943 *val = state->rotation;
947 DRM_ERROR("failed to get vop plane property\n");
951 static const struct drm_plane_funcs vop_plane_funcs = {
952 .update_plane = drm_atomic_helper_update_plane,
953 .disable_plane = drm_atomic_helper_disable_plane,
954 .destroy = vop_plane_destroy,
955 .reset = vop_atomic_plane_reset,
956 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
957 .atomic_destroy_state = vop_atomic_plane_destroy_state,
958 .atomic_set_property = vop_atomic_plane_set_property,
959 .atomic_get_property = vop_atomic_plane_get_property,
962 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
964 struct vop *vop = to_vop(crtc);
967 if (!vop->is_enabled)
970 spin_lock_irqsave(&vop->irq_lock, flags);
972 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
974 spin_unlock_irqrestore(&vop->irq_lock, flags);
979 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
981 struct vop *vop = to_vop(crtc);
984 if (!vop->is_enabled)
987 spin_lock_irqsave(&vop->irq_lock, flags);
989 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
991 spin_unlock_irqrestore(&vop->irq_lock, flags);
994 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
996 struct vop *vop = to_vop(crtc);
998 reinit_completion(&vop->wait_update_complete);
999 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1002 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1003 struct drm_file *file_priv)
1005 struct drm_device *drm = crtc->dev;
1006 struct vop *vop = to_vop(crtc);
1007 struct drm_pending_vblank_event *e;
1008 unsigned long flags;
1010 spin_lock_irqsave(&drm->event_lock, flags);
1012 if (e && e->base.file_priv == file_priv) {
1015 e->base.destroy(&e->base);
1016 file_priv->event_space += sizeof(e->event);
1018 spin_unlock_irqrestore(&drm->event_lock, flags);
1021 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1022 .enable_vblank = vop_crtc_enable_vblank,
1023 .disable_vblank = vop_crtc_disable_vblank,
1024 .wait_for_update = vop_crtc_wait_for_update,
1025 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1028 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1029 const struct drm_display_mode *mode,
1030 struct drm_display_mode *adjusted_mode)
1032 struct vop *vop = to_vop(crtc);
1034 adjusted_mode->clock =
1035 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1040 static void vop_crtc_enable(struct drm_crtc *crtc)
1042 struct vop *vop = to_vop(crtc);
1043 const struct vop_data *vop_data = vop->data;
1044 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1045 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1046 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1047 u16 hdisplay = adjusted_mode->hdisplay;
1048 u16 htotal = adjusted_mode->htotal;
1049 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1050 u16 hact_end = hact_st + hdisplay;
1051 u16 vdisplay = adjusted_mode->vdisplay;
1052 u16 vtotal = adjusted_mode->vtotal;
1053 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1054 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1055 u16 vact_end = vact_st + vdisplay;
1060 * If dclk rate is zero, mean that scanout is stop,
1061 * we don't need wait any more.
1063 if (clk_get_rate(vop->dclk)) {
1065 * Rk3288 vop timing register is immediately, when configure
1066 * display timing on display time, may cause tearing.
1068 * Vop standby will take effect at end of current frame,
1069 * if dsp hold valid irq happen, it means standby complete.
1072 * standby and wait complete --> |----
1075 * |---> dsp hold irq
1076 * configure display timing --> |
1078 * | new frame start.
1081 reinit_completion(&vop->dsp_hold_completion);
1082 vop_dsp_hold_valid_irq_enable(vop);
1084 spin_lock(&vop->reg_lock);
1086 VOP_CTRL_SET(vop, standby, 1);
1088 spin_unlock(&vop->reg_lock);
1090 wait_for_completion(&vop->dsp_hold_completion);
1092 vop_dsp_hold_valid_irq_disable(vop);
1096 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1097 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1098 VOP_CTRL_SET(vop, pin_pol, val);
1099 switch (s->output_type) {
1100 case DRM_MODE_CONNECTOR_LVDS:
1101 VOP_CTRL_SET(vop, rgb_en, 1);
1102 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1104 case DRM_MODE_CONNECTOR_eDP:
1105 VOP_CTRL_SET(vop, edp_en, 1);
1106 VOP_CTRL_SET(vop, edp_pin_pol, val);
1108 case DRM_MODE_CONNECTOR_HDMIA:
1109 VOP_CTRL_SET(vop, hdmi_en, 1);
1110 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1112 case DRM_MODE_CONNECTOR_DSI:
1113 VOP_CTRL_SET(vop, mipi_en, 1);
1114 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1117 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1120 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1121 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1122 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1124 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1126 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1127 val = hact_st << 16;
1129 VOP_CTRL_SET(vop, hact_st_end, val);
1130 VOP_CTRL_SET(vop, hpost_st_end, val);
1132 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1133 val = vact_st << 16;
1135 VOP_CTRL_SET(vop, vact_st_end, val);
1136 VOP_CTRL_SET(vop, vpost_st_end, val);
1138 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1140 VOP_CTRL_SET(vop, standby, 0);
1143 static int vop_zpos_cmp(const void *a, const void *b)
1145 struct vop_zpos *pa = (struct vop_zpos *)a;
1146 struct vop_zpos *pb = (struct vop_zpos *)b;
1148 return pa->zpos - pb->zpos;
1151 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1152 struct drm_crtc_state *crtc_state)
1154 struct drm_atomic_state *state = crtc_state->state;
1155 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1156 struct vop *vop = to_vop(crtc);
1157 const struct vop_data *vop_data = vop->data;
1158 struct drm_plane *plane;
1159 struct drm_plane_state *pstate;
1160 struct vop_plane_state *plane_state;
1161 struct vop_zpos *pzpos;
1162 int dsp_layer_sel = 0;
1163 int i, j, cnt = 0, ret = 0;
1165 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1169 for (i = 0; i < vop_data->win_size; i++) {
1170 const struct vop_win_data *win_data = &vop_data->win[i];
1171 struct vop_win *win;
1176 for (j = 0; j < vop->num_wins; j++) {
1179 if (win->win_id == i && !win->area_id)
1182 if (WARN_ON(j >= vop->num_wins)) {
1184 goto err_free_pzpos;
1188 pstate = state->plane_states[drm_plane_index(plane)];
1190 * plane might not have changed, in which case take
1194 pstate = plane->state;
1195 plane_state = to_vop_plane_state(pstate);
1196 pzpos[cnt].zpos = plane_state->zpos;
1197 pzpos[cnt++].win_id = win->win_id;
1200 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1202 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1203 const struct vop_win_data *win_data = &vop_data->win[i];
1206 if (win_data->phy) {
1207 struct vop_zpos *zpos = &pzpos[cnt++];
1209 dsp_layer_sel |= zpos->win_id << shift;
1211 dsp_layer_sel |= i << shift;
1215 s->dsp_layer_sel = dsp_layer_sel;
1222 static void vop_cfg_update(struct drm_crtc *crtc,
1223 struct drm_crtc_state *old_crtc_state)
1225 struct rockchip_crtc_state *s =
1226 to_rockchip_crtc_state(crtc->state);
1227 struct vop *vop = to_vop(crtc);
1229 spin_lock(&vop->reg_lock);
1231 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1234 spin_unlock(&vop->reg_lock);
1237 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1238 struct drm_crtc_state *old_crtc_state)
1240 struct vop *vop = to_vop(crtc);
1242 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1244 if (!vop_is_allwin_disabled(vop)) {
1245 vop_cfg_update(crtc, old_crtc_state);
1246 while(!vop_is_cfg_done_complete(vop));
1248 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1250 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1252 vop->is_iommu_enabled = true;
1255 vop_cfg_update(crtc, old_crtc_state);
1258 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1259 struct drm_crtc_state *old_crtc_state)
1261 struct vop *vop = to_vop(crtc);
1263 if (crtc->state->event) {
1264 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1266 vop->event = crtc->state->event;
1267 crtc->state->event = NULL;
1271 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1272 .enable = vop_crtc_enable,
1273 .disable = vop_crtc_disable,
1274 .mode_fixup = vop_crtc_mode_fixup,
1275 .atomic_check = vop_crtc_atomic_check,
1276 .atomic_flush = vop_crtc_atomic_flush,
1277 .atomic_begin = vop_crtc_atomic_begin,
1280 static void vop_crtc_destroy(struct drm_crtc *crtc)
1282 drm_crtc_cleanup(crtc);
1285 static void vop_crtc_reset(struct drm_crtc *crtc)
1288 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1291 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1293 crtc->state->crtc = crtc;
1296 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1298 struct rockchip_crtc_state *rockchip_state;
1300 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1301 if (!rockchip_state)
1304 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1305 return &rockchip_state->base;
1308 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1309 struct drm_crtc_state *state)
1311 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1313 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1317 static const struct drm_crtc_funcs vop_crtc_funcs = {
1318 .set_config = drm_atomic_helper_set_config,
1319 .page_flip = drm_atomic_helper_page_flip,
1320 .destroy = vop_crtc_destroy,
1321 .reset = vop_crtc_reset,
1322 .atomic_duplicate_state = vop_crtc_duplicate_state,
1323 .atomic_destroy_state = vop_crtc_destroy_state,
1326 static void vop_handle_vblank(struct vop *vop)
1328 struct drm_device *drm = vop->drm_dev;
1329 struct drm_crtc *crtc = &vop->crtc;
1330 unsigned long flags;
1332 if (!vop_is_cfg_done_complete(vop))
1336 spin_lock_irqsave(&drm->event_lock, flags);
1338 drm_crtc_send_vblank_event(crtc, vop->event);
1339 drm_crtc_vblank_put(crtc);
1342 spin_unlock_irqrestore(&drm->event_lock, flags);
1344 if (!completion_done(&vop->wait_update_complete))
1345 complete(&vop->wait_update_complete);
1348 static irqreturn_t vop_isr(int irq, void *data)
1350 struct vop *vop = data;
1351 struct drm_crtc *crtc = &vop->crtc;
1352 uint32_t active_irqs;
1353 unsigned long flags;
1357 * interrupt register has interrupt status, enable and clear bits, we
1358 * must hold irq_lock to avoid a race with enable/disable_vblank().
1360 spin_lock_irqsave(&vop->irq_lock, flags);
1362 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1363 /* Clear all active interrupt sources */
1365 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1367 spin_unlock_irqrestore(&vop->irq_lock, flags);
1369 /* This is expected for vop iommu irqs, since the irq is shared */
1373 if (active_irqs & DSP_HOLD_VALID_INTR) {
1374 complete(&vop->dsp_hold_completion);
1375 active_irqs &= ~DSP_HOLD_VALID_INTR;
1379 if (active_irqs & FS_INTR) {
1380 drm_crtc_handle_vblank(crtc);
1381 vop_handle_vblank(vop);
1382 active_irqs &= ~FS_INTR;
1386 /* Unhandled irqs are spurious. */
1388 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1393 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1394 unsigned long possible_crtcs)
1396 struct drm_plane *share = NULL;
1397 unsigned int rotations = 0;
1398 struct drm_property *prop;
1399 uint64_t feature = 0;
1403 share = &win->parent->base;
1405 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1406 possible_crtcs, &vop_plane_funcs,
1407 win->data_formats, win->nformats, win->type);
1409 DRM_ERROR("failed to initialize plane\n");
1412 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1413 drm_object_attach_property(&win->base.base,
1414 vop->plane_zpos_prop, win->win_id);
1416 if (VOP_WIN_SUPPORT(vop, win, xmirror))
1417 rotations |= BIT(DRM_REFLECT_X);
1419 if (VOP_WIN_SUPPORT(vop, win, ymirror))
1420 rotations |= BIT(DRM_REFLECT_Y);
1423 rotations |= BIT(DRM_ROTATE_0);
1424 prop = drm_mode_create_rotation_property(vop->drm_dev,
1427 DRM_ERROR("failed to create zpos property\n");
1430 drm_object_attach_property(&win->base.base, prop,
1432 win->rotation_prop = prop;
1435 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1436 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1437 VOP_WIN_SUPPORT(vop, win, alpha_en))
1438 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1440 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1446 static int vop_create_crtc(struct vop *vop)
1448 struct device *dev = vop->dev;
1449 struct drm_device *drm_dev = vop->drm_dev;
1450 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1451 struct drm_crtc *crtc = &vop->crtc;
1452 struct device_node *port;
1457 * Create drm_plane for primary and cursor planes first, since we need
1458 * to pass them to drm_crtc_init_with_planes, which sets the
1459 * "possible_crtcs" to the newly initialized crtc.
1461 for (i = 0; i < vop->num_wins; i++) {
1462 struct vop_win *win = &vop->win[i];
1464 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1465 win->type != DRM_PLANE_TYPE_CURSOR)
1468 ret = vop_plane_init(vop, win, 0);
1470 goto err_cleanup_planes;
1473 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1475 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1480 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1481 &vop_crtc_funcs, NULL);
1483 goto err_cleanup_planes;
1485 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1488 * Create drm_planes for overlay windows with possible_crtcs restricted
1489 * to the newly created crtc.
1491 for (i = 0; i < vop->num_wins; i++) {
1492 struct vop_win *win = &vop->win[i];
1493 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1495 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1498 ret = vop_plane_init(vop, win, possible_crtcs);
1500 goto err_cleanup_crtc;
1503 port = of_get_child_by_name(dev->of_node, "port");
1505 DRM_ERROR("no port node found in %s\n",
1506 dev->of_node->full_name);
1508 goto err_cleanup_crtc;
1511 init_completion(&vop->dsp_hold_completion);
1512 init_completion(&vop->wait_update_complete);
1514 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1519 drm_crtc_cleanup(crtc);
1521 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1523 drm_plane_cleanup(plane);
1527 static void vop_destroy_crtc(struct vop *vop)
1529 struct drm_crtc *crtc = &vop->crtc;
1530 struct drm_device *drm_dev = vop->drm_dev;
1531 struct drm_plane *plane, *tmp;
1533 rockchip_unregister_crtc_funcs(crtc);
1534 of_node_put(crtc->port);
1537 * We need to cleanup the planes now. Why?
1539 * The planes are "&vop->win[i].base". That means the memory is
1540 * all part of the big "struct vop" chunk of memory. That memory
1541 * was devm allocated and associated with this component. We need to
1542 * free it ourselves before vop_unbind() finishes.
1544 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1546 vop_plane_destroy(plane);
1549 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1550 * references the CRTC.
1552 drm_crtc_cleanup(crtc);
1556 * Initialize the vop->win array elements.
1558 static int vop_win_init(struct vop *vop)
1560 const struct vop_data *vop_data = vop->data;
1562 unsigned int num_wins = 0;
1563 struct drm_property *prop;
1564 static const struct drm_prop_enum_list props[] = {
1565 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1566 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1569 for (i = 0; i < vop_data->win_size; i++) {
1570 struct vop_win *vop_win = &vop->win[num_wins];
1571 const struct vop_win_data *win_data = &vop_data->win[i];
1576 vop_win->phy = win_data->phy;
1577 vop_win->offset = win_data->base;
1578 vop_win->type = win_data->type;
1579 vop_win->data_formats = win_data->phy->data_formats;
1580 vop_win->nformats = win_data->phy->nformats;
1582 vop_win->win_id = i;
1583 vop_win->area_id = 0;
1586 for (j = 0; j < win_data->area_size; j++) {
1587 struct vop_win *vop_area = &vop->win[num_wins];
1588 const struct vop_win_phy *area = win_data->area[j];
1590 vop_area->parent = vop_win;
1591 vop_area->offset = vop_win->offset;
1592 vop_area->phy = area;
1593 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1594 vop_area->data_formats = vop_win->data_formats;
1595 vop_area->nformats = vop_win->nformats;
1596 vop_area->vop = vop;
1597 vop_area->win_id = i;
1598 vop_area->area_id = j;
1603 vop->num_wins = num_wins;
1605 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1606 "ZPOS", 0, vop->data->win_size);
1608 DRM_ERROR("failed to create zpos property\n");
1611 vop->plane_zpos_prop = prop;
1613 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1614 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1615 props, ARRAY_SIZE(props),
1616 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1617 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1618 if (!vop->plane_feature_prop) {
1619 DRM_ERROR("failed to create feature property\n");
1626 static int vop_bind(struct device *dev, struct device *master, void *data)
1628 struct platform_device *pdev = to_platform_device(dev);
1629 const struct vop_data *vop_data;
1630 struct drm_device *drm_dev = data;
1632 struct resource *res;
1637 vop_data = of_device_get_match_data(dev);
1641 for (i = 0; i < vop_data->win_size; i++) {
1642 const struct vop_win_data *win_data = &vop_data->win[i];
1644 num_wins += win_data->area_size + 1;
1647 /* Allocate vop struct and its vop_win array */
1648 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1649 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1654 vop->data = vop_data;
1655 vop->drm_dev = drm_dev;
1656 vop->num_wins = num_wins;
1657 dev_set_drvdata(dev, vop);
1659 ret = vop_win_init(vop);
1663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1664 vop->len = resource_size(res);
1665 vop->regs = devm_ioremap_resource(dev, res);
1666 if (IS_ERR(vop->regs))
1667 return PTR_ERR(vop->regs);
1669 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1673 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1674 if (IS_ERR(vop->hclk)) {
1675 dev_err(vop->dev, "failed to get hclk source\n");
1676 return PTR_ERR(vop->hclk);
1678 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1679 if (IS_ERR(vop->aclk)) {
1680 dev_err(vop->dev, "failed to get aclk source\n");
1681 return PTR_ERR(vop->aclk);
1683 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1684 if (IS_ERR(vop->dclk)) {
1685 dev_err(vop->dev, "failed to get dclk source\n");
1686 return PTR_ERR(vop->dclk);
1689 irq = platform_get_irq(pdev, 0);
1691 dev_err(dev, "cannot find irq for vop\n");
1694 vop->irq = (unsigned int)irq;
1696 spin_lock_init(&vop->reg_lock);
1697 spin_lock_init(&vop->irq_lock);
1699 mutex_init(&vop->vsync_mutex);
1701 ret = devm_request_irq(dev, vop->irq, vop_isr,
1702 IRQF_SHARED, dev_name(dev), vop);
1706 /* IRQ is initially disabled; it gets enabled in power_on */
1707 disable_irq(vop->irq);
1709 ret = vop_create_crtc(vop);
1713 pm_runtime_enable(&pdev->dev);
1717 static void vop_unbind(struct device *dev, struct device *master, void *data)
1719 struct vop *vop = dev_get_drvdata(dev);
1721 pm_runtime_disable(dev);
1722 vop_destroy_crtc(vop);
1725 const struct component_ops vop_component_ops = {
1727 .unbind = vop_unbind,
1729 EXPORT_SYMBOL_GPL(vop_component_ops);