drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/iopoll.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/component.h>
  31
  32 #include <linux/reset.h>
  33 #include <linux/delay.h>
  34 #include <linux/sort.h>
  35 #include <uapi/drm/rockchip_drm.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop.h"
  41
  42 #define VOP_REG_SUPPORT(vop, reg) \
  43                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  44                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  45                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  46                 reg.mask))
  47
  48 #define VOP_WIN_SUPPORT(vop, win, name) \
  49                 VOP_REG_SUPPORT(vop, win->phy->name)
  50
  51 #define VOP_CTRL_SUPPORT(vop, name) \
  52                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  53
  54 #define VOP_INTR_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  56
  57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  58                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  59
  60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  61         do { \
  62                 if (VOP_REG_SUPPORT(vop, reg)) \
  63                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  64                                   v, reg.write_mask, relaxed); \
  65                 else \
  66                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  67         } while(0)
  68
  69 #define REG_SET(x, name, off, reg, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  73
  74 #define VOP_WIN_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  77                 REG_SET(x, name, 0, win->ext->name, v, true)
  78 #define VOP_SCL_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  80 #define VOP_SCL_SET_EXT(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  82
  83 #define VOP_CTRL_SET(x, name, v) \
  84                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  85
  86 #define VOP_INTR_GET(vop, name) \
  87                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  88
  89 #define VOP_INTR_SET(vop, name, v) \
  90                 REG_SET(vop, name, 0, vop->data->intr->name, \
  91                         v, false)
  92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  93                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  94                              mask, v, false)
  95
  96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  97         do { \
  98                 int i, reg = 0, mask = 0; \
  99                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 100                         if (vop->data->intr->intrs[i] & type) { \
 101                                 reg |= (v) << i; \
 102                                 mask |= 1 << i; \
 103                         } \
 104                 } \
 105                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 106         } while (0)
 107 #define VOP_INTR_GET_TYPE(vop, name, type) \
 108                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 109
 110 #define VOP_CTRL_GET(x, name) \
 111                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 112
 113 #define VOP_WIN_GET(x, win, name) \
 114                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 115
 116 #define VOP_WIN_NAME(win, name) \
 117                 (vop_get_win_phy(win, &win->phy->name)->name)
 118
 119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 120                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 121
 122 #define to_vop(x) container_of(x, struct vop, crtc)
 123 #define to_vop_win(x) container_of(x, struct vop_win, base)
 124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 125
 126 struct vop_zpos {
 127         int win_id;
 128         int zpos;
 129 };
 130
 131 struct vop_plane_state {
 132         struct drm_plane_state base;
 133         int format;
 134         int zpos;
 135         struct drm_rect src;
 136         struct drm_rect dest;
 137         dma_addr_t yrgb_mst;
 138         dma_addr_t uv_mst;
 139         const uint32_t *y2r_table;
 140         const uint32_t *r2r_table;
 141         const uint32_t *r2y_table;
 142         bool enable;
 143 };
 144
 145 struct vop_win {
 146         struct vop_win *parent;
 147         struct drm_plane base;
 148
 149         int win_id;
 150         int area_id;
 151         uint32_t offset;
 152         enum drm_plane_type type;
 153         const struct vop_win_phy *phy;
 154         const struct vop_csc *csc;
 155         const uint32_t *data_formats;
 156         uint32_t nformats;
 157         struct vop *vop;
 158
 159         struct drm_property *rotation_prop;
 160         struct vop_plane_state state;
 161 };
 162
 163 struct vop {
 164         struct drm_crtc crtc;
 165         struct device *dev;
 166         struct drm_device *drm_dev;
 167         struct drm_property *plane_zpos_prop;
 168         struct drm_property *plane_feature_prop;
 169         struct drm_property *feature_prop;
 170         bool is_iommu_enabled;
 171         bool is_iommu_needed;
 172         bool is_enabled;
 173
 174         /* mutex vsync_ work */
 175         struct mutex vsync_mutex;
 176         bool vsync_work_pending;
 177         bool loader_protect;
 178         struct completion dsp_hold_completion;
 179         struct completion wait_update_complete;
 180         struct drm_pending_vblank_event *event;
 181
 182         struct completion line_flag_completion;
 183
 184         const struct vop_data *data;
 185         int num_wins;
 186
 187         uint32_t *regsbak;
 188         void __iomem *regs;
 189
 190         /* physical map length of vop register */
 191         uint32_t len;
 192
 193         /* one time only one process allowed to config the register */
 194         spinlock_t reg_lock;
 195         /* lock vop irq reg */
 196         spinlock_t irq_lock;
 197
 198         unsigned int irq;
 199
 200         /* vop AHP clk */
 201         struct clk *hclk;
 202         /* vop dclk */
 203         struct clk *dclk;
 204         /* vop share memory frequency */
 205         struct clk *aclk;
 206
 207         /* vop dclk reset */
 208         struct reset_control *dclk_rst;
 209
 210         struct vop_win win[];
 211 };
 212
 213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 214 {
 215         writel(v, vop->regs + offset);
 216         vop->regsbak[offset >> 2] = v;
 217 }
 218
 219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 220 {
 221         return readl(vop->regs + offset);
 222 }
 223
 224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 225                                     const struct vop_reg *reg)
 226 {
 227         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 228 }
 229
 230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 231                                   uint32_t mask, uint32_t shift, uint32_t v,
 232                                   bool write_mask, bool relaxed)
 233 {
 234         if (!mask)
 235                 return;
 236
 237         if (write_mask) {
 238                 v = ((v & mask) << shift) | (mask << (shift + 16));
 239         } else {
 240                 uint32_t cached_val = vop->regsbak[offset >> 2];
 241
 242                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 243                 vop->regsbak[offset >> 2] = v;
 244         }
 245
 246         if (relaxed)
 247                 writel_relaxed(v, vop->regs + offset);
 248         else
 249                 writel(v, vop->regs + offset);
 250 }
 251
 252 static inline const struct vop_win_phy *
 253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 254 {
 255         if (!reg->mask && win->parent)
 256                 return win->parent->phy;
 257
 258         return win->phy;
 259 }
 260
 261 static inline uint32_t vop_get_intr_type(struct vop *vop,
 262                                          const struct vop_reg *reg, int type)
 263 {
 264         uint32_t i, ret = 0;
 265         uint32_t regs = vop_read_reg(vop, 0, reg);
 266
 267         for (i = 0; i < vop->data->intr->nintrs; i++) {
 268                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 269                         ret |= vop->data->intr->intrs[i];
 270         }
 271
 272         return ret;
 273 }
 274
 275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 276 {
 277         int i;
 278
 279         if (!table)
 280                 return;
 281
 282         for (i = 0; i < 8; i++)
 283                 vop_writel(vop, offset + i * 4, table[i]);
 284 }
 285
 286 static inline void vop_cfg_done(struct vop *vop)
 287 {
 288         VOP_CTRL_SET(vop, cfg_done, 1);
 289 }
 290
 291 static bool vop_is_allwin_disabled(struct vop *vop)
 292 {
 293         int i;
 294
 295         for (i = 0; i < vop->num_wins; i++) {
 296                 struct vop_win *win = &vop->win[i];
 297
 298                 if (VOP_WIN_GET(vop, win, enable) != 0)
 299                         return false;
 300         }
 301
 302         return true;
 303 }
 304
 305 static bool vop_is_cfg_done_complete(struct vop *vop)
 306 {
 307         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 308 }
 309
 310 static bool vop_fs_irq_is_active(struct vop *vop)
 311 {
 312         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 313 }
 314
 315 static bool vop_line_flag_is_active(struct vop *vop)
 316 {
 317         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 318 }
 319
 320 static bool has_rb_swapped(uint32_t format)
 321 {
 322         switch (format) {
 323         case DRM_FORMAT_XBGR8888:
 324         case DRM_FORMAT_ABGR8888:
 325         case DRM_FORMAT_BGR888:
 326         case DRM_FORMAT_BGR565:
 327                 return true;
 328         default:
 329                 return false;
 330         }
 331 }
 332
 333 static enum vop_data_format vop_convert_format(uint32_t format)
 334 {
 335         switch (format) {
 336         case DRM_FORMAT_XRGB8888:
 337         case DRM_FORMAT_ARGB8888:
 338         case DRM_FORMAT_XBGR8888:
 339         case DRM_FORMAT_ABGR8888:
 340                 return VOP_FMT_ARGB8888;
 341         case DRM_FORMAT_RGB888:
 342         case DRM_FORMAT_BGR888:
 343                 return VOP_FMT_RGB888;
 344         case DRM_FORMAT_RGB565:
 345         case DRM_FORMAT_BGR565:
 346                 return VOP_FMT_RGB565;
 347         case DRM_FORMAT_NV12:
 348         case DRM_FORMAT_NV12_10:
 349                 return VOP_FMT_YUV420SP;
 350         case DRM_FORMAT_NV16:
 351         case DRM_FORMAT_NV16_10:
 352                 return VOP_FMT_YUV422SP;
 353         case DRM_FORMAT_NV24:
 354         case DRM_FORMAT_NV24_10:
 355                 return VOP_FMT_YUV444SP;
 356         default:
 357                 DRM_ERROR("unsupport format[%08x]\n", format);
 358                 return -EINVAL;
 359         }
 360 }
 361
 362 static bool is_yuv_output(uint32_t bus_format)
 363 {
 364         switch (bus_format) {
 365         case MEDIA_BUS_FMT_YUV8_1X24:
 366         case MEDIA_BUS_FMT_YUV10_1X30:
 367                 return true;
 368         default:
 369                 return false;
 370         }
 371 }
 372
 373 static bool is_yuv_support(uint32_t format)
 374 {
 375         switch (format) {
 376         case DRM_FORMAT_NV12:
 377         case DRM_FORMAT_NV12_10:
 378         case DRM_FORMAT_NV16:
 379         case DRM_FORMAT_NV16_10:
 380         case DRM_FORMAT_NV24:
 381         case DRM_FORMAT_NV24_10:
 382                 return true;
 383         default:
 384                 return false;
 385         }
 386 }
 387
 388 static bool is_yuv_10bit(uint32_t format)
 389 {
 390         switch (format) {
 391         case DRM_FORMAT_NV12_10:
 392         case DRM_FORMAT_NV16_10:
 393         case DRM_FORMAT_NV24_10:
 394                 return true;
 395         default:
 396                 return false;
 397         }
 398 }
 399
 400 static bool is_alpha_support(uint32_t format)
 401 {
 402         switch (format) {
 403         case DRM_FORMAT_ARGB8888:
 404         case DRM_FORMAT_ABGR8888:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410
 411 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 412                                   uint32_t dst, bool is_horizontal,
 413                                   int vsu_mode, int *vskiplines)
 414 {
 415         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 416
 417         if (is_horizontal) {
 418                 if (mode == SCALE_UP)
 419                         val = GET_SCL_FT_BIC(src, dst);
 420                 else if (mode == SCALE_DOWN)
 421                         val = GET_SCL_FT_BILI_DN(src, dst);
 422         } else {
 423                 if (mode == SCALE_UP) {
 424                         if (vsu_mode == SCALE_UP_BIL)
 425                                 val = GET_SCL_FT_BILI_UP(src, dst);
 426                         else
 427                                 val = GET_SCL_FT_BIC(src, dst);
 428                 } else if (mode == SCALE_DOWN) {
 429                         if (vskiplines) {
 430                                 *vskiplines = scl_get_vskiplines(src, dst);
 431                                 val = scl_get_bili_dn_vskip(src, dst,
 432                                                             *vskiplines);
 433                         } else {
 434                                 val = GET_SCL_FT_BILI_DN(src, dst);
 435                         }
 436                 }
 437         }
 438
 439         return val;
 440 }
 441
 442 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 443                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 444                                 uint32_t dst_h, uint32_t pixel_format)
 445 {
 446         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 447         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 448         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 449         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 450         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 451         bool is_yuv = is_yuv_support(pixel_format);
 452         uint16_t cbcr_src_w = src_w / hsub;
 453         uint16_t cbcr_src_h = src_h / vsub;
 454         uint16_t vsu_mode;
 455         uint16_t lb_mode;
 456         uint32_t val;
 457         int vskiplines = 0;
 458
 459         if (!win->phy->scl)
 460                 return;
 461
 462         if (!win->phy->scl->ext) {
 463                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 464                             scl_cal_scale2(src_w, dst_w));
 465                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 466                             scl_cal_scale2(src_h, dst_h));
 467                 if (is_yuv) {
 468                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 469                                     scl_cal_scale2(cbcr_src_w, dst_w));
 470                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 471                                     scl_cal_scale2(cbcr_src_h, dst_h));
 472                 }
 473                 return;
 474         }
 475
 476         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 477         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 478
 479         if (is_yuv) {
 480                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 481                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 482                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 483                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 484                 else
 485                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 486         } else {
 487                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 488                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 489                 else
 490                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 491         }
 492
 493         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 494         if (lb_mode == LB_RGB_3840X2) {
 495                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 496                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 497                         return;
 498                 }
 499                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 500                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 501                         return;
 502                 }
 503                 vsu_mode = SCALE_UP_BIL;
 504         } else if (lb_mode == LB_RGB_2560X4) {
 505                 vsu_mode = SCALE_UP_BIL;
 506         } else {
 507                 vsu_mode = SCALE_UP_BIC;
 508         }
 509
 510         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 511                                 true, 0, NULL);
 512         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 513         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 514                                 false, vsu_mode, &vskiplines);
 515         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 516
 517         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 518         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 519
 520         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 521         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 522         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 523         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 524         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 525         if (is_yuv) {
 526                 vskiplines = 0;
 527
 528                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 529                                         dst_w, true, 0, NULL);
 530                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 531                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 532                                         dst_h, false, vsu_mode, &vskiplines);
 533                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 534
 535                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 536                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 537                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 538                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 539                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 540                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 541                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 542         }
 543 }
 544
 545 /*
 546  * rk3399 colorspace path:
 547  *      Input        Win csc                     Output
 548  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 549  *    RGB        --> R2Y                  __/
 550  *
 551  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 552  *    RGB        --> 709To2020->R2Y       __/
 553  *
 554  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 555  *    RGB        --> R2Y                  __/
 556  *
 557  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 558  *    RGB        --> 709To2020->R2Y       __/
 559  *
 560  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 561  *    RGB        --> R2Y                  __/
 562  *
 563  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 564  *    RGB        --> R2Y(601)             __/
 565  *
 566  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 567  *    RGB        --> bypass               __/
 568  *
 569  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 570  *
 571  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 572  *
 573  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 574  *
 575  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 576  */
 577 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 578                          bool is_input_yuv, bool is_output_yuv,
 579                          int input_csc, int output_csc,
 580                          const uint32_t **y2r_table,
 581                          const uint32_t **r2r_table,
 582                          const uint32_t **r2y_table)
 583 {
 584         *y2r_table = NULL;
 585         *r2r_table = NULL;
 586         *r2y_table = NULL;
 587
 588         if (is_output_yuv) {
 589                 if (output_csc == CSC_BT2020) {
 590                         if (is_input_yuv) {
 591                                 if (input_csc == CSC_BT2020)
 592                                         return 0;
 593                                 *y2r_table = csc_table->y2r_bt709;
 594                         }
 595                         if (input_csc != CSC_BT2020)
 596                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 597                         *r2y_table = csc_table->r2y_bt2020;
 598                 } else {
 599                         if (is_input_yuv && input_csc == CSC_BT2020)
 600                                 *y2r_table = csc_table->y2r_bt2020;
 601                         if (input_csc == CSC_BT2020)
 602                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 603                         if (!is_input_yuv || *y2r_table) {
 604                                 if (output_csc == CSC_BT709)
 605                                         *r2y_table = csc_table->r2y_bt709;
 606                                 else
 607                                         *r2y_table = csc_table->r2y_bt601;
 608                         }
 609                 }
 610         } else {
 611                 if (!is_input_yuv)
 612                         return 0;
 613
 614                 /*
 615                  * is possible use bt2020 on rgb mode?
 616                  */
 617                 if (WARN_ON(output_csc == CSC_BT2020))
 618                         return -EINVAL;
 619
 620                 if (input_csc == CSC_BT2020)
 621                         *y2r_table = csc_table->y2r_bt2020;
 622                 else if (input_csc == CSC_BT709)
 623                         *y2r_table = csc_table->y2r_bt709;
 624                 else
 625                         *y2r_table = csc_table->y2r_bt601;
 626
 627                 if (input_csc == CSC_BT2020)
 628                         /*
 629                          * We don't have bt601 to bt709 table, force use bt709.
 630                          */
 631                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 632         }
 633
 634         return 0;
 635 }
 636
 637 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 638                                 struct drm_crtc_state *crtc_state)
 639 {
 640         struct vop *vop = to_vop(crtc);
 641         struct drm_atomic_state *state = crtc_state->state;
 642         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 643         const struct vop_csc_table *csc_table = vop->data->csc_table;
 644         struct drm_plane_state *pstate;
 645         struct drm_plane *plane;
 646         bool is_input_yuv, is_output_yuv;
 647         int ret;
 648
 649         if (!csc_table)
 650                 return 0;
 651
 652         is_output_yuv = is_yuv_output(s->bus_format);
 653
 654         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 655                 struct vop_plane_state *vop_plane_state;
 656
 657                 pstate = drm_atomic_get_plane_state(state, plane);
 658                 if (IS_ERR(pstate))
 659                         return PTR_ERR(pstate);
 660                 vop_plane_state = to_vop_plane_state(pstate);
 661
 662                 if (!pstate->fb)
 663                         continue;
 664                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 665
 666                 /*
 667                  * TODO: force set input and output csc mode.
 668                  */
 669                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 670                                     CSC_BT709, CSC_BT709,
 671                                     &vop_plane_state->y2r_table,
 672                                     &vop_plane_state->r2r_table,
 673                                     &vop_plane_state->r2y_table);
 674                 if (ret)
 675                         return ret;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 682 {
 683         unsigned long flags;
 684
 685         spin_lock_irqsave(&vop->irq_lock, flags);
 686
 687         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 688         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 689
 690         spin_unlock_irqrestore(&vop->irq_lock, flags);
 691 }
 692
 693 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 694 {
 695         unsigned long flags;
 696
 697         spin_lock_irqsave(&vop->irq_lock, flags);
 698
 699         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 700
 701         spin_unlock_irqrestore(&vop->irq_lock, flags);
 702 }
 703
 704 /*
 705  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 706  *     the "FRAME_SYNC" interrupt.
 707  * (2) the active data region of each frame ends at dsp_vact_end
 708  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 709  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 710  *
 711  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 712  * Interrupts
 713  * LINE_FLAG -------------------------------+
 714  * FRAME_SYNC ----+                         |
 715  *                |                         |
 716  *                v                         v
 717  *                | Vsync | Vbp |  Vactive  | Vfp |
 718  *                        ^     ^           ^     ^
 719  *                        |     |           |     |
 720  *                        |     |           |     |
 721  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 722  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 723  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 724  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 725  */
 726 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 727 {
 728         uint32_t line_flag_irq;
 729         unsigned long flags;
 730
 731         spin_lock_irqsave(&vop->irq_lock, flags);
 732
 733         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 734
 735         spin_unlock_irqrestore(&vop->irq_lock, flags);
 736
 737         return !!line_flag_irq;
 738 }
 739
 740 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 741 {
 742         unsigned long flags;
 743
 744         if (WARN_ON(!vop->is_enabled))
 745                 return;
 746
 747         spin_lock_irqsave(&vop->irq_lock, flags);
 748
 749         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 750         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 751         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 752
 753         spin_unlock_irqrestore(&vop->irq_lock, flags);
 754 }
 755
 756 static void vop_line_flag_irq_disable(struct vop *vop)
 757 {
 758         unsigned long flags;
 759
 760         if (WARN_ON(!vop->is_enabled))
 761                 return;
 762
 763         spin_lock_irqsave(&vop->irq_lock, flags);
 764
 765         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 766
 767         spin_unlock_irqrestore(&vop->irq_lock, flags);
 768 }
 769
 770 static void vop_power_enable(struct drm_crtc *crtc)
 771 {
 772         struct vop *vop = to_vop(crtc);
 773         int ret;
 774
 775         ret = clk_prepare_enable(vop->hclk);
 776         if (ret < 0) {
 777                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 778                 return;
 779         }
 780
 781         ret = clk_prepare_enable(vop->dclk);
 782         if (ret < 0) {
 783                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 784                 goto err_disable_hclk;
 785         }
 786
 787         ret = clk_prepare_enable(vop->aclk);
 788         if (ret < 0) {
 789                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 790                 goto err_disable_dclk;
 791         }
 792
 793         ret = pm_runtime_get_sync(vop->dev);
 794         if (ret < 0) {
 795                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 796                 return;
 797         }
 798
 799         memcpy(vop->regsbak, vop->regs, vop->len);
 800
 801         vop->is_enabled = true;
 802
 803         return;
 804
 805 err_disable_dclk:
 806         clk_disable_unprepare(vop->dclk);
 807 err_disable_hclk:
 808         clk_disable_unprepare(vop->hclk);
 809 }
 810
 811 static void vop_initial(struct drm_crtc *crtc)
 812 {
 813         struct vop *vop = to_vop(crtc);
 814         int i;
 815
 816         vop_power_enable(crtc);
 817
 818         VOP_CTRL_SET(vop, global_regdone_en, 1);
 819         VOP_CTRL_SET(vop, dsp_blank, 0);
 820
 821         /*
 822          * We need to make sure that all windows are disabled before resume
 823          * the crtc. Otherwise we might try to scan from a destroyed
 824          * buffer later.
 825          */
 826         for (i = 0; i < vop->num_wins; i++) {
 827                 struct vop_win *win = &vop->win[i];
 828                 int channel = i * 2 + 1;
 829
 830                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 831                 if (win->phy->scl && win->phy->scl->ext) {
 832                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 833                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 834                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 835                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 836                 }
 837                 VOP_WIN_SET(vop, win, enable, 0);
 838                 VOP_WIN_SET(vop, win, gate, 1);
 839         }
 840         VOP_CTRL_SET(vop, afbdc_en, 0);
 841 }
 842
 843 static void vop_crtc_disable(struct drm_crtc *crtc)
 844 {
 845         struct vop *vop = to_vop(crtc);
 846
 847         drm_crtc_vblank_off(crtc);
 848
 849         /*
 850          * Vop standby will take effect at end of current frame,
 851          * if dsp hold valid irq happen, it means standby complete.
 852          *
 853          * we must wait standby complete when we want to disable aclk,
 854          * if not, memory bus maybe dead.
 855          */
 856         reinit_completion(&vop->dsp_hold_completion);
 857         vop_dsp_hold_valid_irq_enable(vop);
 858
 859         spin_lock(&vop->reg_lock);
 860
 861         VOP_CTRL_SET(vop, standby, 1);
 862
 863         spin_unlock(&vop->reg_lock);
 864
 865         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 866                                              msecs_to_jiffies(50)));
 867
 868         vop_dsp_hold_valid_irq_disable(vop);
 869
 870         disable_irq(vop->irq);
 871
 872         vop->is_enabled = false;
 873         if (vop->is_iommu_enabled) {
 874                 /*
 875                  * vop standby complete, so iommu detach is safe.
 876                  */
 877                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 878                 vop->is_iommu_enabled = false;
 879         }
 880
 881         pm_runtime_put(vop->dev);
 882         clk_disable_unprepare(vop->dclk);
 883         clk_disable_unprepare(vop->aclk);
 884         clk_disable_unprepare(vop->hclk);
 885 }
 886
 887 static void vop_plane_destroy(struct drm_plane *plane)
 888 {
 889         drm_plane_cleanup(plane);
 890 }
 891
 892 static int vop_plane_prepare_fb(struct drm_plane *plane,
 893                                 const struct drm_plane_state *new_state)
 894 {
 895         if (plane->state->fb)
 896                 drm_framebuffer_reference(plane->state->fb);
 897
 898         return 0;
 899 }
 900
 901 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 902                                  const struct drm_plane_state *old_state)
 903 {
 904         if (old_state->fb)
 905                 drm_framebuffer_unreference(old_state->fb);
 906 }
 907
 908 static int vop_plane_atomic_check(struct drm_plane *plane,
 909                            struct drm_plane_state *state)
 910 {
 911         struct drm_crtc *crtc = state->crtc;
 912         struct drm_framebuffer *fb = state->fb;
 913         struct vop_win *win = to_vop_win(plane);
 914         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 915         struct drm_crtc_state *crtc_state;
 916         const struct vop_data *vop_data;
 917         struct vop *vop;
 918         bool visible;
 919         int ret;
 920         struct drm_rect *dest = &vop_plane_state->dest;
 921         struct drm_rect *src = &vop_plane_state->src;
 922         struct drm_rect clip;
 923         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 924                                         DRM_PLANE_HELPER_NO_SCALING;
 925         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 926                                         DRM_PLANE_HELPER_NO_SCALING;
 927         unsigned long offset;
 928         dma_addr_t dma_addr;
 929         u16 vdisplay;
 930
 931         crtc = crtc ? crtc : plane->state->crtc;
 932         /*
 933          * Both crtc or plane->state->crtc can be null.
 934          */
 935         if (!crtc || !fb)
 936                 goto out_disable;
 937
 938         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 939         if (IS_ERR(crtc_state))
 940                 return PTR_ERR(crtc_state);
 941
 942         src->x1 = state->src_x;
 943         src->y1 = state->src_y;
 944         src->x2 = state->src_x + state->src_w;
 945         src->y2 = state->src_y + state->src_h;
 946         dest->x1 = state->crtc_x;
 947         dest->y1 = state->crtc_y;
 948         dest->x2 = state->crtc_x + state->crtc_w;
 949         dest->y2 = state->crtc_y + state->crtc_h;
 950
 951         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
 952         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 953                 vdisplay *= 2;
 954
 955         clip.x1 = 0;
 956         clip.y1 = 0;
 957         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
 958         clip.y2 = vdisplay;
 959
 960         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 961                                             src, dest, &clip,
 962                                             min_scale,
 963                                             max_scale,
 964                                             true, true, &visible);
 965         if (ret)
 966                 return ret;
 967
 968         if (!visible)
 969                 goto out_disable;
 970
 971         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 972         if (vop_plane_state->format < 0)
 973                 return vop_plane_state->format;
 974
 975         vop = to_vop(crtc);
 976         vop_data = vop->data;
 977
 978         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
 979             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
 980                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
 981                           drm_rect_width(src) >> 16,
 982                           drm_rect_height(src) >> 16,
 983                           vop_data->max_input.width,
 984                           vop_data->max_input.height);
 985                 return -EINVAL;
 986         }
 987
 988         /*
 989          * Src.x1 can be odd when do clip, but yuv plane start point
 990          * need align with 2 pixel.
 991          */
 992         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
 993                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
 994                 return -EINVAL;
 995         }
 996
 997         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 998         if (state->rotation & BIT(DRM_REFLECT_Y))
 999                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1000         else
1001                 offset += (src->y1 >> 16) * fb->pitches[0];
1002
1003         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1004         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1005         if (is_yuv_support(fb->pixel_format)) {
1006                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1007                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1008                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1009
1010                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1011                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1012
1013                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1014                 dma_addr += offset + fb->offsets[1];
1015                 vop_plane_state->uv_mst = dma_addr;
1016         }
1017
1018         vop_plane_state->enable = true;
1019
1020         return 0;
1021
1022 out_disable:
1023         vop_plane_state->enable = false;
1024         return 0;
1025 }
1026
1027 static void vop_plane_atomic_disable(struct drm_plane *plane,
1028                                      struct drm_plane_state *old_state)
1029 {
1030         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1031         struct vop_win *win = to_vop_win(plane);
1032         struct vop *vop = to_vop(old_state->crtc);
1033
1034         if (!old_state->crtc)
1035                 return;
1036
1037         spin_lock(&vop->reg_lock);
1038
1039         /*
1040          * FIXUP: some of the vop scale would be abnormal after windows power
1041          * on/off so deinit scale to scale_none mode.
1042          */
1043         if (win->phy->scl && win->phy->scl->ext) {
1044                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1045                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1046                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1047                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1048         }
1049         VOP_WIN_SET(vop, win, enable, 0);
1050
1051         spin_unlock(&vop->reg_lock);
1052
1053         vop_plane_state->enable = false;
1054 }
1055
1056 static void vop_plane_atomic_update(struct drm_plane *plane,
1057                 struct drm_plane_state *old_state)
1058 {
1059         struct drm_plane_state *state = plane->state;
1060         struct drm_crtc *crtc = state->crtc;
1061         struct vop_win *win = to_vop_win(plane);
1062         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1063         struct rockchip_crtc_state *s;
1064         struct vop *vop;
1065         struct drm_framebuffer *fb = state->fb;
1066         unsigned int actual_w, actual_h;
1067         unsigned int dsp_stx, dsp_sty;
1068         uint32_t act_info, dsp_info, dsp_st;
1069         struct drm_rect *src = &vop_plane_state->src;
1070         struct drm_rect *dest = &vop_plane_state->dest;
1071         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1072         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1073         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1074         int ymirror, xmirror;
1075         uint32_t val;
1076         bool rb_swap;
1077
1078         /*
1079          * can't update plane when vop is disabled.
1080          */
1081         if (!crtc)
1082                 return;
1083
1084         if (!vop_plane_state->enable) {
1085                 vop_plane_atomic_disable(plane, old_state);
1086                 return;
1087         }
1088
1089         actual_w = drm_rect_width(src) >> 16;
1090         actual_h = drm_rect_height(src) >> 16;
1091         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1092
1093         dsp_info = (drm_rect_height(dest) - 1) << 16;
1094         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1095
1096         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1097         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1098         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1099
1100         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1101         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1102
1103         vop = to_vop(state->crtc);
1104         s = to_rockchip_crtc_state(crtc->state);
1105
1106         spin_lock(&vop->reg_lock);
1107
1108         VOP_WIN_SET(vop, win, xmirror, xmirror);
1109         VOP_WIN_SET(vop, win, ymirror, ymirror);
1110         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1111         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1112         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1113         if (is_yuv_support(fb->pixel_format)) {
1114                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1115                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1116         }
1117         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1118
1119         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1120                             drm_rect_width(dest), drm_rect_height(dest),
1121                             fb->pixel_format);
1122
1123         VOP_WIN_SET(vop, win, act_info, act_info);
1124         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1125         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1126
1127         rb_swap = has_rb_swapped(fb->pixel_format);
1128         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1129
1130         if (is_alpha_support(fb->pixel_format) &&
1131             (s->dsp_layer_sel & 0x3) != win->win_id) {
1132                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1133                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1134                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1135                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1136                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1137                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1138                         SRC_FACTOR_M0(ALPHA_ONE);
1139                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1140                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1141                 VOP_WIN_SET(vop, win, alpha_en, 1);
1142         } else {
1143                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1144                 VOP_WIN_SET(vop, win, alpha_en, 0);
1145         }
1146
1147         if (win->csc) {
1148                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1149                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1150                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1151                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1152                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1153                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1154         }
1155         VOP_WIN_SET(vop, win, enable, 1);
1156         spin_unlock(&vop->reg_lock);
1157         vop->is_iommu_needed = true;
1158 }
1159
1160 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1161         .prepare_fb = vop_plane_prepare_fb,
1162         .cleanup_fb = vop_plane_cleanup_fb,
1163         .atomic_check = vop_plane_atomic_check,
1164         .atomic_update = vop_plane_atomic_update,
1165         .atomic_disable = vop_plane_atomic_disable,
1166 };
1167
1168 void vop_atomic_plane_reset(struct drm_plane *plane)
1169 {
1170         struct vop_win *win = to_vop_win(plane);
1171         struct vop_plane_state *vop_plane_state =
1172                                         to_vop_plane_state(plane->state);
1173
1174         if (plane->state && plane->state->fb)
1175                 drm_framebuffer_unreference(plane->state->fb);
1176
1177         kfree(vop_plane_state);
1178         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1179         if (!vop_plane_state)
1180                 return;
1181
1182         vop_plane_state->zpos = win->win_id;
1183         plane->state = &vop_plane_state->base;
1184         plane->state->plane = plane;
1185 }
1186
1187 struct drm_plane_state *
1188 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1189 {
1190         struct vop_plane_state *old_vop_plane_state;
1191         struct vop_plane_state *vop_plane_state;
1192
1193         if (WARN_ON(!plane->state))
1194                 return NULL;
1195
1196         old_vop_plane_state = to_vop_plane_state(plane->state);
1197         vop_plane_state = kmemdup(old_vop_plane_state,
1198                                   sizeof(*vop_plane_state), GFP_KERNEL);
1199         if (!vop_plane_state)
1200                 return NULL;
1201
1202         __drm_atomic_helper_plane_duplicate_state(plane,
1203                                                   &vop_plane_state->base);
1204
1205         return &vop_plane_state->base;
1206 }
1207
1208 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1209                                            struct drm_plane_state *state)
1210 {
1211         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1212
1213         __drm_atomic_helper_plane_destroy_state(plane, state);
1214
1215         kfree(vop_state);
1216 }
1217
1218 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1219                                          struct drm_plane_state *state,
1220                                          struct drm_property *property,
1221                                          uint64_t val)
1222 {
1223         struct vop_win *win = to_vop_win(plane);
1224         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1225
1226         if (property == win->vop->plane_zpos_prop) {
1227                 plane_state->zpos = val;
1228                 return 0;
1229         }
1230
1231         if (property == win->rotation_prop) {
1232                 state->rotation = val;
1233                 return 0;
1234         }
1235
1236         DRM_ERROR("failed to set vop plane property\n");
1237         return -EINVAL;
1238 }
1239
1240 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1241                                          const struct drm_plane_state *state,
1242                                          struct drm_property *property,
1243                                          uint64_t *val)
1244 {
1245         struct vop_win *win = to_vop_win(plane);
1246         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1247
1248         if (property == win->vop->plane_zpos_prop) {
1249                 *val = plane_state->zpos;
1250                 return 0;
1251         }
1252
1253         if (property == win->rotation_prop) {
1254                 *val = state->rotation;
1255                 return 0;
1256         }
1257
1258         DRM_ERROR("failed to get vop plane property\n");
1259         return -EINVAL;
1260 }
1261
1262 static const struct drm_plane_funcs vop_plane_funcs = {
1263         .update_plane   = drm_atomic_helper_update_plane,
1264         .disable_plane  = drm_atomic_helper_disable_plane,
1265         .destroy = vop_plane_destroy,
1266         .reset = vop_atomic_plane_reset,
1267         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1268         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1269         .atomic_set_property = vop_atomic_plane_set_property,
1270         .atomic_get_property = vop_atomic_plane_get_property,
1271 };
1272
1273 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1274 {
1275         struct vop *vop = to_vop(crtc);
1276         unsigned long flags;
1277
1278         if (!vop->is_enabled)
1279                 return -EPERM;
1280
1281         spin_lock_irqsave(&vop->irq_lock, flags);
1282
1283         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1284         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1285
1286         spin_unlock_irqrestore(&vop->irq_lock, flags);
1287
1288         return 0;
1289 }
1290
1291 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1292 {
1293         struct vop *vop = to_vop(crtc);
1294         unsigned long flags;
1295
1296         if (!vop->is_enabled)
1297                 return;
1298
1299         spin_lock_irqsave(&vop->irq_lock, flags);
1300
1301         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1302
1303         spin_unlock_irqrestore(&vop->irq_lock, flags);
1304 }
1305
1306 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1307 {
1308         struct vop *vop = to_vop(crtc);
1309
1310         reinit_completion(&vop->wait_update_complete);
1311         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1312 }
1313
1314 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1315                                            struct drm_file *file_priv)
1316 {
1317         struct drm_device *drm = crtc->dev;
1318         struct vop *vop = to_vop(crtc);
1319         struct drm_pending_vblank_event *e;
1320         unsigned long flags;
1321
1322         spin_lock_irqsave(&drm->event_lock, flags);
1323         e = vop->event;
1324         if (e && e->base.file_priv == file_priv) {
1325                 vop->event = NULL;
1326
1327                 e->base.destroy(&e->base);
1328                 file_priv->event_space += sizeof(e->event);
1329         }
1330         spin_unlock_irqrestore(&drm->event_lock, flags);
1331 }
1332
1333 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1334 {
1335         struct vop *vop = to_vop(crtc);
1336
1337         if (on == vop->loader_protect)
1338                 return 0;
1339
1340         if (on) {
1341                 vop_power_enable(crtc);
1342                 enable_irq(vop->irq);
1343                 drm_crtc_vblank_on(crtc);
1344                 vop->loader_protect = true;
1345         } else {
1346                 vop_crtc_disable(crtc);
1347
1348                 vop->loader_protect = false;
1349         }
1350
1351         return 0;
1352 }
1353
1354 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1355 {
1356         struct vop_win *win = to_vop_win(plane);
1357         struct drm_plane_state *state = plane->state;
1358         struct vop_plane_state *pstate = to_vop_plane_state(state);
1359         struct drm_rect *src, *dest;
1360         struct drm_framebuffer *fb = state->fb;
1361         int i;
1362
1363         seq_printf(s, "    win%d-%d: %s\n", win->win_id, win->area_id,
1364                    pstate->enable ? "ACTIVE" : "DISABLED");
1365         if (!fb)
1366                 return 0;
1367
1368         src = &pstate->src;
1369         dest = &pstate->dest;
1370
1371         seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1372                    fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1373         seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1374         seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1375                    src->y1 >> 16, drm_rect_width(src) >> 16,
1376                    drm_rect_height(src) >> 16);
1377         seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1378                    drm_rect_width(dest), drm_rect_height(dest));
1379
1380         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1381                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1382                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1383                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1390 {
1391         struct vop *vop = to_vop(crtc);
1392         struct drm_crtc_state *crtc_state = crtc->state;
1393         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1394         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1395         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1396         struct drm_plane *plane;
1397         int i;
1398
1399         seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
1400                    crtc_state->active ? "ACTIVE" : "DISABLED");
1401
1402         if (!crtc_state->active)
1403                 return 0;
1404
1405         seq_printf(s, "    Connector: %s\n",
1406                    drm_get_connector_name(state->output_type));
1407         seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
1408                    state->bus_format, state->output_mode);
1409         seq_printf(s, "    Display mode: %dx%d%s%d\n",
1410                    mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1411                    drm_mode_vrefresh(mode));
1412         seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1413                    mode->clock, mode->crtc_clock, mode->type, mode->flags);
1414         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1415                    mode->hsync_end, mode->htotal);
1416         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1417                    mode->vsync_end, mode->vtotal);
1418
1419         for (i = 0; i < vop->num_wins; i++) {
1420                 plane = &vop->win[i].base;
1421                 vop_plane_info_dump(s, plane);
1422         }
1423
1424         return 0;
1425 }
1426
1427 static enum drm_mode_status
1428 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1429                     int output_type)
1430 {
1431         struct vop *vop = to_vop(crtc);
1432         const struct vop_data *vop_data = vop->data;
1433         int request_clock = mode->clock;
1434         int clock;
1435
1436         if (mode->hdisplay > vop_data->max_output.width)
1437                 return MODE_BAD_HVALUE;
1438         if (mode->vdisplay > vop_data->max_output.height)
1439                 return MODE_BAD_VVALUE;
1440
1441         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1442                 request_clock *= 2;
1443         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1444
1445         /*
1446          * Hdmi or DisplayPort request a Accurate clock.
1447          */
1448         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1449             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1450                 if (clock != request_clock)
1451                         return MODE_CLOCK_RANGE;
1452
1453         return MODE_OK;
1454 }
1455
1456 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1457         .loader_protect = vop_crtc_loader_protect,
1458         .enable_vblank = vop_crtc_enable_vblank,
1459         .disable_vblank = vop_crtc_disable_vblank,
1460         .wait_for_update = vop_crtc_wait_for_update,
1461         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1462         .debugfs_dump = vop_crtc_debugfs_dump,
1463         .mode_valid = vop_crtc_mode_valid,
1464 };
1465
1466 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1467                                 const struct drm_display_mode *mode,
1468                                 struct drm_display_mode *adj_mode)
1469 {
1470         struct vop *vop = to_vop(crtc);
1471         const struct vop_data *vop_data = vop->data;
1472
1473         if (mode->hdisplay > vop_data->max_output.width ||
1474             mode->vdisplay > vop_data->max_output.height)
1475                 return false;
1476
1477         drm_mode_set_crtcinfo(adj_mode,
1478                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1479
1480         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1481                 adj_mode->crtc_clock *= 2;
1482
1483         adj_mode->crtc_clock =
1484                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1485
1486         return true;
1487 }
1488
1489 static void vop_crtc_enable(struct drm_crtc *crtc)
1490 {
1491         struct vop *vop = to_vop(crtc);
1492         const struct vop_data *vop_data = vop->data;
1493         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1494         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1495         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1496         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1497         u16 htotal = adjusted_mode->crtc_htotal;
1498         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1499         u16 hact_end = hact_st + hdisplay;
1500         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1501         u16 vtotal = adjusted_mode->crtc_vtotal;
1502         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1503         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1504         u16 vact_end = vact_st + vdisplay;
1505         uint32_t val;
1506
1507         vop_initial(crtc);
1508
1509         val = BIT(DCLK_INVERT);
1510         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1511                    0 : BIT(HSYNC_POSITIVE);
1512         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1513                    0 : BIT(VSYNC_POSITIVE);
1514         VOP_CTRL_SET(vop, pin_pol, val);
1515         switch (s->output_type) {
1516         case DRM_MODE_CONNECTOR_LVDS:
1517                 VOP_CTRL_SET(vop, rgb_en, 1);
1518                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1519                 break;
1520         case DRM_MODE_CONNECTOR_eDP:
1521                 VOP_CTRL_SET(vop, edp_en, 1);
1522                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1523                 break;
1524         case DRM_MODE_CONNECTOR_HDMIA:
1525                 VOP_CTRL_SET(vop, hdmi_en, 1);
1526                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1527                 break;
1528         case DRM_MODE_CONNECTOR_DSI:
1529                 VOP_CTRL_SET(vop, mipi_en, 1);
1530                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1531                 break;
1532         case DRM_MODE_CONNECTOR_DisplayPort:
1533                 val &= ~BIT(DCLK_INVERT);
1534                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1535                 VOP_CTRL_SET(vop, dp_en, 1);
1536                 break;
1537         default:
1538                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1539         }
1540
1541         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1542             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1543                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1544
1545         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1546         switch (s->bus_format) {
1547         case MEDIA_BUS_FMT_RGB565_1X16:
1548                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1549                 break;
1550         case MEDIA_BUS_FMT_RGB666_1X18:
1551         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1552                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1553                 break;
1554         case MEDIA_BUS_FMT_YUV8_1X24:
1555                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1556                 break;
1557         case MEDIA_BUS_FMT_YUV10_1X30:
1558                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1559                 break;
1560         case MEDIA_BUS_FMT_RGB888_1X24:
1561         default:
1562                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1563                 break;
1564         }
1565
1566         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1567                 val |= PRE_DITHER_DOWN_EN(0);
1568         else
1569                 val |= PRE_DITHER_DOWN_EN(1);
1570         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1571         VOP_CTRL_SET(vop, dither_down, val);
1572         VOP_CTRL_SET(vop, dclk_ddr,
1573                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1574         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1575         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1576         VOP_CTRL_SET(vop, dsp_background,
1577                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1578
1579         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1580         val = hact_st << 16;
1581         val |= hact_end;
1582         VOP_CTRL_SET(vop, hact_st_end, val);
1583         VOP_CTRL_SET(vop, hpost_st_end, val);
1584
1585         val = vact_st << 16;
1586         val |= vact_end;
1587         VOP_CTRL_SET(vop, vact_st_end, val);
1588         VOP_CTRL_SET(vop, vpost_st_end, val);
1589         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1590                 u16 vact_st_f1 = vtotal + vact_st + 1;
1591                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1592
1593                 val = vact_st_f1 << 16 | vact_end_f1;
1594                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1595                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1596
1597                 val = vtotal << 16 | (vtotal + vsync_len);
1598                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1599                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1600                 VOP_CTRL_SET(vop, p2i_en, 1);
1601                 vtotal = vtotal + 1;
1602         } else {
1603                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1604                 VOP_CTRL_SET(vop, p2i_en, 0);
1605         }
1606         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1607
1608         VOP_CTRL_SET(vop, core_dclk_div,
1609                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1610
1611         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1612
1613         vop_cfg_done(vop);
1614         /*
1615          * enable vop, all the register would take effect when vop exit standby
1616          */
1617         VOP_CTRL_SET(vop, standby, 0);
1618
1619         enable_irq(vop->irq);
1620         drm_crtc_vblank_on(crtc);
1621 }
1622
1623 static int vop_zpos_cmp(const void *a, const void *b)
1624 {
1625         struct vop_zpos *pa = (struct vop_zpos *)a;
1626         struct vop_zpos *pb = (struct vop_zpos *)b;
1627
1628         return pa->zpos - pb->zpos;
1629 }
1630
1631 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1632                                   struct drm_crtc_state *crtc_state)
1633 {
1634         struct vop *vop = to_vop(crtc);
1635         const struct vop_data *vop_data = vop->data;
1636         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1637         struct drm_atomic_state *state = crtc_state->state;
1638         struct drm_plane *plane;
1639         struct drm_plane_state *pstate;
1640         struct vop_plane_state *plane_state;
1641         struct vop_win *win;
1642         int afbdc_format;
1643         int i;
1644
1645         s->afbdc_en = 0;
1646
1647         for_each_plane_in_state(state, plane, pstate, i) {
1648                 struct drm_framebuffer *fb = pstate->fb;
1649                 struct drm_rect *src;
1650
1651                 win = to_vop_win(plane);
1652                 plane_state = to_vop_plane_state(pstate);
1653
1654                 if (pstate->crtc != crtc || !fb)
1655                         continue;
1656
1657                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1658                         continue;
1659
1660                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1661                         DRM_ERROR("not support afbdc\n");
1662                         return -EINVAL;
1663                 }
1664
1665                 switch (plane_state->format) {
1666                 case VOP_FMT_ARGB8888:
1667                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1668                         break;
1669                 case VOP_FMT_RGB888:
1670                         afbdc_format = AFBDC_FMT_U8U8U8;
1671                         break;
1672                 case VOP_FMT_RGB565:
1673                         afbdc_format = AFBDC_FMT_RGB565;
1674                         break;
1675                 default:
1676                         return -EINVAL;
1677                 }
1678
1679                 if (s->afbdc_en) {
1680                         DRM_ERROR("vop only support one afbc layer\n");
1681                         return -EINVAL;
1682                 }
1683
1684                 src = &plane_state->src;
1685                 if (src->x1 || src->y1 || fb->offsets[0]) {
1686                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1687                                   win->win_id);
1688                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1689                                   src->x1, src->y1, fb->offsets[0]);
1690                         return -EINVAL;
1691                 }
1692                 s->afbdc_win_format = afbdc_format;
1693                 s->afbdc_win_width = pstate->fb->width - 1;
1694                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1695                 s->afbdc_win_id = win->win_id;
1696                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1697                 s->afbdc_en = 1;
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1704                                  struct drm_crtc_state *crtc_state)
1705 {
1706         struct drm_atomic_state *state = crtc_state->state;
1707         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1708         struct vop *vop = to_vop(crtc);
1709         const struct vop_data *vop_data = vop->data;
1710         struct drm_plane *plane;
1711         struct drm_plane_state *pstate;
1712         struct vop_plane_state *plane_state;
1713         struct vop_zpos *pzpos;
1714         int dsp_layer_sel = 0;
1715         int i, j, cnt = 0, ret = 0;
1716
1717         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1718         if (ret)
1719                 return ret;
1720
1721         ret = vop_csc_atomic_check(crtc, crtc_state);
1722         if (ret)
1723                 return ret;
1724
1725         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1726         if (!pzpos)
1727                 return -ENOMEM;
1728
1729         for (i = 0; i < vop_data->win_size; i++) {
1730                 const struct vop_win_data *win_data = &vop_data->win[i];
1731                 struct vop_win *win;
1732
1733                 if (!win_data->phy)
1734                         continue;
1735
1736                 for (j = 0; j < vop->num_wins; j++) {
1737                         win = &vop->win[j];
1738
1739                         if (win->win_id == i && !win->area_id)
1740                                 break;
1741                 }
1742                 if (WARN_ON(j >= vop->num_wins)) {
1743                         ret = -EINVAL;
1744                         goto err_free_pzpos;
1745                 }
1746
1747                 plane = &win->base;
1748                 pstate = state->plane_states[drm_plane_index(plane)];
1749                 /*
1750                  * plane might not have changed, in which case take
1751                  * current state:
1752                  */
1753                 if (!pstate)
1754                         pstate = plane->state;
1755                 plane_state = to_vop_plane_state(pstate);
1756                 pzpos[cnt].zpos = plane_state->zpos;
1757                 pzpos[cnt++].win_id = win->win_id;
1758         }
1759
1760         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1761
1762         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1763                 const struct vop_win_data *win_data = &vop_data->win[i];
1764                 int shift = i * 2;
1765
1766                 if (win_data->phy) {
1767                         struct vop_zpos *zpos = &pzpos[cnt++];
1768
1769                         dsp_layer_sel |= zpos->win_id << shift;
1770                 } else {
1771                         dsp_layer_sel |= i << shift;
1772                 }
1773         }
1774
1775         s->dsp_layer_sel = dsp_layer_sel;
1776
1777 err_free_pzpos:
1778         kfree(pzpos);
1779         return ret;
1780 }
1781
1782 static void vop_post_config(struct drm_crtc *crtc)
1783 {
1784         struct vop *vop = to_vop(crtc);
1785         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1786         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1787         u16 vtotal = mode->crtc_vtotal;
1788         u16 hdisplay = mode->crtc_hdisplay;
1789         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1790         u16 vdisplay = mode->crtc_vdisplay;
1791         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1792         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1793         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1794         u16 hact_end, vact_end;
1795         u32 val;
1796
1797         hact_st += hdisplay * (100 - s->left_margin) / 200;
1798         hact_end = hact_st + hsize;
1799         val = hact_st << 16;
1800         val |= hact_end;
1801         VOP_CTRL_SET(vop, hpost_st_end, val);
1802         vact_st += vdisplay * (100 - s->top_margin) / 200;
1803         vact_end = vact_st + vsize;
1804         val = vact_st << 16;
1805         val |= vact_end;
1806         VOP_CTRL_SET(vop, vpost_st_end, val);
1807         val = scl_cal_scale2(vdisplay, vsize) << 16;
1808         val |= scl_cal_scale2(hdisplay, hsize);
1809         VOP_CTRL_SET(vop, post_scl_factor, val);
1810         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1811         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1812                 u16 vact_st_f1 = vtotal + vact_st + 1;
1813                 u16 vact_end_f1 = vact_st_f1 + vsize;
1814
1815                 val = vact_st_f1 << 16 | vact_end_f1;
1816                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1817         }
1818 }
1819
1820 static void vop_cfg_update(struct drm_crtc *crtc,
1821                            struct drm_crtc_state *old_crtc_state)
1822 {
1823         struct rockchip_crtc_state *s =
1824                         to_rockchip_crtc_state(crtc->state);
1825         struct vop *vop = to_vop(crtc);
1826
1827         spin_lock(&vop->reg_lock);
1828
1829         if (s->afbdc_en) {
1830                 uint32_t pic_size;
1831
1832                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1833                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1834                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1835                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1836                 pic_size = (s->afbdc_win_width & 0xffff);
1837                 pic_size |= s->afbdc_win_height << 16;
1838                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1839         }
1840
1841         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1842         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1843         vop_post_config(crtc);
1844
1845         spin_unlock(&vop->reg_lock);
1846 }
1847
1848 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1849                                   struct drm_crtc_state *old_crtc_state)
1850 {
1851         struct vop *vop = to_vop(crtc);
1852
1853         vop_cfg_update(crtc, old_crtc_state);
1854
1855         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1856                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1857                 int ret;
1858
1859                 if (need_wait_vblank) {
1860                         bool active;
1861
1862                         disable_irq(vop->irq);
1863                         drm_crtc_vblank_get(crtc);
1864                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1865
1866                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1867                                                         vop, active, active,
1868                                                         0, 50 * 1000);
1869                         if (ret)
1870                                 dev_err(vop->dev, "wait fs irq timeout\n");
1871
1872                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1873                         vop_cfg_done(vop);
1874
1875                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1876                                                         vop, active, active,
1877                                                         0, 50 * 1000);
1878                         if (ret)
1879                                 dev_err(vop->dev, "wait line flag timeout\n");
1880
1881                         enable_irq(vop->irq);
1882                 }
1883                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1884                 if (ret)
1885                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1886                                 ret);
1887
1888                 if (need_wait_vblank) {
1889                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1890                         drm_crtc_vblank_put(crtc);
1891                 }
1892
1893                 vop->is_iommu_enabled = true;
1894         }
1895
1896         vop_cfg_done(vop);
1897 }
1898
1899 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1900                                   struct drm_crtc_state *old_crtc_state)
1901 {
1902         struct vop *vop = to_vop(crtc);
1903
1904         if (crtc->state->event) {
1905                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1906
1907                 vop->event = crtc->state->event;
1908                 crtc->state->event = NULL;
1909         }
1910 }
1911
1912 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1913         .enable = vop_crtc_enable,
1914         .disable = vop_crtc_disable,
1915         .mode_fixup = vop_crtc_mode_fixup,
1916         .atomic_check = vop_crtc_atomic_check,
1917         .atomic_flush = vop_crtc_atomic_flush,
1918         .atomic_begin = vop_crtc_atomic_begin,
1919 };
1920
1921 static void vop_crtc_destroy(struct drm_crtc *crtc)
1922 {
1923         drm_crtc_cleanup(crtc);
1924 }
1925
1926 static void vop_crtc_reset(struct drm_crtc *crtc)
1927 {
1928         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1929
1930         if (crtc->state) {
1931                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1932                 kfree(s);
1933         }
1934
1935         s = kzalloc(sizeof(*s), GFP_KERNEL);
1936         if (!s)
1937                 return;
1938         crtc->state = &s->base;
1939         crtc->state->crtc = crtc;
1940         s->left_margin = 100;
1941         s->right_margin = 100;
1942         s->top_margin = 100;
1943         s->bottom_margin = 100;
1944 }
1945
1946 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1947 {
1948         struct rockchip_crtc_state *rockchip_state, *old_state;
1949
1950         old_state = to_rockchip_crtc_state(crtc->state);
1951         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1952         if (!rockchip_state)
1953                 return NULL;
1954
1955         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1956         return &rockchip_state->base;
1957 }
1958
1959 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1960                                    struct drm_crtc_state *state)
1961 {
1962         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1963
1964         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1965         kfree(s);
1966 }
1967
1968 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1969                                         const struct drm_crtc_state *state,
1970                                         struct drm_property *property,
1971                                         uint64_t *val)
1972 {
1973         struct drm_device *drm_dev = crtc->dev;
1974         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1975         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1976
1977         if (property == mode_config->tv_left_margin_property) {
1978                 *val = s->left_margin;
1979                 return 0;
1980         }
1981
1982         if (property == mode_config->tv_right_margin_property) {
1983                 *val = s->right_margin;
1984                 return 0;
1985         }
1986
1987         if (property == mode_config->tv_top_margin_property) {
1988                 *val = s->top_margin;
1989                 return 0;
1990         }
1991
1992         if (property == mode_config->tv_bottom_margin_property) {
1993                 *val = s->bottom_margin;
1994                 return 0;
1995         }
1996
1997         DRM_ERROR("failed to get vop crtc property\n");
1998         return -EINVAL;
1999 }
2000
2001 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2002                                         struct drm_crtc_state *state,
2003                                         struct drm_property *property,
2004                                         uint64_t val)
2005 {
2006         struct drm_device *drm_dev = crtc->dev;
2007         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2008         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2009
2010         if (property == mode_config->tv_left_margin_property) {
2011                 s->left_margin = val;
2012                 return 0;
2013         }
2014
2015         if (property == mode_config->tv_right_margin_property) {
2016                 s->right_margin = val;
2017                 return 0;
2018         }
2019
2020         if (property == mode_config->tv_top_margin_property) {
2021                 s->top_margin = val;
2022                 return 0;
2023         }
2024
2025         if (property == mode_config->tv_bottom_margin_property) {
2026                 s->bottom_margin = val;
2027                 return 0;
2028         }
2029
2030         DRM_ERROR("failed to set vop crtc property\n");
2031         return -EINVAL;
2032 }
2033
2034 static const struct drm_crtc_funcs vop_crtc_funcs = {
2035         .set_config = drm_atomic_helper_set_config,
2036         .page_flip = drm_atomic_helper_page_flip,
2037         .destroy = vop_crtc_destroy,
2038         .reset = vop_crtc_reset,
2039         .atomic_get_property = vop_crtc_atomic_get_property,
2040         .atomic_set_property = vop_crtc_atomic_set_property,
2041         .atomic_duplicate_state = vop_crtc_duplicate_state,
2042         .atomic_destroy_state = vop_crtc_destroy_state,
2043 };
2044
2045 static void vop_handle_vblank(struct vop *vop)
2046 {
2047         struct drm_device *drm = vop->drm_dev;
2048         struct drm_crtc *crtc = &vop->crtc;
2049         unsigned long flags;
2050
2051         if (!vop_is_cfg_done_complete(vop))
2052                 return;
2053
2054         if (vop->event) {
2055                 spin_lock_irqsave(&drm->event_lock, flags);
2056
2057                 drm_crtc_send_vblank_event(crtc, vop->event);
2058                 drm_crtc_vblank_put(crtc);
2059                 vop->event = NULL;
2060
2061                 spin_unlock_irqrestore(&drm->event_lock, flags);
2062         }
2063         if (!completion_done(&vop->wait_update_complete))
2064                 complete(&vop->wait_update_complete);
2065 }
2066
2067 static irqreturn_t vop_isr(int irq, void *data)
2068 {
2069         struct vop *vop = data;
2070         struct drm_crtc *crtc = &vop->crtc;
2071         uint32_t active_irqs;
2072         unsigned long flags;
2073         int ret = IRQ_NONE;
2074
2075         /*
2076          * interrupt register has interrupt status, enable and clear bits, we
2077          * must hold irq_lock to avoid a race with enable/disable_vblank().
2078         */
2079         spin_lock_irqsave(&vop->irq_lock, flags);
2080
2081         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2082         /* Clear all active interrupt sources */
2083         if (active_irqs)
2084                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2085
2086         spin_unlock_irqrestore(&vop->irq_lock, flags);
2087
2088         /* This is expected for vop iommu irqs, since the irq is shared */
2089         if (!active_irqs)
2090                 return IRQ_NONE;
2091
2092         if (active_irqs & DSP_HOLD_VALID_INTR) {
2093                 complete(&vop->dsp_hold_completion);
2094                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2095                 ret = IRQ_HANDLED;
2096         }
2097
2098         if (active_irqs & LINE_FLAG_INTR) {
2099                 complete(&vop->line_flag_completion);
2100                 active_irqs &= ~LINE_FLAG_INTR;
2101                 ret = IRQ_HANDLED;
2102         }
2103
2104         if (active_irqs & FS_INTR) {
2105                 drm_crtc_handle_vblank(crtc);
2106                 vop_handle_vblank(vop);
2107                 active_irqs &= ~FS_INTR;
2108                 ret = IRQ_HANDLED;
2109         }
2110
2111         /* Unhandled irqs are spurious. */
2112         if (active_irqs)
2113                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2114
2115         return ret;
2116 }
2117
2118 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2119                           unsigned long possible_crtcs)
2120 {
2121         struct drm_plane *share = NULL;
2122         unsigned int rotations = 0;
2123         struct drm_property *prop;
2124         uint64_t feature = 0;
2125         int ret;
2126
2127         if (win->parent)
2128                 share = &win->parent->base;
2129
2130         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2131                                    possible_crtcs, &vop_plane_funcs,
2132                                    win->data_formats, win->nformats, win->type);
2133         if (ret) {
2134                 DRM_ERROR("failed to initialize plane\n");
2135                 return ret;
2136         }
2137         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2138         drm_object_attach_property(&win->base.base,
2139                                    vop->plane_zpos_prop, win->win_id);
2140
2141         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2142                 rotations |= BIT(DRM_REFLECT_X);
2143
2144         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2145                 rotations |= BIT(DRM_REFLECT_Y);
2146
2147         if (rotations) {
2148                 rotations |= BIT(DRM_ROTATE_0);
2149                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2150                                                          rotations);
2151                 if (!prop) {
2152                         DRM_ERROR("failed to create zpos property\n");
2153                         return -EINVAL;
2154                 }
2155                 drm_object_attach_property(&win->base.base, prop,
2156                                            BIT(DRM_ROTATE_0));
2157                 win->rotation_prop = prop;
2158         }
2159         if (win->phy->scl)
2160                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2161         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2162             VOP_WIN_SUPPORT(vop, win, alpha_en))
2163                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2164
2165         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2166                                    feature);
2167
2168         return 0;
2169 }
2170
2171 static int vop_create_crtc(struct vop *vop)
2172 {
2173         struct device *dev = vop->dev;
2174         const struct vop_data *vop_data = vop->data;
2175         struct drm_device *drm_dev = vop->drm_dev;
2176         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2177         struct drm_crtc *crtc = &vop->crtc;
2178         struct device_node *port;
2179         uint64_t feature = 0;
2180         int ret;
2181         int i;
2182
2183         /*
2184          * Create drm_plane for primary and cursor planes first, since we need
2185          * to pass them to drm_crtc_init_with_planes, which sets the
2186          * "possible_crtcs" to the newly initialized crtc.
2187          */
2188         for (i = 0; i < vop->num_wins; i++) {
2189                 struct vop_win *win = &vop->win[i];
2190
2191                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2192                     win->type != DRM_PLANE_TYPE_CURSOR)
2193                         continue;
2194
2195                 ret = vop_plane_init(vop, win, 0);
2196                 if (ret)
2197                         goto err_cleanup_planes;
2198
2199                 plane = &win->base;
2200                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2201                         primary = plane;
2202                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2203                         cursor = plane;
2204
2205         }
2206
2207         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2208                                         &vop_crtc_funcs, NULL);
2209         if (ret)
2210                 goto err_cleanup_planes;
2211
2212         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2213
2214         /*
2215          * Create drm_planes for overlay windows with possible_crtcs restricted
2216          * to the newly created crtc.
2217          */
2218         for (i = 0; i < vop->num_wins; i++) {
2219                 struct vop_win *win = &vop->win[i];
2220                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2221
2222                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2223                         continue;
2224
2225                 ret = vop_plane_init(vop, win, possible_crtcs);
2226                 if (ret)
2227                         goto err_cleanup_crtc;
2228         }
2229
2230         port = of_get_child_by_name(dev->of_node, "port");
2231         if (!port) {
2232                 DRM_ERROR("no port node found in %s\n",
2233                           dev->of_node->full_name);
2234                 ret = -ENOENT;
2235                 goto err_cleanup_crtc;
2236         }
2237
2238         init_completion(&vop->dsp_hold_completion);
2239         init_completion(&vop->wait_update_complete);
2240         init_completion(&vop->line_flag_completion);
2241         crtc->port = port;
2242         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2243
2244         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2245         if (ret)
2246                 goto err_unregister_crtc_funcs;
2247 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2248         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2249
2250         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2251         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2252         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2253         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2254 #undef VOP_ATTACH_MODE_CONFIG_PROP
2255
2256         if (vop_data->feature & VOP_FEATURE_AFBDC)
2257                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2258         drm_object_attach_property(&crtc->base, vop->feature_prop,
2259                                    feature);
2260
2261         return 0;
2262
2263 err_unregister_crtc_funcs:
2264         rockchip_unregister_crtc_funcs(crtc);
2265 err_cleanup_crtc:
2266         drm_crtc_cleanup(crtc);
2267 err_cleanup_planes:
2268         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2269                                  head)
2270                 drm_plane_cleanup(plane);
2271         return ret;
2272 }
2273
2274 static void vop_destroy_crtc(struct vop *vop)
2275 {
2276         struct drm_crtc *crtc = &vop->crtc;
2277         struct drm_device *drm_dev = vop->drm_dev;
2278         struct drm_plane *plane, *tmp;
2279
2280         rockchip_unregister_crtc_funcs(crtc);
2281         of_node_put(crtc->port);
2282
2283         /*
2284          * We need to cleanup the planes now.  Why?
2285          *
2286          * The planes are "&vop->win[i].base".  That means the memory is
2287          * all part of the big "struct vop" chunk of memory.  That memory
2288          * was devm allocated and associated with this component.  We need to
2289          * free it ourselves before vop_unbind() finishes.
2290          */
2291         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2292                                  head)
2293                 vop_plane_destroy(plane);
2294
2295         /*
2296          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2297          * references the CRTC.
2298          */
2299         drm_crtc_cleanup(crtc);
2300 }
2301
2302 /*
2303  * Initialize the vop->win array elements.
2304  */
2305 static int vop_win_init(struct vop *vop)
2306 {
2307         const struct vop_data *vop_data = vop->data;
2308         unsigned int i, j;
2309         unsigned int num_wins = 0;
2310         struct drm_property *prop;
2311         static const struct drm_prop_enum_list props[] = {
2312                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2313                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2314         };
2315         static const struct drm_prop_enum_list crtc_props[] = {
2316                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2317         };
2318
2319         for (i = 0; i < vop_data->win_size; i++) {
2320                 struct vop_win *vop_win = &vop->win[num_wins];
2321                 const struct vop_win_data *win_data = &vop_data->win[i];
2322
2323                 if (!win_data->phy)
2324                         continue;
2325
2326                 vop_win->phy = win_data->phy;
2327                 vop_win->csc = win_data->csc;
2328                 vop_win->offset = win_data->base;
2329                 vop_win->type = win_data->type;
2330                 vop_win->data_formats = win_data->phy->data_formats;
2331                 vop_win->nformats = win_data->phy->nformats;
2332                 vop_win->vop = vop;
2333                 vop_win->win_id = i;
2334                 vop_win->area_id = 0;
2335                 num_wins++;
2336
2337                 for (j = 0; j < win_data->area_size; j++) {
2338                         struct vop_win *vop_area = &vop->win[num_wins];
2339                         const struct vop_win_phy *area = win_data->area[j];
2340
2341                         vop_area->parent = vop_win;
2342                         vop_area->offset = vop_win->offset;
2343                         vop_area->phy = area;
2344                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2345                         vop_area->data_formats = vop_win->data_formats;
2346                         vop_area->nformats = vop_win->nformats;
2347                         vop_area->vop = vop;
2348                         vop_area->win_id = i;
2349                         vop_area->area_id = j;
2350                         num_wins++;
2351                 }
2352         }
2353
2354         vop->num_wins = num_wins;
2355
2356         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2357                                          "ZPOS", 0, vop->data->win_size);
2358         if (!prop) {
2359                 DRM_ERROR("failed to create zpos property\n");
2360                 return -EINVAL;
2361         }
2362         vop->plane_zpos_prop = prop;
2363
2364         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2365                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2366                                 props, ARRAY_SIZE(props),
2367                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2368                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2369         if (!vop->plane_feature_prop) {
2370                 DRM_ERROR("failed to create feature property\n");
2371                 return -EINVAL;
2372         }
2373
2374         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2375                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2376                                 crtc_props, ARRAY_SIZE(crtc_props),
2377                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2378         if (!vop->feature_prop) {
2379                 DRM_ERROR("failed to create vop feature property\n");
2380                 return -EINVAL;
2381         }
2382
2383         return 0;
2384 }
2385
2386 /**
2387  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2388  * @crtc: CRTC to enable line flag
2389  * @line_num: interested line number
2390  * @mstimeout: millisecond for timeout
2391  *
2392  * Driver would hold here until the interested line flag interrupt have
2393  * happened or timeout to wait.
2394  *
2395  * Returns:
2396  * Zero on success, negative errno on failure.
2397  */
2398 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2399                                 unsigned int mstimeout)
2400 {
2401         struct vop *vop = to_vop(crtc);
2402         unsigned long jiffies_left;
2403
2404         if (!crtc || !vop->is_enabled)
2405                 return -ENODEV;
2406
2407         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2408                 return -EINVAL;
2409
2410         if (vop_line_flag_irq_is_enabled(vop))
2411                 return -EBUSY;
2412
2413         reinit_completion(&vop->line_flag_completion);
2414         vop_line_flag_irq_enable(vop, line_num);
2415
2416         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2417                                                    msecs_to_jiffies(mstimeout));
2418         vop_line_flag_irq_disable(vop);
2419
2420         if (jiffies_left == 0) {
2421                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2422                 return -ETIMEDOUT;
2423         }
2424
2425         return 0;
2426 }
2427 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2428
2429 static int vop_bind(struct device *dev, struct device *master, void *data)
2430 {
2431         struct platform_device *pdev = to_platform_device(dev);
2432         const struct vop_data *vop_data;
2433         struct drm_device *drm_dev = data;
2434         struct vop *vop;
2435         struct resource *res;
2436         size_t alloc_size;
2437         int ret, irq, i;
2438         int num_wins = 0;
2439
2440         vop_data = of_device_get_match_data(dev);
2441         if (!vop_data)
2442                 return -ENODEV;
2443
2444         for (i = 0; i < vop_data->win_size; i++) {
2445                 const struct vop_win_data *win_data = &vop_data->win[i];
2446
2447                 num_wins += win_data->area_size + 1;
2448         }
2449
2450         /* Allocate vop struct and its vop_win array */
2451         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2452         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2453         if (!vop)
2454                 return -ENOMEM;
2455
2456         vop->dev = dev;
2457         vop->data = vop_data;
2458         vop->drm_dev = drm_dev;
2459         vop->num_wins = num_wins;
2460         dev_set_drvdata(dev, vop);
2461
2462         ret = vop_win_init(vop);
2463         if (ret)
2464                 return ret;
2465
2466         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2467         vop->len = resource_size(res);
2468         vop->regs = devm_ioremap_resource(dev, res);
2469         if (IS_ERR(vop->regs))
2470                 return PTR_ERR(vop->regs);
2471
2472         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2473         if (!vop->regsbak)
2474                 return -ENOMEM;
2475
2476         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2477         if (IS_ERR(vop->hclk)) {
2478                 dev_err(vop->dev, "failed to get hclk source\n");
2479                 return PTR_ERR(vop->hclk);
2480         }
2481         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2482         if (IS_ERR(vop->aclk)) {
2483                 dev_err(vop->dev, "failed to get aclk source\n");
2484                 return PTR_ERR(vop->aclk);
2485         }
2486         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2487         if (IS_ERR(vop->dclk)) {
2488                 dev_err(vop->dev, "failed to get dclk source\n");
2489                 return PTR_ERR(vop->dclk);
2490         }
2491
2492         irq = platform_get_irq(pdev, 0);
2493         if (irq < 0) {
2494                 dev_err(dev, "cannot find irq for vop\n");
2495                 return irq;
2496         }
2497         vop->irq = (unsigned int)irq;
2498
2499         spin_lock_init(&vop->reg_lock);
2500         spin_lock_init(&vop->irq_lock);
2501
2502         mutex_init(&vop->vsync_mutex);
2503
2504         ret = devm_request_irq(dev, vop->irq, vop_isr,
2505                                IRQF_SHARED, dev_name(dev), vop);
2506         if (ret)
2507                 return ret;
2508
2509         /* IRQ is initially disabled; it gets enabled in power_on */
2510         disable_irq(vop->irq);
2511
2512         ret = vop_create_crtc(vop);
2513         if (ret)
2514                 return ret;
2515
2516         pm_runtime_enable(&pdev->dev);
2517         return 0;
2518 }
2519
2520 static void vop_unbind(struct device *dev, struct device *master, void *data)
2521 {
2522         struct vop *vop = dev_get_drvdata(dev);
2523
2524         pm_runtime_disable(dev);
2525         vop_destroy_crtc(vop);
2526 }
2527
2528 const struct component_ops vop_component_ops = {
2529         .bind = vop_bind,
2530         .unbind = vop_unbind,
2531 };
2532 EXPORT_SYMBOL_GPL(vop_component_ops);