drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_of.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_encoder_slave.h>
  21 #include <drm/bridge/dw_hdmi.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define RK3288_GRF_SOC_CON6             0x025C
  27 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  28 #define RK3399_GRF_SOC_CON20            0x6250
  29 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  30
  31 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  32
  33 struct rockchip_hdmi {
  34         struct device *dev;
  35         struct regmap *regmap;
  36         struct drm_encoder encoder;
  37         enum dw_hdmi_devtype dev_type;
  38         struct clk *vpll_clk;
  39         struct clk *grf_clk;
  40 };
  41
  42 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  43
  44 /*
  45  * There are some rates that would be ranged for better clock jitter at
  46  * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
  47  * to the clock is aglined to KHz in struct drm_display_mode, this would
  48  * bring some inaccurate error if we still run the compute_n math, so
  49  * let's just code an const table for it until we can actually get the
  50  * right clock rate.
  51  */
  52 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
  53         /* 25176471 for 25.175 MHz = 428000000 / 17. */
  54         { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
  55         /* 57290323 for 57.284 MHz */
  56         { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
  57         /* 74437500 for 74.44 MHz = 297750000 / 4 */
  58         { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
  59         /* 118666667 for 118.68 MHz */
  60         { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
  61         /* 121714286 for 121.75 MHz */
  62         { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
  63         /* 136800000 for 136.75 MHz */
  64         { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  65         /* End of table */
  66         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
  67 };
  68
  69 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  70         {
  71                 30666000, {
  72                         { 0x00b3, 0x0000 },
  73                         { 0x2153, 0x0000 },
  74                         { 0x40f3, 0x0000 },
  75                 },
  76         },  {
  77                 36800000, {
  78                         { 0x00b3, 0x0000 },
  79                         { 0x2153, 0x0000 },
  80                         { 0x40a2, 0x0001 },
  81                 },
  82         },  {
  83                 46000000, {
  84                         { 0x00b3, 0x0000 },
  85                         { 0x2142, 0x0001 },
  86                         { 0x40a2, 0x0001 },
  87                 },
  88         },  {
  89                 61333000, {
  90                         { 0x0072, 0x0001 },
  91                         { 0x2142, 0x0001 },
  92                         { 0x40a2, 0x0001 },
  93                 },
  94         },  {
  95                 73600000, {
  96                         { 0x0072, 0x0001 },
  97                         { 0x2142, 0x0001 },
  98                         { 0x4061, 0x0002 },
  99                 },
 100         },  {
 101                 92000000, {
 102                         { 0x0072, 0x0001 },
 103                         { 0x2145, 0x0002 },
 104                         { 0x4061, 0x0002 },
 105                 },
 106         },  {
 107                 122666000, {
 108                         { 0x0051, 0x0002 },
 109                         { 0x2145, 0x0002 },
 110                         { 0x4061, 0x0002 },
 111                 },
 112         },  {
 113                 147200000, {
 114                         { 0x0051, 0x0002 },
 115                         { 0x2145, 0x0002 },
 116                         { 0x4064, 0x0003 },
 117                 },
 118         },  {
 119                 184000000, {
 120                         { 0x0051, 0x0002 },
 121                         { 0x214c, 0x0003 },
 122                         { 0x4064, 0x0003 },
 123                 },
 124         },  {
 125                 226666000, {
 126                         { 0x0040, 0x0003 },
 127                         { 0x214c, 0x0003 },
 128                         { 0x4064, 0x0003 },
 129                 },
 130         },  {
 131                 272000000, {
 132                         { 0x0040, 0x0003 },
 133                         { 0x214c, 0x0003 },
 134                         { 0x5a64, 0x0003 },
 135                 },
 136         },  {
 137                 340000000, {
 138                         { 0x0040, 0x0003 },
 139                         { 0x3b4c, 0x0003 },
 140                         { 0x5a64, 0x0003 },
 141                 },
 142         },  {
 143                 600000000, {
 144                         { 0x1a40, 0x0003 },
 145                         { 0x3b4c, 0x0003 },
 146                         { 0x5a64, 0x0003 },
 147                 },
 148         },  {
 149                 ~0UL, {
 150                         { 0x0000, 0x0000 },
 151                         { 0x0000, 0x0000 },
 152                         { 0x0000, 0x0000 },
 153                 },
 154         }
 155 };
 156
 157 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 158         /*      pixelclk    bpp8    bpp10   bpp12 */
 159         {
 160                 600000000, { 0x0000, 0x0000, 0x0000 },
 161         },  {
 162                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 163         }
 164 };
 165
 166 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 167         /*pixelclk   symbol   term   vlev*/
 168         { 74250000,  0x8009, 0x0004, 0x0272},
 169         { 165000000, 0x802b, 0x0004, 0x0209},
 170         { 297000000, 0x8039, 0x0005, 0x028d},
 171         { ~0UL,      0x0000, 0x0000, 0x0000}
 172 };
 173
 174 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 175 {
 176         struct device_node *np = hdmi->dev->of_node;
 177         int ret;
 178
 179         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 180         if (IS_ERR(hdmi->regmap)) {
 181                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 182                 return PTR_ERR(hdmi->regmap);
 183         }
 184
 185         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 186         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 187                 hdmi->vpll_clk = NULL;
 188         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 189                 return -EPROBE_DEFER;
 190         } else if (IS_ERR(hdmi->vpll_clk)) {
 191                 dev_err(hdmi->dev, "failed to get grf clock\n");
 192                 return PTR_ERR(hdmi->vpll_clk);
 193         }
 194
 195         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
 196         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
 197                 hdmi->grf_clk = NULL;
 198         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
 199                 return -EPROBE_DEFER;
 200         } else if (IS_ERR(hdmi->grf_clk)) {
 201                 dev_err(hdmi->dev, "failed to get grf clock\n");
 202                 return PTR_ERR(hdmi->grf_clk);
 203         }
 204
 205         ret = clk_prepare_enable(hdmi->vpll_clk);
 206         if (ret) {
 207                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 208                 return ret;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static enum drm_mode_status
 215 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 216                             struct drm_display_mode *mode)
 217 {
 218         struct drm_encoder *encoder = connector->encoder;
 219         enum drm_mode_status status = MODE_OK;
 220         struct drm_device *dev = connector->dev;
 221         struct rockchip_drm_private *priv = dev->dev_private;
 222         struct drm_crtc *crtc;
 223
 224         /*
 225          * Pixel clocks we support are always < 2GHz and so fit in an
 226          * int.  We should make sure source rate does too so we don't get
 227          * overflow when we multiply by 1000.
 228          */
 229         if (mode->clock > INT_MAX / 1000)
 230                 return MODE_BAD;
 231
 232         if (!encoder) {
 233                 const struct drm_connector_helper_funcs *funcs;
 234
 235                 funcs = connector->helper_private;
 236                 if (funcs->atomic_best_encoder)
 237                         encoder = funcs->atomic_best_encoder(connector,
 238                                                              connector->state);
 239                 else
 240                         encoder = funcs->best_encoder(connector);
 241         }
 242
 243         if (!encoder || !encoder->possible_crtcs)
 244                 return MODE_BAD;
 245         /*
 246          * ensure all drm display mode can work, if someone want support more
 247          * resolutions, please limit the possible_crtc, only connect to
 248          * needed crtc.
 249          */
 250         drm_for_each_crtc(crtc, connector->dev) {
 251                 int pipe = drm_crtc_index(crtc);
 252                 const struct rockchip_crtc_funcs *funcs =
 253                                                 priv->crtc_funcs[pipe];
 254
 255                 if (!(encoder->possible_crtcs & drm_crtc_mask(crtc)))
 256                         continue;
 257                 if (!funcs || !funcs->mode_valid)
 258                         continue;
 259
 260                 status = funcs->mode_valid(crtc, mode,
 261                                            DRM_MODE_CONNECTOR_HDMIA);
 262                 if (status != MODE_OK)
 263                         return status;
 264         }
 265
 266         return status;
 267 }
 268
 269 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 270         .destroy = drm_encoder_cleanup,
 271 };
 272
 273 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 274 {
 275 }
 276
 277 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 278 {
 279         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 280         struct drm_crtc *crtc = encoder->crtc;
 281         u32 lcdsel_grf_reg, lcdsel_mask;
 282         u32 val;
 283         int mux;
 284         int ret;
 285
 286         if (WARN_ON(!crtc || !crtc->state))
 287                 return;
 288
 289         clk_set_rate(hdmi->vpll_clk,
 290                      crtc->state->adjusted_mode.crtc_clock * 1000);
 291
 292         switch (hdmi->dev_type) {
 293         case RK3288_HDMI:
 294                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 295                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 296                 break;
 297         case RK3399_HDMI:
 298                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 299                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 300                 break;
 301         default:
 302                 return;
 303         };
 304
 305         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 306         if (mux)
 307                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 308         else
 309                 val = HIWORD_UPDATE(0, lcdsel_mask);
 310
 311         ret = clk_prepare_enable(hdmi->grf_clk);
 312         if (ret < 0) {
 313                 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
 314                 return;
 315         }
 316
 317         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 318         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 319                 (mux) ? "LIT" : "BIG");
 320
 321         clk_disable_unprepare(hdmi->grf_clk);
 322 }
 323
 324 static int
 325 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 326                                       struct drm_crtc_state *crtc_state,
 327                                       struct drm_connector_state *conn_state)
 328 {
 329         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 330
 331         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 332         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 333         s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 334
 335         return 0;
 336 }
 337
 338 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 339         .enable     = dw_hdmi_rockchip_encoder_enable,
 340         .disable    = dw_hdmi_rockchip_encoder_disable,
 341         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 342 };
 343
 344 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 345         .mode_valid = dw_hdmi_rockchip_mode_valid,
 346         .mpll_cfg   = rockchip_mpll_cfg,
 347         .cur_ctr    = rockchip_cur_ctr,
 348         .phy_config = rockchip_phy_config,
 349         .dev_type   = RK3288_HDMI,
 350         .tmds_n_table = rockchip_werid_tmds_n_table,
 351 };
 352
 353 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 354         .mode_valid = dw_hdmi_rockchip_mode_valid,
 355         .mpll_cfg   = rockchip_mpll_cfg,
 356         .cur_ctr    = rockchip_cur_ctr,
 357         .phy_config = rockchip_phy_config,
 358         .dev_type   = RK3399_HDMI,
 359 };
 360
 361 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 362         { .compatible = "rockchip,rk3288-dw-hdmi",
 363           .data = &rk3288_hdmi_drv_data
 364         },
 365         { .compatible = "rockchip,rk3399-dw-hdmi",
 366           .data = &rk3399_hdmi_drv_data
 367         },
 368         {},
 369 };
 370 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 371
 372 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 373                                  void *data)
 374 {
 375         struct platform_device *pdev = to_platform_device(dev);
 376         const struct dw_hdmi_plat_data *plat_data;
 377         const struct of_device_id *match;
 378         struct drm_device *drm = data;
 379         struct drm_encoder *encoder;
 380         struct rockchip_hdmi *hdmi;
 381         struct resource *iores;
 382         int irq;
 383         int ret;
 384
 385         if (!pdev->dev.of_node)
 386                 return -ENODEV;
 387
 388         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 389         if (!hdmi)
 390                 return -ENOMEM;
 391
 392         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 393         plat_data = match->data;
 394         hdmi->dev = &pdev->dev;
 395         hdmi->dev_type = plat_data->dev_type;
 396         encoder = &hdmi->encoder;
 397
 398         irq = platform_get_irq(pdev, 0);
 399         if (irq < 0)
 400                 return irq;
 401
 402         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 403         if (!iores)
 404                 return -ENXIO;
 405
 406         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 407         /*
 408          * If we failed to find the CRTC(s) which this encoder is
 409          * supposed to be connected to, it's because the CRTC has
 410          * not been registered yet.  Defer probing, and hope that
 411          * the required CRTC is added later.
 412          */
 413         if (encoder->possible_crtcs == 0)
 414                 return -EPROBE_DEFER;
 415
 416         ret = rockchip_hdmi_parse_dt(hdmi);
 417         if (ret) {
 418                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 419                 return ret;
 420         }
 421
 422         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 423         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 424                          DRM_MODE_ENCODER_TMDS, NULL);
 425
 426         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 427
 428         /*
 429          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 430          * which would have called the encoder cleanup.  Do it manually.
 431          */
 432         if (ret)
 433                 drm_encoder_cleanup(encoder);
 434
 435         return ret;
 436 }
 437
 438 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 439                                     void *data)
 440 {
 441         return dw_hdmi_unbind(dev, master, data);
 442 }
 443
 444 static const struct component_ops dw_hdmi_rockchip_ops = {
 445         .bind   = dw_hdmi_rockchip_bind,
 446         .unbind = dw_hdmi_rockchip_unbind,
 447 };
 448
 449 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 450 {
 451         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 452 }
 453
 454 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 455 {
 456         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 457
 458         return 0;
 459 }
 460
 461 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 462         .probe  = dw_hdmi_rockchip_probe,
 463         .remove = dw_hdmi_rockchip_remove,
 464         .driver = {
 465                 .name = "dwhdmi-rockchip",
 466                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 467         },
 468 };
 469
 470 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 471
 472 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 473 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 474 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 475 MODULE_LICENSE("GPL");
 476 MODULE_ALIAS("platform:dwhdmi-rockchip");