drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_crtc.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drmP.h>
  25 #include <video/mipi_display.h>
  26
  27 #include "rockchip_drm_drv.h"
  28 #include "rockchip_drm_vop.h"
  29
  30 #define DRIVER_NAME    "dw-mipi-dsi"
  31
  32 #define RK3288_GRF_SOC_CON6             0x025c
  33 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  34 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  35
  36 #define RK3399_GRF_SOC_CON19            0x6250
  37 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  38 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  39
  40 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  41 #define RK3399_GRF_SOC_CON22            0x6258
  42 #define RK3399_GRF_DSI_MODE             0xffff0000
  43
  44 #define DSI_VERSION                     0x00
  45 #define DSI_PWR_UP                      0x04
  46 #define RESET                           0
  47 #define POWERUP                         BIT(0)
  48
  49 #define DSI_CLKMGR_CFG                  0x08
  50 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  51 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  52
  53 #define DSI_DPI_VCID                    0x0c
  54 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  55
  56 #define DSI_DPI_COLOR_CODING            0x10
  57 #define EN18_LOOSELY                    BIT(8)
  58 #define DPI_COLOR_CODING_16BIT_1        0x0
  59 #define DPI_COLOR_CODING_16BIT_2        0x1
  60 #define DPI_COLOR_CODING_16BIT_3        0x2
  61 #define DPI_COLOR_CODING_18BIT_1        0x3
  62 #define DPI_COLOR_CODING_18BIT_2        0x4
  63 #define DPI_COLOR_CODING_24BIT          0x5
  64
  65 #define DSI_DPI_CFG_POL                 0x14
  66 #define COLORM_ACTIVE_LOW               BIT(4)
  67 #define SHUTD_ACTIVE_LOW                BIT(3)
  68 #define HSYNC_ACTIVE_LOW                BIT(2)
  69 #define VSYNC_ACTIVE_LOW                BIT(1)
  70 #define DATAEN_ACTIVE_LOW               BIT(0)
  71
  72 #define DSI_DPI_LP_CMD_TIM              0x18
  73 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  74 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  75
  76 #define DSI_DBI_CFG                     0x20
  77 #define DSI_DBI_CMDSIZE                 0x28
  78
  79 #define DSI_PCKHDL_CFG                  0x2c
  80 #define EN_CRC_RX                       BIT(4)
  81 #define EN_ECC_RX                       BIT(3)
  82 #define EN_BTA                          BIT(2)
  83 #define EN_EOTP_RX                      BIT(1)
  84 #define EN_EOTP_TX                      BIT(0)
  85
  86 #define DSI_MODE_CFG                    0x34
  87 #define ENABLE_VIDEO_MODE               0
  88 #define ENABLE_CMD_MODE                 BIT(0)
  89
  90 #define DSI_VID_MODE_CFG                0x38
  91 #define FRAME_BTA_ACK                   BIT(14)
  92 #define ENABLE_LOW_POWER                (0x3f << 8)
  93 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  94 #define VID_MODE_TYPE_BURST_SYNC_PULSES         0x2
  95 #define VID_MODE_TYPE_MASK                      0x3
  96
  97 #define DSI_VID_PKT_SIZE                0x3c
  98 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
  99 #define VID_PKT_MAX_SIZE                0x3fff
 100
 101 #define DSI_VID_HSA_TIME                0x48
 102 #define DSI_VID_HBP_TIME                0x4c
 103 #define DSI_VID_HLINE_TIME              0x50
 104 #define DSI_VID_VSA_LINES               0x54
 105 #define DSI_VID_VBP_LINES               0x58
 106 #define DSI_VID_VFP_LINES               0x5c
 107 #define DSI_VID_VACTIVE_LINES           0x60
 108 #define DSI_CMD_MODE_CFG                0x68
 109 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 110 #define DCS_LW_TX_LP                    BIT(19)
 111 #define DCS_SR_0P_TX_LP                 BIT(18)
 112 #define DCS_SW_1P_TX_LP                 BIT(17)
 113 #define DCS_SW_0P_TX_LP                 BIT(16)
 114 #define GEN_LW_TX_LP                    BIT(14)
 115 #define GEN_SR_2P_TX_LP                 BIT(13)
 116 #define GEN_SR_1P_TX_LP                 BIT(12)
 117 #define GEN_SR_0P_TX_LP                 BIT(11)
 118 #define GEN_SW_2P_TX_LP                 BIT(10)
 119 #define GEN_SW_1P_TX_LP                 BIT(9)
 120 #define GEN_SW_0P_TX_LP                 BIT(8)
 121 #define EN_ACK_RQST                     BIT(1)
 122 #define EN_TEAR_FX                      BIT(0)
 123
 124 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 125                                          DCS_LW_TX_LP | \
 126                                          DCS_SR_0P_TX_LP | \
 127                                          DCS_SW_1P_TX_LP | \
 128                                          DCS_SW_0P_TX_LP | \
 129                                          GEN_LW_TX_LP | \
 130                                          GEN_SR_2P_TX_LP | \
 131                                          GEN_SR_1P_TX_LP | \
 132                                          GEN_SR_0P_TX_LP | \
 133                                          GEN_SW_2P_TX_LP | \
 134                                          GEN_SW_1P_TX_LP | \
 135                                          GEN_SW_0P_TX_LP)
 136
 137 #define DSI_GEN_HDR                     0x6c
 138 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 139 #define GEN_HDATA_MASK                  (0xffff << 8)
 140 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 141 #define GEN_HTYPE_MASK                  0xff
 142
 143 #define DSI_GEN_PLD_DATA                0x70
 144
 145 #define DSI_CMD_PKT_STATUS              0x74
 146 #define GEN_CMD_EMPTY                   BIT(0)
 147 #define GEN_CMD_FULL                    BIT(1)
 148 #define GEN_PLD_W_EMPTY                 BIT(2)
 149 #define GEN_PLD_W_FULL                  BIT(3)
 150 #define GEN_PLD_R_EMPTY                 BIT(4)
 151 #define GEN_PLD_R_FULL                  BIT(5)
 152 #define GEN_RD_CMD_BUSY                 BIT(6)
 153
 154 #define DSI_TO_CNT_CFG                  0x78
 155 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 156 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 157
 158 #define DSI_BTA_TO_CNT                  0x8c
 159 #define DSI_LPCLK_CTRL                  0x94
 160 #define AUTO_CLKLANE_CTRL               BIT(1)
 161 #define PHY_TXREQUESTCLKHS              BIT(0)
 162
 163 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 164 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 165 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 166
 167 #define DSI_PHY_TMR_CFG                 0x9c
 168 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 169 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 170 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 171
 172 #define DSI_PHY_RSTZ                    0xa0
 173 #define PHY_DISFORCEPLL                 0
 174 #define PHY_ENFORCEPLL                  BIT(3)
 175 #define PHY_DISABLECLK                  0
 176 #define PHY_ENABLECLK                   BIT(2)
 177 #define PHY_RSTZ                        0
 178 #define PHY_UNRSTZ                      BIT(1)
 179 #define PHY_SHUTDOWNZ                   0
 180 #define PHY_UNSHUTDOWNZ                 BIT(0)
 181
 182 #define DSI_PHY_IF_CFG                  0xa4
 183 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 184 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 185
 186 #define DSI_PHY_STATUS                  0xb0
 187 #define LOCK                            BIT(0)
 188 #define STOP_STATE_CLK_LANE             BIT(2)
 189
 190 #define DSI_PHY_TST_CTRL0               0xb4
 191 #define PHY_TESTCLK                     BIT(1)
 192 #define PHY_UNTESTCLK                   0
 193 #define PHY_TESTCLR                     BIT(0)
 194 #define PHY_UNTESTCLR                   0
 195
 196 #define DSI_PHY_TST_CTRL1               0xb8
 197 #define PHY_TESTEN                      BIT(16)
 198 #define PHY_UNTESTEN                    0
 199 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 200 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 201
 202 #define DSI_INT_ST0                     0xbc
 203 #define DSI_INT_ST1                     0xc0
 204 #define DSI_INT_MSK0                    0xc4
 205 #define DSI_INT_MSK1                    0xc8
 206
 207 #define PHY_STATUS_TIMEOUT_US           10000
 208 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 209
 210 #define BYPASS_VCO_RANGE        BIT(7)
 211 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 212 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 213 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 214 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 215 #define REF_BIAS_CUR_SEL        BIT(0)
 216
 217 #define CP_CURRENT_3MA          BIT(3)
 218 #define CP_PROGRAM_EN           BIT(7)
 219 #define LPF_PROGRAM_EN          BIT(6)
 220 #define LPF_RESISTORS_20_KOHM   0
 221
 222 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 223
 224 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 225 #define LOW_PROGRAM_EN          0
 226 #define HIGH_PROGRAM_EN         BIT(7)
 227 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 228 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 229 #define PLL_LOOP_DIV_EN         BIT(5)
 230 #define PLL_INPUT_DIV_EN        BIT(4)
 231
 232 #define POWER_CONTROL           BIT(6)
 233 #define INTERNAL_REG_CURRENT    BIT(3)
 234 #define BIAS_BLOCK_ON           BIT(2)
 235 #define BANDGAP_ON              BIT(0)
 236
 237 #define TER_RESISTOR_HIGH       BIT(7)
 238 #define TER_RESISTOR_LOW        0
 239 #define LEVEL_SHIFTERS_ON       BIT(6)
 240 #define TER_CAL_DONE            BIT(5)
 241 #define SETRD_MAX               (0x7 << 2)
 242 #define POWER_MANAGE            BIT(1)
 243 #define TER_RESISTORS_ON        BIT(0)
 244
 245 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 246 #define BANDGAP_SEL(val)        ((val) & 0x7)
 247 #define TLP_PROGRAM_EN          BIT(7)
 248 #define THS_PRE_PROGRAM_EN      BIT(7)
 249 #define THS_ZERO_PROGRAM_EN     BIT(6)
 250
 251 enum {
 252         BANDGAP_97_07,
 253         BANDGAP_98_05,
 254         BANDGAP_99_02,
 255         BANDGAP_100_00,
 256         BANDGAP_93_17,
 257         BANDGAP_94_15,
 258         BANDGAP_95_12,
 259         BANDGAP_96_10,
 260 };
 261
 262 enum {
 263         BIASEXTR_87_1,
 264         BIASEXTR_91_5,
 265         BIASEXTR_95_9,
 266         BIASEXTR_100,
 267         BIASEXTR_105_94,
 268         BIASEXTR_111_88,
 269         BIASEXTR_118_8,
 270         BIASEXTR_127_7,
 271 };
 272
 273 struct dw_mipi_dsi_plat_data {
 274         u32 dsi0_en_bit;
 275         u32 dsi1_en_bit;
 276         u32 grf_switch_reg;
 277         u32 grf_dsi0_mode;
 278         u32 grf_dsi0_mode_reg;
 279         unsigned int max_data_lanes;
 280         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 281                                            struct drm_display_mode *mode);
 282 };
 283
 284 struct dw_mipi_dsi {
 285         struct drm_encoder encoder;
 286         struct drm_connector connector;
 287         struct mipi_dsi_host dsi_host;
 288         struct drm_panel *panel;
 289         struct device *dev;
 290         struct regmap *grf_regmap;
 291         void __iomem *base;
 292
 293         struct clk *pllref_clk;
 294         struct clk *pclk;
 295         struct clk *phy_cfg_clk;
 296
 297         int dpms_mode;
 298         unsigned int lane_mbps; /* per lane */
 299         u32 channel;
 300         u32 lanes;
 301         u32 format;
 302         u16 input_div;
 303         u16 feedback_div;
 304         struct drm_display_mode *mode;
 305
 306         const struct dw_mipi_dsi_plat_data *pdata;
 307 };
 308
 309 enum dw_mipi_dsi_mode {
 310         DW_MIPI_DSI_CMD_MODE,
 311         DW_MIPI_DSI_VID_MODE,
 312 };
 313
 314 struct dphy_pll_testdin_map {
 315         unsigned int max_mbps;
 316         u8 testdin;
 317 };
 318
 319 /* The table is based on 27MHz DPHY pll reference clock. */
 320 static const struct dphy_pll_testdin_map dptdin_map[] = {
 321         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 322         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 323         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 324         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 325         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 326         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 327         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 328         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 329         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 330         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 331 };
 332
 333 static int max_mbps_to_testdin(unsigned int max_mbps)
 334 {
 335         int i;
 336
 337         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 338                 if (dptdin_map[i].max_mbps > max_mbps)
 339                         return dptdin_map[i].testdin;
 340
 341         return -EINVAL;
 342 }
 343
 344 /*
 345  * The controller should generate 2 frames before
 346  * preparing the peripheral.
 347  */
 348 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 349 {
 350         int refresh, two_frames;
 351
 352         refresh = drm_mode_vrefresh(dsi->mode);
 353         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 354         msleep(two_frames);
 355 }
 356
 357 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 358 {
 359         return container_of(host, struct dw_mipi_dsi, dsi_host);
 360 }
 361
 362 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 363 {
 364         return container_of(con, struct dw_mipi_dsi, connector);
 365 }
 366
 367 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 368 {
 369         return container_of(encoder, struct dw_mipi_dsi, encoder);
 370 }
 371 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 372 {
 373         writel(val, dsi->base + reg);
 374 }
 375
 376 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 377 {
 378         return readl(dsi->base + reg);
 379 }
 380
 381 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 382                                  u8 test_data)
 383 {
 384         /*
 385          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 386          * is latched internally as the current test code. Test data is
 387          * programmed internally by rising edge on TESTCLK.
 388          */
 389         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 390
 391         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 392                                           PHY_TESTDIN(test_code));
 393
 394         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 395
 396         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 397                                           PHY_TESTDIN(test_data));
 398
 399         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 400 }
 401
 402 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 403 {
 404         int ret, testdin, vco, val;
 405
 406         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 407
 408         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 409         if (testdin < 0) {
 410                 dev_err(dsi->dev,
 411                         "failed to get testdin for %dmbps lane clock\n",
 412                         dsi->lane_mbps);
 413                 return testdin;
 414         }
 415
 416         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 417
 418         if (!IS_ERR(dsi->phy_cfg_clk)) {
 419                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 420                 if (ret) {
 421                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 422                         return ret;
 423                 }
 424         }
 425
 426         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 427                                          VCO_RANGE_CON_SEL(vco) |
 428                                          VCO_IN_CAP_CON_LOW |
 429                                          REF_BIAS_CUR_SEL);
 430
 431         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 432         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 433                                          LPF_RESISTORS_20_KOHM);
 434
 435         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 436
 437         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 438         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 439         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 440                                          LOW_PROGRAM_EN);
 441         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 442                                          HIGH_PROGRAM_EN);
 443
 444         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 445                                          BIAS_BLOCK_ON | BANDGAP_ON);
 446
 447         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 448                                          SETRD_MAX | TER_RESISTORS_ON);
 449         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 450                                          SETRD_MAX | POWER_MANAGE |
 451                                          TER_RESISTORS_ON);
 452
 453         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 454                                          BIASEXTR_SEL(BIASEXTR_127_7));
 455         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 456                                          BANDGAP_SEL(BANDGAP_96_10));
 457
 458         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 459         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
 460         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 461
 462         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 463                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 464
 465
 466         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 467                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 468         if (ret < 0) {
 469                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 470                 goto phy_init_end;
 471         }
 472
 473         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 474                                  val, val & STOP_STATE_CLK_LANE, 1000,
 475                                  PHY_STATUS_TIMEOUT_US);
 476         if (ret < 0)
 477                 dev_err(dsi->dev,
 478                         "failed to wait for phy clk lane stop state\n");
 479
 480 phy_init_end:
 481         if (!IS_ERR(dsi->phy_cfg_clk))
 482                 clk_disable_unprepare(dsi->phy_cfg_clk);
 483
 484         return ret;
 485 }
 486
 487 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 488 {
 489         unsigned int i, pre;
 490         unsigned long mpclk, pllref, tmp;
 491         unsigned int m = 1, n = 1, target_mbps = 1000;
 492         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 493         int bpp;
 494
 495         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 496         if (bpp < 0) {
 497                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 498                         dsi->format);
 499                 return bpp;
 500         }
 501
 502         mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
 503         if (mpclk) {
 504                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 505                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 506                 if (tmp < max_mbps)
 507                         target_mbps = tmp;
 508                 else
 509                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 510         }
 511
 512         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 513         tmp = pllref;
 514
 515         for (i = 1; i < 6; i++) {
 516                 pre = pllref / i;
 517                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 518                         tmp = target_mbps % pre;
 519                         n = i;
 520                         m = target_mbps / pre;
 521                 }
 522                 if (tmp == 0)
 523                         break;
 524         }
 525
 526         dsi->lane_mbps = pllref / n * m;
 527         dsi->input_div = n;
 528         dsi->feedback_div = m;
 529
 530         return 0;
 531 }
 532
 533 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 534                                    struct mipi_dsi_device *device)
 535 {
 536         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 537
 538         if (device->lanes > dsi->pdata->max_data_lanes) {
 539                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 540                                 device->lanes);
 541                 return -EINVAL;
 542         }
 543
 544         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
 545             !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
 546                 dev_err(dsi->dev, "device mode is unsupported\n");
 547                 return -EINVAL;
 548         }
 549
 550         dsi->lanes = device->lanes;
 551         dsi->channel = device->channel;
 552         dsi->format = device->format;
 553         dsi->panel = of_drm_find_panel(device->dev.of_node);
 554         if (!dsi->panel) {
 555                 DRM_ERROR("failed to find panel\n");
 556                 return -EPROBE_DEFER;
 557         }
 558
 559         drm_panel_attach(dsi->panel, &dsi->connector);
 560
 561         return 0;
 562 }
 563
 564 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 565                                    struct mipi_dsi_device *device)
 566 {
 567         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 568
 569         if (dsi->panel)
 570                 drm_panel_detach(dsi->panel);
 571
 572         return 0;
 573 }
 574
 575 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 576 {
 577         int ret;
 578
 579         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 580                                  val, !(val & GEN_CMD_FULL), 1000,
 581                                  CMD_PKT_STATUS_TIMEOUT_US);
 582         if (ret < 0) {
 583                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 584                 return ret;
 585         }
 586
 587         dsi_write(dsi, DSI_GEN_HDR, val);
 588
 589         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 590                                  val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 591                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 592         if (ret < 0) {
 593                 dev_err(dsi->dev, "failed to write command FIFO\n");
 594                 return ret;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
 601                                        const struct mipi_dsi_msg *msg)
 602 {
 603         const u16 *tx_buf = msg->tx_buf;
 604         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 605
 606         if (msg->tx_len > 2) {
 607                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 608                         msg->tx_len);
 609                 return -EINVAL;
 610         }
 611
 612         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 613 }
 614
 615 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 616                                       const struct mipi_dsi_msg *msg)
 617 {
 618         const u32 *tx_buf = msg->tx_buf;
 619         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 620         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 621         u32 remainder = 0;
 622
 623         if (msg->tx_len < 3) {
 624                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 625                         msg->tx_len);
 626                 return -EINVAL;
 627         }
 628
 629         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 630                 if (len < pld_data_bytes) {
 631                         memcpy(&remainder, tx_buf, len);
 632                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 633                         len = 0;
 634                 } else {
 635                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 636                         tx_buf++;
 637                         len -= pld_data_bytes;
 638                 }
 639
 640                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 641                                          val, !(val & GEN_PLD_W_FULL), 1000,
 642                                          CMD_PKT_STATUS_TIMEOUT_US);
 643                 if (ret < 0) {
 644                         dev_err(dsi->dev,
 645                                 "failed to get available write payload FIFO\n");
 646                         return ret;
 647                 }
 648         }
 649
 650         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 651 }
 652
 653 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 654                                          const struct mipi_dsi_msg *msg)
 655 {
 656         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 657         int ret;
 658
 659         switch (msg->type) {
 660         case MIPI_DSI_DCS_SHORT_WRITE:
 661         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 662         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 663                 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
 664                 break;
 665         case MIPI_DSI_DCS_LONG_WRITE:
 666                 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
 667                 break;
 668         default:
 669                 dev_err(dsi->dev, "unsupported message type\n");
 670                 ret = -EINVAL;
 671         }
 672
 673         return ret;
 674 }
 675
 676 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 677         .attach = dw_mipi_dsi_host_attach,
 678         .detach = dw_mipi_dsi_host_detach,
 679         .transfer = dw_mipi_dsi_host_transfer,
 680 };
 681
 682 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 683 {
 684         u32 val;
 685
 686         val = VID_MODE_TYPE_BURST_SYNC_PULSES | ENABLE_LOW_POWER;
 687
 688         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 689 }
 690
 691 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 692                                  enum dw_mipi_dsi_mode mode)
 693 {
 694         if (mode == DW_MIPI_DSI_CMD_MODE) {
 695                 dsi_write(dsi, DSI_PWR_UP, RESET);
 696                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 697                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 698         } else {
 699                 dsi_write(dsi, DSI_PWR_UP, RESET);
 700                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 701                 dw_mipi_dsi_video_mode_config(dsi);
 702                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 703         }
 704 }
 705
 706 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 707 {
 708         dsi_write(dsi, DSI_PWR_UP, RESET);
 709         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 710 }
 711
 712 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 713 {
 714         dsi_write(dsi, DSI_PWR_UP, RESET);
 715         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 716                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 717         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 718                   TX_ESC_CLK_DIVIDSION(7));
 719         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 720 }
 721
 722 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 723                                    struct drm_display_mode *mode)
 724 {
 725         u32 val = 0, color = 0;
 726
 727         switch (dsi->format) {
 728         case MIPI_DSI_FMT_RGB888:
 729                 color = DPI_COLOR_CODING_24BIT;
 730                 break;
 731         case MIPI_DSI_FMT_RGB666:
 732                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 733                 break;
 734         case MIPI_DSI_FMT_RGB666_PACKED:
 735                 color = DPI_COLOR_CODING_18BIT_1;
 736                 break;
 737         case MIPI_DSI_FMT_RGB565:
 738                 color = DPI_COLOR_CODING_16BIT_1;
 739                 break;
 740         }
 741
 742         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 743                 val |= VSYNC_ACTIVE_LOW;
 744         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 745                 val |= HSYNC_ACTIVE_LOW;
 746
 747         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 748         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 749         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 750         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 751                   | INVACT_LPCMD_TIME(4));
 752 }
 753
 754 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 755 {
 756         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 757 }
 758
 759 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 760                                             struct drm_display_mode *mode)
 761 {
 762         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 763 }
 764
 765 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 766 {
 767         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 768         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 769         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 770         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 771 }
 772
 773 /* Get lane byte clock cycles. */
 774 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 775                                            u32 hcomponent)
 776 {
 777         u32 frac, lbcc;
 778
 779         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 780
 781         frac = lbcc % dsi->mode->clock;
 782         lbcc = lbcc / dsi->mode->clock;
 783         if (frac)
 784                 lbcc++;
 785
 786         return lbcc;
 787 }
 788
 789 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 790 {
 791         u32 htotal, hsa, hbp, lbcc;
 792         struct drm_display_mode *mode = dsi->mode;
 793
 794         htotal = mode->htotal;
 795         hsa = mode->hsync_end - mode->hsync_start;
 796         hbp = mode->htotal - mode->hsync_end;
 797
 798         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 799         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 800
 801         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 802         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 803
 804         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 805         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 806 }
 807
 808 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 809 {
 810         u32 vactive, vsa, vfp, vbp;
 811         struct drm_display_mode *mode = dsi->mode;
 812
 813         vactive = mode->vdisplay;
 814         vsa = mode->vsync_end - mode->vsync_start;
 815         vfp = mode->vsync_start - mode->vdisplay;
 816         vbp = mode->vtotal - mode->vsync_end;
 817
 818         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 819         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 820         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 821         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 822 }
 823
 824 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 825 {
 826         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 827                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 828
 829         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 830                   | PHY_CLKLP2HS_TIME(0x40));
 831 }
 832
 833 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 834 {
 835         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 836                   N_LANES(dsi->lanes));
 837 }
 838
 839 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 840 {
 841         dsi_read(dsi, DSI_INT_ST0);
 842         dsi_read(dsi, DSI_INT_ST1);
 843         dsi_write(dsi, DSI_INT_MSK0, 0);
 844         dsi_write(dsi, DSI_INT_MSK1, 0);
 845 }
 846
 847 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 848                                         struct drm_display_mode *mode,
 849                                         struct drm_display_mode *adjusted_mode)
 850 {
 851         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 852         int ret;
 853
 854         if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
 855                 return;
 856
 857         dsi->mode = adjusted_mode;
 858
 859         ret = dw_mipi_dsi_get_lane_bps(dsi);
 860         if (ret < 0)
 861                 return;
 862
 863         if (clk_prepare_enable(dsi->pclk)) {
 864                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 865                 return;
 866         }
 867
 868         pm_runtime_get_sync(dsi->dev);
 869
 870         dw_mipi_dsi_init(dsi);
 871         dw_mipi_dsi_dpi_config(dsi, mode);
 872         dw_mipi_dsi_packet_handler_config(dsi);
 873         dw_mipi_dsi_video_mode_config(dsi);
 874         dw_mipi_dsi_video_packet_config(dsi, mode);
 875         dw_mipi_dsi_command_mode_config(dsi);
 876         dw_mipi_dsi_line_timer_config(dsi);
 877         dw_mipi_dsi_vertical_timing_config(dsi);
 878         dw_mipi_dsi_dphy_timing_config(dsi);
 879         dw_mipi_dsi_dphy_interface_config(dsi);
 880         dw_mipi_dsi_clear_err(dsi);
 881         if (drm_panel_prepare(dsi->panel))
 882                 dev_err(dsi->dev, "failed to prepare panel\n");
 883
 884         clk_disable_unprepare(dsi->pclk);
 885 }
 886
 887 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 888 {
 889         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 890
 891         if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
 892                 return;
 893
 894         drm_panel_disable(dsi->panel);
 895
 896         if (clk_prepare_enable(dsi->pclk)) {
 897                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 898                 return;
 899         }
 900
 901         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 902         drm_panel_unprepare(dsi->panel);
 903         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 904
 905         /*
 906          * This is necessary to make sure the peripheral will be driven
 907          * normally when the display is enabled again later.
 908          */
 909         msleep(120);
 910
 911         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 912         dw_mipi_dsi_disable(dsi);
 913         pm_runtime_put(dsi->dev);
 914         clk_disable_unprepare(dsi->pclk);
 915         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
 916 }
 917
 918 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 919                                         const struct drm_display_mode *mode,
 920                                         struct drm_display_mode *adjusted_mode)
 921 {
 922         return true;
 923 }
 924
 925 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
 926 {
 927         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 928         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 929         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 930         u32 val;
 931
 932         if (clk_prepare_enable(dsi->pclk)) {
 933                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 934                 return;
 935         }
 936
 937         if (pdata->grf_dsi0_mode_reg)
 938                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 939                              pdata->grf_dsi0_mode);
 940
 941         dw_mipi_dsi_phy_init(dsi);
 942         dw_mipi_dsi_wait_for_two_frames(dsi);
 943
 944         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 945         drm_panel_enable(dsi->panel);
 946
 947         clk_disable_unprepare(dsi->pclk);
 948
 949         if (mux)
 950                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 951         else
 952                 val = pdata->dsi0_en_bit << 16;
 953
 954         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 955         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 956         dsi->dpms_mode = DRM_MODE_DPMS_ON;
 957 }
 958
 959 static int
 960 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 961                                  struct drm_crtc_state *crtc_state,
 962                                  struct drm_connector_state *conn_state)
 963 {
 964         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 965         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 966
 967         switch (dsi->format) {
 968         case MIPI_DSI_FMT_RGB888:
 969                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 970                 break;
 971         case MIPI_DSI_FMT_RGB666:
 972                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 973                 break;
 974         case MIPI_DSI_FMT_RGB565:
 975                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 976                 break;
 977         default:
 978                 WARN_ON(1);
 979                 return -EINVAL;
 980         }
 981
 982         s->output_type = DRM_MODE_CONNECTOR_DSI;
 983
 984         return 0;
 985 }
 986
 987 static struct drm_encoder_helper_funcs
 988 dw_mipi_dsi_encoder_helper_funcs = {
 989         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
 990         .commit = dw_mipi_dsi_encoder_commit,
 991         .mode_set = dw_mipi_dsi_encoder_mode_set,
 992         .disable = dw_mipi_dsi_encoder_disable,
 993         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 994 };
 995
 996 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 997         .destroy = drm_encoder_cleanup,
 998 };
 999
1000 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1001 {
1002         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1003
1004         return drm_panel_get_modes(dsi->panel);
1005 }
1006
1007 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1008                                         struct drm_connector *connector,
1009                                         struct drm_display_mode *mode)
1010 {
1011         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1012
1013         enum drm_mode_status mode_status = MODE_OK;
1014
1015         if (dsi->pdata->mode_valid)
1016                 mode_status = dsi->pdata->mode_valid(connector, mode);
1017
1018         return mode_status;
1019 }
1020
1021 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1022                                         struct drm_connector *connector)
1023 {
1024         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1025
1026         return &dsi->encoder;
1027 }
1028
1029 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1030         .get_modes = dw_mipi_dsi_connector_get_modes,
1031         .mode_valid = dw_mipi_dsi_mode_valid,
1032         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1033 };
1034
1035 static enum drm_connector_status
1036 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1037 {
1038         return connector_status_connected;
1039 }
1040
1041 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1042 {
1043         drm_connector_unregister(connector);
1044         drm_connector_cleanup(connector);
1045 }
1046
1047 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1048         .dpms = drm_atomic_helper_connector_dpms,
1049         .fill_modes = drm_helper_probe_single_connector_modes,
1050         .detect = dw_mipi_dsi_detect,
1051         .destroy = dw_mipi_dsi_drm_connector_destroy,
1052         .reset = drm_atomic_helper_connector_reset,
1053         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1054         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1055 };
1056
1057 static int dw_mipi_dsi_register(struct drm_device *drm,
1058                                       struct dw_mipi_dsi *dsi)
1059 {
1060         struct drm_encoder *encoder = &dsi->encoder;
1061         struct drm_connector *connector = &dsi->connector;
1062         struct device *dev = dsi->dev;
1063         int ret;
1064
1065         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1066                                                              dev->of_node);
1067         /*
1068          * If we failed to find the CRTC(s) which this encoder is
1069          * supposed to be connected to, it's because the CRTC has
1070          * not been registered yet.  Defer probing, and hope that
1071          * the required CRTC is added later.
1072          */
1073         if (encoder->possible_crtcs == 0)
1074                 return -EPROBE_DEFER;
1075
1076         drm_encoder_helper_add(&dsi->encoder,
1077                                &dw_mipi_dsi_encoder_helper_funcs);
1078         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1079                          DRM_MODE_ENCODER_DSI, NULL);
1080         if (ret) {
1081                 dev_err(dev, "Failed to initialize encoder with drm\n");
1082                 return ret;
1083         }
1084
1085         drm_connector_helper_add(connector,
1086                         &dw_mipi_dsi_connector_helper_funcs);
1087
1088         drm_connector_init(drm, &dsi->connector,
1089                            &dw_mipi_dsi_atomic_connector_funcs,
1090                            DRM_MODE_CONNECTOR_DSI);
1091
1092         drm_mode_connector_attach_encoder(connector, encoder);
1093
1094         return 0;
1095 }
1096
1097 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1098 {
1099         struct device_node *np = dsi->dev->of_node;
1100
1101         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1102         if (IS_ERR(dsi->grf_regmap)) {
1103                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1104                 return PTR_ERR(dsi->grf_regmap);
1105         }
1106
1107         return 0;
1108 }
1109
1110 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1111         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1112         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1113         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1114         .max_data_lanes = 4,
1115 };
1116
1117 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1118         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1119         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1120         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1121         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1122         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1123         .max_data_lanes = 4,
1124 };
1125
1126 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1127         {
1128          .compatible = "rockchip,rk3288-mipi-dsi",
1129          .data = &rk3288_mipi_dsi_drv_data,
1130         },{
1131          .compatible = "rockchip,rk3399-mipi-dsi",
1132          .data = &rk3399_mipi_dsi_drv_data,
1133         },
1134         { /* sentinel */ }
1135 };
1136 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1137
1138 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1139                              void *data)
1140 {
1141         const struct of_device_id *of_id =
1142                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1143         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1144         struct platform_device *pdev = to_platform_device(dev);
1145         struct drm_device *drm = data;
1146         struct dw_mipi_dsi *dsi;
1147         struct resource *res;
1148         int ret;
1149
1150         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1151         if (!dsi)
1152                 return -ENOMEM;
1153
1154         dsi->dev = dev;
1155         dsi->pdata = pdata;
1156         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1157
1158         ret = rockchip_mipi_parse_dt(dsi);
1159         if (ret)
1160                 return ret;
1161
1162         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1163         if (!res)
1164                 return -ENODEV;
1165
1166         dsi->base = devm_ioremap_resource(dev, res);
1167         if (IS_ERR(dsi->base))
1168                 return PTR_ERR(dsi->base);
1169
1170         dsi->pllref_clk = devm_clk_get(dev, "ref");
1171         if (IS_ERR(dsi->pllref_clk)) {
1172                 ret = PTR_ERR(dsi->pllref_clk);
1173                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1174                 return ret;
1175         }
1176
1177         dsi->pclk = devm_clk_get(dev, "pclk");
1178         if (IS_ERR(dsi->pclk)) {
1179                 ret = PTR_ERR(dsi->pclk);
1180                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1181                 return ret;
1182         }
1183
1184         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1185         if (IS_ERR(dsi->phy_cfg_clk))
1186                 dev_dbg(dev, "have not phy_cfg_clk\n");
1187
1188         ret = clk_prepare_enable(dsi->pllref_clk);
1189         if (ret) {
1190                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1191                 return ret;
1192         }
1193
1194         ret = dw_mipi_dsi_register(drm, dsi);
1195         if (ret) {
1196                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1197                 goto err_pllref;
1198         }
1199
1200         dev_set_drvdata(dev, dsi);
1201
1202         pm_runtime_enable(dev);
1203
1204         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1205         dsi->dsi_host.dev = dev;
1206         return mipi_dsi_host_register(&dsi->dsi_host);
1207
1208 err_pllref:
1209         clk_disable_unprepare(dsi->pllref_clk);
1210         return ret;
1211 }
1212
1213 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1214         void *data)
1215 {
1216         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1217
1218         mipi_dsi_host_unregister(&dsi->dsi_host);
1219         pm_runtime_disable(dev);
1220         clk_disable_unprepare(dsi->pllref_clk);
1221 }
1222
1223 static const struct component_ops dw_mipi_dsi_ops = {
1224         .bind   = dw_mipi_dsi_bind,
1225         .unbind = dw_mipi_dsi_unbind,
1226 };
1227
1228 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1229 {
1230         return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1231 }
1232
1233 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1234 {
1235         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1236         return 0;
1237 }
1238
1239 static struct platform_driver dw_mipi_dsi_driver = {
1240         .probe          = dw_mipi_dsi_probe,
1241         .remove         = dw_mipi_dsi_remove,
1242         .driver         = {
1243                 .of_match_table = dw_mipi_dsi_dt_ids,
1244                 .name   = DRIVER_NAME,
1245         },
1246 };
1247 module_platform_driver(dw_mipi_dsi_driver);
1248
1249 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1250 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1251 MODULE_LICENSE("GPL");
1252 MODULE_ALIAS("platform:" DRIVER_NAME);