drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/mipi_display.h>
  38 #include <video/of_display_timing.h>
  39 #include <video/videomode.h>
  40
  41 struct dsi_ctrl_hdr {
  42         u8 dtype;       /* data type */
  43         u8 wait;        /* ms */
  44         u16 dlen;       /* payload len */
  45 } __packed;
  46
  47 struct dsi_cmd_desc {
  48         struct dsi_ctrl_hdr dchdr;
  49         u8 *payload;
  50 };
  51
  52 struct dsi_panel_cmds {
  53         u8 *buf;
  54         int blen;
  55         struct dsi_cmd_desc *cmds;
  56         int cmd_cnt;
  57 };
  58
  59 struct panel_desc {
  60         const struct drm_display_mode *modes;
  61         unsigned int num_modes;
  62         const struct display_timing *timings;
  63         unsigned int num_timings;
  64
  65         unsigned int bpc;
  66
  67         struct {
  68                 unsigned int width;
  69                 unsigned int height;
  70         } size;
  71
  72         /**
  73          * @prepare: the time (in milliseconds) that it takes for the panel to
  74          *           become ready and start receiving video data
  75          * @enable: the time (in milliseconds) that it takes for the panel to
  76          *          display the first valid frame after starting to receive
  77          *          video data
  78          * @disable: the time (in milliseconds) that it takes for the panel to
  79          *           turn the display off (no content is visible)
  80          * @unprepare: the time (in milliseconds) that it takes for the panel
  81          *             to power itself down completely
  82          */
  83         struct {
  84                 unsigned int prepare;
  85                 unsigned int enable;
  86                 unsigned int disable;
  87                 unsigned int unprepare;
  88         } delay;
  89
  90         u32 bus_format;
  91 };
  92
  93 struct panel_simple {
  94         struct drm_panel base;
  95         struct mipi_dsi_device *dsi;
  96         bool prepared;
  97         bool enabled;
  98
  99         struct device *dev;
 100         const struct panel_desc *desc;
 101
 102         struct backlight_device *backlight;
 103         struct regulator *supply;
 104         struct i2c_adapter *ddc;
 105
 106         struct gpio_desc *enable_gpio;
 107         struct gpio_desc *reset_gpio;
 108         unsigned int reset_delay;
 109
 110         struct dsi_panel_cmds *on_cmds;
 111         struct dsi_panel_cmds *off_cmds;
 112 };
 113
 114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 115 {
 116         return container_of(panel, struct panel_simple, base);
 117 }
 118
 119 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
 120 {
 121         if (p->on_cmds) {
 122                 kfree(p->on_cmds->buf);
 123                 kfree(p->on_cmds->cmds);
 124         }
 125
 126         if (p->off_cmds) {
 127                 kfree(p->off_cmds->buf);
 128                 kfree(p->off_cmds->cmds);
 129         }
 130 }
 131
 132 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
 133                                            const u8 *data, int blen,
 134                                            struct dsi_panel_cmds *pcmds)
 135 {
 136         int len;
 137         char *buf, *bp;
 138         struct dsi_ctrl_hdr *dchdr;
 139         int i, cnt;
 140
 141         if (!pcmds)
 142                 return -EINVAL;
 143
 144         buf = kmemdup(data, blen, GFP_KERNEL);
 145         if (!buf)
 146                 return -ENOMEM;
 147
 148         /* scan dcs commands */
 149         bp = buf;
 150         len = blen;
 151         cnt = 0;
 152         while (len > sizeof(*dchdr)) {
 153                 dchdr = (struct dsi_ctrl_hdr *)bp;
 154                 dchdr->dlen = ntohs(dchdr->dlen);
 155
 156                 if (dchdr->dlen > len) {
 157                         dev_err(dev, "%s: error, len=%d", __func__,
 158                                 dchdr->dlen);
 159                         return -EINVAL;
 160                 }
 161
 162                 bp += sizeof(*dchdr);
 163                 len -= sizeof(*dchdr);
 164                 bp += dchdr->dlen;
 165                 len -= dchdr->dlen;
 166                 cnt++;
 167         }
 168
 169         if (len != 0) {
 170                 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
 171                         __func__, buf[0], blen);
 172                 kfree(buf);
 173                 return -EINVAL;
 174         }
 175
 176         pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
 177         if (!pcmds->cmds) {
 178                 kfree(buf);
 179                 return -ENOMEM;
 180         }
 181
 182         pcmds->cmd_cnt = cnt;
 183         pcmds->buf = buf;
 184         pcmds->blen = blen;
 185
 186         bp = buf;
 187         len = blen;
 188         for (i = 0; i < cnt; i++) {
 189                 dchdr = (struct dsi_ctrl_hdr *)bp;
 190                 len -= sizeof(*dchdr);
 191                 bp += sizeof(*dchdr);
 192                 pcmds->cmds[i].dchdr = *dchdr;
 193                 pcmds->cmds[i].payload = bp;
 194                 bp += dchdr->dlen;
 195                 len -= dchdr->dlen;
 196         }
 197
 198         dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
 199                  pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
 200         return 0;
 201 }
 202
 203 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
 204                                       struct dsi_panel_cmds *cmds)
 205 {
 206         struct mipi_dsi_device *dsi = panel->dsi;
 207         int i, err;
 208
 209         if (!cmds)
 210                 return -EINVAL;
 211
 212         for (i = 0; i < cmds->cmd_cnt; i++) {
 213                 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
 214
 215                 switch (cmd->dchdr.dtype) {
 216                 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 217                 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 218                 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 219                 case MIPI_DSI_GENERIC_LONG_WRITE:
 220                         err = mipi_dsi_generic_write(dsi, cmd->payload,
 221                                                      cmd->dchdr.dlen);
 222                         break;
 223                 case MIPI_DSI_DCS_SHORT_WRITE:
 224                 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 225                 case MIPI_DSI_DCS_LONG_WRITE:
 226                         err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
 227                                                         cmd->dchdr.dlen);
 228                         break;
 229                 default:
 230                         return -EINVAL;
 231                 }
 232
 233                 if (err)
 234                         dev_err(panel->dev, "failed to write dcs cmd: %d\n",
 235                                 err);
 236
 237                 if (cmd->dchdr.wait)
 238                         msleep(cmd->dchdr.wait);
 239         }
 240
 241         return 0;
 242 }
 243
 244 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 245 {
 246         struct drm_connector *connector = panel->base.connector;
 247         struct drm_device *drm = panel->base.drm;
 248         struct drm_display_mode *mode;
 249         unsigned int i, num = 0;
 250
 251         if (!panel->desc)
 252                 return 0;
 253
 254         for (i = 0; i < panel->desc->num_timings; i++) {
 255                 const struct display_timing *dt = &panel->desc->timings[i];
 256                 struct videomode vm;
 257
 258                 videomode_from_timing(dt, &vm);
 259                 mode = drm_mode_create(drm);
 260                 if (!mode) {
 261                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 262                                 dt->hactive.typ, dt->vactive.typ);
 263                         continue;
 264                 }
 265
 266                 drm_display_mode_from_videomode(&vm, mode);
 267                 drm_mode_set_name(mode);
 268
 269                 drm_mode_probed_add(connector, mode);
 270                 num++;
 271         }
 272
 273         for (i = 0; i < panel->desc->num_modes; i++) {
 274                 const struct drm_display_mode *m = &panel->desc->modes[i];
 275
 276                 mode = drm_mode_duplicate(drm, m);
 277                 if (!mode) {
 278                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 279                                 m->hdisplay, m->vdisplay, m->vrefresh);
 280                         continue;
 281                 }
 282
 283                 drm_mode_set_name(mode);
 284
 285                 drm_mode_probed_add(connector, mode);
 286                 num++;
 287         }
 288
 289         connector->display_info.bpc = panel->desc->bpc;
 290         connector->display_info.width_mm = panel->desc->size.width;
 291         connector->display_info.height_mm = panel->desc->size.height;
 292         if (panel->desc->bus_format)
 293                 drm_display_info_set_bus_formats(&connector->display_info,
 294                                                  &panel->desc->bus_format, 1);
 295
 296         return num;
 297 }
 298
 299 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
 300 {
 301         struct drm_connector *connector = panel->base.connector;
 302         struct drm_device *drm = panel->base.drm;
 303         struct drm_display_mode *mode;
 304         struct device_node *timings_np;
 305         int ret;
 306
 307         timings_np = of_get_child_by_name(panel->dev->of_node,
 308                                           "display-timings");
 309         if (!timings_np) {
 310                 dev_dbg(panel->dev, "failed to find display-timings node\n");
 311                 return 0;
 312         }
 313
 314         of_node_put(timings_np);
 315         mode = drm_mode_create(drm);
 316         if (!mode)
 317                 return 0;
 318
 319         ret = of_get_drm_display_mode(panel->dev->of_node, mode,
 320                                       OF_USE_NATIVE_MODE);
 321         if (ret) {
 322                 dev_dbg(panel->dev, "failed to find dts display timings\n");
 323                 drm_mode_destroy(drm, mode);
 324                 return 0;
 325         }
 326
 327         drm_mode_set_name(mode);
 328         mode->type |= DRM_MODE_TYPE_PREFERRED;
 329         drm_mode_probed_add(connector, mode);
 330
 331         return 1;
 332 }
 333
 334 static int panel_simple_disable(struct drm_panel *panel)
 335 {
 336         struct panel_simple *p = to_panel_simple(panel);
 337
 338         if (!p->enabled)
 339                 return 0;
 340
 341         if (p->backlight) {
 342                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 343                 backlight_update_status(p->backlight);
 344         }
 345
 346         if (p->desc && p->desc->delay.disable)
 347                 msleep(p->desc->delay.disable);
 348
 349         p->enabled = false;
 350
 351         return 0;
 352 }
 353
 354 static int panel_simple_unprepare(struct drm_panel *panel)
 355 {
 356         struct panel_simple *p = to_panel_simple(panel);
 357         int err;
 358
 359         if (!p->prepared)
 360                 return 0;
 361
 362         if (p->off_cmds) {
 363                 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
 364                 if (err)
 365                         dev_err(p->dev, "failed to send off cmds\n");
 366         }
 367
 368         if (p->reset_gpio)
 369                 gpiod_direction_output(p->reset_gpio, 1);
 370
 371         if (p->enable_gpio)
 372                 gpiod_direction_output(p->enable_gpio, 0);
 373
 374         regulator_disable(p->supply);
 375
 376         if (p->desc && p->desc->delay.unprepare)
 377                 msleep(p->desc->delay.unprepare);
 378
 379         p->prepared = false;
 380
 381         return 0;
 382 }
 383
 384 static int panel_simple_prepare(struct drm_panel *panel)
 385 {
 386         struct panel_simple *p = to_panel_simple(panel);
 387         int err;
 388
 389         if (p->prepared)
 390                 return 0;
 391
 392         err = regulator_enable(p->supply);
 393         if (err < 0) {
 394                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 395                 return err;
 396         }
 397
 398         if (p->enable_gpio)
 399                 gpiod_direction_output(p->enable_gpio, 1);
 400
 401         if (p->desc && p->desc->delay.prepare)
 402                 msleep(p->desc->delay.prepare);
 403
 404         if (p->reset_gpio)
 405                 gpiod_direction_output(p->reset_gpio, 1);
 406
 407         if (p->reset_delay)
 408                 msleep(p->reset_delay);
 409
 410         if (p->reset_gpio)
 411                 gpiod_direction_output(p->reset_gpio, 0);
 412
 413         p->prepared = true;
 414
 415         return 0;
 416 }
 417
 418 static int panel_simple_enable(struct drm_panel *panel)
 419 {
 420         struct panel_simple *p = to_panel_simple(panel);
 421         int err;
 422
 423         if (p->enabled)
 424                 return 0;
 425
 426         if (p->on_cmds) {
 427                 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
 428                 if (err)
 429                         dev_err(p->dev, "failed to send on cmds\n");
 430         }
 431
 432         if (p->desc && p->desc->delay.enable)
 433                 msleep(p->desc->delay.enable);
 434
 435         if (p->backlight) {
 436                 p->backlight->props.power = FB_BLANK_UNBLANK;
 437                 backlight_update_status(p->backlight);
 438         }
 439
 440         p->enabled = true;
 441
 442         return 0;
 443 }
 444
 445 static int panel_simple_get_modes(struct drm_panel *panel)
 446 {
 447         struct panel_simple *p = to_panel_simple(panel);
 448         int num = 0;
 449
 450         /* add device node plane modes */
 451         num += panel_simple_of_get_native_mode(p);
 452
 453         /* add hard-coded panel modes */
 454         num += panel_simple_get_fixed_modes(p);
 455
 456         /* probe EDID if a DDC bus is available */
 457         if (p->ddc) {
 458                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 459                 drm_mode_connector_update_edid_property(panel->connector, edid);
 460                 if (edid) {
 461                         num += drm_add_edid_modes(panel->connector, edid);
 462                         kfree(edid);
 463                 }
 464         }
 465
 466         return num;
 467 }
 468
 469 static int panel_simple_get_timings(struct drm_panel *panel,
 470                                     unsigned int num_timings,
 471                                     struct display_timing *timings)
 472 {
 473         struct panel_simple *p = to_panel_simple(panel);
 474         unsigned int i;
 475
 476         if (!p->desc)
 477                 return 0;
 478
 479         if (p->desc->num_timings < num_timings)
 480                 num_timings = p->desc->num_timings;
 481
 482         if (timings)
 483                 for (i = 0; i < num_timings; i++)
 484                         timings[i] = p->desc->timings[i];
 485
 486         return p->desc->num_timings;
 487 }
 488
 489 static const struct drm_panel_funcs panel_simple_funcs = {
 490         .disable = panel_simple_disable,
 491         .unprepare = panel_simple_unprepare,
 492         .prepare = panel_simple_prepare,
 493         .enable = panel_simple_enable,
 494         .get_modes = panel_simple_get_modes,
 495         .get_timings = panel_simple_get_timings,
 496 };
 497
 498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 499 {
 500         struct device_node *backlight, *ddc;
 501         struct panel_simple *panel;
 502         struct panel_desc *of_desc;
 503         u32 val;
 504         int err;
 505
 506         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 507         if (!panel)
 508                 return -ENOMEM;
 509
 510         if (!desc)
 511                 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
 512         else
 513                 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
 514
 515         if (!of_property_read_u32(dev->of_node, "bus-format", &val))
 516                 of_desc->bus_format = val;
 517         if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
 518                 of_desc->delay.prepare = val;
 519         if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
 520                 of_desc->delay.enable = val;
 521         if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
 522                 of_desc->delay.disable = val;
 523         if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
 524                 of_desc->delay.unprepare = val;
 525
 526         panel->enabled = false;
 527         panel->prepared = false;
 528         panel->desc = of_desc;
 529         panel->dev = dev;
 530
 531         panel->supply = devm_regulator_get(dev, "power");
 532         if (IS_ERR(panel->supply))
 533                 return PTR_ERR(panel->supply);
 534
 535         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
 536         if (IS_ERR(panel->enable_gpio)) {
 537                 err = PTR_ERR(panel->enable_gpio);
 538                 dev_err(dev, "failed to request enable GPIO: %d\n", err);
 539                 return err;
 540         }
 541
 542         panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
 543         if (IS_ERR(panel->reset_gpio)) {
 544                 err = PTR_ERR(panel->reset_gpio);
 545                 dev_err(dev, "failed to request reset GPIO: %d\n", err);
 546                 return err;
 547         }
 548
 549         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 550         if (backlight) {
 551                 panel->backlight = of_find_backlight_by_node(backlight);
 552                 of_node_put(backlight);
 553
 554                 if (!panel->backlight)
 555                         return -EPROBE_DEFER;
 556         }
 557
 558         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 559         if (ddc) {
 560                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 561                 of_node_put(ddc);
 562
 563                 if (!panel->ddc) {
 564                         err = -EPROBE_DEFER;
 565                         goto free_backlight;
 566                 }
 567         }
 568
 569         drm_panel_init(&panel->base);
 570         panel->base.dev = dev;
 571         panel->base.funcs = &panel_simple_funcs;
 572
 573         err = drm_panel_add(&panel->base);
 574         if (err < 0)
 575                 goto free_ddc;
 576
 577         dev_set_drvdata(dev, panel);
 578
 579         return 0;
 580
 581 free_ddc:
 582         if (panel->ddc)
 583                 put_device(&panel->ddc->dev);
 584 free_backlight:
 585         if (panel->backlight)
 586                 put_device(&panel->backlight->dev);
 587
 588         return err;
 589 }
 590
 591 static int panel_simple_remove(struct device *dev)
 592 {
 593         struct panel_simple *panel = dev_get_drvdata(dev);
 594
 595         drm_panel_detach(&panel->base);
 596         drm_panel_remove(&panel->base);
 597
 598         panel_simple_disable(&panel->base);
 599
 600         if (panel->ddc)
 601                 put_device(&panel->ddc->dev);
 602
 603         if (panel->backlight)
 604                 put_device(&panel->backlight->dev);
 605
 606         panel_simple_dsi_cmds_cleanup(panel);
 607
 608         return 0;
 609 }
 610
 611 static void panel_simple_shutdown(struct device *dev)
 612 {
 613         struct panel_simple *panel = dev_get_drvdata(dev);
 614
 615         panel_simple_disable(&panel->base);
 616 }
 617
 618 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 619         .clock = 33333,
 620         .hdisplay = 800,
 621         .hsync_start = 800 + 0,
 622         .hsync_end = 800 + 0 + 255,
 623         .htotal = 800 + 0 + 255 + 0,
 624         .vdisplay = 480,
 625         .vsync_start = 480 + 2,
 626         .vsync_end = 480 + 2 + 45,
 627         .vtotal = 480 + 2 + 45 + 0,
 628         .vrefresh = 60,
 629         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 630 };
 631
 632 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 633         .modes = &ampire_am800480r3tmqwa1h_mode,
 634         .num_modes = 1,
 635         .bpc = 6,
 636         .size = {
 637                 .width = 152,
 638                 .height = 91,
 639         },
 640         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 641 };
 642
 643 static const struct drm_display_mode auo_b101aw03_mode = {
 644         .clock = 51450,
 645         .hdisplay = 1024,
 646         .hsync_start = 1024 + 156,
 647         .hsync_end = 1024 + 156 + 8,
 648         .htotal = 1024 + 156 + 8 + 156,
 649         .vdisplay = 600,
 650         .vsync_start = 600 + 16,
 651         .vsync_end = 600 + 16 + 6,
 652         .vtotal = 600 + 16 + 6 + 16,
 653         .vrefresh = 60,
 654 };
 655
 656 static const struct panel_desc auo_b101aw03 = {
 657         .modes = &auo_b101aw03_mode,
 658         .num_modes = 1,
 659         .bpc = 6,
 660         .size = {
 661                 .width = 223,
 662                 .height = 125,
 663         },
 664 };
 665
 666 static const struct drm_display_mode auo_b101ean01_mode = {
 667         .clock = 72500,
 668         .hdisplay = 1280,
 669         .hsync_start = 1280 + 119,
 670         .hsync_end = 1280 + 119 + 32,
 671         .htotal = 1280 + 119 + 32 + 21,
 672         .vdisplay = 800,
 673         .vsync_start = 800 + 4,
 674         .vsync_end = 800 + 4 + 20,
 675         .vtotal = 800 + 4 + 20 + 8,
 676         .vrefresh = 60,
 677 };
 678
 679 static const struct panel_desc auo_b101ean01 = {
 680         .modes = &auo_b101ean01_mode,
 681         .num_modes = 1,
 682         .bpc = 6,
 683         .size = {
 684                 .width = 217,
 685                 .height = 136,
 686         },
 687 };
 688
 689 static const struct drm_display_mode auo_b101ew05_mode = {
 690         .clock = 71000,
 691         .hdisplay = 1280,
 692         .hsync_start = 1280 + 18,
 693         .hsync_end = 1280 + 18 + 10,
 694         .htotal = 1280 + 18 + 10 + 100,
 695         .vdisplay = 800,
 696         .vsync_start = 800 + 6,
 697         .vsync_end = 800 + 6 + 2,
 698         .vtotal = 800 + 6 + 2 + 8,
 699         .vrefresh = 60,
 700 };
 701
 702 static const struct panel_desc auo_b101ew05 = {
 703         .modes = &auo_b101ew05_mode,
 704         .num_modes = 1,
 705         .bpc = 6,
 706         .size = {
 707                 .width = 217,
 708                 .height = 136,
 709         },
 710 };
 711
 712 static const struct drm_display_mode auo_b101xtn01_mode = {
 713         .clock = 72000,
 714         .hdisplay = 1366,
 715         .hsync_start = 1366 + 20,
 716         .hsync_end = 1366 + 20 + 70,
 717         .htotal = 1366 + 20 + 70,
 718         .vdisplay = 768,
 719         .vsync_start = 768 + 14,
 720         .vsync_end = 768 + 14 + 42,
 721         .vtotal = 768 + 14 + 42,
 722         .vrefresh = 60,
 723         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 724 };
 725
 726 static const struct panel_desc auo_b101xtn01 = {
 727         .modes = &auo_b101xtn01_mode,
 728         .num_modes = 1,
 729         .bpc = 6,
 730         .size = {
 731                 .width = 223,
 732                 .height = 125,
 733         },
 734 };
 735
 736 static const struct drm_display_mode auo_b116xw03_mode = {
 737         .clock = 70589,
 738         .hdisplay = 1366,
 739         .hsync_start = 1366 + 40,
 740         .hsync_end = 1366 + 40 + 40,
 741         .htotal = 1366 + 40 + 40 + 32,
 742         .vdisplay = 768,
 743         .vsync_start = 768 + 10,
 744         .vsync_end = 768 + 10 + 12,
 745         .vtotal = 768 + 10 + 12 + 6,
 746         .vrefresh = 60,
 747 };
 748
 749 static const struct panel_desc auo_b116xw03 = {
 750         .modes = &auo_b116xw03_mode,
 751         .num_modes = 1,
 752         .bpc = 6,
 753         .size = {
 754                 .width = 256,
 755                 .height = 144,
 756         },
 757 };
 758
 759 static const struct drm_display_mode auo_b125han03_mode = {
 760         .clock = 146900,
 761         .hdisplay = 1920,
 762         .hsync_start = 1920 + 48,
 763         .hsync_end = 1920 + 48 + 32,
 764         .htotal = 1920 + 48 + 32 + 140,
 765         .vdisplay = 1080,
 766         .vsync_start = 1080 + 2,
 767         .vsync_end = 1080 + 2 + 5,
 768         .vtotal = 1080 + 2 + 5 + 57,
 769         .vrefresh = 60,
 770         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 771 };
 772
 773 static const struct panel_desc auo_b125han03 = {
 774         .modes = &auo_b125han03_mode,
 775         .num_modes = 1,
 776         .bpc = 6,
 777         .size = {
 778                 .width = 276,
 779                 .height = 156,
 780         },
 781         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 782 };
 783
 784 static const struct drm_display_mode auo_b133xtn01_mode = {
 785         .clock = 69500,
 786         .hdisplay = 1366,
 787         .hsync_start = 1366 + 48,
 788         .hsync_end = 1366 + 48 + 32,
 789         .htotal = 1366 + 48 + 32 + 20,
 790         .vdisplay = 768,
 791         .vsync_start = 768 + 3,
 792         .vsync_end = 768 + 3 + 6,
 793         .vtotal = 768 + 3 + 6 + 13,
 794         .vrefresh = 60,
 795 };
 796
 797 static const struct panel_desc auo_b133xtn01 = {
 798         .modes = &auo_b133xtn01_mode,
 799         .num_modes = 1,
 800         .bpc = 6,
 801         .size = {
 802                 .width = 293,
 803                 .height = 165,
 804         },
 805 };
 806
 807 static const struct drm_display_mode auo_b133htn01_mode = {
 808         .clock = 150660,
 809         .hdisplay = 1920,
 810         .hsync_start = 1920 + 172,
 811         .hsync_end = 1920 + 172 + 80,
 812         .htotal = 1920 + 172 + 80 + 60,
 813         .vdisplay = 1080,
 814         .vsync_start = 1080 + 25,
 815         .vsync_end = 1080 + 25 + 10,
 816         .vtotal = 1080 + 25 + 10 + 10,
 817         .vrefresh = 60,
 818 };
 819
 820 static const struct panel_desc auo_b133htn01 = {
 821         .modes = &auo_b133htn01_mode,
 822         .num_modes = 1,
 823         .bpc = 6,
 824         .size = {
 825                 .width = 293,
 826                 .height = 165,
 827         },
 828         .delay = {
 829                 .prepare = 105,
 830                 .enable = 20,
 831                 .unprepare = 50,
 832         },
 833 };
 834
 835 static const struct drm_display_mode avic_tm070ddh03_mode = {
 836         .clock = 51200,
 837         .hdisplay = 1024,
 838         .hsync_start = 1024 + 160,
 839         .hsync_end = 1024 + 160 + 4,
 840         .htotal = 1024 + 160 + 4 + 156,
 841         .vdisplay = 600,
 842         .vsync_start = 600 + 17,
 843         .vsync_end = 600 + 17 + 1,
 844         .vtotal = 600 + 17 + 1 + 17,
 845         .vrefresh = 60,
 846 };
 847
 848 static const struct panel_desc avic_tm070ddh03 = {
 849         .modes = &avic_tm070ddh03_mode,
 850         .num_modes = 1,
 851         .bpc = 8,
 852         .size = {
 853                 .width = 154,
 854                 .height = 90,
 855         },
 856         .delay = {
 857                 .prepare = 20,
 858                 .enable = 200,
 859                 .disable = 200,
 860         },
 861 };
 862
 863 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
 864         .clock = 72300,
 865         .hdisplay = 1366,
 866         .hsync_start = 1366 + 80,
 867         .hsync_end = 1366 + 80 + 20,
 868         .htotal = 1366 + 80 + 20 + 60,
 869         .vdisplay = 768,
 870         .vsync_start = 768 + 12,
 871         .vsync_end = 768 + 12 + 2,
 872         .vtotal = 768 + 12 + 2 + 8,
 873         .vrefresh = 60,
 874         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 875 };
 876
 877 static const struct panel_desc boe_nv125fhm_n73 = {
 878         .modes = &boe_nv125fhm_n73_mode,
 879         .num_modes = 1,
 880         .bpc = 6,
 881         .size = {
 882                 .width = 276,
 883                 .height = 156,
 884         },
 885         .delay = {
 886                 .unprepare = 160,
 887         },
 888         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 889 };
 890
 891 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 892         .clock = 67000,
 893         .hdisplay = 800,
 894         .hsync_start = 800 + 24,
 895         .hsync_end = 800 + 24 + 16,
 896         .htotal = 800 + 24 + 16 + 24,
 897         .vdisplay = 1280,
 898         .vsync_start = 1280 + 2,
 899         .vsync_end = 1280 + 2 + 2,
 900         .vtotal = 1280 + 2 + 2 + 4,
 901         .vrefresh = 60,
 902 };
 903
 904 static const struct panel_desc chunghwa_claa070wp03xg = {
 905         .modes = &chunghwa_claa070wp03xg_mode,
 906         .num_modes = 1,
 907         .bpc = 6,
 908         .size = {
 909                 .width = 94,
 910                 .height = 151,
 911         },
 912 };
 913
 914 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 915         .clock = 72070,
 916         .hdisplay = 1366,
 917         .hsync_start = 1366 + 58,
 918         .hsync_end = 1366 + 58 + 58,
 919         .htotal = 1366 + 58 + 58 + 58,
 920         .vdisplay = 768,
 921         .vsync_start = 768 + 4,
 922         .vsync_end = 768 + 4 + 4,
 923         .vtotal = 768 + 4 + 4 + 4,
 924         .vrefresh = 60,
 925 };
 926
 927 static const struct panel_desc chunghwa_claa101wa01a = {
 928         .modes = &chunghwa_claa101wa01a_mode,
 929         .num_modes = 1,
 930         .bpc = 6,
 931         .size = {
 932                 .width = 220,
 933                 .height = 120,
 934         },
 935 };
 936
 937 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 938         .clock = 69300,
 939         .hdisplay = 1366,
 940         .hsync_start = 1366 + 48,
 941         .hsync_end = 1366 + 48 + 32,
 942         .htotal = 1366 + 48 + 32 + 20,
 943         .vdisplay = 768,
 944         .vsync_start = 768 + 16,
 945         .vsync_end = 768 + 16 + 8,
 946         .vtotal = 768 + 16 + 8 + 16,
 947         .vrefresh = 60,
 948 };
 949
 950 static const struct panel_desc chunghwa_claa101wb01 = {
 951         .modes = &chunghwa_claa101wb01_mode,
 952         .num_modes = 1,
 953         .bpc = 6,
 954         .size = {
 955                 .width = 223,
 956                 .height = 125,
 957         },
 958 };
 959
 960 static const struct drm_display_mode edt_et057090dhu_mode = {
 961         .clock = 25175,
 962         .hdisplay = 640,
 963         .hsync_start = 640 + 16,
 964         .hsync_end = 640 + 16 + 30,
 965         .htotal = 640 + 16 + 30 + 114,
 966         .vdisplay = 480,
 967         .vsync_start = 480 + 10,
 968         .vsync_end = 480 + 10 + 3,
 969         .vtotal = 480 + 10 + 3 + 32,
 970         .vrefresh = 60,
 971         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 972 };
 973
 974 static const struct panel_desc edt_et057090dhu = {
 975         .modes = &edt_et057090dhu_mode,
 976         .num_modes = 1,
 977         .bpc = 6,
 978         .size = {
 979                 .width = 115,
 980                 .height = 86,
 981         },
 982 };
 983
 984 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
 985         .clock = 33260,
 986         .hdisplay = 800,
 987         .hsync_start = 800 + 40,
 988         .hsync_end = 800 + 40 + 128,
 989         .htotal = 800 + 40 + 128 + 88,
 990         .vdisplay = 480,
 991         .vsync_start = 480 + 10,
 992         .vsync_end = 480 + 10 + 2,
 993         .vtotal = 480 + 10 + 2 + 33,
 994         .vrefresh = 60,
 995         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 996 };
 997
 998 static const struct panel_desc edt_etm0700g0dh6 = {
 999         .modes = &edt_etm0700g0dh6_mode,
1000         .num_modes = 1,
1001         .bpc = 6,
1002         .size = {
1003                 .width = 152,
1004                 .height = 91,
1005         },
1006 };
1007
1008 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1009         .clock = 32260,
1010         .hdisplay = 800,
1011         .hsync_start = 800 + 168,
1012         .hsync_end = 800 + 168 + 64,
1013         .htotal = 800 + 168 + 64 + 88,
1014         .vdisplay = 480,
1015         .vsync_start = 480 + 37,
1016         .vsync_end = 480 + 37 + 2,
1017         .vtotal = 480 + 37 + 2 + 8,
1018         .vrefresh = 60,
1019 };
1020
1021 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1022         .modes = &foxlink_fl500wvr00_a0t_mode,
1023         .num_modes = 1,
1024         .bpc = 8,
1025         .size = {
1026                 .width = 108,
1027                 .height = 65,
1028         },
1029         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1030 };
1031
1032 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1033         .clock = 9000,
1034         .hdisplay = 480,
1035         .hsync_start = 480 + 5,
1036         .hsync_end = 480 + 5 + 1,
1037         .htotal = 480 + 5 + 1 + 40,
1038         .vdisplay = 272,
1039         .vsync_start = 272 + 8,
1040         .vsync_end = 272 + 8 + 1,
1041         .vtotal = 272 + 8 + 1 + 8,
1042         .vrefresh = 60,
1043 };
1044
1045 static const struct panel_desc giantplus_gpg482739qs5 = {
1046         .modes = &giantplus_gpg482739qs5_mode,
1047         .num_modes = 1,
1048         .bpc = 8,
1049         .size = {
1050                 .width = 95,
1051                 .height = 54,
1052         },
1053         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1054 };
1055
1056 static const struct display_timing hannstar_hsd070pww1_timing = {
1057         .pixelclock = { 64300000, 71100000, 82000000 },
1058         .hactive = { 1280, 1280, 1280 },
1059         .hfront_porch = { 1, 1, 10 },
1060         .hback_porch = { 1, 1, 10 },
1061         /*
1062          * According to the data sheet, the minimum horizontal blanking interval
1063          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1064          * minimum working horizontal blanking interval to be 60 clocks.
1065          */
1066         .hsync_len = { 58, 158, 661 },
1067         .vactive = { 800, 800, 800 },
1068         .vfront_porch = { 1, 1, 10 },
1069         .vback_porch = { 1, 1, 10 },
1070         .vsync_len = { 1, 21, 203 },
1071         .flags = DISPLAY_FLAGS_DE_HIGH,
1072 };
1073
1074 static const struct panel_desc hannstar_hsd070pww1 = {
1075         .timings = &hannstar_hsd070pww1_timing,
1076         .num_timings = 1,
1077         .bpc = 6,
1078         .size = {
1079                 .width = 151,
1080                 .height = 94,
1081         },
1082         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1083 };
1084
1085 static const struct display_timing hannstar_hsd100pxn1_timing = {
1086         .pixelclock = { 55000000, 65000000, 75000000 },
1087         .hactive = { 1024, 1024, 1024 },
1088         .hfront_porch = { 40, 40, 40 },
1089         .hback_porch = { 220, 220, 220 },
1090         .hsync_len = { 20, 60, 100 },
1091         .vactive = { 768, 768, 768 },
1092         .vfront_porch = { 7, 7, 7 },
1093         .vback_porch = { 21, 21, 21 },
1094         .vsync_len = { 10, 10, 10 },
1095         .flags = DISPLAY_FLAGS_DE_HIGH,
1096 };
1097
1098 static const struct panel_desc hannstar_hsd100pxn1 = {
1099         .timings = &hannstar_hsd100pxn1_timing,
1100         .num_timings = 1,
1101         .bpc = 6,
1102         .size = {
1103                 .width = 203,
1104                 .height = 152,
1105         },
1106         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1107 };
1108
1109 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1110         .clock = 33333,
1111         .hdisplay = 800,
1112         .hsync_start = 800 + 85,
1113         .hsync_end = 800 + 85 + 86,
1114         .htotal = 800 + 85 + 86 + 85,
1115         .vdisplay = 480,
1116         .vsync_start = 480 + 16,
1117         .vsync_end = 480 + 16 + 13,
1118         .vtotal = 480 + 16 + 13 + 16,
1119         .vrefresh = 60,
1120 };
1121
1122 static const struct panel_desc hitachi_tx23d38vm0caa = {
1123         .modes = &hitachi_tx23d38vm0caa_mode,
1124         .num_modes = 1,
1125         .bpc = 6,
1126         .size = {
1127                 .width = 195,
1128                 .height = 117,
1129         },
1130 };
1131
1132 static const struct drm_display_mode innolux_at043tn24_mode = {
1133         .clock = 9000,
1134         .hdisplay = 480,
1135         .hsync_start = 480 + 2,
1136         .hsync_end = 480 + 2 + 41,
1137         .htotal = 480 + 2 + 41 + 2,
1138         .vdisplay = 272,
1139         .vsync_start = 272 + 2,
1140         .vsync_end = 272 + 2 + 11,
1141         .vtotal = 272 + 2 + 11 + 2,
1142         .vrefresh = 60,
1143         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1144 };
1145
1146 static const struct panel_desc innolux_at043tn24 = {
1147         .modes = &innolux_at043tn24_mode,
1148         .num_modes = 1,
1149         .bpc = 8,
1150         .size = {
1151                 .width = 95,
1152                 .height = 54,
1153         },
1154         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1155 };
1156
1157 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1158         .clock = 71000,
1159         .hdisplay = 1280,
1160         .hsync_start = 1280 + 64,
1161         .hsync_end = 1280 + 64 + 32,
1162         .htotal = 1280 + 64 + 32 + 64,
1163         .vdisplay = 800,
1164         .vsync_start = 800 + 9,
1165         .vsync_end = 800 + 9 + 6,
1166         .vtotal = 800 + 9 + 6 + 9,
1167         .vrefresh = 60,
1168 };
1169
1170 static const struct panel_desc innolux_g121i1_l01 = {
1171         .modes = &innolux_g121i1_l01_mode,
1172         .num_modes = 1,
1173         .bpc = 6,
1174         .size = {
1175                 .width = 261,
1176                 .height = 163,
1177         },
1178 };
1179
1180 static const struct drm_display_mode innolux_n116bge_mode = {
1181         .clock = 76420,
1182         .hdisplay = 1366,
1183         .hsync_start = 1366 + 136,
1184         .hsync_end = 1366 + 136 + 30,
1185         .htotal = 1366 + 136 + 30 + 60,
1186         .vdisplay = 768,
1187         .vsync_start = 768 + 8,
1188         .vsync_end = 768 + 8 + 12,
1189         .vtotal = 768 + 8 + 12 + 12,
1190         .vrefresh = 60,
1191         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1192 };
1193
1194 static const struct panel_desc innolux_n116bge = {
1195         .modes = &innolux_n116bge_mode,
1196         .num_modes = 1,
1197         .bpc = 6,
1198         .size = {
1199                 .width = 256,
1200                 .height = 144,
1201         },
1202 };
1203
1204 static const struct drm_display_mode innolux_n125hce_mode = {
1205         .clock = 138780,
1206         .hdisplay = 1920,
1207         .hsync_start = 1920 + 80,
1208         .hsync_end = 1920 + 80 + 30,
1209         .htotal = 1920 + 80 + 30 + 50,
1210         .vdisplay = 1080,
1211         .vsync_start = 1080 + 12,
1212         .vsync_end = 1080 + 12 + 4,
1213         .vtotal = 1080 + 12 + 4 + 16,
1214         .vrefresh = 60,
1215         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1216 };
1217
1218 static const struct panel_desc innolux_n125hce = {
1219         .modes = &innolux_n125hce_mode,
1220         .num_modes = 1,
1221         .bpc = 6,
1222         .size = {
1223                 .width = 283,
1224                 .height = 168,
1225         },
1226         .delay = {
1227                 .unprepare = 600,
1228                 .enable = 100,
1229         },
1230         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1231 };
1232
1233 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1234         .clock = 69300,
1235         .hdisplay = 1366,
1236         .hsync_start = 1366 + 16,
1237         .hsync_end = 1366 + 16 + 34,
1238         .htotal = 1366 + 16 + 34 + 50,
1239         .vdisplay = 768,
1240         .vsync_start = 768 + 2,
1241         .vsync_end = 768 + 2 + 6,
1242         .vtotal = 768 + 2 + 6 + 12,
1243         .vrefresh = 60,
1244 };
1245
1246 static const struct panel_desc innolux_n156bge_l21 = {
1247         .modes = &innolux_n156bge_l21_mode,
1248         .num_modes = 1,
1249         .bpc = 6,
1250         .size = {
1251                 .width = 344,
1252                 .height = 193,
1253         },
1254 };
1255
1256 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1257         .clock = 51501,
1258         .hdisplay = 1024,
1259         .hsync_start = 1024 + 128,
1260         .hsync_end = 1024 + 128 + 64,
1261         .htotal = 1024 + 128 + 64 + 128,
1262         .vdisplay = 600,
1263         .vsync_start = 600 + 16,
1264         .vsync_end = 600 + 16 + 4,
1265         .vtotal = 600 + 16 + 4 + 16,
1266         .vrefresh = 60,
1267 };
1268
1269 static const struct panel_desc innolux_zj070na_01p = {
1270         .modes = &innolux_zj070na_01p_mode,
1271         .num_modes = 1,
1272         .bpc = 6,
1273         .size = {
1274                 .width = 1024,
1275                 .height = 600,
1276         },
1277 };
1278
1279 static const struct drm_display_mode lg_lb070wv8_mode = {
1280         .clock = 33246,
1281         .hdisplay = 800,
1282         .hsync_start = 800 + 88,
1283         .hsync_end = 800 + 88 + 80,
1284         .htotal = 800 + 88 + 80 + 88,
1285         .vdisplay = 480,
1286         .vsync_start = 480 + 10,
1287         .vsync_end = 480 + 10 + 25,
1288         .vtotal = 480 + 10 + 25 + 10,
1289         .vrefresh = 60,
1290 };
1291
1292 static const struct panel_desc lg_lb070wv8 = {
1293         .modes = &lg_lb070wv8_mode,
1294         .num_modes = 1,
1295         .bpc = 16,
1296         .size = {
1297                 .width = 151,
1298                 .height = 91,
1299         },
1300         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1301 };
1302
1303 static const struct drm_display_mode sharp_lcd_f402_mode = {
1304         .clock = 205000,
1305         .hdisplay = 1536,
1306         .hsync_start = 1536 + 12,
1307         .hsync_end = 1536 + 12 + 48,
1308         .htotal = 1536 + 12 + 48 + 16,
1309         .vdisplay = 2048,
1310         .vsync_start = 2048 + 8,
1311         .vsync_end = 2048 + 8 + 8,
1312         .vtotal = 2048 + 8 + 8 + 4,
1313         .vrefresh = 60,
1314         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1315 };
1316
1317 static const struct panel_desc sharp_lcd_f402 = {
1318         .modes = &sharp_lcd_f402_mode,
1319         .num_modes = 1,
1320         .bpc = 8,
1321         .size = {
1322                 .width = 95,
1323                 .height = 54,
1324         },
1325         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1326 };
1327
1328 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1329         .clock = 200000,
1330         .hdisplay = 1536,
1331         .hsync_start = 1536 + 12,
1332         .hsync_end = 1536 + 12 + 16,
1333         .htotal = 1536 + 12 + 16 + 48,
1334         .vdisplay = 2048,
1335         .vsync_start = 2048 + 8,
1336         .vsync_end = 2048 + 8 + 4,
1337         .vtotal = 2048 + 8 + 4 + 8,
1338         .vrefresh = 60,
1339         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1340 };
1341
1342 static const struct panel_desc lg_lp079qx1_sp0v = {
1343         .modes = &lg_lp079qx1_sp0v_mode,
1344         .num_modes = 1,
1345         .size = {
1346                 .width = 129,
1347                 .height = 171,
1348         },
1349         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1350 };
1351
1352 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1353         .clock = 205210,
1354         .hdisplay = 2048,
1355         .hsync_start = 2048 + 150,
1356         .hsync_end = 2048 + 150 + 5,
1357         .htotal = 2048 + 150 + 5 + 5,
1358         .vdisplay = 1536,
1359         .vsync_start = 1536 + 3,
1360         .vsync_end = 1536 + 3 + 1,
1361         .vtotal = 1536 + 3 + 1 + 9,
1362         .vrefresh = 60,
1363 };
1364
1365 static const struct panel_desc lg_lp097qx1_spa1 = {
1366         .modes = &lg_lp097qx1_spa1_mode,
1367         .num_modes = 1,
1368         .size = {
1369                 .width = 320,
1370                 .height = 187,
1371         },
1372 };
1373
1374 static const struct drm_display_mode lg_lp129qe_mode = {
1375         .clock = 285250,
1376         .hdisplay = 2560,
1377         .hsync_start = 2560 + 48,
1378         .hsync_end = 2560 + 48 + 32,
1379         .htotal = 2560 + 48 + 32 + 80,
1380         .vdisplay = 1700,
1381         .vsync_start = 1700 + 3,
1382         .vsync_end = 1700 + 3 + 10,
1383         .vtotal = 1700 + 3 + 10 + 36,
1384         .vrefresh = 60,
1385 };
1386
1387 static const struct panel_desc lg_lp129qe = {
1388         .modes = &lg_lp129qe_mode,
1389         .num_modes = 1,
1390         .bpc = 8,
1391         .size = {
1392                 .width = 272,
1393                 .height = 181,
1394         },
1395 };
1396
1397 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1398         .clock = 10870,
1399         .hdisplay = 480,
1400         .hsync_start = 480 + 2,
1401         .hsync_end = 480 + 2 + 41,
1402         .htotal = 480 + 2 + 41 + 2,
1403         .vdisplay = 272,
1404         .vsync_start = 272 + 2,
1405         .vsync_end = 272 + 2 + 4,
1406         .vtotal = 272 + 2 + 4 + 2,
1407         .vrefresh = 74,
1408 };
1409
1410 static const struct panel_desc nec_nl4827hc19_05b = {
1411         .modes = &nec_nl4827hc19_05b_mode,
1412         .num_modes = 1,
1413         .bpc = 8,
1414         .size = {
1415                 .width = 95,
1416                 .height = 54,
1417         },
1418         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1419 };
1420
1421 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1422         .pixelclock = { 30000000, 30000000, 40000000 },
1423         .hactive = { 800, 800, 800 },
1424         .hfront_porch = { 40, 40, 40 },
1425         .hback_porch = { 40, 40, 40 },
1426         .hsync_len = { 1, 48, 48 },
1427         .vactive = { 480, 480, 480 },
1428         .vfront_porch = { 13, 13, 13 },
1429         .vback_porch = { 29, 29, 29 },
1430         .vsync_len = { 3, 3, 3 },
1431         .flags = DISPLAY_FLAGS_DE_HIGH,
1432 };
1433
1434 static const struct panel_desc okaya_rs800480t_7x0gp = {
1435         .timings = &okaya_rs800480t_7x0gp_timing,
1436         .num_timings = 1,
1437         .bpc = 6,
1438         .size = {
1439                 .width = 154,
1440                 .height = 87,
1441         },
1442         .delay = {
1443                 .prepare = 41,
1444                 .enable = 50,
1445                 .unprepare = 41,
1446                 .disable = 50,
1447         },
1448         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1449 };
1450
1451 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1452         .clock = 25000,
1453         .hdisplay = 480,
1454         .hsync_start = 480 + 10,
1455         .hsync_end = 480 + 10 + 10,
1456         .htotal = 480 + 10 + 10 + 15,
1457         .vdisplay = 800,
1458         .vsync_start = 800 + 3,
1459         .vsync_end = 800 + 3 + 3,
1460         .vtotal = 800 + 3 + 3 + 3,
1461         .vrefresh = 60,
1462 };
1463
1464 static const struct panel_desc ortustech_com43h4m85ulc = {
1465         .modes = &ortustech_com43h4m85ulc_mode,
1466         .num_modes = 1,
1467         .bpc = 8,
1468         .size = {
1469                 .width = 56,
1470                 .height = 93,
1471         },
1472         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1473 };
1474
1475 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1476         .clock = 271560,
1477         .hdisplay = 2560,
1478         .hsync_start = 2560 + 48,
1479         .hsync_end = 2560 + 48 + 32,
1480         .htotal = 2560 + 48 + 32 + 80,
1481         .vdisplay = 1600,
1482         .vsync_start = 1600 + 2,
1483         .vsync_end = 1600 + 2 + 5,
1484         .vtotal = 1600 + 2 + 5 + 57,
1485         .vrefresh = 60,
1486 };
1487
1488 static const struct panel_desc samsung_lsn122dl01_c01 = {
1489         .modes = &samsung_lsn122dl01_c01_mode,
1490         .num_modes = 1,
1491         .size = {
1492                 .width = 2560,
1493                 .height = 1600,
1494         },
1495 };
1496
1497 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1498         .clock = 54030,
1499         .hdisplay = 1024,
1500         .hsync_start = 1024 + 24,
1501         .hsync_end = 1024 + 24 + 136,
1502         .htotal = 1024 + 24 + 136 + 160,
1503         .vdisplay = 600,
1504         .vsync_start = 600 + 3,
1505         .vsync_end = 600 + 3 + 6,
1506         .vtotal = 600 + 3 + 6 + 61,
1507         .vrefresh = 60,
1508 };
1509
1510 static const struct panel_desc samsung_ltn101nt05 = {
1511         .modes = &samsung_ltn101nt05_mode,
1512         .num_modes = 1,
1513         .bpc = 6,
1514         .size = {
1515                 .width = 1024,
1516                 .height = 600,
1517         },
1518 };
1519
1520 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1521         .clock = 76300,
1522         .hdisplay = 1366,
1523         .hsync_start = 1366 + 64,
1524         .hsync_end = 1366 + 64 + 48,
1525         .htotal = 1366 + 64 + 48 + 128,
1526         .vdisplay = 768,
1527         .vsync_start = 768 + 2,
1528         .vsync_end = 768 + 2 + 5,
1529         .vtotal = 768 + 2 + 5 + 17,
1530         .vrefresh = 60,
1531 };
1532
1533 static const struct panel_desc samsung_ltn140at29_301 = {
1534         .modes = &samsung_ltn140at29_301_mode,
1535         .num_modes = 1,
1536         .bpc = 6,
1537         .size = {
1538                 .width = 320,
1539                 .height = 187,
1540         },
1541 };
1542
1543 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1544         .clock = 33300,
1545         .hdisplay = 800,
1546         .hsync_start = 800 + 1,
1547         .hsync_end = 800 + 1 + 64,
1548         .htotal = 800 + 1 + 64 + 64,
1549         .vdisplay = 480,
1550         .vsync_start = 480 + 1,
1551         .vsync_end = 480 + 1 + 23,
1552         .vtotal = 480 + 1 + 23 + 22,
1553         .vrefresh = 60,
1554 };
1555
1556 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1557         .modes = &shelly_sca07010_bfn_lnn_mode,
1558         .num_modes = 1,
1559         .size = {
1560                 .width = 152,
1561                 .height = 91,
1562         },
1563         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1564 };
1565
1566 static const struct of_device_id platform_of_match[] = {
1567         {
1568                 .compatible = "simple-panel",
1569                 .data = NULL,
1570         }, {
1571                 .compatible = "ampire,am800480r3tmqwa1h",
1572                 .data = &ampire_am800480r3tmqwa1h,
1573         }, {
1574                 .compatible = "auo,b101aw03",
1575                 .data = &auo_b101aw03,
1576         }, {
1577                 .compatible = "auo,b101ean01",
1578                 .data = &auo_b101ean01,
1579         }, {
1580                 .compatible = "auo,b101ew05",
1581                 .data = &auo_b101ew05,
1582         }, {
1583                 .compatible = "auo,b101xtn01",
1584                 .data = &auo_b101xtn01,
1585         }, {
1586                 .compatible = "auo,b116xw03",
1587                 .data = &auo_b116xw03,
1588         }, {
1589                 .compatible = "auo,b125han03",
1590                 .data = &auo_b125han03,
1591         }, {
1592                 .compatible = "auo,b133htn01",
1593                 .data = &auo_b133htn01,
1594         }, {
1595                 .compatible = "auo,b133xtn01",
1596                 .data = &auo_b133xtn01,
1597         }, {
1598                 .compatible = "avic,tm070ddh03",
1599                 .data = &avic_tm070ddh03,
1600         }, {
1601                 .compatible = "boe,nv125fhm-n73",
1602                 .data = &boe_nv125fhm_n73,
1603         }, {
1604                 .compatible = "chunghwa,claa070wp03xg",
1605                 .data = &chunghwa_claa070wp03xg,
1606         }, {
1607                 .compatible = "chunghwa,claa101wa01a",
1608                 .data = &chunghwa_claa101wa01a
1609         }, {
1610                 .compatible = "chunghwa,claa101wb01",
1611                 .data = &chunghwa_claa101wb01
1612         }, {
1613                 .compatible = "edt,et057090dhu",
1614                 .data = &edt_et057090dhu,
1615         }, {
1616                 .compatible = "edt,et070080dh6",
1617                 .data = &edt_etm0700g0dh6,
1618         }, {
1619                 .compatible = "edt,etm0700g0dh6",
1620                 .data = &edt_etm0700g0dh6,
1621         }, {
1622                 .compatible = "foxlink,fl500wvr00-a0t",
1623                 .data = &foxlink_fl500wvr00_a0t,
1624         }, {
1625                 .compatible = "giantplus,gpg482739qs5",
1626                 .data = &giantplus_gpg482739qs5
1627         }, {
1628                 .compatible = "hannstar,hsd070pww1",
1629                 .data = &hannstar_hsd070pww1,
1630         }, {
1631                 .compatible = "hannstar,hsd100pxn1",
1632                 .data = &hannstar_hsd100pxn1,
1633         }, {
1634                 .compatible = "hit,tx23d38vm0caa",
1635                 .data = &hitachi_tx23d38vm0caa
1636         }, {
1637                 .compatible = "innolux,at043tn24",
1638                 .data = &innolux_at043tn24,
1639         }, {
1640                 .compatible ="innolux,g121i1-l01",
1641                 .data = &innolux_g121i1_l01
1642         }, {
1643                 .compatible = "innolux,n116bge",
1644                 .data = &innolux_n116bge,
1645         }, {
1646                 .compatible = "innolux,n125hce",
1647                 .data = &innolux_n125hce,
1648         }, {
1649                 .compatible = "innolux,n156bge-l21",
1650                 .data = &innolux_n156bge_l21,
1651         }, {
1652                 .compatible = "innolux,zj070na-01p",
1653                 .data = &innolux_zj070na_01p,
1654         }, {
1655                 .compatible = "lg,lb070wv8",
1656                 .data = &lg_lb070wv8,
1657         }, {
1658                 .compatible = "lg,lp079qx1-sp0v",
1659                 .data = &lg_lp079qx1_sp0v,
1660         }, {
1661                 .compatible = "lg,lp097qx1-spa1",
1662                 .data = &lg_lp097qx1_spa1,
1663         }, {
1664                 .compatible = "lg,lp129qe",
1665                 .data = &lg_lp129qe,
1666         }, {
1667                 .compatible = "nec,nl4827hc19-05b",
1668                 .data = &nec_nl4827hc19_05b,
1669         }, {
1670                 .compatible = "okaya,rs800480t-7x0gp",
1671                 .data = &okaya_rs800480t_7x0gp,
1672         }, {
1673                 .compatible = "ortustech,com43h4m85ulc",
1674                 .data = &ortustech_com43h4m85ulc,
1675         }, {
1676                 .compatible = "samsung,lsn122dl01-c01",
1677                 .data = &samsung_lsn122dl01_c01,
1678         }, {
1679                 .compatible = "samsung,ltn101nt05",
1680                 .data = &samsung_ltn101nt05,
1681         }, {
1682                 .compatible = "samsung,ltn140at29-301",
1683                 .data = &samsung_ltn140at29_301,
1684         }, {
1685                 .compatible = "sharp,lcd-f402",
1686                 .data = &sharp_lcd_f402,
1687         }, {
1688                 .compatible = "shelly,sca07010-bfn-lnn",
1689                 .data = &shelly_sca07010_bfn_lnn,
1690         }, {
1691                 /* sentinel */
1692         }
1693 };
1694 MODULE_DEVICE_TABLE(of, platform_of_match);
1695
1696 static int panel_simple_platform_probe(struct platform_device *pdev)
1697 {
1698         const struct of_device_id *id;
1699
1700         id = of_match_node(platform_of_match, pdev->dev.of_node);
1701         if (!id)
1702                 return -ENODEV;
1703
1704         return panel_simple_probe(&pdev->dev, id->data);
1705 }
1706
1707 static int panel_simple_platform_remove(struct platform_device *pdev)
1708 {
1709         return panel_simple_remove(&pdev->dev);
1710 }
1711
1712 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1713 {
1714         panel_simple_shutdown(&pdev->dev);
1715 }
1716
1717 static struct platform_driver panel_simple_platform_driver = {
1718         .driver = {
1719                 .name = "panel-simple",
1720                 .of_match_table = platform_of_match,
1721         },
1722         .probe = panel_simple_platform_probe,
1723         .remove = panel_simple_platform_remove,
1724         .shutdown = panel_simple_platform_shutdown,
1725 };
1726
1727 struct panel_desc_dsi {
1728         struct panel_desc desc;
1729
1730         unsigned long flags;
1731         enum mipi_dsi_pixel_format format;
1732         unsigned int lanes;
1733 };
1734
1735 static const struct drm_display_mode auo_b080uan01_mode = {
1736         .clock = 154500,
1737         .hdisplay = 1200,
1738         .hsync_start = 1200 + 62,
1739         .hsync_end = 1200 + 62 + 4,
1740         .htotal = 1200 + 62 + 4 + 62,
1741         .vdisplay = 1920,
1742         .vsync_start = 1920 + 9,
1743         .vsync_end = 1920 + 9 + 2,
1744         .vtotal = 1920 + 9 + 2 + 8,
1745         .vrefresh = 60,
1746 };
1747
1748 static const struct panel_desc_dsi auo_b080uan01 = {
1749         .desc = {
1750                 .modes = &auo_b080uan01_mode,
1751                 .num_modes = 1,
1752                 .bpc = 8,
1753                 .size = {
1754                         .width = 108,
1755                         .height = 272,
1756                 },
1757         },
1758         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1759         .format = MIPI_DSI_FMT_RGB888,
1760         .lanes = 4,
1761 };
1762
1763 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1764         .clock = 160000,
1765         .hdisplay = 1200,
1766         .hsync_start = 1200 + 120,
1767         .hsync_end = 1200 + 120 + 20,
1768         .htotal = 1200 + 120 + 20 + 21,
1769         .vdisplay = 1920,
1770         .vsync_start = 1920 + 21,
1771         .vsync_end = 1920 + 21 + 3,
1772         .vtotal = 1920 + 21 + 3 + 18,
1773         .vrefresh = 60,
1774         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1775 };
1776
1777 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1778         .desc = {
1779                 .modes = &boe_tv080wum_nl0_mode,
1780                 .num_modes = 1,
1781                 .size = {
1782                         .width = 107,
1783                         .height = 172,
1784                 },
1785         },
1786         .flags = MIPI_DSI_MODE_VIDEO |
1787                  MIPI_DSI_MODE_VIDEO_BURST |
1788                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1789         .format = MIPI_DSI_FMT_RGB888,
1790         .lanes = 4,
1791 };
1792
1793 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1794         .clock = 71000,
1795         .hdisplay = 800,
1796         .hsync_start = 800 + 32,
1797         .hsync_end = 800 + 32 + 1,
1798         .htotal = 800 + 32 + 1 + 57,
1799         .vdisplay = 1280,
1800         .vsync_start = 1280 + 28,
1801         .vsync_end = 1280 + 28 + 1,
1802         .vtotal = 1280 + 28 + 1 + 14,
1803         .vrefresh = 60,
1804 };
1805
1806 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1807         .desc = {
1808                 .modes = &lg_ld070wx3_sl01_mode,
1809                 .num_modes = 1,
1810                 .bpc = 8,
1811                 .size = {
1812                         .width = 94,
1813                         .height = 151,
1814                 },
1815         },
1816         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1817         .format = MIPI_DSI_FMT_RGB888,
1818         .lanes = 4,
1819 };
1820
1821 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1822         .clock = 67000,
1823         .hdisplay = 720,
1824         .hsync_start = 720 + 12,
1825         .hsync_end = 720 + 12 + 4,
1826         .htotal = 720 + 12 + 4 + 112,
1827         .vdisplay = 1280,
1828         .vsync_start = 1280 + 8,
1829         .vsync_end = 1280 + 8 + 4,
1830         .vtotal = 1280 + 8 + 4 + 12,
1831         .vrefresh = 60,
1832 };
1833
1834 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1835         .desc = {
1836                 .modes = &lg_lh500wx1_sd03_mode,
1837                 .num_modes = 1,
1838                 .bpc = 8,
1839                 .size = {
1840                         .width = 62,
1841                         .height = 110,
1842                 },
1843         },
1844         .flags = MIPI_DSI_MODE_VIDEO,
1845         .format = MIPI_DSI_FMT_RGB888,
1846         .lanes = 4,
1847 };
1848
1849 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1850         .clock = 157200,
1851         .hdisplay = 1920,
1852         .hsync_start = 1920 + 154,
1853         .hsync_end = 1920 + 154 + 16,
1854         .htotal = 1920 + 154 + 16 + 32,
1855         .vdisplay = 1200,
1856         .vsync_start = 1200 + 17,
1857         .vsync_end = 1200 + 17 + 2,
1858         .vtotal = 1200 + 17 + 2 + 16,
1859         .vrefresh = 60,
1860 };
1861
1862 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1863         .desc = {
1864                 .modes = &panasonic_vvx10f004b00_mode,
1865                 .num_modes = 1,
1866                 .bpc = 8,
1867                 .size = {
1868                         .width = 217,
1869                         .height = 136,
1870                 },
1871         },
1872         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1873                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1874         .format = MIPI_DSI_FMT_RGB888,
1875         .lanes = 4,
1876 };
1877
1878
1879 static const struct of_device_id dsi_of_match[] = {
1880         {
1881                 .compatible = "simple-panel-dsi",
1882                 .data = NULL
1883         }, {
1884                 .compatible = "auo,b080uan01",
1885                 .data = &auo_b080uan01
1886         }, {
1887                 .compatible = "boe,tv080wum-nl0",
1888                 .data = &boe_tv080wum_nl0
1889         }, {
1890                 .compatible = "lg,ld070wx3-sl01",
1891                 .data = &lg_ld070wx3_sl01
1892         }, {
1893                 .compatible = "lg,lh500wx1-sd03",
1894                 .data = &lg_lh500wx1_sd03
1895         }, {
1896                 .compatible = "panasonic,vvx10f004b00",
1897                 .data = &panasonic_vvx10f004b00
1898         }, {
1899                 /* sentinel */
1900         }
1901 };
1902 MODULE_DEVICE_TABLE(of, dsi_of_match);
1903
1904 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1905 {
1906         struct panel_simple *panel;
1907         const struct panel_desc_dsi *desc;
1908         const struct of_device_id *id;
1909         const struct panel_desc *pdesc;
1910         const void *data;
1911         int len;
1912         u32 val;
1913         int err;
1914
1915         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1916         if (!id)
1917                 return -ENODEV;
1918
1919         desc = id->data;
1920
1921         if (desc) {
1922                 dsi->mode_flags = desc->flags;
1923                 dsi->format = desc->format;
1924                 dsi->lanes = desc->lanes;
1925                 pdesc = &desc->desc;
1926         } else {
1927                 pdesc = NULL;
1928         }
1929
1930         err = panel_simple_probe(&dsi->dev, pdesc);
1931         if (err < 0)
1932                 return err;
1933
1934         panel = dev_get_drvdata(&dsi->dev);
1935         panel->dsi = dsi;
1936
1937         if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1938                 dsi->mode_flags = val;
1939
1940         if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1941                 dsi->format = val;
1942
1943         if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1944                 dsi->lanes = val;
1945
1946         if (!of_property_read_u32(dsi->dev.of_node, "reset-delay-ms", &val))
1947                 panel->reset_delay = val;
1948
1949         data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1950         if (data) {
1951                 panel->on_cmds = devm_kzalloc(&dsi->dev,
1952                                               sizeof(*panel->on_cmds),
1953                                               GFP_KERNEL);
1954                 if (!panel->on_cmds)
1955                         return -ENOMEM;
1956
1957                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1958                                                       panel->on_cmds);
1959                 if (err) {
1960                         dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1961                         return err;
1962                 }
1963         }
1964
1965         data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1966         if (data) {
1967                 panel->off_cmds = devm_kzalloc(&dsi->dev,
1968                                                sizeof(*panel->off_cmds),
1969                                                GFP_KERNEL);
1970                 if (!panel->off_cmds)
1971                         return -ENOMEM;
1972
1973                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1974                                                       panel->off_cmds);
1975                 if (err) {
1976                         dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
1977                         return err;
1978                 }
1979         }
1980
1981         return mipi_dsi_attach(dsi);
1982 }
1983
1984 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1985 {
1986         int err;
1987
1988         err = mipi_dsi_detach(dsi);
1989         if (err < 0)
1990                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1991
1992         return panel_simple_remove(&dsi->dev);
1993 }
1994
1995 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1996 {
1997         panel_simple_shutdown(&dsi->dev);
1998 }
1999
2000 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2001         .driver = {
2002                 .name = "panel-simple-dsi",
2003                 .of_match_table = dsi_of_match,
2004         },
2005         .probe = panel_simple_dsi_probe,
2006         .remove = panel_simple_dsi_remove,
2007         .shutdown = panel_simple_dsi_shutdown,
2008 };
2009
2010 static int __init panel_simple_init(void)
2011 {
2012         int err;
2013
2014         err = platform_driver_register(&panel_simple_platform_driver);
2015         if (err < 0)
2016                 return err;
2017
2018         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2019                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2020                 if (err < 0)
2021                         return err;
2022         }
2023
2024         return 0;
2025 }
2026 module_init(panel_simple_init);
2027
2028 static void __exit panel_simple_exit(void)
2029 {
2030         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2031                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2032
2033         platform_driver_unregister(&panel_simple_platform_driver);
2034 }
2035 module_exit(panel_simple_exit);
2036
2037 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2038 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2039 MODULE_LICENSE("GPL and additional rights");