drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/mipi_display.h>
  38 #include <video/of_display_timing.h>
  39 #include <video/videomode.h>
  40
  41 struct dsi_ctrl_hdr {
  42         u8 dtype;       /* data type */
  43         u8 wait;        /* ms */
  44         u8 dlen;        /* payload len */
  45 } __packed;
  46
  47 struct dsi_cmd_desc {
  48         struct dsi_ctrl_hdr dchdr;
  49         u8 *payload;
  50 };
  51
  52 struct dsi_panel_cmds {
  53         u8 *buf;
  54         int blen;
  55         struct dsi_cmd_desc *cmds;
  56         int cmd_cnt;
  57 };
  58
  59 struct panel_desc {
  60         const struct drm_display_mode *modes;
  61         unsigned int num_modes;
  62         const struct display_timing *timings;
  63         unsigned int num_timings;
  64
  65         unsigned int bpc;
  66
  67         struct {
  68                 unsigned int width;
  69                 unsigned int height;
  70         } size;
  71
  72         /**
  73          * @prepare: the time (in milliseconds) that it takes for the panel to
  74          *           become ready and start receiving video data
  75          * @enable: the time (in milliseconds) that it takes for the panel to
  76          *          display the first valid frame after starting to receive
  77          *          video data
  78          * @disable: the time (in milliseconds) that it takes for the panel to
  79          *           turn the display off (no content is visible)
  80          * @unprepare: the time (in milliseconds) that it takes for the panel
  81          *             to power itself down completely
  82          */
  83         struct {
  84                 unsigned int prepare;
  85                 unsigned int enable;
  86                 unsigned int disable;
  87                 unsigned int unprepare;
  88         } delay;
  89
  90         u32 bus_format;
  91 };
  92
  93 struct panel_simple {
  94         struct drm_panel base;
  95         struct mipi_dsi_device *dsi;
  96         bool prepared;
  97         bool enabled;
  98
  99         struct device *dev;
 100         const struct panel_desc *desc;
 101
 102         struct backlight_device *backlight;
 103         struct regulator *supply;
 104         struct i2c_adapter *ddc;
 105
 106         struct gpio_desc *enable_gpio;
 107         struct gpio_desc *reset_gpio;
 108         unsigned int reset_delay;
 109
 110         struct dsi_panel_cmds *on_cmds;
 111         struct dsi_panel_cmds *off_cmds;
 112 };
 113
 114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 115 {
 116         return container_of(panel, struct panel_simple, base);
 117 }
 118
 119 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
 120 {
 121         if (p->on_cmds) {
 122                 kfree(p->on_cmds->buf);
 123                 kfree(p->on_cmds->cmds);
 124         }
 125
 126         if (p->off_cmds) {
 127                 kfree(p->off_cmds->buf);
 128                 kfree(p->off_cmds->cmds);
 129         }
 130 }
 131
 132 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
 133                                            const u8 *data, int blen,
 134                                            struct dsi_panel_cmds *pcmds)
 135 {
 136         int len;
 137         char *buf, *bp;
 138         struct dsi_ctrl_hdr *dchdr;
 139         int i, cnt;
 140
 141         if (!pcmds)
 142                 return -EINVAL;
 143
 144         buf = kmemdup(data, blen, GFP_KERNEL);
 145         if (!buf)
 146                 return -ENOMEM;
 147
 148         /* scan dcs commands */
 149         bp = buf;
 150         len = blen;
 151         cnt = 0;
 152         while (len > sizeof(*dchdr)) {
 153                 dchdr = (struct dsi_ctrl_hdr *)bp;
 154
 155                 if (dchdr->dlen > len) {
 156                         dev_err(dev, "%s: error, len=%d", __func__,
 157                                 dchdr->dlen);
 158                         return -EINVAL;
 159                 }
 160
 161                 bp += sizeof(*dchdr);
 162                 len -= sizeof(*dchdr);
 163                 bp += dchdr->dlen;
 164                 len -= dchdr->dlen;
 165                 cnt++;
 166         }
 167
 168         if (len != 0) {
 169                 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
 170                         __func__, buf[0], blen);
 171                 kfree(buf);
 172                 return -EINVAL;
 173         }
 174
 175         pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
 176         if (!pcmds->cmds) {
 177                 kfree(buf);
 178                 return -ENOMEM;
 179         }
 180
 181         pcmds->cmd_cnt = cnt;
 182         pcmds->buf = buf;
 183         pcmds->blen = blen;
 184
 185         bp = buf;
 186         len = blen;
 187         for (i = 0; i < cnt; i++) {
 188                 dchdr = (struct dsi_ctrl_hdr *)bp;
 189                 len -= sizeof(*dchdr);
 190                 bp += sizeof(*dchdr);
 191                 pcmds->cmds[i].dchdr = *dchdr;
 192                 pcmds->cmds[i].payload = bp;
 193                 bp += dchdr->dlen;
 194                 len -= dchdr->dlen;
 195         }
 196
 197         dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
 198                  pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
 199         return 0;
 200 }
 201
 202 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
 203                                       struct dsi_panel_cmds *cmds)
 204 {
 205         struct mipi_dsi_device *dsi = panel->dsi;
 206         int i, err;
 207
 208         if (!cmds)
 209                 return -EINVAL;
 210
 211         for (i = 0; i < cmds->cmd_cnt; i++) {
 212                 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
 213
 214                 switch (cmd->dchdr.dtype) {
 215                 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 216                 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 217                 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 218                 case MIPI_DSI_GENERIC_LONG_WRITE:
 219                         err = mipi_dsi_generic_write(dsi, cmd->payload,
 220                                                      cmd->dchdr.dlen);
 221                         break;
 222                 case MIPI_DSI_DCS_SHORT_WRITE:
 223                 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 224                 case MIPI_DSI_DCS_LONG_WRITE:
 225                         err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
 226                                                         cmd->dchdr.dlen);
 227                         break;
 228                 default:
 229                         return -EINVAL;
 230                 }
 231
 232                 if (err)
 233                         dev_err(panel->dev, "failed to write dcs cmd: %d\n",
 234                                 err);
 235
 236                 if (cmd->dchdr.wait)
 237                         msleep(cmd->dchdr.wait);
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 244 {
 245         struct drm_connector *connector = panel->base.connector;
 246         struct drm_device *drm = panel->base.drm;
 247         struct drm_display_mode *mode;
 248         unsigned int i, num = 0;
 249
 250         if (!panel->desc)
 251                 return 0;
 252
 253         for (i = 0; i < panel->desc->num_timings; i++) {
 254                 const struct display_timing *dt = &panel->desc->timings[i];
 255                 struct videomode vm;
 256
 257                 videomode_from_timing(dt, &vm);
 258                 mode = drm_mode_create(drm);
 259                 if (!mode) {
 260                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 261                                 dt->hactive.typ, dt->vactive.typ);
 262                         continue;
 263                 }
 264
 265                 drm_display_mode_from_videomode(&vm, mode);
 266                 drm_mode_set_name(mode);
 267
 268                 drm_mode_probed_add(connector, mode);
 269                 num++;
 270         }
 271
 272         for (i = 0; i < panel->desc->num_modes; i++) {
 273                 const struct drm_display_mode *m = &panel->desc->modes[i];
 274
 275                 mode = drm_mode_duplicate(drm, m);
 276                 if (!mode) {
 277                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 278                                 m->hdisplay, m->vdisplay, m->vrefresh);
 279                         continue;
 280                 }
 281
 282                 drm_mode_set_name(mode);
 283
 284                 drm_mode_probed_add(connector, mode);
 285                 num++;
 286         }
 287
 288         connector->display_info.bpc = panel->desc->bpc;
 289         connector->display_info.width_mm = panel->desc->size.width;
 290         connector->display_info.height_mm = panel->desc->size.height;
 291         if (panel->desc->bus_format)
 292                 drm_display_info_set_bus_formats(&connector->display_info,
 293                                                  &panel->desc->bus_format, 1);
 294
 295         return num;
 296 }
 297
 298 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
 299 {
 300         struct drm_connector *connector = panel->base.connector;
 301         struct drm_device *drm = panel->base.drm;
 302         struct drm_display_mode *mode;
 303         struct device_node *timings_np;
 304         int ret;
 305
 306         timings_np = of_get_child_by_name(panel->dev->of_node,
 307                                           "display-timings");
 308         if (!timings_np) {
 309                 dev_dbg(panel->dev, "failed to find display-timings node\n");
 310                 return 0;
 311         }
 312
 313         of_node_put(timings_np);
 314         mode = drm_mode_create(drm);
 315         if (!mode)
 316                 return 0;
 317
 318         ret = of_get_drm_display_mode(panel->dev->of_node, mode,
 319                                       OF_USE_NATIVE_MODE);
 320         if (ret) {
 321                 dev_dbg(panel->dev, "failed to find dts display timings\n");
 322                 drm_mode_destroy(drm, mode);
 323                 return 0;
 324         }
 325
 326         drm_mode_set_name(mode);
 327         mode->type |= DRM_MODE_TYPE_PREFERRED;
 328         drm_mode_probed_add(connector, mode);
 329
 330         return 1;
 331 }
 332
 333 static int panel_simple_disable(struct drm_panel *panel)
 334 {
 335         struct panel_simple *p = to_panel_simple(panel);
 336
 337         if (!p->enabled)
 338                 return 0;
 339
 340         if (p->backlight) {
 341                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 342                 backlight_update_status(p->backlight);
 343         }
 344
 345         if (p->desc && p->desc->delay.disable)
 346                 msleep(p->desc->delay.disable);
 347
 348         p->enabled = false;
 349
 350         return 0;
 351 }
 352
 353 static int panel_simple_unprepare(struct drm_panel *panel)
 354 {
 355         struct panel_simple *p = to_panel_simple(panel);
 356         int err;
 357
 358         if (!p->prepared)
 359                 return 0;
 360
 361         if (p->off_cmds) {
 362                 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
 363                 if (err)
 364                         dev_err(p->dev, "failed to send off cmds\n");
 365         }
 366
 367         if (p->reset_gpio)
 368                 gpiod_direction_output(p->reset_gpio, 1);
 369
 370         if (p->enable_gpio)
 371                 gpiod_direction_output(p->enable_gpio, 0);
 372
 373         regulator_disable(p->supply);
 374
 375         if (p->desc && p->desc->delay.unprepare)
 376                 msleep(p->desc->delay.unprepare);
 377
 378         p->prepared = false;
 379
 380         return 0;
 381 }
 382
 383 static int panel_simple_prepare(struct drm_panel *panel)
 384 {
 385         struct panel_simple *p = to_panel_simple(panel);
 386         int err;
 387
 388         if (p->prepared)
 389                 return 0;
 390
 391         err = regulator_enable(p->supply);
 392         if (err < 0) {
 393                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 394                 return err;
 395         }
 396
 397         if (p->enable_gpio)
 398                 gpiod_direction_output(p->enable_gpio, 1);
 399
 400         if (p->desc && p->desc->delay.prepare)
 401                 msleep(p->desc->delay.prepare);
 402
 403         if (p->reset_gpio)
 404                 gpiod_direction_output(p->reset_gpio, 1);
 405
 406         if (p->reset_delay)
 407                 msleep(p->reset_delay);
 408
 409         if (p->reset_gpio)
 410                 gpiod_direction_output(p->reset_gpio, 0);
 411
 412         p->prepared = true;
 413
 414         return 0;
 415 }
 416
 417 static int panel_simple_enable(struct drm_panel *panel)
 418 {
 419         struct panel_simple *p = to_panel_simple(panel);
 420         int err;
 421
 422         if (p->enabled)
 423                 return 0;
 424
 425         if (p->on_cmds) {
 426                 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
 427                 if (err)
 428                         dev_err(p->dev, "failed to send on cmds\n");
 429         }
 430
 431         if (p->desc && p->desc->delay.enable)
 432                 msleep(p->desc->delay.enable);
 433
 434         if (p->backlight) {
 435                 p->backlight->props.power = FB_BLANK_UNBLANK;
 436                 backlight_update_status(p->backlight);
 437         }
 438
 439         p->enabled = true;
 440
 441         return 0;
 442 }
 443
 444 static int panel_simple_get_modes(struct drm_panel *panel)
 445 {
 446         struct panel_simple *p = to_panel_simple(panel);
 447         int num = 0;
 448
 449         /* add device node plane modes */
 450         num += panel_simple_of_get_native_mode(p);
 451
 452         /* add hard-coded panel modes */
 453         num += panel_simple_get_fixed_modes(p);
 454
 455         /* probe EDID if a DDC bus is available */
 456         if (p->ddc) {
 457                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 458                 drm_mode_connector_update_edid_property(panel->connector, edid);
 459                 if (edid) {
 460                         num += drm_add_edid_modes(panel->connector, edid);
 461                         kfree(edid);
 462                 }
 463         }
 464
 465         return num;
 466 }
 467
 468 static int panel_simple_get_timings(struct drm_panel *panel,
 469                                     unsigned int num_timings,
 470                                     struct display_timing *timings)
 471 {
 472         struct panel_simple *p = to_panel_simple(panel);
 473         unsigned int i;
 474
 475         if (!p->desc)
 476                 return 0;
 477
 478         if (p->desc->num_timings < num_timings)
 479                 num_timings = p->desc->num_timings;
 480
 481         if (timings)
 482                 for (i = 0; i < num_timings; i++)
 483                         timings[i] = p->desc->timings[i];
 484
 485         return p->desc->num_timings;
 486 }
 487
 488 static const struct drm_panel_funcs panel_simple_funcs = {
 489         .disable = panel_simple_disable,
 490         .unprepare = panel_simple_unprepare,
 491         .prepare = panel_simple_prepare,
 492         .enable = panel_simple_enable,
 493         .get_modes = panel_simple_get_modes,
 494         .get_timings = panel_simple_get_timings,
 495 };
 496
 497 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 498 {
 499         struct device_node *backlight, *ddc;
 500         struct panel_simple *panel;
 501         struct panel_desc *of_desc;
 502         u32 val;
 503         int err;
 504
 505         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 506         if (!panel)
 507                 return -ENOMEM;
 508
 509         if (!desc)
 510                 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
 511         else
 512                 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
 513
 514         if (!of_property_read_u32(dev->of_node, "bus-format", &val))
 515                 of_desc->bus_format = val;
 516         if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
 517                 of_desc->delay.prepare = val;
 518         if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
 519                 of_desc->delay.enable = val;
 520         if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
 521                 of_desc->delay.disable = val;
 522         if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
 523                 of_desc->delay.unprepare = val;
 524
 525         panel->enabled = false;
 526         panel->prepared = false;
 527         panel->desc = of_desc;
 528         panel->dev = dev;
 529
 530         panel->supply = devm_regulator_get(dev, "power");
 531         if (IS_ERR(panel->supply))
 532                 return PTR_ERR(panel->supply);
 533
 534         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
 535         if (IS_ERR(panel->enable_gpio)) {
 536                 err = PTR_ERR(panel->enable_gpio);
 537                 dev_err(dev, "failed to request enable GPIO: %d\n", err);
 538                 return err;
 539         }
 540
 541         panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
 542         if (IS_ERR(panel->reset_gpio)) {
 543                 err = PTR_ERR(panel->reset_gpio);
 544                 dev_err(dev, "failed to request reset GPIO: %d\n", err);
 545                 return err;
 546         }
 547
 548         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 549         if (backlight) {
 550                 panel->backlight = of_find_backlight_by_node(backlight);
 551                 of_node_put(backlight);
 552
 553                 if (!panel->backlight)
 554                         return -EPROBE_DEFER;
 555         }
 556
 557         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 558         if (ddc) {
 559                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 560                 of_node_put(ddc);
 561
 562                 if (!panel->ddc) {
 563                         err = -EPROBE_DEFER;
 564                         goto free_backlight;
 565                 }
 566         }
 567
 568         drm_panel_init(&panel->base);
 569         panel->base.dev = dev;
 570         panel->base.funcs = &panel_simple_funcs;
 571
 572         err = drm_panel_add(&panel->base);
 573         if (err < 0)
 574                 goto free_ddc;
 575
 576         dev_set_drvdata(dev, panel);
 577
 578         return 0;
 579
 580 free_ddc:
 581         if (panel->ddc)
 582                 put_device(&panel->ddc->dev);
 583 free_backlight:
 584         if (panel->backlight)
 585                 put_device(&panel->backlight->dev);
 586
 587         return err;
 588 }
 589
 590 static int panel_simple_remove(struct device *dev)
 591 {
 592         struct panel_simple *panel = dev_get_drvdata(dev);
 593
 594         drm_panel_detach(&panel->base);
 595         drm_panel_remove(&panel->base);
 596
 597         panel_simple_disable(&panel->base);
 598
 599         if (panel->ddc)
 600                 put_device(&panel->ddc->dev);
 601
 602         if (panel->backlight)
 603                 put_device(&panel->backlight->dev);
 604
 605         panel_simple_dsi_cmds_cleanup(panel);
 606
 607         return 0;
 608 }
 609
 610 static void panel_simple_shutdown(struct device *dev)
 611 {
 612         struct panel_simple *panel = dev_get_drvdata(dev);
 613
 614         panel_simple_disable(&panel->base);
 615 }
 616
 617 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 618         .clock = 33333,
 619         .hdisplay = 800,
 620         .hsync_start = 800 + 0,
 621         .hsync_end = 800 + 0 + 255,
 622         .htotal = 800 + 0 + 255 + 0,
 623         .vdisplay = 480,
 624         .vsync_start = 480 + 2,
 625         .vsync_end = 480 + 2 + 45,
 626         .vtotal = 480 + 2 + 45 + 0,
 627         .vrefresh = 60,
 628         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 629 };
 630
 631 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 632         .modes = &ampire_am800480r3tmqwa1h_mode,
 633         .num_modes = 1,
 634         .bpc = 6,
 635         .size = {
 636                 .width = 152,
 637                 .height = 91,
 638         },
 639         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 640 };
 641
 642 static const struct drm_display_mode auo_b101aw03_mode = {
 643         .clock = 51450,
 644         .hdisplay = 1024,
 645         .hsync_start = 1024 + 156,
 646         .hsync_end = 1024 + 156 + 8,
 647         .htotal = 1024 + 156 + 8 + 156,
 648         .vdisplay = 600,
 649         .vsync_start = 600 + 16,
 650         .vsync_end = 600 + 16 + 6,
 651         .vtotal = 600 + 16 + 6 + 16,
 652         .vrefresh = 60,
 653 };
 654
 655 static const struct panel_desc auo_b101aw03 = {
 656         .modes = &auo_b101aw03_mode,
 657         .num_modes = 1,
 658         .bpc = 6,
 659         .size = {
 660                 .width = 223,
 661                 .height = 125,
 662         },
 663 };
 664
 665 static const struct drm_display_mode auo_b101ean01_mode = {
 666         .clock = 72500,
 667         .hdisplay = 1280,
 668         .hsync_start = 1280 + 119,
 669         .hsync_end = 1280 + 119 + 32,
 670         .htotal = 1280 + 119 + 32 + 21,
 671         .vdisplay = 800,
 672         .vsync_start = 800 + 4,
 673         .vsync_end = 800 + 4 + 20,
 674         .vtotal = 800 + 4 + 20 + 8,
 675         .vrefresh = 60,
 676 };
 677
 678 static const struct panel_desc auo_b101ean01 = {
 679         .modes = &auo_b101ean01_mode,
 680         .num_modes = 1,
 681         .bpc = 6,
 682         .size = {
 683                 .width = 217,
 684                 .height = 136,
 685         },
 686 };
 687
 688 static const struct drm_display_mode auo_b101ew05_mode = {
 689         .clock = 71000,
 690         .hdisplay = 1280,
 691         .hsync_start = 1280 + 18,
 692         .hsync_end = 1280 + 18 + 10,
 693         .htotal = 1280 + 18 + 10 + 100,
 694         .vdisplay = 800,
 695         .vsync_start = 800 + 6,
 696         .vsync_end = 800 + 6 + 2,
 697         .vtotal = 800 + 6 + 2 + 8,
 698         .vrefresh = 60,
 699 };
 700
 701 static const struct panel_desc auo_b101ew05 = {
 702         .modes = &auo_b101ew05_mode,
 703         .num_modes = 1,
 704         .bpc = 6,
 705         .size = {
 706                 .width = 217,
 707                 .height = 136,
 708         },
 709 };
 710
 711 static const struct drm_display_mode auo_b101xtn01_mode = {
 712         .clock = 72000,
 713         .hdisplay = 1366,
 714         .hsync_start = 1366 + 20,
 715         .hsync_end = 1366 + 20 + 70,
 716         .htotal = 1366 + 20 + 70,
 717         .vdisplay = 768,
 718         .vsync_start = 768 + 14,
 719         .vsync_end = 768 + 14 + 42,
 720         .vtotal = 768 + 14 + 42,
 721         .vrefresh = 60,
 722         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 723 };
 724
 725 static const struct panel_desc auo_b101xtn01 = {
 726         .modes = &auo_b101xtn01_mode,
 727         .num_modes = 1,
 728         .bpc = 6,
 729         .size = {
 730                 .width = 223,
 731                 .height = 125,
 732         },
 733 };
 734
 735 static const struct drm_display_mode auo_b116xw03_mode = {
 736         .clock = 70589,
 737         .hdisplay = 1366,
 738         .hsync_start = 1366 + 40,
 739         .hsync_end = 1366 + 40 + 40,
 740         .htotal = 1366 + 40 + 40 + 32,
 741         .vdisplay = 768,
 742         .vsync_start = 768 + 10,
 743         .vsync_end = 768 + 10 + 12,
 744         .vtotal = 768 + 10 + 12 + 6,
 745         .vrefresh = 60,
 746 };
 747
 748 static const struct panel_desc auo_b116xw03 = {
 749         .modes = &auo_b116xw03_mode,
 750         .num_modes = 1,
 751         .bpc = 6,
 752         .size = {
 753                 .width = 256,
 754                 .height = 144,
 755         },
 756 };
 757
 758 static const struct drm_display_mode auo_b125han03_mode = {
 759         .clock = 146900,
 760         .hdisplay = 1920,
 761         .hsync_start = 1920 + 48,
 762         .hsync_end = 1920 + 48 + 32,
 763         .htotal = 1920 + 48 + 32 + 140,
 764         .vdisplay = 1080,
 765         .vsync_start = 1080 + 2,
 766         .vsync_end = 1080 + 2 + 5,
 767         .vtotal = 1080 + 2 + 5 + 57,
 768         .vrefresh = 60,
 769         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 770 };
 771
 772 static const struct panel_desc auo_b125han03 = {
 773         .modes = &auo_b125han03_mode,
 774         .num_modes = 1,
 775         .bpc = 6,
 776         .size = {
 777                 .width = 276,
 778                 .height = 156,
 779         },
 780         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 781 };
 782
 783 static const struct drm_display_mode auo_b133xtn01_mode = {
 784         .clock = 69500,
 785         .hdisplay = 1366,
 786         .hsync_start = 1366 + 48,
 787         .hsync_end = 1366 + 48 + 32,
 788         .htotal = 1366 + 48 + 32 + 20,
 789         .vdisplay = 768,
 790         .vsync_start = 768 + 3,
 791         .vsync_end = 768 + 3 + 6,
 792         .vtotal = 768 + 3 + 6 + 13,
 793         .vrefresh = 60,
 794 };
 795
 796 static const struct panel_desc auo_b133xtn01 = {
 797         .modes = &auo_b133xtn01_mode,
 798         .num_modes = 1,
 799         .bpc = 6,
 800         .size = {
 801                 .width = 293,
 802                 .height = 165,
 803         },
 804 };
 805
 806 static const struct drm_display_mode auo_b133htn01_mode = {
 807         .clock = 150660,
 808         .hdisplay = 1920,
 809         .hsync_start = 1920 + 172,
 810         .hsync_end = 1920 + 172 + 80,
 811         .htotal = 1920 + 172 + 80 + 60,
 812         .vdisplay = 1080,
 813         .vsync_start = 1080 + 25,
 814         .vsync_end = 1080 + 25 + 10,
 815         .vtotal = 1080 + 25 + 10 + 10,
 816         .vrefresh = 60,
 817 };
 818
 819 static const struct panel_desc auo_b133htn01 = {
 820         .modes = &auo_b133htn01_mode,
 821         .num_modes = 1,
 822         .bpc = 6,
 823         .size = {
 824                 .width = 293,
 825                 .height = 165,
 826         },
 827         .delay = {
 828                 .prepare = 105,
 829                 .enable = 20,
 830                 .unprepare = 50,
 831         },
 832 };
 833
 834 static const struct drm_display_mode avic_tm070ddh03_mode = {
 835         .clock = 51200,
 836         .hdisplay = 1024,
 837         .hsync_start = 1024 + 160,
 838         .hsync_end = 1024 + 160 + 4,
 839         .htotal = 1024 + 160 + 4 + 156,
 840         .vdisplay = 600,
 841         .vsync_start = 600 + 17,
 842         .vsync_end = 600 + 17 + 1,
 843         .vtotal = 600 + 17 + 1 + 17,
 844         .vrefresh = 60,
 845 };
 846
 847 static const struct panel_desc avic_tm070ddh03 = {
 848         .modes = &avic_tm070ddh03_mode,
 849         .num_modes = 1,
 850         .bpc = 8,
 851         .size = {
 852                 .width = 154,
 853                 .height = 90,
 854         },
 855         .delay = {
 856                 .prepare = 20,
 857                 .enable = 200,
 858                 .disable = 200,
 859         },
 860 };
 861
 862 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
 863         .clock = 72300,
 864         .hdisplay = 1366,
 865         .hsync_start = 1366 + 80,
 866         .hsync_end = 1366 + 80 + 20,
 867         .htotal = 1366 + 80 + 20 + 60,
 868         .vdisplay = 768,
 869         .vsync_start = 768 + 12,
 870         .vsync_end = 768 + 12 + 2,
 871         .vtotal = 768 + 12 + 2 + 8,
 872         .vrefresh = 60,
 873         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 874 };
 875
 876 static const struct panel_desc boe_nv125fhm_n73 = {
 877         .modes = &boe_nv125fhm_n73_mode,
 878         .num_modes = 1,
 879         .bpc = 6,
 880         .size = {
 881                 .width = 276,
 882                 .height = 156,
 883         },
 884         .delay = {
 885                 .unprepare = 160,
 886         },
 887         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 888 };
 889
 890 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 891         .clock = 67000,
 892         .hdisplay = 800,
 893         .hsync_start = 800 + 24,
 894         .hsync_end = 800 + 24 + 16,
 895         .htotal = 800 + 24 + 16 + 24,
 896         .vdisplay = 1280,
 897         .vsync_start = 1280 + 2,
 898         .vsync_end = 1280 + 2 + 2,
 899         .vtotal = 1280 + 2 + 2 + 4,
 900         .vrefresh = 60,
 901 };
 902
 903 static const struct panel_desc chunghwa_claa070wp03xg = {
 904         .modes = &chunghwa_claa070wp03xg_mode,
 905         .num_modes = 1,
 906         .bpc = 6,
 907         .size = {
 908                 .width = 94,
 909                 .height = 151,
 910         },
 911 };
 912
 913 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 914         .clock = 72070,
 915         .hdisplay = 1366,
 916         .hsync_start = 1366 + 58,
 917         .hsync_end = 1366 + 58 + 58,
 918         .htotal = 1366 + 58 + 58 + 58,
 919         .vdisplay = 768,
 920         .vsync_start = 768 + 4,
 921         .vsync_end = 768 + 4 + 4,
 922         .vtotal = 768 + 4 + 4 + 4,
 923         .vrefresh = 60,
 924 };
 925
 926 static const struct panel_desc chunghwa_claa101wa01a = {
 927         .modes = &chunghwa_claa101wa01a_mode,
 928         .num_modes = 1,
 929         .bpc = 6,
 930         .size = {
 931                 .width = 220,
 932                 .height = 120,
 933         },
 934 };
 935
 936 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 937         .clock = 69300,
 938         .hdisplay = 1366,
 939         .hsync_start = 1366 + 48,
 940         .hsync_end = 1366 + 48 + 32,
 941         .htotal = 1366 + 48 + 32 + 20,
 942         .vdisplay = 768,
 943         .vsync_start = 768 + 16,
 944         .vsync_end = 768 + 16 + 8,
 945         .vtotal = 768 + 16 + 8 + 16,
 946         .vrefresh = 60,
 947 };
 948
 949 static const struct panel_desc chunghwa_claa101wb01 = {
 950         .modes = &chunghwa_claa101wb01_mode,
 951         .num_modes = 1,
 952         .bpc = 6,
 953         .size = {
 954                 .width = 223,
 955                 .height = 125,
 956         },
 957 };
 958
 959 static const struct drm_display_mode edt_et057090dhu_mode = {
 960         .clock = 25175,
 961         .hdisplay = 640,
 962         .hsync_start = 640 + 16,
 963         .hsync_end = 640 + 16 + 30,
 964         .htotal = 640 + 16 + 30 + 114,
 965         .vdisplay = 480,
 966         .vsync_start = 480 + 10,
 967         .vsync_end = 480 + 10 + 3,
 968         .vtotal = 480 + 10 + 3 + 32,
 969         .vrefresh = 60,
 970         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 971 };
 972
 973 static const struct panel_desc edt_et057090dhu = {
 974         .modes = &edt_et057090dhu_mode,
 975         .num_modes = 1,
 976         .bpc = 6,
 977         .size = {
 978                 .width = 115,
 979                 .height = 86,
 980         },
 981 };
 982
 983 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
 984         .clock = 33260,
 985         .hdisplay = 800,
 986         .hsync_start = 800 + 40,
 987         .hsync_end = 800 + 40 + 128,
 988         .htotal = 800 + 40 + 128 + 88,
 989         .vdisplay = 480,
 990         .vsync_start = 480 + 10,
 991         .vsync_end = 480 + 10 + 2,
 992         .vtotal = 480 + 10 + 2 + 33,
 993         .vrefresh = 60,
 994         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 995 };
 996
 997 static const struct panel_desc edt_etm0700g0dh6 = {
 998         .modes = &edt_etm0700g0dh6_mode,
 999         .num_modes = 1,
1000         .bpc = 6,
1001         .size = {
1002                 .width = 152,
1003                 .height = 91,
1004         },
1005 };
1006
1007 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1008         .clock = 32260,
1009         .hdisplay = 800,
1010         .hsync_start = 800 + 168,
1011         .hsync_end = 800 + 168 + 64,
1012         .htotal = 800 + 168 + 64 + 88,
1013         .vdisplay = 480,
1014         .vsync_start = 480 + 37,
1015         .vsync_end = 480 + 37 + 2,
1016         .vtotal = 480 + 37 + 2 + 8,
1017         .vrefresh = 60,
1018 };
1019
1020 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1021         .modes = &foxlink_fl500wvr00_a0t_mode,
1022         .num_modes = 1,
1023         .bpc = 8,
1024         .size = {
1025                 .width = 108,
1026                 .height = 65,
1027         },
1028         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1029 };
1030
1031 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1032         .clock = 9000,
1033         .hdisplay = 480,
1034         .hsync_start = 480 + 5,
1035         .hsync_end = 480 + 5 + 1,
1036         .htotal = 480 + 5 + 1 + 40,
1037         .vdisplay = 272,
1038         .vsync_start = 272 + 8,
1039         .vsync_end = 272 + 8 + 1,
1040         .vtotal = 272 + 8 + 1 + 8,
1041         .vrefresh = 60,
1042 };
1043
1044 static const struct panel_desc giantplus_gpg482739qs5 = {
1045         .modes = &giantplus_gpg482739qs5_mode,
1046         .num_modes = 1,
1047         .bpc = 8,
1048         .size = {
1049                 .width = 95,
1050                 .height = 54,
1051         },
1052         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1053 };
1054
1055 static const struct display_timing hannstar_hsd070pww1_timing = {
1056         .pixelclock = { 64300000, 71100000, 82000000 },
1057         .hactive = { 1280, 1280, 1280 },
1058         .hfront_porch = { 1, 1, 10 },
1059         .hback_porch = { 1, 1, 10 },
1060         /*
1061          * According to the data sheet, the minimum horizontal blanking interval
1062          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1063          * minimum working horizontal blanking interval to be 60 clocks.
1064          */
1065         .hsync_len = { 58, 158, 661 },
1066         .vactive = { 800, 800, 800 },
1067         .vfront_porch = { 1, 1, 10 },
1068         .vback_porch = { 1, 1, 10 },
1069         .vsync_len = { 1, 21, 203 },
1070         .flags = DISPLAY_FLAGS_DE_HIGH,
1071 };
1072
1073 static const struct panel_desc hannstar_hsd070pww1 = {
1074         .timings = &hannstar_hsd070pww1_timing,
1075         .num_timings = 1,
1076         .bpc = 6,
1077         .size = {
1078                 .width = 151,
1079                 .height = 94,
1080         },
1081         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1082 };
1083
1084 static const struct display_timing hannstar_hsd100pxn1_timing = {
1085         .pixelclock = { 55000000, 65000000, 75000000 },
1086         .hactive = { 1024, 1024, 1024 },
1087         .hfront_porch = { 40, 40, 40 },
1088         .hback_porch = { 220, 220, 220 },
1089         .hsync_len = { 20, 60, 100 },
1090         .vactive = { 768, 768, 768 },
1091         .vfront_porch = { 7, 7, 7 },
1092         .vback_porch = { 21, 21, 21 },
1093         .vsync_len = { 10, 10, 10 },
1094         .flags = DISPLAY_FLAGS_DE_HIGH,
1095 };
1096
1097 static const struct panel_desc hannstar_hsd100pxn1 = {
1098         .timings = &hannstar_hsd100pxn1_timing,
1099         .num_timings = 1,
1100         .bpc = 6,
1101         .size = {
1102                 .width = 203,
1103                 .height = 152,
1104         },
1105         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1106 };
1107
1108 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1109         .clock = 33333,
1110         .hdisplay = 800,
1111         .hsync_start = 800 + 85,
1112         .hsync_end = 800 + 85 + 86,
1113         .htotal = 800 + 85 + 86 + 85,
1114         .vdisplay = 480,
1115         .vsync_start = 480 + 16,
1116         .vsync_end = 480 + 16 + 13,
1117         .vtotal = 480 + 16 + 13 + 16,
1118         .vrefresh = 60,
1119 };
1120
1121 static const struct panel_desc hitachi_tx23d38vm0caa = {
1122         .modes = &hitachi_tx23d38vm0caa_mode,
1123         .num_modes = 1,
1124         .bpc = 6,
1125         .size = {
1126                 .width = 195,
1127                 .height = 117,
1128         },
1129 };
1130
1131 static const struct drm_display_mode innolux_at043tn24_mode = {
1132         .clock = 9000,
1133         .hdisplay = 480,
1134         .hsync_start = 480 + 2,
1135         .hsync_end = 480 + 2 + 41,
1136         .htotal = 480 + 2 + 41 + 2,
1137         .vdisplay = 272,
1138         .vsync_start = 272 + 2,
1139         .vsync_end = 272 + 2 + 11,
1140         .vtotal = 272 + 2 + 11 + 2,
1141         .vrefresh = 60,
1142         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1143 };
1144
1145 static const struct panel_desc innolux_at043tn24 = {
1146         .modes = &innolux_at043tn24_mode,
1147         .num_modes = 1,
1148         .bpc = 8,
1149         .size = {
1150                 .width = 95,
1151                 .height = 54,
1152         },
1153         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1154 };
1155
1156 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1157         .clock = 71000,
1158         .hdisplay = 1280,
1159         .hsync_start = 1280 + 64,
1160         .hsync_end = 1280 + 64 + 32,
1161         .htotal = 1280 + 64 + 32 + 64,
1162         .vdisplay = 800,
1163         .vsync_start = 800 + 9,
1164         .vsync_end = 800 + 9 + 6,
1165         .vtotal = 800 + 9 + 6 + 9,
1166         .vrefresh = 60,
1167 };
1168
1169 static const struct panel_desc innolux_g121i1_l01 = {
1170         .modes = &innolux_g121i1_l01_mode,
1171         .num_modes = 1,
1172         .bpc = 6,
1173         .size = {
1174                 .width = 261,
1175                 .height = 163,
1176         },
1177 };
1178
1179 static const struct drm_display_mode innolux_n116bge_mode = {
1180         .clock = 76420,
1181         .hdisplay = 1366,
1182         .hsync_start = 1366 + 136,
1183         .hsync_end = 1366 + 136 + 30,
1184         .htotal = 1366 + 136 + 30 + 60,
1185         .vdisplay = 768,
1186         .vsync_start = 768 + 8,
1187         .vsync_end = 768 + 8 + 12,
1188         .vtotal = 768 + 8 + 12 + 12,
1189         .vrefresh = 60,
1190         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1191 };
1192
1193 static const struct panel_desc innolux_n116bge = {
1194         .modes = &innolux_n116bge_mode,
1195         .num_modes = 1,
1196         .bpc = 6,
1197         .size = {
1198                 .width = 256,
1199                 .height = 144,
1200         },
1201 };
1202
1203 static const struct drm_display_mode innolux_n125hce_mode = {
1204         .clock = 138780,
1205         .hdisplay = 1920,
1206         .hsync_start = 1920 + 80,
1207         .hsync_end = 1920 + 80 + 30,
1208         .htotal = 1920 + 80 + 30 + 50,
1209         .vdisplay = 1080,
1210         .vsync_start = 1080 + 12,
1211         .vsync_end = 1080 + 12 + 4,
1212         .vtotal = 1080 + 12 + 4 + 16,
1213         .vrefresh = 60,
1214         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1215 };
1216
1217 static const struct panel_desc innolux_n125hce = {
1218         .modes = &innolux_n125hce_mode,
1219         .num_modes = 1,
1220         .bpc = 6,
1221         .size = {
1222                 .width = 283,
1223                 .height = 168,
1224         },
1225         .delay = {
1226                 .unprepare = 600,
1227                 .enable = 100,
1228         },
1229         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1230 };
1231
1232 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1233         .clock = 69300,
1234         .hdisplay = 1366,
1235         .hsync_start = 1366 + 16,
1236         .hsync_end = 1366 + 16 + 34,
1237         .htotal = 1366 + 16 + 34 + 50,
1238         .vdisplay = 768,
1239         .vsync_start = 768 + 2,
1240         .vsync_end = 768 + 2 + 6,
1241         .vtotal = 768 + 2 + 6 + 12,
1242         .vrefresh = 60,
1243 };
1244
1245 static const struct panel_desc innolux_n156bge_l21 = {
1246         .modes = &innolux_n156bge_l21_mode,
1247         .num_modes = 1,
1248         .bpc = 6,
1249         .size = {
1250                 .width = 344,
1251                 .height = 193,
1252         },
1253 };
1254
1255 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1256         .clock = 51501,
1257         .hdisplay = 1024,
1258         .hsync_start = 1024 + 128,
1259         .hsync_end = 1024 + 128 + 64,
1260         .htotal = 1024 + 128 + 64 + 128,
1261         .vdisplay = 600,
1262         .vsync_start = 600 + 16,
1263         .vsync_end = 600 + 16 + 4,
1264         .vtotal = 600 + 16 + 4 + 16,
1265         .vrefresh = 60,
1266 };
1267
1268 static const struct panel_desc innolux_zj070na_01p = {
1269         .modes = &innolux_zj070na_01p_mode,
1270         .num_modes = 1,
1271         .bpc = 6,
1272         .size = {
1273                 .width = 1024,
1274                 .height = 600,
1275         },
1276 };
1277
1278 static const struct drm_display_mode lg_lb070wv8_mode = {
1279         .clock = 33246,
1280         .hdisplay = 800,
1281         .hsync_start = 800 + 88,
1282         .hsync_end = 800 + 88 + 80,
1283         .htotal = 800 + 88 + 80 + 88,
1284         .vdisplay = 480,
1285         .vsync_start = 480 + 10,
1286         .vsync_end = 480 + 10 + 25,
1287         .vtotal = 480 + 10 + 25 + 10,
1288         .vrefresh = 60,
1289 };
1290
1291 static const struct panel_desc lg_lb070wv8 = {
1292         .modes = &lg_lb070wv8_mode,
1293         .num_modes = 1,
1294         .bpc = 16,
1295         .size = {
1296                 .width = 151,
1297                 .height = 91,
1298         },
1299         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1300 };
1301
1302 static const struct drm_display_mode sharp_lcd_f402_mode = {
1303         .clock = 205000,
1304         .hdisplay = 1536,
1305         .hsync_start = 1536 + 12,
1306         .hsync_end = 1536 + 12 + 48,
1307         .htotal = 1536 + 12 + 48 + 16,
1308         .vdisplay = 2048,
1309         .vsync_start = 2048 + 8,
1310         .vsync_end = 2048 + 8 + 8,
1311         .vtotal = 2048 + 8 + 8 + 4,
1312         .vrefresh = 60,
1313         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1314 };
1315
1316 static const struct panel_desc sharp_lcd_f402 = {
1317         .modes = &sharp_lcd_f402_mode,
1318         .num_modes = 1,
1319         .bpc = 8,
1320         .size = {
1321                 .width = 95,
1322                 .height = 54,
1323         },
1324         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1325 };
1326
1327 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1328         .clock = 200000,
1329         .hdisplay = 1536,
1330         .hsync_start = 1536 + 12,
1331         .hsync_end = 1536 + 12 + 16,
1332         .htotal = 1536 + 12 + 16 + 48,
1333         .vdisplay = 2048,
1334         .vsync_start = 2048 + 8,
1335         .vsync_end = 2048 + 8 + 4,
1336         .vtotal = 2048 + 8 + 4 + 8,
1337         .vrefresh = 60,
1338         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1339 };
1340
1341 static const struct panel_desc lg_lp079qx1_sp0v = {
1342         .modes = &lg_lp079qx1_sp0v_mode,
1343         .num_modes = 1,
1344         .size = {
1345                 .width = 129,
1346                 .height = 171,
1347         },
1348         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1349 };
1350
1351 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1352         .clock = 205210,
1353         .hdisplay = 2048,
1354         .hsync_start = 2048 + 150,
1355         .hsync_end = 2048 + 150 + 5,
1356         .htotal = 2048 + 150 + 5 + 5,
1357         .vdisplay = 1536,
1358         .vsync_start = 1536 + 3,
1359         .vsync_end = 1536 + 3 + 1,
1360         .vtotal = 1536 + 3 + 1 + 9,
1361         .vrefresh = 60,
1362 };
1363
1364 static const struct panel_desc lg_lp097qx1_spa1 = {
1365         .modes = &lg_lp097qx1_spa1_mode,
1366         .num_modes = 1,
1367         .size = {
1368                 .width = 320,
1369                 .height = 187,
1370         },
1371 };
1372
1373 static const struct drm_display_mode lg_lp129qe_mode = {
1374         .clock = 285250,
1375         .hdisplay = 2560,
1376         .hsync_start = 2560 + 48,
1377         .hsync_end = 2560 + 48 + 32,
1378         .htotal = 2560 + 48 + 32 + 80,
1379         .vdisplay = 1700,
1380         .vsync_start = 1700 + 3,
1381         .vsync_end = 1700 + 3 + 10,
1382         .vtotal = 1700 + 3 + 10 + 36,
1383         .vrefresh = 60,
1384 };
1385
1386 static const struct panel_desc lg_lp129qe = {
1387         .modes = &lg_lp129qe_mode,
1388         .num_modes = 1,
1389         .bpc = 8,
1390         .size = {
1391                 .width = 272,
1392                 .height = 181,
1393         },
1394 };
1395
1396 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1397         .clock = 10870,
1398         .hdisplay = 480,
1399         .hsync_start = 480 + 2,
1400         .hsync_end = 480 + 2 + 41,
1401         .htotal = 480 + 2 + 41 + 2,
1402         .vdisplay = 272,
1403         .vsync_start = 272 + 2,
1404         .vsync_end = 272 + 2 + 4,
1405         .vtotal = 272 + 2 + 4 + 2,
1406         .vrefresh = 74,
1407 };
1408
1409 static const struct panel_desc nec_nl4827hc19_05b = {
1410         .modes = &nec_nl4827hc19_05b_mode,
1411         .num_modes = 1,
1412         .bpc = 8,
1413         .size = {
1414                 .width = 95,
1415                 .height = 54,
1416         },
1417         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1418 };
1419
1420 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1421         .pixelclock = { 30000000, 30000000, 40000000 },
1422         .hactive = { 800, 800, 800 },
1423         .hfront_porch = { 40, 40, 40 },
1424         .hback_porch = { 40, 40, 40 },
1425         .hsync_len = { 1, 48, 48 },
1426         .vactive = { 480, 480, 480 },
1427         .vfront_porch = { 13, 13, 13 },
1428         .vback_porch = { 29, 29, 29 },
1429         .vsync_len = { 3, 3, 3 },
1430         .flags = DISPLAY_FLAGS_DE_HIGH,
1431 };
1432
1433 static const struct panel_desc okaya_rs800480t_7x0gp = {
1434         .timings = &okaya_rs800480t_7x0gp_timing,
1435         .num_timings = 1,
1436         .bpc = 6,
1437         .size = {
1438                 .width = 154,
1439                 .height = 87,
1440         },
1441         .delay = {
1442                 .prepare = 41,
1443                 .enable = 50,
1444                 .unprepare = 41,
1445                 .disable = 50,
1446         },
1447         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1448 };
1449
1450 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1451         .clock = 25000,
1452         .hdisplay = 480,
1453         .hsync_start = 480 + 10,
1454         .hsync_end = 480 + 10 + 10,
1455         .htotal = 480 + 10 + 10 + 15,
1456         .vdisplay = 800,
1457         .vsync_start = 800 + 3,
1458         .vsync_end = 800 + 3 + 3,
1459         .vtotal = 800 + 3 + 3 + 3,
1460         .vrefresh = 60,
1461 };
1462
1463 static const struct panel_desc ortustech_com43h4m85ulc = {
1464         .modes = &ortustech_com43h4m85ulc_mode,
1465         .num_modes = 1,
1466         .bpc = 8,
1467         .size = {
1468                 .width = 56,
1469                 .height = 93,
1470         },
1471         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1472 };
1473
1474 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1475         .clock = 271560,
1476         .hdisplay = 2560,
1477         .hsync_start = 2560 + 48,
1478         .hsync_end = 2560 + 48 + 32,
1479         .htotal = 2560 + 48 + 32 + 80,
1480         .vdisplay = 1600,
1481         .vsync_start = 1600 + 2,
1482         .vsync_end = 1600 + 2 + 5,
1483         .vtotal = 1600 + 2 + 5 + 57,
1484         .vrefresh = 60,
1485 };
1486
1487 static const struct panel_desc samsung_lsn122dl01_c01 = {
1488         .modes = &samsung_lsn122dl01_c01_mode,
1489         .num_modes = 1,
1490         .size = {
1491                 .width = 2560,
1492                 .height = 1600,
1493         },
1494 };
1495
1496 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1497         .clock = 54030,
1498         .hdisplay = 1024,
1499         .hsync_start = 1024 + 24,
1500         .hsync_end = 1024 + 24 + 136,
1501         .htotal = 1024 + 24 + 136 + 160,
1502         .vdisplay = 600,
1503         .vsync_start = 600 + 3,
1504         .vsync_end = 600 + 3 + 6,
1505         .vtotal = 600 + 3 + 6 + 61,
1506         .vrefresh = 60,
1507 };
1508
1509 static const struct panel_desc samsung_ltn101nt05 = {
1510         .modes = &samsung_ltn101nt05_mode,
1511         .num_modes = 1,
1512         .bpc = 6,
1513         .size = {
1514                 .width = 1024,
1515                 .height = 600,
1516         },
1517 };
1518
1519 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1520         .clock = 76300,
1521         .hdisplay = 1366,
1522         .hsync_start = 1366 + 64,
1523         .hsync_end = 1366 + 64 + 48,
1524         .htotal = 1366 + 64 + 48 + 128,
1525         .vdisplay = 768,
1526         .vsync_start = 768 + 2,
1527         .vsync_end = 768 + 2 + 5,
1528         .vtotal = 768 + 2 + 5 + 17,
1529         .vrefresh = 60,
1530 };
1531
1532 static const struct panel_desc samsung_ltn140at29_301 = {
1533         .modes = &samsung_ltn140at29_301_mode,
1534         .num_modes = 1,
1535         .bpc = 6,
1536         .size = {
1537                 .width = 320,
1538                 .height = 187,
1539         },
1540 };
1541
1542 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1543         .clock = 33300,
1544         .hdisplay = 800,
1545         .hsync_start = 800 + 1,
1546         .hsync_end = 800 + 1 + 64,
1547         .htotal = 800 + 1 + 64 + 64,
1548         .vdisplay = 480,
1549         .vsync_start = 480 + 1,
1550         .vsync_end = 480 + 1 + 23,
1551         .vtotal = 480 + 1 + 23 + 22,
1552         .vrefresh = 60,
1553 };
1554
1555 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1556         .modes = &shelly_sca07010_bfn_lnn_mode,
1557         .num_modes = 1,
1558         .size = {
1559                 .width = 152,
1560                 .height = 91,
1561         },
1562         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1563 };
1564
1565 static const struct of_device_id platform_of_match[] = {
1566         {
1567                 .compatible = "simple-panel",
1568                 .data = NULL,
1569         }, {
1570                 .compatible = "ampire,am800480r3tmqwa1h",
1571                 .data = &ampire_am800480r3tmqwa1h,
1572         }, {
1573                 .compatible = "auo,b101aw03",
1574                 .data = &auo_b101aw03,
1575         }, {
1576                 .compatible = "auo,b101ean01",
1577                 .data = &auo_b101ean01,
1578         }, {
1579                 .compatible = "auo,b101ew05",
1580                 .data = &auo_b101ew05,
1581         }, {
1582                 .compatible = "auo,b101xtn01",
1583                 .data = &auo_b101xtn01,
1584         }, {
1585                 .compatible = "auo,b116xw03",
1586                 .data = &auo_b116xw03,
1587         }, {
1588                 .compatible = "auo,b125han03",
1589                 .data = &auo_b125han03,
1590         }, {
1591                 .compatible = "auo,b133htn01",
1592                 .data = &auo_b133htn01,
1593         }, {
1594                 .compatible = "auo,b133xtn01",
1595                 .data = &auo_b133xtn01,
1596         }, {
1597                 .compatible = "avic,tm070ddh03",
1598                 .data = &avic_tm070ddh03,
1599         }, {
1600                 .compatible = "boe,nv125fhm-n73",
1601                 .data = &boe_nv125fhm_n73,
1602         }, {
1603                 .compatible = "chunghwa,claa070wp03xg",
1604                 .data = &chunghwa_claa070wp03xg,
1605         }, {
1606                 .compatible = "chunghwa,claa101wa01a",
1607                 .data = &chunghwa_claa101wa01a
1608         }, {
1609                 .compatible = "chunghwa,claa101wb01",
1610                 .data = &chunghwa_claa101wb01
1611         }, {
1612                 .compatible = "edt,et057090dhu",
1613                 .data = &edt_et057090dhu,
1614         }, {
1615                 .compatible = "edt,et070080dh6",
1616                 .data = &edt_etm0700g0dh6,
1617         }, {
1618                 .compatible = "edt,etm0700g0dh6",
1619                 .data = &edt_etm0700g0dh6,
1620         }, {
1621                 .compatible = "foxlink,fl500wvr00-a0t",
1622                 .data = &foxlink_fl500wvr00_a0t,
1623         }, {
1624                 .compatible = "giantplus,gpg482739qs5",
1625                 .data = &giantplus_gpg482739qs5
1626         }, {
1627                 .compatible = "hannstar,hsd070pww1",
1628                 .data = &hannstar_hsd070pww1,
1629         }, {
1630                 .compatible = "hannstar,hsd100pxn1",
1631                 .data = &hannstar_hsd100pxn1,
1632         }, {
1633                 .compatible = "hit,tx23d38vm0caa",
1634                 .data = &hitachi_tx23d38vm0caa
1635         }, {
1636                 .compatible = "innolux,at043tn24",
1637                 .data = &innolux_at043tn24,
1638         }, {
1639                 .compatible ="innolux,g121i1-l01",
1640                 .data = &innolux_g121i1_l01
1641         }, {
1642                 .compatible = "innolux,n116bge",
1643                 .data = &innolux_n116bge,
1644         }, {
1645                 .compatible = "innolux,n125hce",
1646                 .data = &innolux_n125hce,
1647         }, {
1648                 .compatible = "innolux,n156bge-l21",
1649                 .data = &innolux_n156bge_l21,
1650         }, {
1651                 .compatible = "innolux,zj070na-01p",
1652                 .data = &innolux_zj070na_01p,
1653         }, {
1654                 .compatible = "lg,lb070wv8",
1655                 .data = &lg_lb070wv8,
1656         }, {
1657                 .compatible = "lg,lp079qx1-sp0v",
1658                 .data = &lg_lp079qx1_sp0v,
1659         }, {
1660                 .compatible = "lg,lp097qx1-spa1",
1661                 .data = &lg_lp097qx1_spa1,
1662         }, {
1663                 .compatible = "lg,lp129qe",
1664                 .data = &lg_lp129qe,
1665         }, {
1666                 .compatible = "nec,nl4827hc19-05b",
1667                 .data = &nec_nl4827hc19_05b,
1668         }, {
1669                 .compatible = "okaya,rs800480t-7x0gp",
1670                 .data = &okaya_rs800480t_7x0gp,
1671         }, {
1672                 .compatible = "ortustech,com43h4m85ulc",
1673                 .data = &ortustech_com43h4m85ulc,
1674         }, {
1675                 .compatible = "samsung,lsn122dl01-c01",
1676                 .data = &samsung_lsn122dl01_c01,
1677         }, {
1678                 .compatible = "samsung,ltn101nt05",
1679                 .data = &samsung_ltn101nt05,
1680         }, {
1681                 .compatible = "samsung,ltn140at29-301",
1682                 .data = &samsung_ltn140at29_301,
1683         }, {
1684                 .compatible = "sharp,lcd-f402",
1685                 .data = &sharp_lcd_f402,
1686         }, {
1687                 .compatible = "shelly,sca07010-bfn-lnn",
1688                 .data = &shelly_sca07010_bfn_lnn,
1689         }, {
1690                 /* sentinel */
1691         }
1692 };
1693 MODULE_DEVICE_TABLE(of, platform_of_match);
1694
1695 static int panel_simple_platform_probe(struct platform_device *pdev)
1696 {
1697         const struct of_device_id *id;
1698
1699         id = of_match_node(platform_of_match, pdev->dev.of_node);
1700         if (!id)
1701                 return -ENODEV;
1702
1703         return panel_simple_probe(&pdev->dev, id->data);
1704 }
1705
1706 static int panel_simple_platform_remove(struct platform_device *pdev)
1707 {
1708         return panel_simple_remove(&pdev->dev);
1709 }
1710
1711 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1712 {
1713         panel_simple_shutdown(&pdev->dev);
1714 }
1715
1716 static struct platform_driver panel_simple_platform_driver = {
1717         .driver = {
1718                 .name = "panel-simple",
1719                 .of_match_table = platform_of_match,
1720         },
1721         .probe = panel_simple_platform_probe,
1722         .remove = panel_simple_platform_remove,
1723         .shutdown = panel_simple_platform_shutdown,
1724 };
1725
1726 struct panel_desc_dsi {
1727         struct panel_desc desc;
1728
1729         unsigned long flags;
1730         enum mipi_dsi_pixel_format format;
1731         unsigned int lanes;
1732 };
1733
1734 static const struct drm_display_mode auo_b080uan01_mode = {
1735         .clock = 154500,
1736         .hdisplay = 1200,
1737         .hsync_start = 1200 + 62,
1738         .hsync_end = 1200 + 62 + 4,
1739         .htotal = 1200 + 62 + 4 + 62,
1740         .vdisplay = 1920,
1741         .vsync_start = 1920 + 9,
1742         .vsync_end = 1920 + 9 + 2,
1743         .vtotal = 1920 + 9 + 2 + 8,
1744         .vrefresh = 60,
1745 };
1746
1747 static const struct panel_desc_dsi auo_b080uan01 = {
1748         .desc = {
1749                 .modes = &auo_b080uan01_mode,
1750                 .num_modes = 1,
1751                 .bpc = 8,
1752                 .size = {
1753                         .width = 108,
1754                         .height = 272,
1755                 },
1756         },
1757         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1758         .format = MIPI_DSI_FMT_RGB888,
1759         .lanes = 4,
1760 };
1761
1762 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1763         .clock = 160000,
1764         .hdisplay = 1200,
1765         .hsync_start = 1200 + 120,
1766         .hsync_end = 1200 + 120 + 20,
1767         .htotal = 1200 + 120 + 20 + 21,
1768         .vdisplay = 1920,
1769         .vsync_start = 1920 + 21,
1770         .vsync_end = 1920 + 21 + 3,
1771         .vtotal = 1920 + 21 + 3 + 18,
1772         .vrefresh = 60,
1773         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1774 };
1775
1776 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1777         .desc = {
1778                 .modes = &boe_tv080wum_nl0_mode,
1779                 .num_modes = 1,
1780                 .size = {
1781                         .width = 107,
1782                         .height = 172,
1783                 },
1784         },
1785         .flags = MIPI_DSI_MODE_VIDEO |
1786                  MIPI_DSI_MODE_VIDEO_BURST |
1787                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1788         .format = MIPI_DSI_FMT_RGB888,
1789         .lanes = 4,
1790 };
1791
1792 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1793         .clock = 71000,
1794         .hdisplay = 800,
1795         .hsync_start = 800 + 32,
1796         .hsync_end = 800 + 32 + 1,
1797         .htotal = 800 + 32 + 1 + 57,
1798         .vdisplay = 1280,
1799         .vsync_start = 1280 + 28,
1800         .vsync_end = 1280 + 28 + 1,
1801         .vtotal = 1280 + 28 + 1 + 14,
1802         .vrefresh = 60,
1803 };
1804
1805 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1806         .desc = {
1807                 .modes = &lg_ld070wx3_sl01_mode,
1808                 .num_modes = 1,
1809                 .bpc = 8,
1810                 .size = {
1811                         .width = 94,
1812                         .height = 151,
1813                 },
1814         },
1815         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1816         .format = MIPI_DSI_FMT_RGB888,
1817         .lanes = 4,
1818 };
1819
1820 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1821         .clock = 67000,
1822         .hdisplay = 720,
1823         .hsync_start = 720 + 12,
1824         .hsync_end = 720 + 12 + 4,
1825         .htotal = 720 + 12 + 4 + 112,
1826         .vdisplay = 1280,
1827         .vsync_start = 1280 + 8,
1828         .vsync_end = 1280 + 8 + 4,
1829         .vtotal = 1280 + 8 + 4 + 12,
1830         .vrefresh = 60,
1831 };
1832
1833 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1834         .desc = {
1835                 .modes = &lg_lh500wx1_sd03_mode,
1836                 .num_modes = 1,
1837                 .bpc = 8,
1838                 .size = {
1839                         .width = 62,
1840                         .height = 110,
1841                 },
1842         },
1843         .flags = MIPI_DSI_MODE_VIDEO,
1844         .format = MIPI_DSI_FMT_RGB888,
1845         .lanes = 4,
1846 };
1847
1848 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1849         .clock = 157200,
1850         .hdisplay = 1920,
1851         .hsync_start = 1920 + 154,
1852         .hsync_end = 1920 + 154 + 16,
1853         .htotal = 1920 + 154 + 16 + 32,
1854         .vdisplay = 1200,
1855         .vsync_start = 1200 + 17,
1856         .vsync_end = 1200 + 17 + 2,
1857         .vtotal = 1200 + 17 + 2 + 16,
1858         .vrefresh = 60,
1859 };
1860
1861 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1862         .desc = {
1863                 .modes = &panasonic_vvx10f004b00_mode,
1864                 .num_modes = 1,
1865                 .bpc = 8,
1866                 .size = {
1867                         .width = 217,
1868                         .height = 136,
1869                 },
1870         },
1871         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1872                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1873         .format = MIPI_DSI_FMT_RGB888,
1874         .lanes = 4,
1875 };
1876
1877
1878 static const struct of_device_id dsi_of_match[] = {
1879         {
1880                 .compatible = "simple-panel-dsi",
1881                 .data = NULL
1882         }, {
1883                 .compatible = "auo,b080uan01",
1884                 .data = &auo_b080uan01
1885         }, {
1886                 .compatible = "boe,tv080wum-nl0",
1887                 .data = &boe_tv080wum_nl0
1888         }, {
1889                 .compatible = "lg,ld070wx3-sl01",
1890                 .data = &lg_ld070wx3_sl01
1891         }, {
1892                 .compatible = "lg,lh500wx1-sd03",
1893                 .data = &lg_lh500wx1_sd03
1894         }, {
1895                 .compatible = "panasonic,vvx10f004b00",
1896                 .data = &panasonic_vvx10f004b00
1897         }, {
1898                 /* sentinel */
1899         }
1900 };
1901 MODULE_DEVICE_TABLE(of, dsi_of_match);
1902
1903 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1904 {
1905         struct panel_simple *panel;
1906         const struct panel_desc_dsi *desc;
1907         const struct of_device_id *id;
1908         const struct panel_desc *pdesc;
1909         const void *data;
1910         int len;
1911         u32 val;
1912         int err;
1913
1914         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1915         if (!id)
1916                 return -ENODEV;
1917
1918         desc = id->data;
1919
1920         if (desc) {
1921                 dsi->mode_flags = desc->flags;
1922                 dsi->format = desc->format;
1923                 dsi->lanes = desc->lanes;
1924                 pdesc = &desc->desc;
1925         } else {
1926                 pdesc = NULL;
1927         }
1928
1929         err = panel_simple_probe(&dsi->dev, pdesc);
1930         if (err < 0)
1931                 return err;
1932
1933         panel = dev_get_drvdata(&dsi->dev);
1934         panel->dsi = dsi;
1935
1936         if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1937                 dsi->mode_flags = val;
1938
1939         if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1940                 dsi->format = val;
1941
1942         if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1943                 dsi->lanes = val;
1944
1945         if (!of_property_read_u32(dsi->dev.of_node, "reset-delay-ms", &val))
1946                 panel->reset_delay = val;
1947
1948         data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1949         if (data) {
1950                 panel->on_cmds = devm_kzalloc(&dsi->dev,
1951                                               sizeof(*panel->on_cmds),
1952                                               GFP_KERNEL);
1953                 if (!panel->on_cmds)
1954                         return -ENOMEM;
1955
1956                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1957                                                       panel->on_cmds);
1958                 if (err) {
1959                         dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1960                         return err;
1961                 }
1962         }
1963
1964         data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1965         if (data) {
1966                 panel->off_cmds = devm_kzalloc(&dsi->dev,
1967                                                sizeof(*panel->off_cmds),
1968                                                GFP_KERNEL);
1969                 if (!panel->off_cmds)
1970                         return -ENOMEM;
1971
1972                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1973                                                       panel->off_cmds);
1974                 if (err) {
1975                         dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
1976                         return err;
1977                 }
1978         }
1979
1980         return mipi_dsi_attach(dsi);
1981 }
1982
1983 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1984 {
1985         int err;
1986
1987         err = mipi_dsi_detach(dsi);
1988         if (err < 0)
1989                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1990
1991         return panel_simple_remove(&dsi->dev);
1992 }
1993
1994 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1995 {
1996         panel_simple_shutdown(&dsi->dev);
1997 }
1998
1999 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2000         .driver = {
2001                 .name = "panel-simple-dsi",
2002                 .of_match_table = dsi_of_match,
2003         },
2004         .probe = panel_simple_dsi_probe,
2005         .remove = panel_simple_dsi_remove,
2006         .shutdown = panel_simple_dsi_shutdown,
2007 };
2008
2009 static int __init panel_simple_init(void)
2010 {
2011         int err;
2012
2013         err = platform_driver_register(&panel_simple_platform_driver);
2014         if (err < 0)
2015                 return err;
2016
2017         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2018                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2019                 if (err < 0)
2020                         return err;
2021         }
2022
2023         return 0;
2024 }
2025 module_init(panel_simple_init);
2026
2027 static void __exit panel_simple_exit(void)
2028 {
2029         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2030                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2031
2032         platform_driver_unregister(&panel_simple_platform_driver);
2033 }
2034 module_exit(panel_simple_exit);
2035
2036 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2037 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2038 MODULE_LICENSE("GPL and additional rights");