drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include "dw-hdmi.h"
  39 #include "dw-hdmi-audio.h"
  40
  41 #define HDMI_EDID_LEN           512
  42
  43 #define RGB                     0
  44 #define YCBCR444                1
  45 #define YCBCR422_16BITS         2
  46 #define YCBCR422_8BITS          3
  47 #define XVYCC444                4
  48 #define YCBCR420                5
  49
  50 enum hdmi_datamap {
  51         RGB444_8B = 0x01,
  52         RGB444_10B = 0x03,
  53         RGB444_12B = 0x05,
  54         RGB444_16B = 0x07,
  55         YCbCr444_8B = 0x09,
  56         YCbCr444_10B = 0x0B,
  57         YCbCr444_12B = 0x0D,
  58         YCbCr444_16B = 0x0F,
  59         YCbCr422_8B = 0x16,
  60         YCbCr422_10B = 0x14,
  61         YCbCr422_12B = 0x12,
  62 };
  63
  64 /*
  65  * Unless otherwise noted, entries in this table are 100% optimization.
  66  * Values can be obtained from hdmi_compute_n() but that function is
  67  * slow so we pre-compute values we expect to see.
  68  *
  69  * All 32k and 48k values are expected to be the same (due to the way
  70  * the math works) for any rate that's an exact kHz.
  71  */
  72 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  73         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  74         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  75         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  76         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  77         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  78         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  79         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  80         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  81         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  82         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  83         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  84         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  85         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  86         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  87         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  88         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  89         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  90         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  91         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  92         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  93         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  94         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  95         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  96         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  97         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  98         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  99         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 100         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
 101         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 102         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 103         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 104         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 105         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 106         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 107         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 108         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 109         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 110
 111         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 112         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 113         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 114
 115         /* End of table */
 116         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 117 };
 118
 119
 120 static const u16 csc_coeff_default[3][4] = {
 121         { 0x2000, 0x0000, 0x0000, 0x0000 },
 122         { 0x0000, 0x2000, 0x0000, 0x0000 },
 123         { 0x0000, 0x0000, 0x2000, 0x0000 }
 124 };
 125
 126 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 127         { 0x2000, 0x6926, 0x74fd, 0x010e },
 128         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 129         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 130 };
 131
 132 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 133         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 134         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 135         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 136 };
 137
 138 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 139         { 0x2591, 0x1322, 0x074b, 0x0000 },
 140         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 141         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 142 };
 143
 144 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 145         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 146         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 147         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 148 };
 149
 150 struct hdmi_vmode {
 151         bool mdataenablepolarity;
 152
 153         unsigned int mpixelclock;
 154         unsigned int mpixelrepetitioninput;
 155         unsigned int mpixelrepetitionoutput;
 156 };
 157
 158 struct hdmi_data_info {
 159         unsigned int enc_in_format;
 160         unsigned int enc_out_format;
 161         unsigned int enc_color_depth;
 162         unsigned int colorimetry;
 163         unsigned int pix_repet_factor;
 164         unsigned int hdcp_enable;
 165         struct hdmi_vmode video_mode;
 166 };
 167
 168 struct dw_hdmi_i2c {
 169         struct i2c_adapter      adap;
 170
 171         struct mutex            lock;
 172         struct completion       cmp;
 173         u8                      stat;
 174
 175         u8                      slave_reg;
 176         bool                    is_regaddr;
 177 };
 178
 179 struct dw_hdmi {
 180         struct drm_connector connector;
 181         struct drm_encoder *encoder;
 182         struct drm_bridge *bridge;
 183
 184         struct platform_device *audio;
 185         enum dw_hdmi_devtype dev_type;
 186         struct device *dev;
 187         struct clk *isfr_clk;
 188         struct clk *iahb_clk;
 189         struct dw_hdmi_i2c *i2c;
 190
 191         struct hdmi_data_info hdmi_data;
 192         const struct dw_hdmi_plat_data *plat_data;
 193
 194         int vic;
 195
 196         u8 edid[HDMI_EDID_LEN];
 197         bool cable_plugin;
 198
 199         bool phy_enabled;
 200         struct drm_display_mode previous_mode;
 201
 202         struct i2c_adapter *ddc;
 203         void __iomem *regs;
 204         bool sink_is_hdmi;
 205         bool sink_has_audio;
 206
 207         struct mutex mutex;             /* for state below and previous_mode */
 208         enum drm_connector_force force; /* mutex-protected force state */
 209         bool disabled;                  /* DRM has disabled our bridge */
 210         bool bridge_is_on;              /* indicates the bridge is on */
 211         bool rxsense;                   /* rxsense state */
 212         u8 phy_mask;                    /* desired phy int mask settings */
 213
 214         spinlock_t audio_lock;
 215         struct mutex audio_mutex;
 216         unsigned int sample_rate;
 217         unsigned int audio_cts;
 218         unsigned int audio_n;
 219         bool audio_enable;
 220
 221 #ifdef CONFIG_SWITCH
 222         struct switch_dev switchdev;
 223 #endif
 224
 225         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 226         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 227 };
 228
 229 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 230         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 231          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 232
 233 #define HDMI_PHY_RX_SENSE \
 234         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 235          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 236
 237 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 238 {
 239         writel(val, hdmi->regs + (offset << 2));
 240 }
 241
 242 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 243 {
 244         return readl(hdmi->regs + (offset << 2));
 245 }
 246
 247 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 248 {
 249         writeb(val, hdmi->regs + offset);
 250 }
 251
 252 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 253 {
 254         return readb(hdmi->regs + offset);
 255 }
 256
 257 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 258 {
 259         hdmi->write(hdmi, val, offset);
 260 }
 261
 262 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 263 {
 264         return hdmi->read(hdmi, offset);
 265 }
 266
 267 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 268 {
 269         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 270
 271         val |= data & mask;
 272         hdmi_writeb(hdmi, val, reg);
 273 }
 274
 275 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 276                              u8 shift, u8 mask)
 277 {
 278         hdmi_modb(hdmi, data << shift, mask, reg);
 279 }
 280
 281 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 282 {
 283         /* Software reset */
 284         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 285
 286         /* Set Standard Mode speed */
 287         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 288                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 289
 290         /* Set done, not acknowledged and arbitration interrupt polarities */
 291         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 292         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 293                     HDMI_I2CM_CTLINT);
 294
 295         /* Clear DONE and ERROR interrupts */
 296         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 297                     HDMI_IH_I2CM_STAT0);
 298
 299         /* Mute DONE and ERROR interrupts */
 300         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 301                     HDMI_IH_MUTE_I2CM_STAT0);
 302 }
 303
 304 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 305                             unsigned char *buf, unsigned int length)
 306 {
 307         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 308         int stat;
 309
 310         if (!i2c->is_regaddr) {
 311                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 312                 i2c->slave_reg = 0x00;
 313                 i2c->is_regaddr = true;
 314         }
 315
 316         while (length--) {
 317                 reinit_completion(&i2c->cmp);
 318
 319                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 320                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 321                             HDMI_I2CM_OPERATION);
 322
 323                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 324                 if (!stat)
 325                         return -EAGAIN;
 326
 327                 /* Check for error condition on the bus */
 328                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 329                         return -EIO;
 330
 331                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 338                              unsigned char *buf, unsigned int length)
 339 {
 340         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 341         int stat;
 342
 343         if (!i2c->is_regaddr) {
 344                 /* Use the first write byte as register address */
 345                 i2c->slave_reg = buf[0];
 346                 length--;
 347                 buf++;
 348                 i2c->is_regaddr = true;
 349         }
 350
 351         while (length--) {
 352                 reinit_completion(&i2c->cmp);
 353
 354                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 355                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 356                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 357                             HDMI_I2CM_OPERATION);
 358
 359         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 360                 if (!stat)
 361                         return -EAGAIN;
 362
 363                 /* Check for error condition on the bus */
 364                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 365                         return -EIO;
 366         }
 367
 368         return 0;
 369 }
 370
 371 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 372                             struct i2c_msg *msgs, int num)
 373 {
 374         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 375         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 376         u8 addr = msgs[0].addr;
 377         int i, ret = 0;
 378
 379         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 380
 381         for (i = 0; i < num; i++) {
 382                 if (msgs[i].addr != addr) {
 383                         dev_warn(hdmi->dev,
 384                                  "unsupported transfer, changed slave address\n");
 385                         return -EOPNOTSUPP;
 386                 }
 387
 388                 if (msgs[i].len == 0) {
 389                         dev_dbg(hdmi->dev,
 390                                 "unsupported transfer %d/%d, no data\n",
 391                                 i + 1, num);
 392                         return -EOPNOTSUPP;
 393                 }
 394         }
 395
 396         mutex_lock(&i2c->lock);
 397
 398         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 399
 400         /* Set slave device address taken from the first I2C message */
 401         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 402
 403         /* Set slave device register address on transfer */
 404         i2c->is_regaddr = false;
 405
 406         for (i = 0; i < num; i++) {
 407                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 408                         i + 1, num, msgs[i].len, msgs[i].flags);
 409
 410                 if (msgs[i].flags & I2C_M_RD)
 411                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 412                 else
 413                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 414
 415                 if (ret < 0)
 416                         break;
 417         }
 418
 419         if (!ret)
 420                 ret = num;
 421
 422         /* Mute DONE and ERROR interrupts */
 423         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 424                     HDMI_IH_MUTE_I2CM_STAT0);
 425
 426         mutex_unlock(&i2c->lock);
 427
 428         return ret;
 429 }
 430
 431 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 432 {
 433         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 434 }
 435
 436 static const struct i2c_algorithm dw_hdmi_algorithm = {
 437         .master_xfer    = dw_hdmi_i2c_xfer,
 438         .functionality  = dw_hdmi_i2c_func,
 439 };
 440
 441 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 442 {
 443         struct i2c_adapter *adap;
 444         struct dw_hdmi_i2c *i2c;
 445         int ret;
 446
 447         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 448         if (!i2c)
 449                 return ERR_PTR(-ENOMEM);
 450
 451         mutex_init(&i2c->lock);
 452         init_completion(&i2c->cmp);
 453
 454         adap = &i2c->adap;
 455         adap->class = I2C_CLASS_DDC;
 456         adap->owner = THIS_MODULE;
 457         adap->dev.parent = hdmi->dev;
 458         adap->dev.of_node = hdmi->dev->of_node;
 459         adap->algo = &dw_hdmi_algorithm;
 460         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 461         i2c_set_adapdata(adap, hdmi);
 462
 463         ret = i2c_add_adapter(adap);
 464         if (ret) {
 465                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 466                 devm_kfree(hdmi->dev, i2c);
 467                 return ERR_PTR(ret);
 468         }
 469
 470         hdmi->i2c = i2c;
 471
 472         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 473
 474         return adap;
 475 }
 476
 477 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 478                            unsigned int n)
 479 {
 480         /* Must be set/cleared first */
 481         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 482
 483         /* nshift factor = 0 */
 484         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 485
 486         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 487                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 488         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 489         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 490
 491         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 492         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 493         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 494 }
 495
 496 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 497                                    unsigned long pixel_clk,
 498                                    unsigned long freq)
 499 {
 500         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 501         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 502         int i;
 503
 504         if (plat_data->tmds_n_table) {
 505                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 506                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 507                                 tmds_n = &plat_data->tmds_n_table[i];
 508                                 break;
 509                         }
 510                 }
 511         }
 512
 513         if (tmds_n == NULL) {
 514                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 515                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 516                                 tmds_n = &common_tmds_n_table[i];
 517                                 break;
 518                         }
 519                 }
 520         }
 521
 522         if (tmds_n == NULL)
 523                 return -ENOENT;
 524
 525         switch (freq) {
 526         case 32000:
 527                 return tmds_n->n_32k;
 528         case 44100:
 529         case 88200:
 530         case 176400:
 531                 return (freq / 44100) * tmds_n->n_44k1;
 532         case 48000:
 533         case 96000:
 534         case 192000:
 535                 return (freq / 48000) * tmds_n->n_48k;
 536         default:
 537                 return -ENOENT;
 538         }
 539 }
 540
 541 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 542                                 unsigned int pixel_clk)
 543 {
 544         u64 final, diff;
 545         u64 cts;
 546
 547         final = (u64)pixel_clk * n;
 548
 549         cts = final;
 550         do_div(cts, 128 * freq);
 551
 552         diff = final - (u64)cts * (128 * freq);
 553
 554         return diff;
 555 }
 556
 557 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 558                                    unsigned long pixel_clk,
 559                                    unsigned long freq)
 560 {
 561         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 562         unsigned int max_n = (128 * freq) / 300;
 563         unsigned int ideal_n = (128 * freq) / 1000;
 564         unsigned int best_n_distance = ideal_n;
 565         unsigned int best_n = 0;
 566         u64 best_diff = U64_MAX;
 567         int n;
 568
 569         /* If the ideal N could satisfy the audio math, then just take it */
 570         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 571                 return ideal_n;
 572
 573         for (n = min_n; n <= max_n; n++) {
 574                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 575
 576                 if (diff < best_diff || (diff == best_diff &&
 577                     abs(n - ideal_n) < best_n_distance)) {
 578                         best_n = n;
 579                         best_diff = diff;
 580                         best_n_distance = abs(best_n - ideal_n);
 581                 }
 582
 583                 /*
 584                  * The best N already satisfy the audio math, and also be
 585                  * the closest value to ideal N, so just cut the loop.
 586                  */
 587                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 588                         break;
 589         }
 590
 591         return best_n;
 592 }
 593
 594 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 595                                 unsigned long sample_rate)
 596 {
 597         int n;
 598
 599         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 600         if (n > 0)
 601                 return n;
 602
 603         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 604                  pixel_clk);
 605
 606         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 607 }
 608
 609 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 610         unsigned long pixel_clk, unsigned int sample_rate)
 611 {
 612         unsigned long ftdms = pixel_clk;
 613         unsigned int n, cts;
 614         u64 tmp;
 615
 616         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 617
 618         /*
 619          * Compute the CTS value from the N value.  Note that CTS and N
 620          * can be up to 20 bits in total, so we need 64-bit math.  Also
 621          * note that our TDMS clock is not fully accurate; it is accurate
 622          * to kHz.  This can introduce an unnecessary remainder in the
 623          * calculation below, so we don't try to warn about that.
 624          */
 625         tmp = (u64)ftdms * n;
 626         do_div(tmp, 128 * sample_rate);
 627         cts = tmp;
 628
 629         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 630                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 631                 n, cts);
 632
 633         spin_lock_irq(&hdmi->audio_lock);
 634         hdmi->audio_n = n;
 635         hdmi->audio_cts = cts;
 636         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 637         spin_unlock_irq(&hdmi->audio_lock);
 638 }
 639
 640 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 641 {
 642         mutex_lock(&hdmi->audio_mutex);
 643         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 644         mutex_unlock(&hdmi->audio_mutex);
 645 }
 646
 647 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 648 {
 649         mutex_lock(&hdmi->audio_mutex);
 650         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 651                                  hdmi->sample_rate);
 652         mutex_unlock(&hdmi->audio_mutex);
 653 }
 654
 655 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 656 {
 657         mutex_lock(&hdmi->audio_mutex);
 658         hdmi->sample_rate = rate;
 659         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 660                                  hdmi->sample_rate);
 661         mutex_unlock(&hdmi->audio_mutex);
 662 }
 663 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 664
 665 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 666 {
 667         unsigned long flags;
 668
 669         spin_lock_irqsave(&hdmi->audio_lock, flags);
 670         hdmi->audio_enable = true;
 671         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 672         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 673 }
 674 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 675
 676 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 677 {
 678         unsigned long flags;
 679
 680         spin_lock_irqsave(&hdmi->audio_lock, flags);
 681         hdmi->audio_enable = false;
 682         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 683         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 684 }
 685 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 686
 687 /*
 688  * this submodule is responsible for the video data synchronization.
 689  * for example, for RGB 4:4:4 input, the data map is defined as
 690  *                      pin{47~40} <==> R[7:0]
 691  *                      pin{31~24} <==> G[7:0]
 692  *                      pin{15~8}  <==> B[7:0]
 693  */
 694 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 695 {
 696         int color_format = 0;
 697         u8 val;
 698
 699         if (hdmi->hdmi_data.enc_in_format == RGB) {
 700                 if (hdmi->hdmi_data.enc_color_depth == 8)
 701                         color_format = 0x01;
 702                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 703                         color_format = 0x03;
 704                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 705                         color_format = 0x05;
 706                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 707                         color_format = 0x07;
 708                 else
 709                         return;
 710         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
 711                    hdmi->hdmi_data.enc_in_format == YCBCR420) {
 712                 if (hdmi->hdmi_data.enc_color_depth == 8)
 713                         color_format = 0x09;
 714                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 715                         color_format = 0x0B;
 716                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 717                         color_format = 0x0D;
 718                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 719                         color_format = 0x0F;
 720                 else
 721                         return;
 722         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 723                 if (hdmi->hdmi_data.enc_color_depth == 8)
 724                         color_format = 0x16;
 725                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 726                         color_format = 0x14;
 727                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 728                         color_format = 0x12;
 729                 else
 730                         return;
 731         }
 732
 733         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 734                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 735                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 736         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 737
 738         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 739         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 740                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 741                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 742         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 743         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 744         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 745         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 746         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 747         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 748         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 749 }
 750
 751 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 752 {
 753         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 754 }
 755
 756 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 757 {
 758         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 759                 return 0;
 760         if (hdmi->hdmi_data.enc_in_format == RGB ||
 761             hdmi->hdmi_data.enc_in_format == YCBCR444)
 762                 return 1;
 763         return 0;
 764 }
 765
 766 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 767 {
 768         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 769                 return 0;
 770         if (hdmi->hdmi_data.enc_out_format == RGB ||
 771             hdmi->hdmi_data.enc_out_format == YCBCR444)
 772                 return 1;
 773         return 0;
 774 }
 775
 776 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 777 {
 778         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 779         unsigned i;
 780         u32 csc_scale = 1;
 781
 782         if (is_color_space_conversion(hdmi)) {
 783                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 784                         if (hdmi->hdmi_data.colorimetry ==
 785                                         HDMI_COLORIMETRY_ITU_601)
 786                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 787                         else
 788                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 789                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 790                         if (hdmi->hdmi_data.colorimetry ==
 791                                         HDMI_COLORIMETRY_ITU_601)
 792                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 793                         else
 794                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 795                         csc_scale = 0;
 796                 }
 797         }
 798
 799         /* The CSC registers are sequential, alternating MSB then LSB */
 800         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 801                 u16 coeff_a = (*csc_coeff)[0][i];
 802                 u16 coeff_b = (*csc_coeff)[1][i];
 803                 u16 coeff_c = (*csc_coeff)[2][i];
 804
 805                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 806                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 807                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 808                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 809                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 810                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 811         }
 812
 813         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 814                   HDMI_CSC_SCALE);
 815 }
 816
 817 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 818 {
 819         int color_depth = 0;
 820         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 821         int decimation = 0;
 822
 823         /* YCC422 interpolation to 444 mode */
 824         if (is_color_space_interpolation(hdmi))
 825                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 826         else if (is_color_space_decimation(hdmi))
 827                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 828
 829         if (hdmi->hdmi_data.enc_color_depth == 8)
 830                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 831         else if (hdmi->hdmi_data.enc_color_depth == 10)
 832                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 833         else if (hdmi->hdmi_data.enc_color_depth == 12)
 834                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 835         else if (hdmi->hdmi_data.enc_color_depth == 16)
 836                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 837         else
 838                 return;
 839
 840         /* Configure the CSC registers */
 841         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 842         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 843                   HDMI_CSC_SCALE);
 844
 845         dw_hdmi_update_csc_coeffs(hdmi);
 846 }
 847
 848 /*
 849  * HDMI video packetizer is used to packetize the data.
 850  * for example, if input is YCC422 mode or repeater is used,
 851  * data should be repacked this module can be bypassed.
 852  */
 853 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 854 {
 855         unsigned int color_depth = 0;
 856         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 857         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 858         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 859         u8 val, vp_conf;
 860
 861         if (hdmi_data->enc_out_format == RGB ||
 862             hdmi_data->enc_out_format == YCBCR444 ||
 863             hdmi_data->enc_out_format == YCBCR420) {
 864                 if (!hdmi_data->enc_color_depth) {
 865                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 866                 } else if (hdmi_data->enc_color_depth == 8) {
 867                         color_depth = 4;
 868                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 869                 } else if (hdmi_data->enc_color_depth == 10) {
 870                         color_depth = 5;
 871                 } else if (hdmi_data->enc_color_depth == 12) {
 872                         color_depth = 6;
 873                 } else if (hdmi_data->enc_color_depth == 16) {
 874                         color_depth = 7;
 875                 } else {
 876                         return;
 877                 }
 878         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 879                 if (!hdmi_data->enc_color_depth ||
 880                     hdmi_data->enc_color_depth == 8)
 881                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 882                 else if (hdmi_data->enc_color_depth == 10)
 883                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 884                 else if (hdmi_data->enc_color_depth == 12)
 885                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 886                 else
 887                         return;
 888                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 889         } else {
 890                 return;
 891         }
 892
 893         /* set the packetizer registers */
 894         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 895                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 896                 ((hdmi_data->pix_repet_factor <<
 897                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 898                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 899         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 900
 901         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 902                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 903
 904         /* Data from pixel repeater block */
 905         if (hdmi_data->pix_repet_factor > 0) {
 906                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 907                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 908         } else { /* data from packetizer block */
 909                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 910                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 911         }
 912
 913         hdmi_modb(hdmi, vp_conf,
 914                   HDMI_VP_CONF_PR_EN_MASK |
 915                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 916
 917         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 918                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 919
 920         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 921
 922         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 923                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 924                           HDMI_VP_CONF_PP_EN_ENABLE |
 925                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 926         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 927                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 928                           HDMI_VP_CONF_PP_EN_DISABLE |
 929                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 930         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 931                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 932                           HDMI_VP_CONF_PP_EN_DISABLE |
 933                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 934         } else {
 935                 return;
 936         }
 937
 938         hdmi_modb(hdmi, vp_conf,
 939                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 940                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 941
 942         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 943                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 944                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 945                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 946
 947         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 948                   HDMI_VP_CONF);
 949 }
 950
 951 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 952                                        unsigned char bit)
 953 {
 954         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 955                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 956 }
 957
 958 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 959                                         unsigned char bit)
 960 {
 961         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 962                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 963 }
 964
 965 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 966                                        unsigned char bit)
 967 {
 968         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 969                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 970 }
 971
 972 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 973                                      unsigned char bit)
 974 {
 975         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 976 }
 977
 978 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 979                                       unsigned char bit)
 980 {
 981         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 982 }
 983
 984 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 985 {
 986         u32 val;
 987
 988         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 989                 if (msec-- == 0)
 990                         return false;
 991                 udelay(1000);
 992         }
 993         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 994
 995         return true;
 996 }
 997
 998 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 999                                  unsigned char addr)
1000 {
1001         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1002         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1003         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1004                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1005         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1006                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1007         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1008                     HDMI_PHY_I2CM_OPERATION_ADDR);
1009         hdmi_phy_wait_i2c_done(hdmi, 1000);
1010 }
1011
1012 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1013                               unsigned char addr)
1014 {
1015         __hdmi_phy_i2c_write(hdmi, data, addr);
1016         return 0;
1017 }
1018
1019 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1020 {
1021         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1022                          HDMI_PHY_CONF0_PDZ_OFFSET,
1023                          HDMI_PHY_CONF0_PDZ_MASK);
1024 }
1025
1026 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1027 {
1028         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1029                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1030                          HDMI_PHY_CONF0_ENTMDS_MASK);
1031 }
1032
1033 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1034 {
1035         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1036                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1037                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1038 }
1039
1040 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1041 {
1042         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1043                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1044                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1045 }
1046
1047 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1048 {
1049         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1050                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1051                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1052 }
1053
1054 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1055 {
1056         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1057                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1058                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1059 }
1060
1061 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1062 {
1063         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1064                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1065                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1066 }
1067
1068 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1069                               unsigned char res, int cscon)
1070 {
1071         unsigned res_idx;
1072         u8 val, msec, tmds_cfg;
1073         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1074         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1075         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1076         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1077
1078         if (prep)
1079                 return -EINVAL;
1080
1081         switch (res) {
1082         case 0: /* color resolution 0 is 8 bit colour depth */
1083         case 8:
1084                 res_idx = DW_HDMI_RES_8;
1085                 break;
1086         case 10:
1087                 res_idx = DW_HDMI_RES_10;
1088                 break;
1089         case 12:
1090                 res_idx = DW_HDMI_RES_12;
1091                 break;
1092         default:
1093                 return -EINVAL;
1094         }
1095
1096         /* PLL/MPLL Cfg - always match on final entry */
1097         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1098                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1099                     mpll_config->mpixelclock)
1100                         break;
1101
1102         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1103                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1104                     curr_ctrl->mpixelclock)
1105                         break;
1106
1107         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1108                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1109                     phy_config->mpixelclock)
1110                         break;
1111
1112         if (mpll_config->mpixelclock == ~0UL ||
1113             curr_ctrl->mpixelclock == ~0UL ||
1114             phy_config->mpixelclock == ~0UL) {
1115                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1116                         hdmi->hdmi_data.video_mode.mpixelclock);
1117                 return -EINVAL;
1118         }
1119
1120         /* Enable csc path */
1121         if (cscon)
1122                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1123         else
1124                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1125
1126         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1127
1128         /* gen2 tx power off */
1129         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1130
1131         /* gen2 pddq */
1132         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1133
1134         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1135         if (hdmi->connector.scdc_present) {
1136                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1137                 if (mpll_config->mpixelclock > 340000000)
1138                         tmds_cfg |= 2;
1139                 else
1140                         tmds_cfg &= 0x1;
1141                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1142         }
1143
1144         /* PHY reset */
1145         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1146         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1147
1148         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1149
1150         hdmi_phy_test_clear(hdmi, 1);
1151         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1152                     HDMI_PHY_I2CM_SLAVE_ADDR);
1153         hdmi_phy_test_clear(hdmi, 0);
1154         /*
1155          * RK3399 mpll clock source is vpll, also is vop clock source.
1156          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1157          * to enable mpll pre-divider.
1158          */
1159         if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1160             hdmi->dev_type == RK3399_HDMI)
1161                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1162                                    0x06);
1163         else
1164                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1165         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1166
1167         /* CURRCTRL */
1168         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1169
1170         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1171         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1172
1173         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1174         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1175         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1176
1177         /* REMOVE CLK TERM */
1178         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1179
1180         dw_hdmi_phy_enable_powerdown(hdmi, false);
1181
1182         /* toggle TMDS disable */
1183         dw_hdmi_phy_enable_tmds(hdmi, 0);
1184
1185         /* Wait for resuming transmission of TMDS clock and data */
1186         if (mpll_config->mpixelclock > 340000000)
1187                 msleep(100);
1188
1189         /* toggle TMDS enable */
1190         dw_hdmi_phy_enable_tmds(hdmi, 1);
1191
1192         /* gen2 tx power on */
1193         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1194         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1195
1196         if (is_rockchip(hdmi->dev_type))
1197                 dw_hdmi_phy_enable_spare(hdmi, 1);
1198
1199         /* Wait for PHY PLL lock */
1200         msec = 5;
1201         do {
1202                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1203                 if (!val)
1204                         break;
1205
1206                 if (msec == 0) {
1207                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1208                         return -ETIMEDOUT;
1209                 }
1210
1211                 udelay(1000);
1212                 msec--;
1213         } while (1);
1214
1215         return 0;
1216 }
1217
1218 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1219 {
1220         int i, ret;
1221         bool cscon;
1222
1223         /*check csc whether needed activated in HDMI mode */
1224         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1225
1226         /* HDMI Phy spec says to do the phy initialization sequence twice */
1227         for (i = 0; i < 2; i++) {
1228                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1229                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1230                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1231                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1232
1233                 /* Enable CSC */
1234                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1235                 if (ret)
1236                         return ret;
1237         }
1238
1239         hdmi->phy_enabled = true;
1240         return 0;
1241 }
1242
1243 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1244 {
1245         u8 de;
1246
1247         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1248                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1249         else
1250                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1251
1252         /* disable rx detect */
1253         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1254                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1255
1256         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1257
1258         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1259                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1260 }
1261
1262 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1263 {
1264         struct hdmi_avi_infoframe frame;
1265         u8 val;
1266
1267         /* Initialise info frame from DRM mode */
1268         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1269
1270         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1271                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1272         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1273                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1274         else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1275                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1276         else
1277                 frame.colorspace = HDMI_COLORSPACE_RGB;
1278
1279         /* Set up colorimetry */
1280         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1281                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1282                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1283                         frame.extended_colorimetry =
1284                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1285                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1286                         frame.extended_colorimetry =
1287                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1288         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1289                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1290                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1291         } else { /* Carries no data */
1292                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1293                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1294         }
1295
1296         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1297
1298         /*
1299          * The Designware IP uses a different byte format from standard
1300          * AVI info frames, though generally the bits are in the correct
1301          * bytes.
1302          */
1303
1304         /*
1305          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1306          * 5,6,7, active aspect present in bit 6 rather than 4.
1307          */
1308         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1309         if (frame.active_aspect & 15)
1310                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1311         if (frame.top_bar || frame.bottom_bar)
1312                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1313         if (frame.left_bar || frame.right_bar)
1314                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1315         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1316
1317         /* AVI data byte 2 differences: none */
1318         val = ((frame.colorimetry & 0x3) << 6) |
1319               ((frame.picture_aspect & 0x3) << 4) |
1320               (frame.active_aspect & 0xf);
1321         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1322
1323         /* AVI data byte 3 differences: none */
1324         val = ((frame.extended_colorimetry & 0x7) << 4) |
1325               ((frame.quantization_range & 0x3) << 2) |
1326               (frame.nups & 0x3);
1327         if (frame.itc)
1328                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1329         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1330
1331         /* AVI data byte 4 differences: none */
1332         val = frame.video_code & 0x7f;
1333         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1334
1335         /* AVI Data Byte 5- set up input and output pixel repetition */
1336         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1337                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1338                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1339                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1340                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1341                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1342         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1343
1344         /*
1345          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1346          * ycc range in bits 2,3 rather than 6,7
1347          */
1348         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1349               (frame.content_type & 0x3);
1350         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1351
1352         /* AVI Data Bytes 6-13 */
1353         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1354         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1355         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1356         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1357         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1358         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1359         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1360         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1361 }
1362
1363 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1364                              const struct drm_display_mode *mode)
1365 {
1366         u8 inv_val, bytes;
1367         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1368         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1369         unsigned int hdisplay, vdisplay;
1370
1371         vmode->mpixelclock = mode->crtc_clock * 1000;
1372         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1373                 vmode->mpixelclock /= 2;
1374         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1375
1376         /* Set up HDMI_FC_INVIDCONF
1377          * fc_invidconf.HDCP_keepout must be set (1'b1)
1378          * when activate the scrambler feature.
1379          */
1380         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1381                    vmode->mpixelclock > 340000000 ||
1382                    hdmi->connector.lte_340mcsc_scramble ?
1383                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1384                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1385
1386         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1387                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1388                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1389
1390         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1391                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1392                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1393
1394         inv_val |= (vmode->mdataenablepolarity ?
1395                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1396                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1397
1398         if (hdmi->vic == 39)
1399                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1400         else
1401                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1402                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1403                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1404
1405         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1406                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1407                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1408
1409         inv_val |= hdmi->sink_is_hdmi ?
1410                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1411                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1412
1413         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1414
1415         hdisplay = mode->hdisplay;
1416         hblank = mode->htotal - mode->hdisplay;
1417         h_de_hs = mode->hsync_start - mode->hdisplay;
1418         hsync_len = mode->hsync_end - mode->hsync_start;
1419
1420         /*
1421          * When we're setting a YCbCr420 mode, we need
1422          * to adjust the horizontal timing to suit.
1423          */
1424         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1425                 hdisplay /= 2;
1426                 hblank /= 2;
1427                 h_de_hs /= 2;
1428                 hsync_len /= 2;
1429         }
1430
1431         vdisplay = mode->vdisplay;
1432         vblank = mode->vtotal - mode->vdisplay;
1433         v_de_vs = mode->vsync_start - mode->vdisplay;
1434         vsync_len = mode->vsync_end - mode->vsync_start;
1435
1436         /*
1437          * When we're setting an interlaced mode, we need
1438          * to adjust the vertical timing to suit.
1439          */
1440         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1441                 vdisplay /= 2;
1442                 vblank /= 2;
1443                 v_de_vs /= 2;
1444                 vsync_len /= 2;
1445         }
1446
1447         /* Scrambling Control */
1448         if (hdmi->connector.scdc_present) {
1449                 if (vmode->mpixelclock > 340000000 ||
1450                     hdmi->connector.lte_340mcsc_scramble) {
1451                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1452                                        &bytes);
1453                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1454                                         bytes);
1455                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1456                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1457                                     HDMI_MC_SWRSTZ);
1458                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1459                 } else {
1460                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1461                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1462                                     HDMI_MC_SWRSTZ);
1463                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1464                 }
1465         }
1466
1467         /* Set up horizontal active pixel width */
1468         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1469         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1470
1471         /* Set up vertical active lines */
1472         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1473         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1474
1475         /* Set up horizontal blanking pixel region width */
1476         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1477         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1478
1479         /* Set up vertical blanking pixel region width */
1480         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1481
1482         /* Set up HSYNC active edge delay width (in pixel clks) */
1483         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1484         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1485
1486         /* Set up VSYNC active edge delay (in lines) */
1487         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1488
1489         /* Set up HSYNC active pulse width (in pixel clks) */
1490         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1491         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1492
1493         /* Set up VSYNC active edge delay (in lines) */
1494         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1495 }
1496
1497 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1498 {
1499         if (!hdmi->phy_enabled)
1500                 return;
1501
1502         dw_hdmi_phy_enable_tmds(hdmi, 0);
1503         dw_hdmi_phy_enable_powerdown(hdmi, true);
1504
1505         hdmi->phy_enabled = false;
1506 }
1507
1508 /* HDMI Initialization Step B.4 */
1509 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1510 {
1511         u8 clkdis;
1512
1513         /* control period minimum duration */
1514         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1515         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1516         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1517
1518         /* Set to fill TMDS data channels */
1519         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1520         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1521         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1522
1523         /* Enable pixel clock and tmds data path */
1524         clkdis = 0x7F;
1525         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1526         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1527
1528         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1529         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1530
1531         /* Enable csc path */
1532         if (is_color_space_conversion(hdmi)) {
1533                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1534                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1535         }
1536
1537         /* Enable pixel repetition path */
1538         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1539                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1540                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1541         }
1542 }
1543
1544 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1545 {
1546         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1547 }
1548
1549 /* Workaround to clear the overflow condition */
1550 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1551 {
1552         int count;
1553         u8 val;
1554
1555         /* TMDS software reset */
1556         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1557
1558         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1559         if (hdmi->dev_type == IMX6DL_HDMI) {
1560                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1561                 return;
1562         }
1563
1564         for (count = 0; count < 4; count++)
1565                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1566 }
1567
1568 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1569 {
1570         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1571         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1572 }
1573
1574 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1575 {
1576         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1577                     HDMI_IH_MUTE_FC_STAT2);
1578 }
1579
1580 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1581 {
1582         int ret;
1583
1584         hdmi_disable_overflow_interrupts(hdmi);
1585
1586         hdmi->vic = drm_match_cea_mode(mode);
1587
1588         if (!hdmi->vic) {
1589                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1590         } else {
1591                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1592         }
1593
1594         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1595             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1596             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1597             (hdmi->vic == 17) || (hdmi->vic == 18))
1598                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1599         else
1600                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1601
1602         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1603                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1604                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1605         } else {
1606                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1607                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1608         }
1609         /* TODO: Get input format from IPU (via FB driver interface) */
1610         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1611                 hdmi->hdmi_data.enc_in_format = YCBCR420;
1612                 hdmi->hdmi_data.enc_out_format = YCBCR420;
1613         } else {
1614                 hdmi->hdmi_data.enc_in_format = RGB;
1615                 hdmi->hdmi_data.enc_out_format = RGB;
1616         }
1617         hdmi->hdmi_data.enc_color_depth = 8;
1618         /*
1619          * According to the dw-hdmi specification 6.4.2
1620          * vp_pr_cd[3:0]:
1621          * 0000b: No pixel repetition (pixel sent only once)
1622          * 0001b: Pixel sent two times (pixel repeated once)
1623          */
1624         hdmi->hdmi_data.pix_repet_factor =
1625                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1626         hdmi->hdmi_data.hdcp_enable = 0;
1627         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1628
1629         /* HDMI Initialization Step B.1 */
1630         hdmi_av_composer(hdmi, mode);
1631
1632         /* HDMI Initializateion Step B.2 */
1633         ret = dw_hdmi_phy_init(hdmi);
1634         if (ret)
1635                 return ret;
1636
1637         /* HDMI Initialization Step B.3 */
1638         dw_hdmi_enable_video_path(hdmi);
1639
1640         if (hdmi->sink_has_audio) {
1641                 dev_dbg(hdmi->dev, "sink has audio support\n");
1642
1643                 /* HDMI Initialization Step E - Configure audio */
1644                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1645                 hdmi_enable_audio_clk(hdmi);
1646         }
1647
1648         /* not for DVI mode */
1649         if (hdmi->sink_is_hdmi) {
1650                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1651
1652                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1653                 hdmi_config_AVI(hdmi, mode);
1654         } else {
1655                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1656         }
1657
1658         hdmi_video_packetize(hdmi);
1659         hdmi_video_csc(hdmi);
1660         hdmi_video_sample(hdmi);
1661         hdmi_tx_hdcp_config(hdmi);
1662
1663         dw_hdmi_clear_overflow(hdmi);
1664         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1665                 hdmi_enable_overflow_interrupts(hdmi);
1666
1667         return 0;
1668 }
1669
1670 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1671 {
1672         u8 ih_mute;
1673
1674         /*
1675          * Boot up defaults are:
1676          * HDMI_IH_MUTE   = 0x03 (disabled)
1677          * HDMI_IH_MUTE_* = 0x00 (enabled)
1678          *
1679          * Disable top level interrupt bits in HDMI block
1680          */
1681         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1682                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1683                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1684
1685         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1686
1687         /* by default mask all interrupts */
1688         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1689         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1690         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1691         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1692         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1693         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1694         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1695         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1696         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1697         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1698         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1699         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1700         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1701         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1702         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1703
1704         /* Disable interrupts in the IH_MUTE_* registers */
1705         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1706         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1707         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1708         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1709         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1710         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1711         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1712         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1713         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1714         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1715
1716         /* Enable top level interrupt bits in HDMI block */
1717         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1718                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1719         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1720 }
1721
1722 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1723 {
1724         hdmi->bridge_is_on = true;
1725         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1726 }
1727
1728 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1729 {
1730         dw_hdmi_phy_disable(hdmi);
1731         hdmi->bridge_is_on = false;
1732 }
1733
1734 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1735 {
1736         int force = hdmi->force;
1737
1738         if (hdmi->disabled) {
1739                 force = DRM_FORCE_OFF;
1740         } else if (force == DRM_FORCE_UNSPECIFIED) {
1741                 if (hdmi->rxsense)
1742                         force = DRM_FORCE_ON;
1743                 else
1744                         force = DRM_FORCE_OFF;
1745         }
1746
1747         if (force == DRM_FORCE_OFF) {
1748                 if (hdmi->bridge_is_on)
1749                         dw_hdmi_poweroff(hdmi);
1750         } else {
1751                 if (!hdmi->bridge_is_on)
1752                         dw_hdmi_poweron(hdmi);
1753         }
1754 }
1755
1756 /*
1757  * Adjust the detection of RXSENSE according to whether we have a forced
1758  * connection mode enabled, or whether we have been disabled.  There is
1759  * no point processing RXSENSE interrupts if we have a forced connection
1760  * state, or DRM has us disabled.
1761  *
1762  * We also disable rxsense interrupts when we think we're disconnected
1763  * to avoid floating TDMS signals giving false rxsense interrupts.
1764  *
1765  * Note: we still need to listen for HPD interrupts even when DRM has us
1766  * disabled so that we can detect a connect event.
1767  */
1768 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1769 {
1770         u8 old_mask = hdmi->phy_mask;
1771
1772         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1773                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1774         else
1775                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1776
1777         if (old_mask != hdmi->phy_mask)
1778                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1779 }
1780
1781 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1782                                     struct drm_display_mode *orig_mode,
1783                                     struct drm_display_mode *mode)
1784 {
1785         struct dw_hdmi *hdmi = bridge->driver_private;
1786
1787         mutex_lock(&hdmi->mutex);
1788
1789         /* Store the display mode for plugin/DKMS poweron events */
1790         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1791
1792         mutex_unlock(&hdmi->mutex);
1793 }
1794
1795 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1796 {
1797         struct dw_hdmi *hdmi = bridge->driver_private;
1798
1799         mutex_lock(&hdmi->mutex);
1800         hdmi->disabled = true;
1801         dw_hdmi_update_power(hdmi);
1802         dw_hdmi_update_phy_mask(hdmi);
1803         mutex_unlock(&hdmi->mutex);
1804 }
1805
1806 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1807 {
1808         struct dw_hdmi *hdmi = bridge->driver_private;
1809
1810         mutex_lock(&hdmi->mutex);
1811         hdmi->disabled = false;
1812         dw_hdmi_update_power(hdmi);
1813         dw_hdmi_update_phy_mask(hdmi);
1814         mutex_unlock(&hdmi->mutex);
1815 }
1816
1817 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1818 {
1819         /* do nothing */
1820 }
1821
1822 static enum drm_connector_status
1823 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1824 {
1825         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1826                                              connector);
1827
1828         mutex_lock(&hdmi->mutex);
1829         hdmi->force = DRM_FORCE_UNSPECIFIED;
1830         dw_hdmi_update_power(hdmi);
1831         dw_hdmi_update_phy_mask(hdmi);
1832         mutex_unlock(&hdmi->mutex);
1833
1834         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1835                 connector_status_connected : connector_status_disconnected;
1836 }
1837
1838 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1839 {
1840         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1841                                              connector);
1842         struct edid *edid;
1843         int ret = 0;
1844
1845         if (!hdmi->ddc)
1846                 return 0;
1847
1848         edid = drm_get_edid(connector, hdmi->ddc);
1849         if (edid) {
1850                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1851                         edid->width_cm, edid->height_cm);
1852
1853                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1854                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1855                 drm_mode_connector_update_edid_property(connector, edid);
1856                 ret = drm_add_edid_modes(connector, edid);
1857                 /* Store the ELD */
1858                 drm_edid_to_eld(connector, edid);
1859                 kfree(edid);
1860         } else {
1861                 dev_dbg(hdmi->dev, "failed to get edid\n");
1862         }
1863
1864         return ret;
1865 }
1866
1867 static enum drm_mode_status
1868 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1869                              struct drm_display_mode *mode)
1870 {
1871         struct dw_hdmi *hdmi = container_of(connector,
1872                                            struct dw_hdmi, connector);
1873         enum drm_mode_status mode_status = MODE_OK;
1874
1875         if (hdmi->plat_data->mode_valid)
1876                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1877
1878         return mode_status;
1879 }
1880
1881 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1882                                                            *connector)
1883 {
1884         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1885                                              connector);
1886
1887         return hdmi->encoder;
1888 }
1889
1890 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1891 {
1892         drm_connector_unregister(connector);
1893         drm_connector_cleanup(connector);
1894 }
1895
1896 static void dw_hdmi_connector_force(struct drm_connector *connector)
1897 {
1898         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1899                                              connector);
1900
1901         mutex_lock(&hdmi->mutex);
1902         hdmi->force = connector->force;
1903         dw_hdmi_update_power(hdmi);
1904         dw_hdmi_update_phy_mask(hdmi);
1905         mutex_unlock(&hdmi->mutex);
1906 }
1907
1908 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1909         .dpms = drm_helper_connector_dpms,
1910         .fill_modes = drm_helper_probe_single_connector_modes,
1911         .detect = dw_hdmi_connector_detect,
1912         .destroy = dw_hdmi_connector_destroy,
1913         .force = dw_hdmi_connector_force,
1914 };
1915
1916 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1917         .dpms = drm_atomic_helper_connector_dpms,
1918         .fill_modes = drm_helper_probe_single_connector_modes,
1919         .detect = dw_hdmi_connector_detect,
1920         .destroy = dw_hdmi_connector_destroy,
1921         .force = dw_hdmi_connector_force,
1922         .reset = drm_atomic_helper_connector_reset,
1923         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1924         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1925 };
1926
1927 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1928         .get_modes = dw_hdmi_connector_get_modes,
1929         .mode_valid = dw_hdmi_connector_mode_valid,
1930         .best_encoder = dw_hdmi_connector_best_encoder,
1931 };
1932
1933 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1934         .enable = dw_hdmi_bridge_enable,
1935         .disable = dw_hdmi_bridge_disable,
1936         .pre_enable = dw_hdmi_bridge_nop,
1937         .post_disable = dw_hdmi_bridge_nop,
1938         .mode_set = dw_hdmi_bridge_mode_set,
1939 };
1940
1941 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1942 {
1943         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1944         unsigned int stat;
1945
1946         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1947         if (!stat)
1948                 return IRQ_NONE;
1949
1950         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1951
1952         i2c->stat = stat;
1953
1954         complete(&i2c->cmp);
1955
1956         return IRQ_HANDLED;
1957 }
1958
1959 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1960 {
1961         struct dw_hdmi *hdmi = dev_id;
1962         u8 intr_stat;
1963         irqreturn_t ret = IRQ_NONE;
1964
1965         if (hdmi->i2c)
1966                 ret = dw_hdmi_i2c_irq(hdmi);
1967
1968         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1969         if (intr_stat) {
1970                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1971                 return IRQ_WAKE_THREAD;
1972         }
1973
1974         return ret;
1975 }
1976
1977 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1978 {
1979         struct dw_hdmi *hdmi = dev_id;
1980         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1981
1982         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1983         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1984         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1985
1986         phy_pol_mask = 0;
1987         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1988                 phy_pol_mask |= HDMI_PHY_HPD;
1989         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1990                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1991         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1992                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1993         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1994                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1995         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1996                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1997
1998         if (phy_pol_mask)
1999                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2000
2001         /*
2002          * RX sense tells us whether the TDMS transmitters are detecting
2003          * load - in other words, there's something listening on the
2004          * other end of the link.  Use this to decide whether we should
2005          * power on the phy as HPD may be toggled by the sink to merely
2006          * ask the source to re-read the EDID.
2007          */
2008         if (intr_stat &
2009             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2010                 mutex_lock(&hdmi->mutex);
2011                 if (!hdmi->bridge_is_on && !hdmi->force) {
2012                         /*
2013                          * If the RX sense status indicates we're disconnected,
2014                          * clear the software rxsense status.
2015                          */
2016                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2017                                 hdmi->rxsense = false;
2018
2019                         /*
2020                          * Only set the software rxsense status when both
2021                          * rxsense and hpd indicates we're connected.
2022                          * This avoids what seems to be bad behaviour in
2023                          * at least iMX6S versions of the phy.
2024                          */
2025                         if (phy_stat & HDMI_PHY_HPD)
2026                                 hdmi->rxsense = true;
2027
2028                         dw_hdmi_update_power(hdmi);
2029                         dw_hdmi_update_phy_mask(hdmi);
2030                 }
2031                 mutex_unlock(&hdmi->mutex);
2032         }
2033
2034         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2035                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2036                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2037                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2038 #ifdef CONFIG_SWITCH
2039                 if (phy_int_pol & HDMI_PHY_HPD)
2040                         switch_set_state(&hdmi->switchdev, 1);
2041                 else
2042                         switch_set_state(&hdmi->switchdev, 0);
2043 #endif
2044         }
2045
2046         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2047         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2048                     HDMI_IH_MUTE_PHY_STAT0);
2049
2050         return IRQ_HANDLED;
2051 }
2052
2053 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2054 {
2055         struct drm_encoder *encoder = hdmi->encoder;
2056         struct drm_bridge *bridge;
2057         int ret;
2058
2059         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2060         if (!bridge) {
2061                 DRM_ERROR("Failed to allocate drm bridge\n");
2062                 return -ENOMEM;
2063         }
2064
2065         hdmi->bridge = bridge;
2066         bridge->driver_private = hdmi;
2067         bridge->funcs = &dw_hdmi_bridge_funcs;
2068         ret = drm_bridge_attach(drm, bridge);
2069         if (ret) {
2070                 DRM_ERROR("Failed to initialize bridge with drm\n");
2071                 return -EINVAL;
2072         }
2073
2074         encoder->bridge = bridge;
2075         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2076         hdmi->connector.port = hdmi->dev->of_node;
2077
2078         drm_connector_helper_add(&hdmi->connector,
2079                                  &dw_hdmi_connector_helper_funcs);
2080
2081         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2082                 drm_connector_init(drm, &hdmi->connector,
2083                                    &dw_hdmi_atomic_connector_funcs,
2084                                    DRM_MODE_CONNECTOR_HDMIA);
2085         else
2086                 drm_connector_init(drm, &hdmi->connector,
2087                                    &dw_hdmi_connector_funcs,
2088                                    DRM_MODE_CONNECTOR_HDMIA);
2089
2090         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2091
2092         return 0;
2093 }
2094
2095 int dw_hdmi_bind(struct device *dev, struct device *master,
2096                  void *data, struct drm_encoder *encoder,
2097                  struct resource *iores, int irq,
2098                  const struct dw_hdmi_plat_data *plat_data)
2099 {
2100         struct drm_device *drm = data;
2101         struct device_node *np = dev->of_node;
2102         struct platform_device_info pdevinfo;
2103         struct device_node *ddc_node;
2104         struct dw_hdmi *hdmi;
2105         int ret;
2106         u32 val = 1;
2107         u8 config0;
2108         u8 config1;
2109
2110         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2111         if (!hdmi)
2112                 return -ENOMEM;
2113
2114         hdmi->connector.interlace_allowed = 1;
2115
2116         hdmi->plat_data = plat_data;
2117         hdmi->dev = dev;
2118         hdmi->dev_type = plat_data->dev_type;
2119         hdmi->sample_rate = 48000;
2120         hdmi->encoder = encoder;
2121         hdmi->disabled = true;
2122         hdmi->rxsense = true;
2123         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2124
2125         mutex_init(&hdmi->mutex);
2126         mutex_init(&hdmi->audio_mutex);
2127         spin_lock_init(&hdmi->audio_lock);
2128
2129         of_property_read_u32(np, "reg-io-width", &val);
2130
2131         switch (val) {
2132         case 4:
2133                 hdmi->write = dw_hdmi_writel;
2134                 hdmi->read = dw_hdmi_readl;
2135                 break;
2136         case 1:
2137                 hdmi->write = dw_hdmi_writeb;
2138                 hdmi->read = dw_hdmi_readb;
2139                 break;
2140         default:
2141                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2142                 return -EINVAL;
2143         }
2144
2145         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2146         if (ddc_node) {
2147                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2148                 of_node_put(ddc_node);
2149                 if (!hdmi->ddc) {
2150                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2151                         return -EPROBE_DEFER;
2152                 }
2153
2154         } else {
2155                 dev_dbg(hdmi->dev, "no ddc property found\n");
2156         }
2157
2158         /* If DDC bus is not specified, try to register HDMI I2C bus */
2159         if (!hdmi->ddc) {
2160                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2161                 if (IS_ERR(hdmi->ddc))
2162                         hdmi->ddc = NULL;
2163         }
2164
2165         hdmi->regs = devm_ioremap_resource(dev, iores);
2166         if (IS_ERR(hdmi->regs))
2167                 return PTR_ERR(hdmi->regs);
2168
2169         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2170         if (IS_ERR(hdmi->isfr_clk)) {
2171                 ret = PTR_ERR(hdmi->isfr_clk);
2172                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2173                 return ret;
2174         }
2175
2176         ret = clk_prepare_enable(hdmi->isfr_clk);
2177         if (ret) {
2178                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2179                 return ret;
2180         }
2181
2182         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2183         if (IS_ERR(hdmi->iahb_clk)) {
2184                 ret = PTR_ERR(hdmi->iahb_clk);
2185                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2186                 goto err_isfr;
2187         }
2188
2189         ret = clk_prepare_enable(hdmi->iahb_clk);
2190         if (ret) {
2191                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2192                 goto err_isfr;
2193         }
2194
2195         /* Product and revision IDs */
2196         dev_info(dev,
2197                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2198                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2199                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2200                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2201                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2202
2203         initialize_hdmi_ih_mutes(hdmi);
2204
2205         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2206                                         dw_hdmi_irq, IRQF_SHARED,
2207                                         dev_name(dev), hdmi);
2208         if (ret)
2209                 goto err_iahb;
2210
2211         /*
2212          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2213          * N and cts values before enabling phy
2214          */
2215         hdmi_init_clk_regenerator(hdmi);
2216
2217         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2218                     HDMI_PHY_I2CM_INT_ADDR);
2219
2220         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2221                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2222                     HDMI_PHY_I2CM_CTLINT_ADDR);
2223
2224         /* Re-init HPD polarity */
2225         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2226
2227         /* Unmask HPD, clear transitory interrupts, then unmute */
2228         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2229
2230         ret = dw_hdmi_register(drm, hdmi);
2231         if (ret)
2232                 goto err_iahb;
2233
2234 #ifdef CONFIG_SWITCH
2235         hdmi->switchdev.name = "hdmi";
2236         switch_dev_register(&hdmi->switchdev);
2237 #endif
2238
2239         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2240                     HDMI_IH_MUTE_PHY_STAT0);
2241
2242         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2243         if (hdmi->i2c)
2244                 dw_hdmi_i2c_init(hdmi);
2245
2246         memset(&pdevinfo, 0, sizeof(pdevinfo));
2247         pdevinfo.parent = dev;
2248         pdevinfo.id = PLATFORM_DEVID_AUTO;
2249
2250         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2251         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2252
2253         if (config1 & HDMI_CONFIG1_AHB) {
2254                 struct dw_hdmi_audio_data audio;
2255
2256                 audio.phys = iores->start;
2257                 audio.base = hdmi->regs;
2258                 audio.irq = irq;
2259                 audio.hdmi = hdmi;
2260                 audio.eld = hdmi->connector.eld;
2261
2262                 pdevinfo.name = "dw-hdmi-ahb-audio";
2263                 pdevinfo.data = &audio;
2264                 pdevinfo.size_data = sizeof(audio);
2265                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2266                 hdmi->audio = platform_device_register_full(&pdevinfo);
2267         } else if (config0 & HDMI_CONFIG0_I2S) {
2268                 struct dw_hdmi_i2s_audio_data audio;
2269
2270                 audio.hdmi      = hdmi;
2271                 audio.write     = hdmi_writeb;
2272                 audio.read      = hdmi_readb;
2273
2274                 pdevinfo.name = "dw-hdmi-i2s-audio";
2275                 pdevinfo.data = &audio;
2276                 pdevinfo.size_data = sizeof(audio);
2277                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2278                 hdmi->audio = platform_device_register_full(&pdevinfo);
2279         }
2280
2281         dev_set_drvdata(dev, hdmi);
2282
2283         return 0;
2284
2285 err_iahb:
2286         if (hdmi->i2c)
2287                 i2c_del_adapter(&hdmi->i2c->adap);
2288
2289         clk_disable_unprepare(hdmi->iahb_clk);
2290 err_isfr:
2291         clk_disable_unprepare(hdmi->isfr_clk);
2292
2293         return ret;
2294 }
2295 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2296
2297 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2298 {
2299         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2300
2301         if (hdmi->audio && !IS_ERR(hdmi->audio))
2302                 platform_device_unregister(hdmi->audio);
2303
2304         /* Disable all interrupts */
2305         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2306
2307 #ifdef CONFIG_SWITCH
2308         switch_dev_unregister(&hdmi->switchdev);
2309 #endif
2310         hdmi->connector.funcs->destroy(&hdmi->connector);
2311         hdmi->encoder->funcs->destroy(hdmi->encoder);
2312
2313         clk_disable_unprepare(hdmi->iahb_clk);
2314         clk_disable_unprepare(hdmi->isfr_clk);
2315
2316         if (hdmi->i2c)
2317                 i2c_del_adapter(&hdmi->i2c->adap);
2318         else
2319                 i2c_put_adapter(hdmi->ddc);
2320 }
2321 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2322
2323 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2324 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2325 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2326 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2327 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2328 MODULE_LICENSE("GPL");
2329 MODULE_ALIAS("platform:dw-hdmi");