4a484a018a70365755d183dc1c609e2e97bf79c7
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / bridge / dw-hdmi.c
1 /*
2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
3  *
4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * Designware High-Definition Multimedia Interface (HDMI) driver
14  *
15  */
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/hdmi.h>
22 #include <linux/mutex.h>
23 #include <linux/of_device.h>
24 #include <linux/spinlock.h>
25
26 #include <drm/drm_of.h>
27 #include <drm/drmP.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_encoder_slave.h>
32 #include <drm/drm_scdc_helper.h>
33 #include <drm/bridge/dw_hdmi.h>
34 #ifdef CONFIG_SWITCH
35 #include <linux/switch.h>
36 #endif
37
38 #include "dw-hdmi.h"
39 #include "dw-hdmi-audio.h"
40
41 #define HDMI_EDID_LEN           512
42 #define DDC_SEGMENT_ADDR       0x30
43
44 #define RGB                     0
45 #define YCBCR444                1
46 #define YCBCR422_16BITS         2
47 #define YCBCR422_8BITS          3
48 #define XVYCC444                4
49 #define YCBCR420                5
50
51 enum hdmi_datamap {
52         RGB444_8B = 0x01,
53         RGB444_10B = 0x03,
54         RGB444_12B = 0x05,
55         RGB444_16B = 0x07,
56         YCbCr444_8B = 0x09,
57         YCbCr444_10B = 0x0B,
58         YCbCr444_12B = 0x0D,
59         YCbCr444_16B = 0x0F,
60         YCbCr422_8B = 0x16,
61         YCbCr422_10B = 0x14,
62         YCbCr422_12B = 0x12,
63 };
64
65 /*
66  * Unless otherwise noted, entries in this table are 100% optimization.
67  * Values can be obtained from hdmi_compute_n() but that function is
68  * slow so we pre-compute values we expect to see.
69  *
70  * All 32k and 48k values are expected to be the same (due to the way
71  * the math works) for any rate that's an exact kHz.
72  */
73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
74         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
75         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
76         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
78         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
79         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
80         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
81         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
82         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
83         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
84         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
85         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
86         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
87         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
88         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
89         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
90         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
91         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
93         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
94         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
95         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
96         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
98         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
99         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
100         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
101         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
102         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
103         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
104         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
105         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
106         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
107         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
108         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
109         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
110         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
111
112         /* For 297 MHz+ HDMI spec have some other rule for setting N */
113         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
114         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
115
116         /* End of table */
117         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
118 };
119
120
121 static const u16 csc_coeff_default[3][4] = {
122         { 0x2000, 0x0000, 0x0000, 0x0000 },
123         { 0x0000, 0x2000, 0x0000, 0x0000 },
124         { 0x0000, 0x0000, 0x2000, 0x0000 }
125 };
126
127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
128         { 0x2000, 0x6926, 0x74fd, 0x010e },
129         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
130         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
131 };
132
133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
134         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
135         { 0x2000, 0x3264, 0x0000, 0x7e6d },
136         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
137 };
138
139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
140         { 0x2591, 0x1322, 0x074b, 0x0000 },
141         { 0x6535, 0x2000, 0x7acc, 0x0200 },
142         { 0x6acd, 0x7534, 0x2000, 0x0200 }
143 };
144
145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
146         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
147         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
148         { 0x6756, 0x78ab, 0x2000, 0x0200 }
149 };
150
151 struct hdmi_vmode {
152         bool mdataenablepolarity;
153
154         unsigned int mpixelclock;
155         unsigned int mpixelrepetitioninput;
156         unsigned int mpixelrepetitionoutput;
157 };
158
159 struct hdmi_data_info {
160         unsigned int enc_in_format;
161         unsigned int enc_out_format;
162         unsigned int enc_color_depth;
163         unsigned int colorimetry;
164         unsigned int pix_repet_factor;
165         unsigned int hdcp_enable;
166         struct hdmi_vmode video_mode;
167 };
168
169 struct dw_hdmi_i2c {
170         struct i2c_adapter      adap;
171
172         struct mutex            lock;
173         struct completion       cmp;
174         u8                      stat;
175
176         u8                      slave_reg;
177         bool                    is_regaddr;
178         bool                    is_segment;
179 };
180
181 struct dw_hdmi {
182         struct drm_connector connector;
183         struct drm_encoder *encoder;
184         struct drm_bridge *bridge;
185
186         struct platform_device *audio;
187         enum dw_hdmi_devtype dev_type;
188         struct device *dev;
189         struct clk *isfr_clk;
190         struct clk *iahb_clk;
191         struct dw_hdmi_i2c *i2c;
192
193         struct hdmi_data_info hdmi_data;
194         const struct dw_hdmi_plat_data *plat_data;
195
196         int vic;
197
198         u8 edid[HDMI_EDID_LEN];
199         bool cable_plugin;
200
201         bool phy_enabled;
202         struct drm_display_mode previous_mode;
203
204         struct i2c_adapter *ddc;
205         void __iomem *regs;
206         bool sink_is_hdmi;
207         bool sink_has_audio;
208
209         struct mutex mutex;             /* for state below and previous_mode */
210         enum drm_connector_force force; /* mutex-protected force state */
211         bool disabled;                  /* DRM has disabled our bridge */
212         bool bridge_is_on;              /* indicates the bridge is on */
213         bool rxsense;                   /* rxsense state */
214         u8 phy_mask;                    /* desired phy int mask settings */
215
216         spinlock_t audio_lock;
217         struct mutex audio_mutex;
218         unsigned int sample_rate;
219         unsigned int audio_cts;
220         unsigned int audio_n;
221         bool audio_enable;
222
223 #ifdef CONFIG_SWITCH
224         struct switch_dev switchdev;
225 #endif
226         int irq;
227
228         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
229         u8 (*read)(struct dw_hdmi *hdmi, int offset);
230 };
231
232 #define HDMI_IH_PHY_STAT0_RX_SENSE \
233         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
234          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
235
236 #define HDMI_PHY_RX_SENSE \
237         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
238          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
239
240 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
241 {
242         writel(val, hdmi->regs + (offset << 2));
243 }
244
245 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
246 {
247         return readl(hdmi->regs + (offset << 2));
248 }
249
250 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
251 {
252         writeb(val, hdmi->regs + offset);
253 }
254
255 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
256 {
257         return readb(hdmi->regs + offset);
258 }
259
260 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
261 {
262         hdmi->write(hdmi, val, offset);
263 }
264
265 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
266 {
267         return hdmi->read(hdmi, offset);
268 }
269
270 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
271 {
272         u8 val = hdmi_readb(hdmi, reg) & ~mask;
273
274         val |= data & mask;
275         hdmi_writeb(hdmi, val, reg);
276 }
277
278 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
279                              u8 shift, u8 mask)
280 {
281         hdmi_modb(hdmi, data << shift, mask, reg);
282 }
283
284 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
285 {
286         /* Software reset */
287         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
288
289         /* Set Standard Mode speed */
290         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
291                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
292
293         /* Set done, not acknowledged and arbitration interrupt polarities */
294         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
295         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
296                     HDMI_I2CM_CTLINT);
297
298         /* Clear DONE and ERROR interrupts */
299         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
300                     HDMI_IH_I2CM_STAT0);
301
302         /* Mute DONE and ERROR interrupts */
303         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
304                     HDMI_IH_MUTE_I2CM_STAT0);
305 }
306
307 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
308                             unsigned char *buf, unsigned int length)
309 {
310         struct dw_hdmi_i2c *i2c = hdmi->i2c;
311         int stat;
312
313         if (!i2c->is_regaddr) {
314                 dev_dbg(hdmi->dev, "set read register address to 0\n");
315                 i2c->slave_reg = 0x00;
316                 i2c->is_regaddr = true;
317         }
318
319         while (length--) {
320                 reinit_completion(&i2c->cmp);
321
322                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
323                 if (i2c->is_segment)
324                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
325                                     HDMI_I2CM_OPERATION);
326                 else
327                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
328                                     HDMI_I2CM_OPERATION);
329
330                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
331                 if (!stat)
332                         return -EAGAIN;
333
334                 /* Check for error condition on the bus */
335                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
336                         return -EIO;
337
338                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
339         }
340         i2c->is_segment = false;
341
342         return 0;
343 }
344
345 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
346                              unsigned char *buf, unsigned int length)
347 {
348         struct dw_hdmi_i2c *i2c = hdmi->i2c;
349         int stat;
350
351         if (!i2c->is_regaddr) {
352                 /* Use the first write byte as register address */
353                 i2c->slave_reg = buf[0];
354                 length--;
355                 buf++;
356                 i2c->is_regaddr = true;
357         }
358
359         while (length--) {
360                 reinit_completion(&i2c->cmp);
361
362                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
363                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
364                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
365                             HDMI_I2CM_OPERATION);
366
367         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
368                 if (!stat)
369                         return -EAGAIN;
370
371                 /* Check for error condition on the bus */
372                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
373                         return -EIO;
374         }
375
376         return 0;
377 }
378
379 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
380                             struct i2c_msg *msgs, int num)
381 {
382         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
383         struct dw_hdmi_i2c *i2c = hdmi->i2c;
384         u8 addr = msgs[0].addr;
385         int i, ret = 0;
386
387         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
388
389         for (i = 0; i < num; i++) {
390                 if (msgs[i].len == 0) {
391                         dev_dbg(hdmi->dev,
392                                 "unsupported transfer %d/%d, no data\n",
393                                 i + 1, num);
394                         return -EOPNOTSUPP;
395                 }
396         }
397
398         mutex_lock(&i2c->lock);
399
400         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
401
402         /* Set slave device address taken from the first I2C message */
403         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
404
405         /* Set slave device register address on transfer */
406         i2c->is_regaddr = false;
407
408         /* Set segment pointer for I2C extended read mode operation */
409         i2c->is_segment = false;
410
411         for (i = 0; i < num; i++) {
412                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
413                         i + 1, num, msgs[i].len, msgs[i].flags);
414                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
415                         i2c->is_segment = true;
416                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
417                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
418                 } else {
419                         if (msgs[i].flags & I2C_M_RD)
420                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
421                                                        msgs[i].len);
422                         else
423                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
424                                                         msgs[i].len);
425                 }
426                 if (ret < 0)
427                         break;
428         }
429
430         if (!ret)
431                 ret = num;
432
433         /* Mute DONE and ERROR interrupts */
434         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
435                     HDMI_IH_MUTE_I2CM_STAT0);
436
437         mutex_unlock(&i2c->lock);
438
439         return ret;
440 }
441
442 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
443 {
444         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
445 }
446
447 static const struct i2c_algorithm dw_hdmi_algorithm = {
448         .master_xfer    = dw_hdmi_i2c_xfer,
449         .functionality  = dw_hdmi_i2c_func,
450 };
451
452 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
453 {
454         struct i2c_adapter *adap;
455         struct dw_hdmi_i2c *i2c;
456         int ret;
457
458         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
459         if (!i2c)
460                 return ERR_PTR(-ENOMEM);
461
462         mutex_init(&i2c->lock);
463         init_completion(&i2c->cmp);
464
465         adap = &i2c->adap;
466         adap->class = I2C_CLASS_DDC;
467         adap->owner = THIS_MODULE;
468         adap->dev.parent = hdmi->dev;
469         adap->dev.of_node = hdmi->dev->of_node;
470         adap->algo = &dw_hdmi_algorithm;
471         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
472         i2c_set_adapdata(adap, hdmi);
473
474         ret = i2c_add_adapter(adap);
475         if (ret) {
476                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
477                 devm_kfree(hdmi->dev, i2c);
478                 return ERR_PTR(ret);
479         }
480
481         hdmi->i2c = i2c;
482
483         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
484
485         return adap;
486 }
487
488 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
489                            unsigned int n)
490 {
491         /* Must be set/cleared first */
492         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
493
494         /* nshift factor = 0 */
495         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
496
497         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
498                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
499         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
500         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
501
502         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
503         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
504         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
505 }
506
507 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
508                                    unsigned long pixel_clk,
509                                    unsigned long freq)
510 {
511         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
512         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
513         int i;
514
515         if (plat_data->tmds_n_table) {
516                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
517                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
518                                 tmds_n = &plat_data->tmds_n_table[i];
519                                 break;
520                         }
521                 }
522         }
523
524         if (tmds_n == NULL) {
525                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
526                         if (pixel_clk == common_tmds_n_table[i].tmds) {
527                                 tmds_n = &common_tmds_n_table[i];
528                                 break;
529                         }
530                 }
531         }
532
533         if (tmds_n == NULL)
534                 return -ENOENT;
535
536         switch (freq) {
537         case 32000:
538                 return tmds_n->n_32k;
539         case 44100:
540         case 88200:
541         case 176400:
542                 return (freq / 44100) * tmds_n->n_44k1;
543         case 48000:
544         case 96000:
545         case 192000:
546                 return (freq / 48000) * tmds_n->n_48k;
547         default:
548                 return -ENOENT;
549         }
550 }
551
552 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
553                                 unsigned int pixel_clk)
554 {
555         u64 final, diff;
556         u64 cts;
557
558         final = (u64)pixel_clk * n;
559
560         cts = final;
561         do_div(cts, 128 * freq);
562
563         diff = final - (u64)cts * (128 * freq);
564
565         return diff;
566 }
567
568 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
569                                    unsigned long pixel_clk,
570                                    unsigned long freq)
571 {
572         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
573         unsigned int max_n = (128 * freq) / 300;
574         unsigned int ideal_n = (128 * freq) / 1000;
575         unsigned int best_n_distance = ideal_n;
576         unsigned int best_n = 0;
577         u64 best_diff = U64_MAX;
578         int n;
579
580         /* If the ideal N could satisfy the audio math, then just take it */
581         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
582                 return ideal_n;
583
584         for (n = min_n; n <= max_n; n++) {
585                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
586
587                 if (diff < best_diff || (diff == best_diff &&
588                     abs(n - ideal_n) < best_n_distance)) {
589                         best_n = n;
590                         best_diff = diff;
591                         best_n_distance = abs(best_n - ideal_n);
592                 }
593
594                 /*
595                  * The best N already satisfy the audio math, and also be
596                  * the closest value to ideal N, so just cut the loop.
597                  */
598                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
599                         break;
600         }
601
602         return best_n;
603 }
604
605 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
606                                 unsigned long sample_rate)
607 {
608         int n;
609
610         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
611         if (n > 0)
612                 return n;
613
614         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
615                  pixel_clk);
616
617         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
618 }
619
620 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
621         unsigned long pixel_clk, unsigned int sample_rate)
622 {
623         unsigned long ftdms = pixel_clk;
624         unsigned int n, cts;
625         u64 tmp;
626
627         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
628
629         /*
630          * Compute the CTS value from the N value.  Note that CTS and N
631          * can be up to 20 bits in total, so we need 64-bit math.  Also
632          * note that our TDMS clock is not fully accurate; it is accurate
633          * to kHz.  This can introduce an unnecessary remainder in the
634          * calculation below, so we don't try to warn about that.
635          */
636         tmp = (u64)ftdms * n;
637         do_div(tmp, 128 * sample_rate);
638         cts = tmp;
639
640         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
641                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
642                 n, cts);
643
644         spin_lock_irq(&hdmi->audio_lock);
645         hdmi->audio_n = n;
646         hdmi->audio_cts = cts;
647         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
648         spin_unlock_irq(&hdmi->audio_lock);
649 }
650
651 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
652 {
653         mutex_lock(&hdmi->audio_mutex);
654         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
655         mutex_unlock(&hdmi->audio_mutex);
656 }
657
658 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
659 {
660         mutex_lock(&hdmi->audio_mutex);
661         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
662                                  hdmi->sample_rate);
663         mutex_unlock(&hdmi->audio_mutex);
664 }
665
666 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
667 {
668         mutex_lock(&hdmi->audio_mutex);
669         hdmi->sample_rate = rate;
670         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
671                                  hdmi->sample_rate);
672         mutex_unlock(&hdmi->audio_mutex);
673 }
674 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
675
676 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
677 {
678         unsigned long flags;
679
680         spin_lock_irqsave(&hdmi->audio_lock, flags);
681         hdmi->audio_enable = true;
682         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
683         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
684 }
685 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
686
687 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
688 {
689         unsigned long flags;
690
691         spin_lock_irqsave(&hdmi->audio_lock, flags);
692         hdmi->audio_enable = false;
693         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
694         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
695 }
696 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
697
698 /*
699  * this submodule is responsible for the video data synchronization.
700  * for example, for RGB 4:4:4 input, the data map is defined as
701  *                      pin{47~40} <==> R[7:0]
702  *                      pin{31~24} <==> G[7:0]
703  *                      pin{15~8}  <==> B[7:0]
704  */
705 static void hdmi_video_sample(struct dw_hdmi *hdmi)
706 {
707         int color_format = 0;
708         u8 val;
709
710         if (hdmi->hdmi_data.enc_in_format == RGB) {
711                 if (hdmi->hdmi_data.enc_color_depth == 8)
712                         color_format = 0x01;
713                 else if (hdmi->hdmi_data.enc_color_depth == 10)
714                         color_format = 0x03;
715                 else if (hdmi->hdmi_data.enc_color_depth == 12)
716                         color_format = 0x05;
717                 else if (hdmi->hdmi_data.enc_color_depth == 16)
718                         color_format = 0x07;
719                 else
720                         return;
721         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
722                    hdmi->hdmi_data.enc_in_format == YCBCR420) {
723                 if (hdmi->hdmi_data.enc_color_depth == 8)
724                         color_format = 0x09;
725                 else if (hdmi->hdmi_data.enc_color_depth == 10)
726                         color_format = 0x0B;
727                 else if (hdmi->hdmi_data.enc_color_depth == 12)
728                         color_format = 0x0D;
729                 else if (hdmi->hdmi_data.enc_color_depth == 16)
730                         color_format = 0x0F;
731                 else
732                         return;
733         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
734                 if (hdmi->hdmi_data.enc_color_depth == 8)
735                         color_format = 0x16;
736                 else if (hdmi->hdmi_data.enc_color_depth == 10)
737                         color_format = 0x14;
738                 else if (hdmi->hdmi_data.enc_color_depth == 12)
739                         color_format = 0x12;
740                 else
741                         return;
742         }
743
744         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
745                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
746                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
747         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
748
749         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
750         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
751                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
752                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
753         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
754         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
755         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
756         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
757         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
758         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
759         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
760 }
761
762 static int is_color_space_conversion(struct dw_hdmi *hdmi)
763 {
764         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
765 }
766
767 static int is_color_space_decimation(struct dw_hdmi *hdmi)
768 {
769         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
770                 return 0;
771         if (hdmi->hdmi_data.enc_in_format == RGB ||
772             hdmi->hdmi_data.enc_in_format == YCBCR444)
773                 return 1;
774         return 0;
775 }
776
777 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
778 {
779         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
780                 return 0;
781         if (hdmi->hdmi_data.enc_out_format == RGB ||
782             hdmi->hdmi_data.enc_out_format == YCBCR444)
783                 return 1;
784         return 0;
785 }
786
787 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
788 {
789         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
790         unsigned i;
791         u32 csc_scale = 1;
792
793         if (is_color_space_conversion(hdmi)) {
794                 if (hdmi->hdmi_data.enc_out_format == RGB) {
795                         if (hdmi->hdmi_data.colorimetry ==
796                                         HDMI_COLORIMETRY_ITU_601)
797                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
798                         else
799                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
800                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
801                         if (hdmi->hdmi_data.colorimetry ==
802                                         HDMI_COLORIMETRY_ITU_601)
803                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
804                         else
805                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
806                         csc_scale = 0;
807                 }
808         }
809
810         /* The CSC registers are sequential, alternating MSB then LSB */
811         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
812                 u16 coeff_a = (*csc_coeff)[0][i];
813                 u16 coeff_b = (*csc_coeff)[1][i];
814                 u16 coeff_c = (*csc_coeff)[2][i];
815
816                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
817                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
818                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
819                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
820                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
821                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
822         }
823
824         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
825                   HDMI_CSC_SCALE);
826 }
827
828 static void hdmi_video_csc(struct dw_hdmi *hdmi)
829 {
830         int color_depth = 0;
831         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
832         int decimation = 0;
833
834         /* YCC422 interpolation to 444 mode */
835         if (is_color_space_interpolation(hdmi))
836                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
837         else if (is_color_space_decimation(hdmi))
838                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
839
840         if (hdmi->hdmi_data.enc_color_depth == 8)
841                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
842         else if (hdmi->hdmi_data.enc_color_depth == 10)
843                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
844         else if (hdmi->hdmi_data.enc_color_depth == 12)
845                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
846         else if (hdmi->hdmi_data.enc_color_depth == 16)
847                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
848         else
849                 return;
850
851         /* Configure the CSC registers */
852         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
853         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
854                   HDMI_CSC_SCALE);
855
856         dw_hdmi_update_csc_coeffs(hdmi);
857 }
858
859 /*
860  * HDMI video packetizer is used to packetize the data.
861  * for example, if input is YCC422 mode or repeater is used,
862  * data should be repacked this module can be bypassed.
863  */
864 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
865 {
866         unsigned int color_depth = 0;
867         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
868         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
869         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
870         u8 val, vp_conf;
871
872         if (hdmi_data->enc_out_format == RGB ||
873             hdmi_data->enc_out_format == YCBCR444 ||
874             hdmi_data->enc_out_format == YCBCR420) {
875                 if (!hdmi_data->enc_color_depth) {
876                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
877                 } else if (hdmi_data->enc_color_depth == 8) {
878                         color_depth = 4;
879                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
880                 } else if (hdmi_data->enc_color_depth == 10) {
881                         color_depth = 5;
882                 } else if (hdmi_data->enc_color_depth == 12) {
883                         color_depth = 6;
884                 } else if (hdmi_data->enc_color_depth == 16) {
885                         color_depth = 7;
886                 } else {
887                         return;
888                 }
889         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
890                 if (!hdmi_data->enc_color_depth ||
891                     hdmi_data->enc_color_depth == 8)
892                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
893                 else if (hdmi_data->enc_color_depth == 10)
894                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
895                 else if (hdmi_data->enc_color_depth == 12)
896                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
897                 else
898                         return;
899                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
900         } else {
901                 return;
902         }
903
904         /* set the packetizer registers */
905         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
906                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
907                 ((hdmi_data->pix_repet_factor <<
908                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
909                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
910         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
911
912         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
913                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
914
915         /* Data from pixel repeater block */
916         if (hdmi_data->pix_repet_factor > 0) {
917                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
918                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
919         } else { /* data from packetizer block */
920                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
921                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
922         }
923
924         hdmi_modb(hdmi, vp_conf,
925                   HDMI_VP_CONF_PR_EN_MASK |
926                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
927
928         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
929                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
930
931         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
932
933         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
934                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
935                           HDMI_VP_CONF_PP_EN_ENABLE |
936                           HDMI_VP_CONF_YCC422_EN_DISABLE;
937         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
938                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
939                           HDMI_VP_CONF_PP_EN_DISABLE |
940                           HDMI_VP_CONF_YCC422_EN_ENABLE;
941         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
942                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
943                           HDMI_VP_CONF_PP_EN_DISABLE |
944                           HDMI_VP_CONF_YCC422_EN_DISABLE;
945         } else {
946                 return;
947         }
948
949         hdmi_modb(hdmi, vp_conf,
950                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
951                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
952
953         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
954                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
955                   HDMI_VP_STUFF_PP_STUFFING_MASK |
956                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
957
958         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
959                   HDMI_VP_CONF);
960 }
961
962 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
963                                        unsigned char bit)
964 {
965         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
966                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
967 }
968
969 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
970                                         unsigned char bit)
971 {
972         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
973                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
974 }
975
976 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
977                                        unsigned char bit)
978 {
979         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
980                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
981 }
982
983 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
984                                      unsigned char bit)
985 {
986         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
987 }
988
989 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
990                                       unsigned char bit)
991 {
992         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
993 }
994
995 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
996 {
997         u32 val;
998
999         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1000                 if (msec-- == 0)
1001                         return false;
1002                 udelay(1000);
1003         }
1004         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1005
1006         return true;
1007 }
1008
1009 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1010                                  unsigned char addr)
1011 {
1012         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1013         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1014         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1015                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1016         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1017                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1018         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1019                     HDMI_PHY_I2CM_OPERATION_ADDR);
1020         hdmi_phy_wait_i2c_done(hdmi, 1000);
1021 }
1022
1023 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1024                               unsigned char addr)
1025 {
1026         __hdmi_phy_i2c_write(hdmi, data, addr);
1027         return 0;
1028 }
1029
1030 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1031 {
1032         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1033                          HDMI_PHY_CONF0_PDZ_OFFSET,
1034                          HDMI_PHY_CONF0_PDZ_MASK);
1035 }
1036
1037 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1038 {
1039         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1040                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1041                          HDMI_PHY_CONF0_ENTMDS_MASK);
1042 }
1043
1044 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1045 {
1046         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1047                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1048                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1049 }
1050
1051 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1052 {
1053         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1054                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1055                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1056 }
1057
1058 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1059 {
1060         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1061                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1062                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1063 }
1064
1065 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1066 {
1067         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1068                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1069                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1070 }
1071
1072 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1073 {
1074         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1075                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1076                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1077 }
1078
1079 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1080                               unsigned char res, int cscon)
1081 {
1082         unsigned res_idx;
1083         u8 val, msec, tmds_cfg;
1084         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1085         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1086         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1087         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1088
1089         if (prep)
1090                 return -EINVAL;
1091
1092         switch (res) {
1093         case 0: /* color resolution 0 is 8 bit colour depth */
1094         case 8:
1095                 res_idx = DW_HDMI_RES_8;
1096                 break;
1097         case 10:
1098                 res_idx = DW_HDMI_RES_10;
1099                 break;
1100         case 12:
1101                 res_idx = DW_HDMI_RES_12;
1102                 break;
1103         default:
1104                 return -EINVAL;
1105         }
1106
1107         /* PLL/MPLL Cfg - always match on final entry */
1108         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1109                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1110                     mpll_config->mpixelclock)
1111                         break;
1112
1113         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1114                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1115                     curr_ctrl->mpixelclock)
1116                         break;
1117
1118         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1119                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1120                     phy_config->mpixelclock)
1121                         break;
1122
1123         if (mpll_config->mpixelclock == ~0UL ||
1124             curr_ctrl->mpixelclock == ~0UL ||
1125             phy_config->mpixelclock == ~0UL) {
1126                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1127                         hdmi->hdmi_data.video_mode.mpixelclock);
1128                 return -EINVAL;
1129         }
1130
1131         /* Enable csc path */
1132         if (cscon)
1133                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1134         else
1135                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1136
1137         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1138
1139         /* gen2 tx power off */
1140         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1141
1142         /* gen2 pddq */
1143         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1144
1145         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1146         if (hdmi->connector.scdc_present) {
1147                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1148                 if (mpll_config->mpixelclock > 340000000)
1149                         tmds_cfg |= 2;
1150                 else
1151                         tmds_cfg &= 0x1;
1152                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1153         }
1154
1155         /* PHY reset */
1156         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1157         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1158
1159         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1160
1161         hdmi_phy_test_clear(hdmi, 1);
1162         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1163                     HDMI_PHY_I2CM_SLAVE_ADDR);
1164         hdmi_phy_test_clear(hdmi, 0);
1165         /*
1166          * RK3399 mpll clock source is vpll, also is vop clock source.
1167          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1168          * to enable mpll pre-divider.
1169          */
1170         if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1171             hdmi->dev_type == RK3399_HDMI)
1172                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1173                                    0x06);
1174         else
1175                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1176         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1177
1178         /* CURRCTRL */
1179         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1180
1181         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1182         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1183
1184         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1185         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1186         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1187
1188         /* REMOVE CLK TERM */
1189         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1190
1191         dw_hdmi_phy_enable_powerdown(hdmi, false);
1192
1193         /* toggle TMDS disable */
1194         dw_hdmi_phy_enable_tmds(hdmi, 0);
1195
1196         /* Wait for resuming transmission of TMDS clock and data */
1197         if (mpll_config->mpixelclock > 340000000)
1198                 msleep(100);
1199
1200         /* toggle TMDS enable */
1201         dw_hdmi_phy_enable_tmds(hdmi, 1);
1202
1203         /* gen2 tx power on */
1204         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1205         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1206
1207         if (is_rockchip(hdmi->dev_type))
1208                 dw_hdmi_phy_enable_spare(hdmi, 1);
1209
1210         /* Wait for PHY PLL lock */
1211         msec = 5;
1212         do {
1213                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1214                 if (!val)
1215                         break;
1216
1217                 if (msec == 0) {
1218                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1219                         return -ETIMEDOUT;
1220                 }
1221
1222                 udelay(1000);
1223                 msec--;
1224         } while (1);
1225
1226         return 0;
1227 }
1228
1229 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1230 {
1231         int i, ret;
1232         bool cscon;
1233
1234         /*check csc whether needed activated in HDMI mode */
1235         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1236
1237         /* HDMI Phy spec says to do the phy initialization sequence twice */
1238         for (i = 0; i < 2; i++) {
1239                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1240                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1241                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1242                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1243
1244                 /* Enable CSC */
1245                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1246                 if (ret)
1247                         return ret;
1248         }
1249
1250         hdmi->phy_enabled = true;
1251         return 0;
1252 }
1253
1254 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1255 {
1256         u8 de;
1257
1258         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1259                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1260         else
1261                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1262
1263         /* disable rx detect */
1264         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1265                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1266
1267         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1268
1269         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1270                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1271 }
1272
1273 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1274 {
1275         struct hdmi_avi_infoframe frame;
1276         u8 val;
1277
1278         /* Initialise info frame from DRM mode */
1279         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1280
1281         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1282                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1283         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1284                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1285         else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1286                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1287         else
1288                 frame.colorspace = HDMI_COLORSPACE_RGB;
1289
1290         /* Set up colorimetry */
1291         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1292                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1293                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1294                         frame.extended_colorimetry =
1295                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1296                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1297                         frame.extended_colorimetry =
1298                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1299         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1300                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1301                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1302         } else { /* Carries no data */
1303                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1304                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1305         }
1306
1307         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1308
1309         /*
1310          * The Designware IP uses a different byte format from standard
1311          * AVI info frames, though generally the bits are in the correct
1312          * bytes.
1313          */
1314
1315         /*
1316          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1317          * 5,6,7, active aspect present in bit 6 rather than 4.
1318          */
1319         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1320         if (frame.active_aspect & 15)
1321                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1322         if (frame.top_bar || frame.bottom_bar)
1323                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1324         if (frame.left_bar || frame.right_bar)
1325                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1326         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1327
1328         /* AVI data byte 2 differences: none */
1329         val = ((frame.colorimetry & 0x3) << 6) |
1330               ((frame.picture_aspect & 0x3) << 4) |
1331               (frame.active_aspect & 0xf);
1332         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1333
1334         /* AVI data byte 3 differences: none */
1335         val = ((frame.extended_colorimetry & 0x7) << 4) |
1336               ((frame.quantization_range & 0x3) << 2) |
1337               (frame.nups & 0x3);
1338         if (frame.itc)
1339                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1340         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1341
1342         /* AVI data byte 4 differences: none */
1343         val = frame.video_code & 0x7f;
1344         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1345
1346         /* AVI Data Byte 5- set up input and output pixel repetition */
1347         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1348                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1349                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1350                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1351                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1352                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1353         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1354
1355         /*
1356          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1357          * ycc range in bits 2,3 rather than 6,7
1358          */
1359         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1360               (frame.content_type & 0x3);
1361         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1362
1363         /* AVI Data Bytes 6-13 */
1364         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1365         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1366         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1367         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1368         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1369         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1370         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1371         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1372 }
1373
1374 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1375                              const struct drm_display_mode *mode)
1376 {
1377         u8 inv_val, bytes;
1378         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1379         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1380         unsigned int hdisplay, vdisplay;
1381
1382         vmode->mpixelclock = mode->crtc_clock * 1000;
1383         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1384                 vmode->mpixelclock /= 2;
1385         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1386
1387         /* Set up HDMI_FC_INVIDCONF
1388          * fc_invidconf.HDCP_keepout must be set (1'b1)
1389          * when activate the scrambler feature.
1390          */
1391         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1392                    vmode->mpixelclock > 340000000 ||
1393                    hdmi->connector.lte_340mcsc_scramble ?
1394                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1395                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1396
1397         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1398                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1399                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1400
1401         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1402                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1403                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1404
1405         inv_val |= (vmode->mdataenablepolarity ?
1406                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1407                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1408
1409         if (hdmi->vic == 39)
1410                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1411         else
1412                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1413                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1414                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1415
1416         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1417                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1418                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1419
1420         inv_val |= hdmi->sink_is_hdmi ?
1421                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1422                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1423
1424         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1425
1426         hdisplay = mode->hdisplay;
1427         hblank = mode->htotal - mode->hdisplay;
1428         h_de_hs = mode->hsync_start - mode->hdisplay;
1429         hsync_len = mode->hsync_end - mode->hsync_start;
1430
1431         /*
1432          * When we're setting a YCbCr420 mode, we need
1433          * to adjust the horizontal timing to suit.
1434          */
1435         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1436                 hdisplay /= 2;
1437                 hblank /= 2;
1438                 h_de_hs /= 2;
1439                 hsync_len /= 2;
1440         }
1441
1442         vdisplay = mode->vdisplay;
1443         vblank = mode->vtotal - mode->vdisplay;
1444         v_de_vs = mode->vsync_start - mode->vdisplay;
1445         vsync_len = mode->vsync_end - mode->vsync_start;
1446
1447         /*
1448          * When we're setting an interlaced mode, we need
1449          * to adjust the vertical timing to suit.
1450          */
1451         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1452                 vdisplay /= 2;
1453                 vblank /= 2;
1454                 v_de_vs /= 2;
1455                 vsync_len /= 2;
1456         }
1457
1458         /* Scrambling Control */
1459         if (hdmi->connector.scdc_present) {
1460                 if (vmode->mpixelclock > 340000000 ||
1461                     hdmi->connector.lte_340mcsc_scramble) {
1462                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1463                                        &bytes);
1464                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1465                                         bytes);
1466                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1467                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1468                                     HDMI_MC_SWRSTZ);
1469                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1470                 } else {
1471                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1472                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1473                                     HDMI_MC_SWRSTZ);
1474                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1475                 }
1476         }
1477
1478         /* Set up horizontal active pixel width */
1479         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1480         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1481
1482         /* Set up vertical active lines */
1483         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1484         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1485
1486         /* Set up horizontal blanking pixel region width */
1487         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1488         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1489
1490         /* Set up vertical blanking pixel region width */
1491         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1492
1493         /* Set up HSYNC active edge delay width (in pixel clks) */
1494         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1495         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1496
1497         /* Set up VSYNC active edge delay (in lines) */
1498         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1499
1500         /* Set up HSYNC active pulse width (in pixel clks) */
1501         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1502         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1503
1504         /* Set up VSYNC active edge delay (in lines) */
1505         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1506 }
1507
1508 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1509 {
1510         if (!hdmi->phy_enabled)
1511                 return;
1512
1513         dw_hdmi_phy_enable_tmds(hdmi, 0);
1514         dw_hdmi_phy_enable_powerdown(hdmi, true);
1515
1516         hdmi->phy_enabled = false;
1517 }
1518
1519 /* HDMI Initialization Step B.4 */
1520 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1521 {
1522         u8 clkdis;
1523
1524         /* control period minimum duration */
1525         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1526         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1527         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1528
1529         /* Set to fill TMDS data channels */
1530         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1531         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1532         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1533
1534         /* Enable pixel clock and tmds data path */
1535         clkdis = 0x7F;
1536         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1537         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1538
1539         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1540         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1541
1542         /* Enable csc path */
1543         if (is_color_space_conversion(hdmi)) {
1544                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1545                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1546         }
1547
1548         /* Enable pixel repetition path */
1549         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1550                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1551                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1552         }
1553 }
1554
1555 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1556 {
1557         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1558 }
1559
1560 /* Workaround to clear the overflow condition */
1561 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1562 {
1563         int count;
1564         u8 val;
1565
1566         /* TMDS software reset */
1567         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1568
1569         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1570         if (hdmi->dev_type == IMX6DL_HDMI) {
1571                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1572                 return;
1573         }
1574
1575         for (count = 0; count < 4; count++)
1576                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1577 }
1578
1579 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1580 {
1581         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1582         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1583 }
1584
1585 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1586 {
1587         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1588                     HDMI_IH_MUTE_FC_STAT2);
1589 }
1590
1591 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1592 {
1593         int ret;
1594
1595         hdmi_disable_overflow_interrupts(hdmi);
1596
1597         hdmi->vic = drm_match_cea_mode(mode);
1598
1599         if (!hdmi->vic) {
1600                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1601         } else {
1602                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1603         }
1604
1605         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1606             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1607             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1608             (hdmi->vic == 17) || (hdmi->vic == 18))
1609                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1610         else
1611                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1612
1613         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1614                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1615                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1616         } else {
1617                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1618                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1619         }
1620         /* TODO: Get input format from IPU (via FB driver interface) */
1621         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1622                 hdmi->hdmi_data.enc_in_format = YCBCR420;
1623                 hdmi->hdmi_data.enc_out_format = YCBCR420;
1624         } else {
1625                 hdmi->hdmi_data.enc_in_format = RGB;
1626                 hdmi->hdmi_data.enc_out_format = RGB;
1627         }
1628         hdmi->hdmi_data.enc_color_depth = 8;
1629         /*
1630          * According to the dw-hdmi specification 6.4.2
1631          * vp_pr_cd[3:0]:
1632          * 0000b: No pixel repetition (pixel sent only once)
1633          * 0001b: Pixel sent two times (pixel repeated once)
1634          */
1635         hdmi->hdmi_data.pix_repet_factor =
1636                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1637         hdmi->hdmi_data.hdcp_enable = 0;
1638         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1639
1640         /* HDMI Initialization Step B.1 */
1641         hdmi_av_composer(hdmi, mode);
1642
1643         /* HDMI Initializateion Step B.2 */
1644         ret = dw_hdmi_phy_init(hdmi);
1645         if (ret)
1646                 return ret;
1647
1648         /* HDMI Initialization Step B.3 */
1649         dw_hdmi_enable_video_path(hdmi);
1650
1651         if (hdmi->sink_has_audio) {
1652                 dev_dbg(hdmi->dev, "sink has audio support\n");
1653
1654                 /* HDMI Initialization Step E - Configure audio */
1655                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1656                 hdmi_enable_audio_clk(hdmi);
1657         }
1658
1659         /* not for DVI mode */
1660         if (hdmi->sink_is_hdmi) {
1661                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1662
1663                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1664                 hdmi_config_AVI(hdmi, mode);
1665         } else {
1666                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1667         }
1668
1669         hdmi_video_packetize(hdmi);
1670         hdmi_video_csc(hdmi);
1671         hdmi_video_sample(hdmi);
1672         hdmi_tx_hdcp_config(hdmi);
1673
1674         dw_hdmi_clear_overflow(hdmi);
1675         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1676                 hdmi_enable_overflow_interrupts(hdmi);
1677
1678         return 0;
1679 }
1680
1681 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1682 {
1683         u8 ih_mute;
1684
1685         /*
1686          * Boot up defaults are:
1687          * HDMI_IH_MUTE   = 0x03 (disabled)
1688          * HDMI_IH_MUTE_* = 0x00 (enabled)
1689          *
1690          * Disable top level interrupt bits in HDMI block
1691          */
1692         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1693                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1694                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1695
1696         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1697
1698         /* by default mask all interrupts */
1699         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1700         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1701         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1702         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1703         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1704         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1705         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1706         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1707         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1708         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1709         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1710         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1711         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1712         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1713         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1714
1715         /* Disable interrupts in the IH_MUTE_* registers */
1716         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1717         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1718         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1719         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1720         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1721         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1722         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1723         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1724         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1725         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1726
1727         /* Enable top level interrupt bits in HDMI block */
1728         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1729                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1730         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1731 }
1732
1733 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1734 {
1735         hdmi->bridge_is_on = true;
1736         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1737 }
1738
1739 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1740 {
1741         dw_hdmi_phy_disable(hdmi);
1742         hdmi->bridge_is_on = false;
1743 }
1744
1745 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1746 {
1747         int force = hdmi->force;
1748
1749         if (hdmi->disabled) {
1750                 force = DRM_FORCE_OFF;
1751         } else if (force == DRM_FORCE_UNSPECIFIED) {
1752                 if (hdmi->rxsense)
1753                         force = DRM_FORCE_ON;
1754                 else
1755                         force = DRM_FORCE_OFF;
1756         }
1757
1758         if (force == DRM_FORCE_OFF) {
1759                 if (hdmi->bridge_is_on)
1760                         dw_hdmi_poweroff(hdmi);
1761         } else {
1762                 if (!hdmi->bridge_is_on)
1763                         dw_hdmi_poweron(hdmi);
1764         }
1765 }
1766
1767 /*
1768  * Adjust the detection of RXSENSE according to whether we have a forced
1769  * connection mode enabled, or whether we have been disabled.  There is
1770  * no point processing RXSENSE interrupts if we have a forced connection
1771  * state, or DRM has us disabled.
1772  *
1773  * We also disable rxsense interrupts when we think we're disconnected
1774  * to avoid floating TDMS signals giving false rxsense interrupts.
1775  *
1776  * Note: we still need to listen for HPD interrupts even when DRM has us
1777  * disabled so that we can detect a connect event.
1778  */
1779 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1780 {
1781         u8 old_mask = hdmi->phy_mask;
1782
1783         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1784                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1785         else
1786                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1787
1788         if (old_mask != hdmi->phy_mask)
1789                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1790 }
1791
1792 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1793                                     struct drm_display_mode *orig_mode,
1794                                     struct drm_display_mode *mode)
1795 {
1796         struct dw_hdmi *hdmi = bridge->driver_private;
1797
1798         mutex_lock(&hdmi->mutex);
1799
1800         /* Store the display mode for plugin/DKMS poweron events */
1801         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1802
1803         mutex_unlock(&hdmi->mutex);
1804 }
1805
1806 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1807 {
1808         struct dw_hdmi *hdmi = bridge->driver_private;
1809
1810         mutex_lock(&hdmi->mutex);
1811         hdmi->disabled = true;
1812         dw_hdmi_update_power(hdmi);
1813         dw_hdmi_update_phy_mask(hdmi);
1814         mutex_unlock(&hdmi->mutex);
1815 }
1816
1817 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1818 {
1819         struct dw_hdmi *hdmi = bridge->driver_private;
1820
1821         mutex_lock(&hdmi->mutex);
1822         hdmi->disabled = false;
1823         dw_hdmi_update_power(hdmi);
1824         dw_hdmi_update_phy_mask(hdmi);
1825         mutex_unlock(&hdmi->mutex);
1826 }
1827
1828 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1829 {
1830         /* do nothing */
1831 }
1832
1833 static enum drm_connector_status
1834 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1835 {
1836         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1837                                              connector);
1838
1839         mutex_lock(&hdmi->mutex);
1840         hdmi->force = DRM_FORCE_UNSPECIFIED;
1841         dw_hdmi_update_power(hdmi);
1842         dw_hdmi_update_phy_mask(hdmi);
1843         mutex_unlock(&hdmi->mutex);
1844
1845         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1846                 connector_status_connected : connector_status_disconnected;
1847 }
1848
1849 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1850 {
1851         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1852                                              connector);
1853         struct edid *edid;
1854         int ret = 0;
1855
1856         if (!hdmi->ddc)
1857                 return 0;
1858
1859         edid = drm_get_edid(connector, hdmi->ddc);
1860         if (edid) {
1861                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1862                         edid->width_cm, edid->height_cm);
1863
1864                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1865                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1866                 drm_mode_connector_update_edid_property(connector, edid);
1867                 ret = drm_add_edid_modes(connector, edid);
1868                 /* Store the ELD */
1869                 drm_edid_to_eld(connector, edid);
1870                 kfree(edid);
1871         } else {
1872                 dev_dbg(hdmi->dev, "failed to get edid\n");
1873         }
1874
1875         return ret;
1876 }
1877
1878 static enum drm_mode_status
1879 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1880                              struct drm_display_mode *mode)
1881 {
1882         struct dw_hdmi *hdmi = container_of(connector,
1883                                            struct dw_hdmi, connector);
1884         enum drm_mode_status mode_status = MODE_OK;
1885
1886         if (hdmi->plat_data->mode_valid)
1887                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1888
1889         return mode_status;
1890 }
1891
1892 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1893                                                            *connector)
1894 {
1895         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1896                                              connector);
1897
1898         return hdmi->encoder;
1899 }
1900
1901 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1902 {
1903         drm_connector_unregister(connector);
1904         drm_connector_cleanup(connector);
1905 }
1906
1907 static void dw_hdmi_connector_force(struct drm_connector *connector)
1908 {
1909         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1910                                              connector);
1911
1912         mutex_lock(&hdmi->mutex);
1913         hdmi->force = connector->force;
1914         dw_hdmi_update_power(hdmi);
1915         dw_hdmi_update_phy_mask(hdmi);
1916         mutex_unlock(&hdmi->mutex);
1917 }
1918
1919 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1920         .dpms = drm_helper_connector_dpms,
1921         .fill_modes = drm_helper_probe_single_connector_modes,
1922         .detect = dw_hdmi_connector_detect,
1923         .destroy = dw_hdmi_connector_destroy,
1924         .force = dw_hdmi_connector_force,
1925 };
1926
1927 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1928         .dpms = drm_atomic_helper_connector_dpms,
1929         .fill_modes = drm_helper_probe_single_connector_modes,
1930         .detect = dw_hdmi_connector_detect,
1931         .destroy = dw_hdmi_connector_destroy,
1932         .force = dw_hdmi_connector_force,
1933         .reset = drm_atomic_helper_connector_reset,
1934         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1935         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1936 };
1937
1938 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1939         .get_modes = dw_hdmi_connector_get_modes,
1940         .mode_valid = dw_hdmi_connector_mode_valid,
1941         .best_encoder = dw_hdmi_connector_best_encoder,
1942 };
1943
1944 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1945         .enable = dw_hdmi_bridge_enable,
1946         .disable = dw_hdmi_bridge_disable,
1947         .pre_enable = dw_hdmi_bridge_nop,
1948         .post_disable = dw_hdmi_bridge_nop,
1949         .mode_set = dw_hdmi_bridge_mode_set,
1950 };
1951
1952 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1953 {
1954         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1955         unsigned int stat;
1956
1957         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1958         if (!stat)
1959                 return IRQ_NONE;
1960
1961         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1962
1963         i2c->stat = stat;
1964
1965         complete(&i2c->cmp);
1966
1967         return IRQ_HANDLED;
1968 }
1969
1970 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1971 {
1972         struct dw_hdmi *hdmi = dev_id;
1973         u8 intr_stat;
1974         irqreturn_t ret = IRQ_NONE;
1975
1976         if (hdmi->i2c)
1977                 ret = dw_hdmi_i2c_irq(hdmi);
1978
1979         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1980         if (intr_stat) {
1981                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1982                 return IRQ_WAKE_THREAD;
1983         }
1984
1985         return ret;
1986 }
1987
1988 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1989 {
1990         struct dw_hdmi *hdmi = dev_id;
1991         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1992
1993         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1994         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1995         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1996
1997         phy_pol_mask = 0;
1998         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1999                 phy_pol_mask |= HDMI_PHY_HPD;
2000         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2001                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2002         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2003                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2004         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2005                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2006         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2007                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2008
2009         if (phy_pol_mask)
2010                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2011
2012         /*
2013          * RX sense tells us whether the TDMS transmitters are detecting
2014          * load - in other words, there's something listening on the
2015          * other end of the link.  Use this to decide whether we should
2016          * power on the phy as HPD may be toggled by the sink to merely
2017          * ask the source to re-read the EDID.
2018          */
2019         if (intr_stat &
2020             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2021                 mutex_lock(&hdmi->mutex);
2022                 if (!hdmi->bridge_is_on && !hdmi->force) {
2023                         /*
2024                          * If the RX sense status indicates we're disconnected,
2025                          * clear the software rxsense status.
2026                          */
2027                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2028                                 hdmi->rxsense = false;
2029
2030                         /*
2031                          * Only set the software rxsense status when both
2032                          * rxsense and hpd indicates we're connected.
2033                          * This avoids what seems to be bad behaviour in
2034                          * at least iMX6S versions of the phy.
2035                          */
2036                         if (phy_stat & HDMI_PHY_HPD)
2037                                 hdmi->rxsense = true;
2038
2039                         dw_hdmi_update_power(hdmi);
2040                         dw_hdmi_update_phy_mask(hdmi);
2041                 }
2042                 mutex_unlock(&hdmi->mutex);
2043         }
2044
2045         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2046                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2047                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2048                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2049 #ifdef CONFIG_SWITCH
2050                 if (phy_int_pol & HDMI_PHY_HPD)
2051                         switch_set_state(&hdmi->switchdev, 1);
2052                 else
2053                         switch_set_state(&hdmi->switchdev, 0);
2054 #endif
2055         }
2056
2057         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2058         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2059                     HDMI_IH_MUTE_PHY_STAT0);
2060
2061         return IRQ_HANDLED;
2062 }
2063
2064 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2065 {
2066         struct drm_encoder *encoder = hdmi->encoder;
2067         struct drm_bridge *bridge;
2068         int ret;
2069
2070         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2071         if (!bridge) {
2072                 DRM_ERROR("Failed to allocate drm bridge\n");
2073                 return -ENOMEM;
2074         }
2075
2076         hdmi->bridge = bridge;
2077         bridge->driver_private = hdmi;
2078         bridge->funcs = &dw_hdmi_bridge_funcs;
2079         ret = drm_bridge_attach(drm, bridge);
2080         if (ret) {
2081                 DRM_ERROR("Failed to initialize bridge with drm\n");
2082                 return -EINVAL;
2083         }
2084
2085         encoder->bridge = bridge;
2086         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2087         hdmi->connector.port = hdmi->dev->of_node;
2088
2089         drm_connector_helper_add(&hdmi->connector,
2090                                  &dw_hdmi_connector_helper_funcs);
2091
2092         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2093                 drm_connector_init(drm, &hdmi->connector,
2094                                    &dw_hdmi_atomic_connector_funcs,
2095                                    DRM_MODE_CONNECTOR_HDMIA);
2096         else
2097                 drm_connector_init(drm, &hdmi->connector,
2098                                    &dw_hdmi_connector_funcs,
2099                                    DRM_MODE_CONNECTOR_HDMIA);
2100
2101         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2102
2103         return 0;
2104 }
2105
2106 int dw_hdmi_bind(struct device *dev, struct device *master,
2107                  void *data, struct drm_encoder *encoder,
2108                  struct resource *iores, int irq,
2109                  const struct dw_hdmi_plat_data *plat_data)
2110 {
2111         struct drm_device *drm = data;
2112         struct device_node *np = dev->of_node;
2113         struct platform_device_info pdevinfo;
2114         struct device_node *ddc_node;
2115         struct dw_hdmi *hdmi;
2116         int ret;
2117         u32 val = 1;
2118         u8 config0;
2119         u8 config1;
2120
2121         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2122         if (!hdmi)
2123                 return -ENOMEM;
2124
2125         hdmi->connector.interlace_allowed = 1;
2126
2127         hdmi->plat_data = plat_data;
2128         hdmi->dev = dev;
2129         hdmi->dev_type = plat_data->dev_type;
2130         hdmi->sample_rate = 48000;
2131         hdmi->encoder = encoder;
2132         hdmi->disabled = true;
2133         hdmi->rxsense = true;
2134         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2135         hdmi->irq = irq;
2136
2137         mutex_init(&hdmi->mutex);
2138         mutex_init(&hdmi->audio_mutex);
2139         spin_lock_init(&hdmi->audio_lock);
2140
2141         of_property_read_u32(np, "reg-io-width", &val);
2142
2143         switch (val) {
2144         case 4:
2145                 hdmi->write = dw_hdmi_writel;
2146                 hdmi->read = dw_hdmi_readl;
2147                 break;
2148         case 1:
2149                 hdmi->write = dw_hdmi_writeb;
2150                 hdmi->read = dw_hdmi_readb;
2151                 break;
2152         default:
2153                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2154                 return -EINVAL;
2155         }
2156
2157         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2158         if (ddc_node) {
2159                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2160                 of_node_put(ddc_node);
2161                 if (!hdmi->ddc) {
2162                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2163                         return -EPROBE_DEFER;
2164                 }
2165
2166         } else {
2167                 dev_dbg(hdmi->dev, "no ddc property found\n");
2168         }
2169
2170         /* If DDC bus is not specified, try to register HDMI I2C bus */
2171         if (!hdmi->ddc) {
2172                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2173                 if (IS_ERR(hdmi->ddc))
2174                         hdmi->ddc = NULL;
2175         }
2176
2177         hdmi->regs = devm_ioremap_resource(dev, iores);
2178         if (IS_ERR(hdmi->regs))
2179                 return PTR_ERR(hdmi->regs);
2180
2181         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2182         if (IS_ERR(hdmi->isfr_clk)) {
2183                 ret = PTR_ERR(hdmi->isfr_clk);
2184                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2185                 return ret;
2186         }
2187
2188         ret = clk_prepare_enable(hdmi->isfr_clk);
2189         if (ret) {
2190                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2191                 return ret;
2192         }
2193
2194         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2195         if (IS_ERR(hdmi->iahb_clk)) {
2196                 ret = PTR_ERR(hdmi->iahb_clk);
2197                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2198                 goto err_isfr;
2199         }
2200
2201         ret = clk_prepare_enable(hdmi->iahb_clk);
2202         if (ret) {
2203                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2204                 goto err_isfr;
2205         }
2206
2207         /* Product and revision IDs */
2208         dev_info(dev,
2209                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2210                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2211                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2212                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2213                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2214
2215         initialize_hdmi_ih_mutes(hdmi);
2216
2217         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2218                                         dw_hdmi_irq, IRQF_SHARED,
2219                                         dev_name(dev), hdmi);
2220         if (ret)
2221                 goto err_iahb;
2222
2223         /*
2224          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2225          * N and cts values before enabling phy
2226          */
2227         hdmi_init_clk_regenerator(hdmi);
2228
2229         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2230                     HDMI_PHY_I2CM_INT_ADDR);
2231
2232         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2233                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2234                     HDMI_PHY_I2CM_CTLINT_ADDR);
2235
2236         /* Re-init HPD polarity */
2237         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2238
2239         /* Unmask HPD, clear transitory interrupts, then unmute */
2240         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2241
2242         ret = dw_hdmi_register(drm, hdmi);
2243         if (ret)
2244                 goto err_iahb;
2245
2246 #ifdef CONFIG_SWITCH
2247         hdmi->switchdev.name = "hdmi";
2248         switch_dev_register(&hdmi->switchdev);
2249 #endif
2250
2251         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2252                     HDMI_IH_MUTE_PHY_STAT0);
2253
2254         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2255         if (hdmi->i2c)
2256                 dw_hdmi_i2c_init(hdmi);
2257
2258         memset(&pdevinfo, 0, sizeof(pdevinfo));
2259         pdevinfo.parent = dev;
2260         pdevinfo.id = PLATFORM_DEVID_AUTO;
2261
2262         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2263         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2264
2265         if (config1 & HDMI_CONFIG1_AHB) {
2266                 struct dw_hdmi_audio_data audio;
2267
2268                 audio.phys = iores->start;
2269                 audio.base = hdmi->regs;
2270                 audio.irq = irq;
2271                 audio.hdmi = hdmi;
2272                 audio.eld = hdmi->connector.eld;
2273
2274                 pdevinfo.name = "dw-hdmi-ahb-audio";
2275                 pdevinfo.data = &audio;
2276                 pdevinfo.size_data = sizeof(audio);
2277                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2278                 hdmi->audio = platform_device_register_full(&pdevinfo);
2279         } else if (config0 & HDMI_CONFIG0_I2S) {
2280                 struct dw_hdmi_i2s_audio_data audio;
2281
2282                 audio.hdmi      = hdmi;
2283                 audio.write     = hdmi_writeb;
2284                 audio.read      = hdmi_readb;
2285
2286                 pdevinfo.name = "dw-hdmi-i2s-audio";
2287                 pdevinfo.data = &audio;
2288                 pdevinfo.size_data = sizeof(audio);
2289                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2290                 hdmi->audio = platform_device_register_full(&pdevinfo);
2291         }
2292
2293         dev_set_drvdata(dev, hdmi);
2294
2295         return 0;
2296
2297 err_iahb:
2298         if (hdmi->i2c)
2299                 i2c_del_adapter(&hdmi->i2c->adap);
2300
2301         clk_disable_unprepare(hdmi->iahb_clk);
2302 err_isfr:
2303         clk_disable_unprepare(hdmi->isfr_clk);
2304
2305         return ret;
2306 }
2307 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2308
2309 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2310 {
2311         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2312
2313         if (hdmi->audio && !IS_ERR(hdmi->audio))
2314                 platform_device_unregister(hdmi->audio);
2315
2316         /* Disable all interrupts */
2317         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2318
2319 #ifdef CONFIG_SWITCH
2320         switch_dev_unregister(&hdmi->switchdev);
2321 #endif
2322         hdmi->connector.funcs->destroy(&hdmi->connector);
2323         hdmi->encoder->funcs->destroy(hdmi->encoder);
2324
2325         clk_disable_unprepare(hdmi->iahb_clk);
2326         clk_disable_unprepare(hdmi->isfr_clk);
2327
2328         if (hdmi->i2c)
2329                 i2c_del_adapter(&hdmi->i2c->adap);
2330         else
2331                 i2c_put_adapter(hdmi->ddc);
2332 }
2333 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2334
2335 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2336 {
2337         if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2338                 initialize_hdmi_ih_mutes(hdmi);
2339                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2340                             HDMI_PHY_I2CM_INT_ADDR);
2341
2342                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2343                             HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2344                             HDMI_PHY_I2CM_CTLINT_ADDR);
2345
2346                 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2347                             HDMI_PHY_POL0);
2348                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2349                 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2350                             HDMI_IH_PHY_STAT0_RX_SENSE),
2351                             HDMI_IH_MUTE_PHY_STAT0);
2352         }
2353 }
2354
2355 void dw_hdmi_suspend(struct device *dev)
2356 {
2357         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2358
2359         mutex_lock(&hdmi->mutex);
2360         if (hdmi->irq)
2361                 disable_irq(hdmi->irq);
2362         mutex_unlock(&hdmi->mutex);
2363 }
2364 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2365
2366 void dw_hdmi_resume(struct device *dev)
2367 {
2368         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2369
2370         mutex_lock(&hdmi->mutex);
2371         dw_hdmi_reg_initial(hdmi);
2372         if (hdmi->irq)
2373                 enable_irq(hdmi->irq);
2374         mutex_unlock(&hdmi->mutex);
2375 }
2376 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2377
2378 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2379 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2380 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2381 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2382 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2383 MODULE_LICENSE("GPL");
2384 MODULE_ALIAS("platform:dw-hdmi");