drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c

   1 /*
   2  * dw-hdmi-i2s-audio.c
   3  *
   4  * Copyright (c) 2016 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <drm/bridge/dw_hdmi.h>
  11
  12 #include <sound/hdmi-codec.h>
  13
  14 #include "dw-hdmi.h"
  15 #include "dw-hdmi-audio.h"
  16
  17 #define DRIVER_NAME "dw-hdmi-i2s-audio"
  18
  19 static inline void hdmi_write(struct dw_hdmi_i2s_audio_data *audio, u8 val, int offset)
  20 {
  21         struct dw_hdmi *hdmi = audio->hdmi;
  22
  23         audio->write(hdmi, val, offset);
  24 }
  25
  26 static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
  27 {
  28         struct dw_hdmi *hdmi = audio->hdmi;
  29
  30         return audio->read(hdmi, offset);
  31 }
  32
  33 static inline void hdmi_update_bits(struct dw_hdmi_i2s_audio_data *audio,
  34                                     u8 data, u8 mask, unsigned int reg)
  35 {
  36         struct dw_hdmi *hdmi = audio->hdmi;
  37
  38         audio->mod(hdmi, data, mask, reg);
  39 }
  40
  41 static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
  42                                  struct hdmi_codec_daifmt *fmt,
  43                                  struct hdmi_codec_params *hparms)
  44 {
  45         struct dw_hdmi_i2s_audio_data *audio = data;
  46         struct dw_hdmi *hdmi = audio->hdmi;
  47         u8 conf0 = 0;
  48         u8 conf1 = 0;
  49         u8 inputclkfs = 0;
  50         u8 val;
  51
  52         /* it cares I2S only */
  53         if ((fmt->fmt != HDMI_I2S) ||
  54             (fmt->bit_clk_master | fmt->frame_clk_master)) {
  55                 dev_err(dev, "unsupported format/settings\n");
  56                 return -EINVAL;
  57         }
  58
  59         inputclkfs = HDMI_AUD_INPUTCLKFS_128FS;
  60
  61         switch (hparms->sample_width) {
  62         case 16:
  63                 conf1 = HDMI_AUD_CONF1_WIDTH_16;
  64                 break;
  65         case 24:
  66         case 32:
  67                 conf1 = HDMI_AUD_CONF1_WIDTH_24;
  68                 break;
  69         default:
  70                 dev_err(dev, "unsupported sample width [%d]\n", hparms->sample_width);
  71                 return -EINVAL;
  72         }
  73
  74         switch (hparms->channels) {
  75         case 2:
  76                 conf0 = HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE;
  77                 break;
  78         case 4:
  79                 conf0 = HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE;
  80                 break;
  81         case 6:
  82                 conf0 = HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE;
  83                 break;
  84         case 8:
  85                 conf0 = HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE;
  86                 break;
  87         default:
  88                 dev_err(dev, "unsupported channels [%d]\n", hparms->channels);
  89                 return -EINVAL;
  90         }
  91
  92         /*
  93          * dw-hdmi introduced insert_pcuv bit in version 2.10a.
  94          * When set (1'b1), this bit enables the insertion of the PCUV
  95          * (Parity, Channel Status, User bit and Validity) bits on the
  96          * incoming audio stream (support limited to Linear PCM audio)
  97          */
  98         val = 0;
  99         if (hdmi_read(audio, HDMI_DESIGN_ID) >= 0x21)
 100                 val = HDMI_AUD_CONF2_INSERT_PCUV;
 101
 102         /*Mask fifo empty and full int and reset fifo*/
 103         hdmi_update_bits(audio,
 104                          HDMI_AUD_INT_FIFO_EMPTY_MSK |
 105                          HDMI_AUD_INT_FIFO_FULL_MSK,
 106                          HDMI_AUD_INT_FIFO_EMPTY_MSK |
 107                          HDMI_AUD_INT_FIFO_FULL_MSK, HDMI_AUD_INT);
 108         hdmi_update_bits(audio, HDMI_AUD_CONF0_SW_RESET,
 109                          HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0);
 110         hdmi_update_bits(audio, HDMI_MC_SWRSTZ_I2S_RESET_MSK,
 111                          HDMI_MC_SWRSTZ_I2S_RESET_MSK, HDMI_MC_SWRSTZ);
 112
 113         switch (hparms->mode) {
 114         case NLPCM:
 115                 hdmi_write(audio, HDMI_AUD_CONF2_NLPCM, HDMI_AUD_CONF2);
 116                 conf1 = HDMI_AUD_CONF1_WIDTH_21;
 117                 break;
 118         case HBR:
 119                 hdmi_write(audio, HDMI_AUD_CONF2_HBR, HDMI_AUD_CONF2);
 120                 conf1 = HDMI_AUD_CONF1_WIDTH_21;
 121                 break;
 122         default:
 123                 hdmi_write(audio, val, HDMI_AUD_CONF2);
 124                 break;
 125         }
 126
 127         dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
 128
 129         hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
 130         hdmi_write(audio, conf0, HDMI_AUD_CONF0);
 131         hdmi_write(audio, conf1, HDMI_AUD_CONF1);
 132
 133         val = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
 134         if (hparms->channels > 2)
 135                 val = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
 136         hdmi_update_bits(audio, val, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
 137                          HDMI_FC_AUDSCONF);
 138
 139         switch (hparms->sample_rate) {
 140         case 32000:
 141                 val = HDMI_FC_AUDSCHNLS_32K;
 142                 break;
 143         case 44100:
 144                 val = HDMI_FC_AUDSCHNLS_441K;
 145                 break;
 146         case 48000:
 147                 val = HDMI_FC_AUDSCHNLS_48K;
 148                 break;
 149         case 88200:
 150                 val = HDMI_FC_AUDSCHNLS_882K;
 151                 break;
 152         case 96000:
 153                 val = HDMI_FC_AUDSCHNLS_96K;
 154                 break;
 155         case 176400:
 156                 val = HDMI_FC_AUDSCHNLS_1764K;
 157                 break;
 158         case 192000:
 159                 val = HDMI_FC_AUDSCHNLS_192K;
 160                 break;
 161         default:
 162                 val = HDMI_FC_AUDSCHNLS_441K;
 163                 break;
 164         }
 165
 166         /* set channel status register */
 167         hdmi_update_bits(audio, val,
 168                          HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK,
 169                          HDMI_FC_AUDSCHNLS7);
 170         hdmi_write(audio,
 171                    ((~val) << HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET),
 172                    HDMI_FC_AUDSCHNLS8);
 173
 174         /* Refer to CEA861-E Audio infoFrame
 175          * Set both Audio Channel Count and Audio Coding
 176          * Type Refer to Stream Head for HDMI
 177          */
 178         hdmi_update_bits(audio,
 179                          (hparms->channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
 180                          HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
 181
 182         /* Set both Audio Sample Size and Sample Frequency
 183          * Refer to Stream Head for HDMI
 184          */
 185         hdmi_write(audio, 0x00, HDMI_FC_AUDICONF1);
 186
 187         /* Set Channel Allocation */
 188         hdmi_write(audio, 0x00, HDMI_FC_AUDICONF2);
 189
 190         /* Set LFEPBLDOWN-MIX INH and LSV */
 191         hdmi_write(audio, 0x00, HDMI_FC_AUDICONF3);
 192
 193         hdmi_update_bits(audio, HDMI_AUD_CONF0_SW_RESET,
 194                          HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0);
 195         hdmi_update_bits(audio, HDMI_MC_SWRSTZ_I2S_RESET_MSK,
 196                          HDMI_MC_SWRSTZ_I2S_RESET_MSK, HDMI_MC_SWRSTZ);
 197
 198         dw_hdmi_audio_enable(hdmi);
 199
 200         return 0;
 201 }
 202
 203 static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data)
 204 {
 205         struct dw_hdmi_i2s_audio_data *audio = data;
 206         struct dw_hdmi *hdmi = audio->hdmi;
 207
 208         dw_hdmi_audio_disable(hdmi);
 209
 210         hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0);
 211 }
 212
 213 static struct hdmi_codec_ops dw_hdmi_i2s_ops = {
 214         .hw_params      = dw_hdmi_i2s_hw_params,
 215         .audio_shutdown = dw_hdmi_i2s_audio_shutdown,
 216 };
 217
 218 static int snd_dw_hdmi_probe(struct platform_device *pdev)
 219 {
 220         struct dw_hdmi_i2s_audio_data *audio = pdev->dev.platform_data;
 221         struct platform_device_info pdevinfo;
 222         struct hdmi_codec_pdata pdata;
 223
 224         pdata.ops               = &dw_hdmi_i2s_ops;
 225         pdata.i2s               = 1;
 226         pdata.max_i2s_channels  = 8;
 227         pdata.data              = audio;
 228
 229         memset(&pdevinfo, 0, sizeof(pdevinfo));
 230         pdevinfo.parent         = pdev->dev.parent;
 231         pdevinfo.id             = PLATFORM_DEVID_AUTO;
 232         pdevinfo.name           = HDMI_CODEC_DRV_NAME;
 233         pdevinfo.data           = &pdata;
 234         pdevinfo.size_data      = sizeof(pdata);
 235         pdevinfo.dma_mask       = DMA_BIT_MASK(32);
 236
 237         return IS_ERR_OR_NULL(platform_device_register_full(&pdevinfo));
 238 }
 239
 240 static struct platform_driver snd_dw_hdmi_driver = {
 241         .probe  = snd_dw_hdmi_probe,
 242         .driver = {
 243                 .name = DRIVER_NAME,
 244                 .owner = THIS_MODULE,
 245         },
 246 };
 247 module_platform_driver(snd_dw_hdmi_driver);
 248
 249 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
 250 MODULE_DESCRIPTION("Synopsis Designware HDMI I2S ALSA SoC interface");
 251 MODULE_LICENSE("GPL v2");
 252 MODULE_ALIAS("platform:" DRIVER_NAME);