98312f9b0d62ea6004b5918d012249c93bf342d8
[firefly-linux-kernel-4.4.55.git] / drivers / devfreq / rk3399_dmc.c
1 /*
2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3  * Author: Lin Huang <hl@rock-chips.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #include <linux/arm-smccc.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/devfreq.h>
19 #include <linux/devfreq-event.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_opp.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/rwsem.h>
27 #include <linux/slab.h>
28 #include <linux/suspend.h>
29
30 #include <soc/rockchip/rkfb_dmc.h>
31 #include <soc/rockchip/rockchip_sip.h>
32
33 struct dram_timing {
34         unsigned int ddr3_speed_bin;
35         unsigned int pd_idle;
36         unsigned int sr_idle;
37         unsigned int sr_mc_gate_idle;
38         unsigned int srpd_lite_idle;
39         unsigned int standby_idle;
40         unsigned int dram_dll_dis_freq;
41         unsigned int phy_dll_dis_freq;
42         unsigned int ddr3_odt_dis_freq;
43         unsigned int ddr3_drv;
44         unsigned int ddr3_odt;
45         unsigned int phy_ddr3_ca_drv;
46         unsigned int phy_ddr3_dq_drv;
47         unsigned int phy_ddr3_odt;
48         unsigned int lpddr3_odt_dis_freq;
49         unsigned int lpddr3_drv;
50         unsigned int lpddr3_odt;
51         unsigned int phy_lpddr3_ca_drv;
52         unsigned int phy_lpddr3_dq_drv;
53         unsigned int phy_lpddr3_odt;
54         unsigned int lpddr4_odt_dis_freq;
55         unsigned int lpddr4_drv;
56         unsigned int lpddr4_dq_odt;
57         unsigned int lpddr4_ca_odt;
58         unsigned int phy_lpddr4_ca_drv;
59         unsigned int phy_lpddr4_ck_cs_drv;
60         unsigned int phy_lpddr4_dq_drv;
61         unsigned int phy_lpddr4_odt;
62 };
63
64 struct rk3399_dmcfreq {
65         struct device *dev;
66         struct devfreq *devfreq;
67         struct devfreq_simple_ondemand_data ondemand_data;
68         struct clk *dmc_clk;
69         struct devfreq_event_dev *edev;
70         struct mutex lock;
71         struct dram_timing *timing;
72
73         /*
74          * DDR Converser of Frequency (DCF) is used to implement DDR frequency
75          * conversion without the participation of CPU, we will implement and
76          * control it in arm trust firmware.
77          */
78         wait_queue_head_t       wait_dcf_queue;
79         int irq;
80         int wait_dcf_flag;
81         struct regulator *vdd_center;
82         unsigned long rate, target_rate;
83         unsigned long volt, target_volt;
84 };
85
86 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
87                                  u32 flags)
88 {
89         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
90         struct dev_pm_opp *opp;
91         unsigned long old_clk_rate = dmcfreq->rate;
92         unsigned long temp_rate, target_volt, target_rate;
93         int err;
94
95         rcu_read_lock();
96         opp = devfreq_recommended_opp(dev, freq, flags);
97         if (IS_ERR(opp)) {
98                 rcu_read_unlock();
99                 return PTR_ERR(opp);
100         }
101
102         temp_rate = dev_pm_opp_get_freq(opp);
103         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
104         if ((long)target_rate <= 0)
105                 target_rate = temp_rate;
106         target_volt = dev_pm_opp_get_voltage(opp);
107
108         rcu_read_unlock();
109
110         if (dmcfreq->rate == target_rate) {
111                 if (dmcfreq->volt == target_volt)
112                         return 0;
113                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
114                                             INT_MAX);
115                 if (err) {
116                         dev_err(dev, "Cannot to set voltage %lu uV\n",
117                                 target_volt);
118                         goto out;
119                 }
120         }
121
122
123         mutex_lock(&dmcfreq->lock);
124
125         /*
126          * If frequency scaling from low to high, adjust voltage first.
127          * If frequency scaling from high to low, adjust frequency first.
128          */
129         if (old_clk_rate < target_rate) {
130                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
131                                             INT_MAX);
132                 if (err) {
133                         dev_err(dev, "Cannot to set voltage %lu uV\n",
134                                 target_volt);
135                         goto out;
136                 }
137         }
138
139         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
140         if (err) {
141                 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
142                         target_rate, err);
143                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
144                                       INT_MAX);
145                 goto out;
146         }
147
148         /*
149          * Check the dpll rate,
150          * There only two result we will get,
151          * 1. Ddr frequency scaling fail, we still get the old rate.
152          * 2. Ddr frequency scaling sucessful, we get the rate we set.
153          */
154         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
155
156         /* If get the incorrect rate, set voltage to old value. */
157         if (dmcfreq->rate != target_rate) {
158                 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
159                         Current frequency %lu\n", target_rate, dmcfreq->rate);
160                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
161                                       INT_MAX);
162                 goto out;
163         } else if (old_clk_rate > target_rate) {
164                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
165                                             INT_MAX);
166                 if (err) {
167                         dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
168                         goto out;
169                 }
170         }
171
172         dmcfreq->volt = target_volt;
173 out:
174         mutex_unlock(&dmcfreq->lock);
175         return err;
176 }
177
178 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
179                                          struct devfreq_dev_status *stat)
180 {
181         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
182         struct devfreq_event_data edata;
183         int ret = 0;
184
185         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
186         if (ret < 0)
187                 return ret;
188
189         stat->current_frequency = dmcfreq->rate;
190         stat->busy_time = edata.load_count;
191         stat->total_time = edata.total_count;
192
193         return ret;
194 }
195
196 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
197 {
198         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
199
200         *freq = dmcfreq->rate;
201
202         return 0;
203 }
204
205 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
206         .polling_ms     = 200,
207         .target         = rk3399_dmcfreq_target,
208         .get_dev_status = rk3399_dmcfreq_get_dev_status,
209         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
210 };
211
212 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
213 {
214         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
215         int ret = 0;
216
217         ret = devfreq_event_disable_edev(dmcfreq->edev);
218         if (ret < 0) {
219                 dev_err(dev, "failed to disable the devfreq-event devices\n");
220                 return ret;
221         }
222
223         ret = devfreq_suspend_device(dmcfreq->devfreq);
224         if (ret < 0) {
225                 dev_err(dev, "failed to suspend the devfreq devices\n");
226                 return ret;
227         }
228
229         return 0;
230 }
231
232 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
233 {
234         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
235         int ret = 0;
236
237         ret = devfreq_event_enable_edev(dmcfreq->edev);
238         if (ret < 0) {
239                 dev_err(dev, "failed to enable the devfreq-event devices\n");
240                 return ret;
241         }
242
243         ret = devfreq_resume_device(dmcfreq->devfreq);
244         if (ret < 0) {
245                 dev_err(dev, "failed to resume the devfreq devices\n");
246                 return ret;
247         }
248         return ret;
249 }
250
251 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
252                          rk3399_dmcfreq_resume);
253
254 static struct dram_timing *of_get_ddr_timings(struct device *dev,
255                                               struct device_node *np)
256 {
257         struct dram_timing      *timing = NULL;
258         struct device_node      *np_tim;
259         int ret;
260
261         np_tim = of_parse_phandle(np, "ddr_timing", 0);
262         if (np_tim) {
263                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
264                 if (!timing)
265                         goto err;
266
267                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
268                                            &timing->ddr3_speed_bin);
269                 ret |= of_property_read_u32(np_tim, "pd_idle",
270                                             &timing->pd_idle);
271                 ret |= of_property_read_u32(np_tim, "sr_idle",
272                                             &timing->sr_idle);
273                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
274                                             &timing->sr_mc_gate_idle);
275                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
276                                             &timing->srpd_lite_idle);
277                 ret |= of_property_read_u32(np_tim, "standby_idle",
278                                             &timing->standby_idle);
279                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
280                                             &timing->dram_dll_dis_freq);
281                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
282                                             &timing->phy_dll_dis_freq);
283                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
284                                             &timing->ddr3_odt_dis_freq);
285                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
286                                             &timing->ddr3_drv);
287                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
288                                             &timing->ddr3_odt);
289                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
290                                             &timing->phy_ddr3_ca_drv);
291                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
292                                             &timing->phy_ddr3_dq_drv);
293                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
294                                             &timing->phy_ddr3_odt);
295                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
296                                             &timing->lpddr3_odt_dis_freq);
297                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
298                                             &timing->lpddr3_drv);
299                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
300                                             &timing->lpddr3_odt);
301                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
302                                             &timing->phy_lpddr3_ca_drv);
303                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
304                                             &timing->phy_lpddr3_dq_drv);
305                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
306                                             &timing->phy_lpddr3_odt);
307                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
308                                             &timing->lpddr4_odt_dis_freq);
309                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
310                                             &timing->lpddr4_drv);
311                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
312                                             &timing->lpddr4_dq_odt);
313                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
314                                             &timing->lpddr4_ca_odt);
315                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
316                                             &timing->phy_lpddr4_ca_drv);
317                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
318                                             &timing->phy_lpddr4_ck_cs_drv);
319                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
320                                             &timing->phy_lpddr4_dq_drv);
321                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
322                                             &timing->phy_lpddr4_odt);
323                 if (ret) {
324                         devm_kfree(dev, timing);
325                         goto err;
326                 }
327                 of_node_put(np_tim);
328                 return timing;
329         }
330
331 err:
332         if (timing) {
333                 devm_kfree(dev, timing);
334                 timing = NULL;
335         }
336         of_node_put(np_tim);
337         return timing;
338 }
339
340 static int rk3399_dmcfreq_init_freq_table(struct device *dev,
341                                           struct devfreq_dev_profile *devp)
342 {
343         int count;
344         int i = 0;
345         unsigned long freq = 0;
346         struct dev_pm_opp *opp;
347
348         rcu_read_lock();
349         count = dev_pm_opp_get_opp_count(dev);
350         if (count < 0) {
351                 rcu_read_unlock();
352                 return count;
353         }
354         rcu_read_unlock();
355
356         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
357                                 GFP_KERNEL);
358         if (!devp->freq_table)
359                 return -ENOMEM;
360
361         rcu_read_lock();
362         for (i = 0; i < count; i++, freq++) {
363                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
364                 if (IS_ERR(opp))
365                         break;
366
367                 devp->freq_table[i] = freq;
368         }
369         rcu_read_unlock();
370
371         if (count != i)
372                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
373                          count, i);
374
375         devp->max_state = i;
376         return 0;
377 }
378
379 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
380 {
381         struct arm_smccc_res res;
382         struct device *dev = &pdev->dev;
383         struct device_node *np = pdev->dev.of_node;
384         struct rk3399_dmcfreq *data;
385         int ret, index, size;
386         uint32_t *timing;
387         struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
388
389         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
390         if (!data)
391                 return -ENOMEM;
392
393         mutex_init(&data->lock);
394
395         data->vdd_center = devm_regulator_get(dev, "center");
396         if (IS_ERR(data->vdd_center)) {
397                 dev_err(dev, "Cannot get the regulator \"center\"\n");
398                 return PTR_ERR(data->vdd_center);
399         }
400
401         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
402         if (IS_ERR(data->dmc_clk)) {
403                 dev_err(dev, "Cannot get the clk dmc_clk\n");
404                 return PTR_ERR(data->dmc_clk);
405         };
406
407         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
408         if (IS_ERR(data->edev))
409                 return -EPROBE_DEFER;
410
411         ret = devfreq_event_enable_edev(data->edev);
412         if (ret < 0) {
413                 dev_err(dev, "failed to enable devfreq-event devices\n");
414                 return ret;
415         }
416
417         /*
418          * Get dram timing and pass it to arm trust firmware,
419          * the dram drvier in arm trust firmware will get these
420          * timing and to do dram initial.
421          */
422         data->timing = of_get_ddr_timings(dev, np);
423         if (data->timing) {
424                 timing = (uint32_t *)data->timing;
425                 size = sizeof(struct dram_timing) / 4;
426                 for (index = 0; index < size; index++) {
427                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
428                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
429                                       0, 0, 0, 0, &res);
430                         if (res.a0) {
431                                 dev_err(dev, "Failed to set dram param: %ld\n",
432                                         res.a0);
433                                 return -EINVAL;
434                         }
435                 }
436         }
437
438         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
439                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
440                       0, 0, 0, 0, &res);
441
442         /*
443          * We add a devfreq driver to our parent since it has a device tree node
444          * with operating points.
445          */
446         if (dev_pm_opp_of_add_table(dev)) {
447                 dev_err(dev, "Invalid operating-points in device tree.\n");
448                 return -EINVAL;
449         }
450
451         if (rk3399_dmcfreq_init_freq_table(dev, devp))
452                 return -EFAULT;
453
454         of_property_read_u32(np, "upthreshold",
455                              &data->ondemand_data.upthreshold);
456         of_property_read_u32(np, "downdifferential",
457                              &data->ondemand_data.downdifferential);
458
459         data->rate = clk_get_rate(data->dmc_clk);
460         data->volt = regulator_get_voltage(data->vdd_center);
461
462         devp->initial_freq = data->rate;
463         data->devfreq = devm_devfreq_add_device(dev, devp,
464                                            "simple_ondemand",
465                                            &data->ondemand_data);
466         if (IS_ERR(data->devfreq))
467                 return PTR_ERR(data->devfreq);
468         devm_devfreq_register_opp_notifier(dev, data->devfreq);
469
470         data->dev = dev;
471         platform_set_drvdata(pdev, data);
472
473         if (vop_register_dmc())
474                 dev_err(dev, "fail to register notify to vop.\n");
475
476         return 0;
477 }
478
479 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
480         { .compatible = "rockchip,rk3399-dmc" },
481         { },
482 };
483 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
484
485 static struct platform_driver rk3399_dmcfreq_driver = {
486         .probe  = rk3399_dmcfreq_probe,
487         .driver = {
488                 .name   = "rk3399-dmc-freq",
489                 .pm     = &rk3399_dmcfreq_pm,
490                 .of_match_table = rk3399dmc_devfreq_of_match,
491         },
492 };
493 module_platform_driver(rk3399_dmcfreq_driver);
494
495 MODULE_LICENSE("GPL v2");
496 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
497 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");