drivers/devfreq/ddr_rk3368.c

   1 /*
   2  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, you can access it online at
  15  * http://www.gnu.org/licenses/gpl-2.0.html.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <linux/kernel.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/cacheflush.h>
  33 #include <asm/tlbflush.h>
  34 #include <linux/cpu.h>
  35 #include <dt-bindings/clock/ddr.h>
  36 #include <linux/rockchip/common.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #include <linux/rockchip/dvfs.h>
  40 #include <linux/rockchip/grf.h>
  41 #include <linux/rockchip/iomap.h>
  42 #include <linux/rockchip/pmu.h>
  43 #include <linux/rk_fb.h>
  44 #include <linux/scpi_protocol.h>
  45
  46 #define GRF_DDRC0_CON0    0x600
  47 #define GRF_SOC_STATUS5  0x494
  48 #define DDR_PCTL_TOGCNT_1U  0xc0
  49
  50 enum ddr_bandwidth_id {
  51         ddrbw_wr_num = 0,
  52         ddrbw_rd_num,
  53         ddrbw_act_num,
  54         ddrbw_time_num,
  55         ddrbw_eff,
  56         ddrbw_id_end
  57 };
  58
  59 struct rockchip_ddr {
  60         struct regmap *ddrpctl_regs;
  61         struct regmap *msch_regs;
  62         struct regmap *grf_regs;
  63 };
  64
  65 static struct rockchip_ddr *ddr_data = NULL;
  66
  67 static int _ddr_change_freq(u32 n_mhz)
  68 {
  69         u32 ret;
  70
  71         printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
  72         if (scpi_ddr_set_clk_rate(n_mhz))
  73                 pr_info("set ddr freq timeout\n");
  74         ret = scpi_ddr_get_clk_rate();
  75         printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
  76         return ret;
  77 }
  78
  79 static long _ddr_round_rate(u32 n_mhz)
  80 {
  81         return (n_mhz / 12) * 12;
  82 }
  83
  84 static int _ddr_recalc_rate(void)
  85 {
  86         return (1000000 * scpi_ddr_get_clk_rate());
  87 }
  88
  89 static void _ddr_set_auto_self_refresh(bool en)
  90 {
  91         if (scpi_ddr_set_auto_self_refresh(en))
  92                 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
  93 }
  94
  95 static void ddr_monitor_start(void)
  96 {
  97         u32 i;
  98
  99         /* cpum, gpu probe */
 100         for (i = 1; i < 3; i++) {
 101                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
 102                              0x8);
 103                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
 104                              0x1);
 105                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
 106                              0x6);
 107                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
 108                              0x10);
 109                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
 110                              0x8);
 111                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
 112                              0x10);
 113         }
 114         /* video, vio0, vio1 probe */
 115         for (i = 0; i < 3; i++) {
 116                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
 117                              0x8);
 118                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
 119                              0x1);
 120                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
 121                              0x6);
 122                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
 123                              0x10);
 124                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
 125                              0x8);
 126                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
 127                              0x10);
 128         }
 129         /* dfi eff start */
 130         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 131                      ((0x3 << 5) << 16) | 0x3 << 5);
 132         /*flash data */
 133         wmb();
 134         /* trigger statistic */
 135         for (i = 1; i < 3; i++)
 136                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
 137                              0x1);
 138         for (i = 0; i < 3; i++)
 139                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
 140                              0x1);
 141 }
 142
 143 static void ddr_monitor_stop(void)
 144 {
 145         /* dfi eff stop */
 146         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 147                      ((0x3 << 5) << 16) | 0x0 << 5);
 148 }
 149
 150 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
 151                                struct ddr_bw_info *ddr_bw_ch1)
 152 {
 153         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
 154         u64 temp64;
 155         int i, j;
 156         u32 tmp32;
 157
 158         if (!ddr_data)
 159                 return;
 160
 161         ddr_monitor_stop();
 162         /* read dfi eff */
 163         for (j = 0; j < 2; j++) {
 164                 for (i = 0; i < ddrbw_eff; i++) {
 165                         regmap_read(ddr_data->grf_regs,
 166                                     GRF_SOC_STATUS5 + 4 * i + j * 16,
 167                                     &ddr_bw_val[j][i]);
 168                 }
 169         }
 170         if (!ddr_bw_val[0][ddrbw_time_num])
 171                 goto end;
 172         if (ddr_bw_ch0) {
 173                 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
 174                             &ddr_freq);
 175                 ddr_freq *= 2;
 176                 dfi_freq = ddr_freq / 2;
 177                 /* dfi eff */
 178                 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
 179                           + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
 180                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
 181                 ddr_bw_val[0][ddrbw_eff] = temp64;
 182                 ddr_bw_ch0->ddr_percent = temp64;
 183                 ddr_bw_ch0->ddr_time =
 184                     ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
 185                 /*unit:MB/s */
 186                 ddr_bw_ch0->ddr_wr = (((u64)
 187                                        (ddr_bw_val[0][ddrbw_wr_num] +
 188                                         ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
 189                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 190                 ddr_bw_ch0->ddr_rd = (((u64)
 191                                        (ddr_bw_val[0][ddrbw_rd_num] +
 192                                         ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
 193                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 194                 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
 195                 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
 196                 /* noc unit:bype */
 197                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
 198                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
 199                             &ddr_bw_ch0->cpum);
 200                 ddr_bw_ch0->cpum += (tmp32 << 16);
 201                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
 202                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
 203                             &ddr_bw_ch0->gpu);
 204                 ddr_bw_ch0->gpu += (tmp32 << 16);
 205                 ddr_bw_ch0->peri = 0;
 206                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
 207                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
 208                             &ddr_bw_ch0->video);
 209                 ddr_bw_ch0->video += (tmp32 << 16);
 210                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
 211                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
 212                             &ddr_bw_ch0->vio0);
 213                 ddr_bw_ch0->vio0 += (tmp32 << 16);
 214                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
 215                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
 216                             &ddr_bw_ch0->vio1);
 217                 ddr_bw_ch0->vio1 += (tmp32 << 16);
 218                 ddr_bw_ch0->vio2 = 0;
 219
 220                 /* B/s => MB/s */
 221                 ddr_bw_ch0->cpum =
 222                     (u64) ddr_bw_ch0->cpum * dfi_freq /
 223                     ddr_bw_val[0][ddrbw_time_num];
 224                 ddr_bw_ch0->gpu =
 225                     (u64) ddr_bw_ch0->gpu * dfi_freq /
 226                     ddr_bw_val[0][ddrbw_time_num];
 227                 ddr_bw_ch0->peri =
 228                     (u64) ddr_bw_ch0->peri * dfi_freq /
 229                     ddr_bw_val[0][ddrbw_time_num];
 230                 ddr_bw_ch0->video =
 231                     (u64) ddr_bw_ch0->video * dfi_freq /
 232                     ddr_bw_val[0][ddrbw_time_num];
 233                 ddr_bw_ch0->vio0 =
 234                     (u64) ddr_bw_ch0->vio0 * dfi_freq /
 235                     ddr_bw_val[0][ddrbw_time_num];
 236                 ddr_bw_ch0->vio1 =
 237                     (u64) ddr_bw_ch0->vio1 * dfi_freq /
 238                     ddr_bw_val[0][ddrbw_time_num];
 239                 ddr_bw_ch0->vio2 =
 240                     (u64) ddr_bw_ch0->vio2 * dfi_freq /
 241                     ddr_bw_val[0][ddrbw_time_num];
 242         }
 243 end:
 244         ddr_monitor_start();
 245 }
 246
 247 static void ddr_init(u32 dram_speed_bin, u32 freq)
 248 {
 249         int lcdc_type;
 250
 251         lcdc_type = rockchip_get_screen_type();
 252         printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
 253                __func__, dram_speed_bin, freq, lcdc_type);
 254         if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type))
 255                 pr_info("ddr init error\n");
 256         else
 257                 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
 258 }
 259
 260 static int ddr_init_resume(struct platform_device *pdev)
 261 {
 262         ddr_init(DDR3_DEFAULT, 0);
 263         return 0;
 264 }
 265
 266 static int __init rockchip_ddr_probe(struct platform_device *pdev)
 267 {
 268         struct device_node *np;
 269
 270         np = pdev->dev.of_node;
 271         ddr_data =
 272             devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
 273         if (!ddr_data) {
 274                 dev_err(&pdev->dev, "no memory for state\n");
 275                 return -ENOMEM;
 276         }
 277         /* ddrpctl */
 278         ddr_data->ddrpctl_regs =
 279             syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
 280         if (IS_ERR(ddr_data->ddrpctl_regs)) {
 281                 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
 282                         __func__);
 283                 return -ENXIO;
 284         }
 285
 286         /* grf */
 287         ddr_data->grf_regs =
 288             syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 289         if (IS_ERR(ddr_data->grf_regs)) {
 290                 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
 291                         __func__);
 292                 return -ENXIO;
 293         }
 294         /* msch */
 295         ddr_data->msch_regs =
 296             syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
 297         if (IS_ERR(ddr_data->msch_regs)) {
 298                 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
 299                         __func__);
 300                 return -ENXIO;
 301         }
 302
 303         platform_set_drvdata(pdev, ddr_data);
 304         ddr_change_freq = _ddr_change_freq;
 305         ddr_round_rate = _ddr_round_rate;
 306         ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 307         ddr_bandwidth_get = _ddr_bandwidth_get;
 308         ddr_recalc_rate = _ddr_recalc_rate;
 309         ddr_init(DDR3_DEFAULT, 0);
 310         pr_info("%s: success\n", __func__);
 311         return 0;
 312 }
 313
 314 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
 315         {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
 316         {},
 317 };
 318
 319 static struct platform_driver rockchip_ddr_driver = {
 320 #ifdef CONFIG_PM
 321         .resume = ddr_init_resume,
 322 #endif /* CONFIG_PM */
 323         .driver = {
 324                    .name = "rockchip_ddr",
 325                    .of_match_table = rockchip_ddr_of_match,
 326         },
 327 };
 328
 329 static int __init rockchip_ddr_init(void)
 330 {
 331         pr_info("rockchip_ddr_init\n");
 332         return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
 333 }
 334
 335 device_initcall(rockchip_ddr_init);