drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30 #include <linux/clk-provider.h>
  31
  32 struct clk;
  33
  34 #define HIWORD_UPDATE(val, mask, shift) \
  35                 ((val) << (shift) | (mask) << ((shift) + 16))
  36
  37 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
  38 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  39 #define RK2928_MODE_CON         0x40
  40 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  41 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  42 #define RK2928_GLB_SRST_FST             0x100
  43 #define RK2928_GLB_SRST_SND             0x104
  44 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  45 #define RK2928_MISC_CON         0x134
  46
  47 #define RK3036_SDMMC_CON0               0x144
  48 #define RK3036_SDMMC_CON1               0x148
  49 #define RK3036_SDIO_CON0                0x14c
  50 #define RK3036_SDIO_CON1                0x150
  51 #define RK3036_EMMC_CON0                0x154
  52 #define RK3036_EMMC_CON1                0x158
  53
  54 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  55 #define RK3288_MODE_CON                 0x50
  56 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  57 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  58 #define RK3288_GLB_SRST_FST             0x1b0
  59 #define RK3288_GLB_SRST_SND             0x1b4
  60 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  61 #define RK3288_MISC_CON                 0x1e8
  62 #define RK3288_SDMMC_CON0               0x200
  63 #define RK3288_SDMMC_CON1               0x204
  64 #define RK3288_SDIO0_CON0               0x208
  65 #define RK3288_SDIO0_CON1               0x20c
  66 #define RK3288_SDIO1_CON0               0x210
  67 #define RK3288_SDIO1_CON1               0x214
  68 #define RK3288_EMMC_CON0                0x218
  69 #define RK3288_EMMC_CON1                0x21c
  70
  71 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  72 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  73 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  74 #define RK3368_GLB_SRST_FST             0x280
  75 #define RK3368_GLB_SRST_SND             0x284
  76 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  77 #define RK3368_MISC_CON                 0x380
  78 #define RK3368_SDMMC_CON0               0x400
  79 #define RK3368_SDMMC_CON1               0x404
  80 #define RK3368_SDIO0_CON0               0x408
  81 #define RK3368_SDIO0_CON1               0x40c
  82 #define RK3368_SDIO1_CON0               0x410
  83 #define RK3368_SDIO1_CON1               0x414
  84 #define RK3368_EMMC_CON0                0x418
  85 #define RK3368_EMMC_CON1                0x41c
  86
  87 enum rockchip_pll_type {
  88         pll_rk3036,
  89         pll_rk3066,
  90         pll_rk3366,
  91         pll_rk3399,
  92 };
  93
  94 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  95                         _postdiv2, _dsmpd, _frac)               \
  96 {                                                               \
  97         .rate   = _rate##U,                                     \
  98         .fbdiv = _fbdiv,                                        \
  99         .postdiv1 = _postdiv1,                                  \
 100         .refdiv = _refdiv,                                      \
 101         .postdiv2 = _postdiv2,                                  \
 102         .dsmpd = _dsmpd,                                        \
 103         .frac = _frac,                                          \
 104 }
 105
 106 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
 107 {                                               \
 108         .rate   = _rate##U,                     \
 109         .nr = _nr,                              \
 110         .nf = _nf,                              \
 111         .no = _no,                              \
 112         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 113 }
 114
 115 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 116 {                                                               \
 117         .rate   = _rate##U,                                     \
 118         .nr = _nr,                                              \
 119         .nf = _nf,                                              \
 120         .no = _no,                                              \
 121         .nb = _nb,                                              \
 122 }
 123
 124 #define RK3399_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
 125                         _postdiv2, _dsmpd, _frac)               \
 126 {                                                               \
 127         .rate   = _rate##U,                                     \
 128         .fbdiv = _fbdiv,                                        \
 129         .postdiv1 = _postdiv1,                                  \
 130         .refdiv = _refdiv,                                      \
 131         .postdiv2 = _postdiv2,                                  \
 132         .dsmpd = _dsmpd,                                        \
 133         .frac = _frac,                                          \
 134 }
 135
 136 /**
 137  * struct rockchip_clk_provider - information about clock provider
 138  * @reg_base: virtual address for the register base.
 139  * @clk_data: holds clock related data like clk* and number of clocks.
 140  * @cru_node: device-node of the clock-provider
 141  * @grf: regmap of the general-register-files syscon
 142  * @lock: maintains exclusion between callbacks for a given clock-provider.
 143  */
 144 struct rockchip_clk_provider {
 145         void __iomem *reg_base;
 146         struct clk_onecell_data clk_data;
 147         struct device_node *cru_node;
 148         struct regmap *grf;
 149         spinlock_t lock;
 150 };
 151
 152 struct rockchip_pll_rate_table {
 153         unsigned long rate;
 154         unsigned int nr;
 155         unsigned int nf;
 156         unsigned int no;
 157         unsigned int nb;
 158         /* for RK3036/RK3399 */
 159         unsigned int fbdiv;
 160         unsigned int postdiv1;
 161         unsigned int refdiv;
 162         unsigned int postdiv2;
 163         unsigned int dsmpd;
 164         unsigned int frac;
 165 };
 166
 167 /**
 168  * struct rockchip_pll_clock - information about pll clock
 169  * @id: platform specific id of the clock.
 170  * @name: name of this pll clock.
 171  * @parent_names: name of the parent clock.
 172  * @num_parents: number of parents
 173  * @flags: optional flags for basic clock.
 174  * @con_offset: offset of the register for configuring the PLL.
 175  * @mode_offset: offset of the register for configuring the PLL-mode.
 176  * @mode_shift: offset inside the mode-register for the mode of this pll.
 177  * @lock_shift: offset inside the lock register for the lock status.
 178  * @type: Type of PLL to be registered.
 179  * @pll_flags: hardware-specific flags
 180  * @rate_table: Table of usable pll rates
 181  *
 182  * Flags:
 183  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 184  *      rate_table parameters and ajust them if necessary.
 185  */
 186 struct rockchip_pll_clock {
 187         unsigned int            id;
 188         const char              *name;
 189         const char              *const *parent_names;
 190         u8                      num_parents;
 191         unsigned long           flags;
 192         int                     con_offset;
 193         int                     mode_offset;
 194         int                     mode_shift;
 195         int                     lock_shift;
 196         enum rockchip_pll_type  type;
 197         u8                      pll_flags;
 198         struct rockchip_pll_rate_table *rate_table;
 199 };
 200
 201 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 202
 203 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 204                 _lshift, _pflags, _rtable)                              \
 205         {                                                               \
 206                 .id             = _id,                                  \
 207                 .type           = _type,                                \
 208                 .name           = _name,                                \
 209                 .parent_names   = _pnames,                              \
 210                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 211                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 212                 .con_offset     = _con,                                 \
 213                 .mode_offset    = _mode,                                \
 214                 .mode_shift     = _mshift,                              \
 215                 .lock_shift     = _lshift,                              \
 216                 .pll_flags      = _pflags,                              \
 217                 .rate_table     = _rtable,                              \
 218         }
 219
 220 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 221                 enum rockchip_pll_type pll_type,
 222                 const char *name, const char *const *parent_names,
 223                 u8 num_parents, int con_offset, int grf_lock_offset,
 224                 int lock_shift, int mode_offset, int mode_shift,
 225                 struct rockchip_pll_rate_table *rate_table,
 226                 u8 clk_pll_flags);
 227
 228 struct rockchip_cpuclk_clksel {
 229         int reg;
 230         u32 val;
 231 };
 232
 233 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 234 struct rockchip_cpuclk_rate_table {
 235         unsigned long prate;
 236         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 237 };
 238
 239 /**
 240  * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
 241  * @core_reg:           register offset of the core settings register
 242  * @div_core_shift:     core divider offset used to divide the pll value
 243  * @div_core_mask:      core divider mask
 244  * @mux_core_alt:       mux value to select alternate parent
 245  * @mux_core_main:      mux value to select main parent of core
 246  * @mux_core_shift:     offset of the core multiplexer
 247  * @mux_core_mask:      core multiplexer mask
 248  */
 249 struct rockchip_cpuclk_reg_data {
 250         int             core_reg;
 251         u8              div_core_shift;
 252         u32             div_core_mask;
 253         u8              mux_core_alt;
 254         u8              mux_core_main;
 255         u8              mux_core_shift;
 256         u32             mux_core_mask;
 257 };
 258
 259 struct clk *rockchip_clk_register_cpuclk(const char *name,
 260                         const char *const *parent_names, u8 num_parents,
 261                         const struct rockchip_cpuclk_reg_data *reg_data,
 262                         const struct rockchip_cpuclk_rate_table *rates,
 263                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 264
 265 struct clk *rockchip_clk_register_mmc(const char *name,
 266                                 const char *const *parent_names, u8 num_parents,
 267                                 void __iomem *reg, int shift);
 268
 269 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 270
 271 struct clk *rockchip_clk_register_inverter(const char *name,
 272                                 const char *const *parent_names, u8 num_parents,
 273                                 void __iomem *reg, int shift, int flags,
 274                                 spinlock_t *lock);
 275
 276 #define PNAME(x) static const char *const x[] __initconst
 277
 278 enum rockchip_clk_branch_type {
 279         branch_composite,
 280         branch_mux,
 281         branch_divider,
 282         branch_fraction_divider,
 283         branch_gate,
 284         branch_mmc,
 285         branch_inverter,
 286         branch_factor,
 287 };
 288
 289 struct rockchip_clk_branch {
 290         unsigned int                    id;
 291         enum rockchip_clk_branch_type   branch_type;
 292         const char                      *name;
 293         const char                      *const *parent_names;
 294         u8                              num_parents;
 295         unsigned long                   flags;
 296         int                             muxdiv_offset;
 297         u8                              mux_shift;
 298         u8                              mux_width;
 299         u8                              mux_flags;
 300         u8                              div_shift;
 301         u8                              div_width;
 302         u8                              div_flags;
 303         struct clk_div_table            *div_table;
 304         int                             gate_offset;
 305         u8                              gate_shift;
 306         u8                              gate_flags;
 307         struct rockchip_clk_branch      *child;
 308 };
 309
 310 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 311                   df, go, gs, gf)                               \
 312         {                                                       \
 313                 .id             = _id,                          \
 314                 .branch_type    = branch_composite,             \
 315                 .name           = cname,                        \
 316                 .parent_names   = pnames,                       \
 317                 .num_parents    = ARRAY_SIZE(pnames),           \
 318                 .flags          = f,                            \
 319                 .muxdiv_offset  = mo,                           \
 320                 .mux_shift      = ms,                           \
 321                 .mux_width      = mw,                           \
 322                 .mux_flags      = mf,                           \
 323                 .div_shift      = ds,                           \
 324                 .div_width      = dw,                           \
 325                 .div_flags      = df,                           \
 326                 .gate_offset    = go,                           \
 327                 .gate_shift     = gs,                           \
 328                 .gate_flags     = gf,                           \
 329         }
 330
 331 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 332                         go, gs, gf)                             \
 333         {                                                       \
 334                 .id             = _id,                          \
 335                 .branch_type    = branch_composite,             \
 336                 .name           = cname,                        \
 337                 .parent_names   = (const char *[]){ pname },    \
 338                 .num_parents    = 1,                            \
 339                 .flags          = f,                            \
 340                 .muxdiv_offset  = mo,                           \
 341                 .div_shift      = ds,                           \
 342                 .div_width      = dw,                           \
 343                 .div_flags      = df,                           \
 344                 .gate_offset    = go,                           \
 345                 .gate_shift     = gs,                           \
 346                 .gate_flags     = gf,                           \
 347         }
 348
 349 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 350                                df, dt, go, gs, gf)              \
 351         {                                                       \
 352                 .id             = _id,                          \
 353                 .branch_type    = branch_composite,             \
 354                 .name           = cname,                        \
 355                 .parent_names   = (const char *[]){ pname },    \
 356                 .num_parents    = 1,                            \
 357                 .flags          = f,                            \
 358                 .muxdiv_offset  = mo,                           \
 359                 .div_shift      = ds,                           \
 360                 .div_width      = dw,                           \
 361                 .div_flags      = df,                           \
 362                 .div_table      = dt,                           \
 363                 .gate_offset    = go,                           \
 364                 .gate_shift     = gs,                           \
 365                 .gate_flags     = gf,                           \
 366         }
 367
 368 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 369                         go, gs, gf)                             \
 370         {                                                       \
 371                 .id             = _id,                          \
 372                 .branch_type    = branch_composite,             \
 373                 .name           = cname,                        \
 374                 .parent_names   = pnames,                       \
 375                 .num_parents    = ARRAY_SIZE(pnames),           \
 376                 .flags          = f,                            \
 377                 .muxdiv_offset  = mo,                           \
 378                 .mux_shift      = ms,                           \
 379                 .mux_width      = mw,                           \
 380                 .mux_flags      = mf,                           \
 381                 .gate_offset    = go,                           \
 382                 .gate_shift     = gs,                           \
 383                 .gate_flags     = gf,                           \
 384         }
 385
 386 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 387                          ds, dw, df)                            \
 388         {                                                       \
 389                 .id             = _id,                          \
 390                 .branch_type    = branch_composite,             \
 391                 .name           = cname,                        \
 392                 .parent_names   = pnames,                       \
 393                 .num_parents    = ARRAY_SIZE(pnames),           \
 394                 .flags          = f,                            \
 395                 .muxdiv_offset  = mo,                           \
 396                 .mux_shift      = ms,                           \
 397                 .mux_width      = mw,                           \
 398                 .mux_flags      = mf,                           \
 399                 .div_shift      = ds,                           \
 400                 .div_width      = dw,                           \
 401                 .div_flags      = df,                           \
 402                 .gate_offset    = -1,                           \
 403         }
 404
 405 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 406                                 mw, mf, ds, dw, df, dt)         \
 407         {                                                       \
 408                 .id             = _id,                          \
 409                 .branch_type    = branch_composite,             \
 410                 .name           = cname,                        \
 411                 .parent_names   = pnames,                       \
 412                 .num_parents    = ARRAY_SIZE(pnames),           \
 413                 .flags          = f,                            \
 414                 .muxdiv_offset  = mo,                           \
 415                 .mux_shift      = ms,                           \
 416                 .mux_width      = mw,                           \
 417                 .mux_flags      = mf,                           \
 418                 .div_shift      = ds,                           \
 419                 .div_width      = dw,                           \
 420                 .div_flags      = df,                           \
 421                 .div_table      = dt,                           \
 422                 .gate_offset    = -1,                           \
 423         }
 424
 425 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 426         {                                                       \
 427                 .id             = _id,                          \
 428                 .branch_type    = branch_fraction_divider,      \
 429                 .name           = cname,                        \
 430                 .parent_names   = (const char *[]){ pname },    \
 431                 .num_parents    = 1,                            \
 432                 .flags          = f,                            \
 433                 .muxdiv_offset  = mo,                           \
 434                 .div_shift      = 16,                           \
 435                 .div_width      = 16,                           \
 436                 .div_flags      = df,                           \
 437                 .gate_offset    = go,                           \
 438                 .gate_shift     = gs,                           \
 439                 .gate_flags     = gf,                           \
 440         }
 441
 442 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
 443         {                                                       \
 444                 .id             = _id,                          \
 445                 .branch_type    = branch_fraction_divider,      \
 446                 .name           = cname,                        \
 447                 .parent_names   = (const char *[]){ pname },    \
 448                 .num_parents    = 1,                            \
 449                 .flags          = f,                            \
 450                 .muxdiv_offset  = mo,                           \
 451                 .div_shift      = 16,                           \
 452                 .div_width      = 16,                           \
 453                 .div_flags      = df,                           \
 454                 .gate_offset    = go,                           \
 455                 .gate_shift     = gs,                           \
 456                 .gate_flags     = gf,                           \
 457                 .child          = ch,                           \
 458         }
 459
 460 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
 461         {                                                       \
 462                 .id             = _id,                          \
 463                 .branch_type    = branch_fraction_divider,      \
 464                 .name           = cname,                        \
 465                 .parent_names   = (const char *[]){ pname },    \
 466                 .num_parents    = 1,                            \
 467                 .flags          = f,                            \
 468                 .muxdiv_offset  = mo,                           \
 469                 .div_shift      = 16,                           \
 470                 .div_width      = 16,                           \
 471                 .div_flags      = df,                           \
 472                 .gate_offset    = -1,                           \
 473                 .child          = ch,                           \
 474         }
 475
 476 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 477         {                                                       \
 478                 .id             = _id,                          \
 479                 .branch_type    = branch_mux,                   \
 480                 .name           = cname,                        \
 481                 .parent_names   = pnames,                       \
 482                 .num_parents    = ARRAY_SIZE(pnames),           \
 483                 .flags          = f,                            \
 484                 .muxdiv_offset  = o,                            \
 485                 .mux_shift      = s,                            \
 486                 .mux_width      = w,                            \
 487                 .mux_flags      = mf,                           \
 488                 .gate_offset    = -1,                           \
 489         }
 490
 491 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 492         {                                                       \
 493                 .id             = _id,                          \
 494                 .branch_type    = branch_divider,               \
 495                 .name           = cname,                        \
 496                 .parent_names   = (const char *[]){ pname },    \
 497                 .num_parents    = 1,                            \
 498                 .flags          = f,                            \
 499                 .muxdiv_offset  = o,                            \
 500                 .div_shift      = s,                            \
 501                 .div_width      = w,                            \
 502                 .div_flags      = df,                           \
 503                 .gate_offset    = -1,                           \
 504         }
 505
 506 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 507         {                                                       \
 508                 .id             = _id,                          \
 509                 .branch_type    = branch_divider,               \
 510                 .name           = cname,                        \
 511                 .parent_names   = (const char *[]){ pname },    \
 512                 .num_parents    = 1,                            \
 513                 .flags          = f,                            \
 514                 .muxdiv_offset  = o,                            \
 515                 .div_shift      = s,                            \
 516                 .div_width      = w,                            \
 517                 .div_flags      = df,                           \
 518                 .div_table      = dt,                           \
 519         }
 520
 521 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 522         {                                                       \
 523                 .id             = _id,                          \
 524                 .branch_type    = branch_gate,                  \
 525                 .name           = cname,                        \
 526                 .parent_names   = (const char *[]){ pname },    \
 527                 .num_parents    = 1,                            \
 528                 .flags          = f,                            \
 529                 .gate_offset    = o,                            \
 530                 .gate_shift     = b,                            \
 531                 .gate_flags     = gf,                           \
 532         }
 533
 534 #define MMC(_id, cname, pname, offset, shift)                   \
 535         {                                                       \
 536                 .id             = _id,                          \
 537                 .branch_type    = branch_mmc,                   \
 538                 .name           = cname,                        \
 539                 .parent_names   = (const char *[]){ pname },    \
 540                 .num_parents    = 1,                            \
 541                 .muxdiv_offset  = offset,                       \
 542                 .div_shift      = shift,                        \
 543         }
 544
 545 #define INVERTER(_id, cname, pname, io, is, if)                 \
 546         {                                                       \
 547                 .id             = _id,                          \
 548                 .branch_type    = branch_inverter,              \
 549                 .name           = cname,                        \
 550                 .parent_names   = (const char *[]){ pname },    \
 551                 .num_parents    = 1,                            \
 552                 .muxdiv_offset  = io,                           \
 553                 .div_shift      = is,                           \
 554                 .div_flags      = if,                           \
 555         }
 556
 557 #define FACTOR(_id, cname, pname,  f, fm, fd)                   \
 558         {                                                       \
 559                 .id             = _id,                          \
 560                 .branch_type    = branch_factor,                \
 561                 .name           = cname,                        \
 562                 .parent_names   = (const char *[]){ pname },    \
 563                 .num_parents    = 1,                            \
 564                 .flags          = f,                            \
 565                 .div_shift      = fm,                           \
 566                 .div_width      = fd,                           \
 567         }
 568
 569 #define FACTOR_GATE(_id, cname, pname,  f, fm, fd, go, gb, gf)  \
 570         {                                                       \
 571                 .id             = _id,                          \
 572                 .branch_type    = branch_factor,                \
 573                 .name           = cname,                        \
 574                 .parent_names   = (const char *[]){ pname },    \
 575                 .num_parents    = 1,                            \
 576                 .flags          = f,                            \
 577                 .div_shift      = fm,                           \
 578                 .div_width      = fd,                           \
 579                 .gate_offset    = go,                           \
 580                 .gate_shift     = gb,                           \
 581                 .gate_flags     = gf,                           \
 582         }
 583
 584 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
 585                         void __iomem *base, unsigned long nr_clks);
 586 void rockchip_clk_of_add_provider(struct device_node *np,
 587                                 struct rockchip_clk_provider *ctx);
 588 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
 589 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 590                              struct clk *clk, unsigned int id);
 591 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
 592                                     struct rockchip_clk_branch *list,
 593                                     unsigned int nr_clk);
 594 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 595                                 struct rockchip_pll_clock *pll_list,
 596                                 unsigned int nr_pll, int grf_lock_offset);
 597 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 598                         unsigned int lookup_id, const char *name,
 599                         const char *const *parent_names, u8 num_parents,
 600                         const struct rockchip_cpuclk_reg_data *reg_data,
 601                         const struct rockchip_cpuclk_rate_table *rates,
 602                         int nrates);
 603 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 604 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 605                                         unsigned int reg, void (*cb)(void));
 606
 607 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 608
 609 #ifdef CONFIG_RESET_CONTROLLER
 610 void rockchip_register_softrst(struct device_node *np,
 611                                unsigned int num_regs,
 612                                void __iomem *base, u8 flags);
 613 #else
 614 static inline void rockchip_register_softrst(struct device_node *np,
 615                                unsigned int num_regs,
 616                                void __iomem *base, u8 flags)
 617 {
 618 }
 619 #endif
 620
 621 #endif