drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30 #include <linux/clk-provider.h>
  31
  32 struct clk;
  33
  34 #define HIWORD_UPDATE(val, mask, shift) \
  35                 ((val) << (shift) | (mask) << ((shift) + 16))
  36
  37 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
  38 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  39 #define RK2928_MODE_CON         0x40
  40 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  41 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  42 #define RK2928_GLB_SRST_FST             0x100
  43 #define RK2928_GLB_SRST_SND             0x104
  44 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  45 #define RK2928_MISC_CON         0x134
  46
  47 #define RK3036_SDMMC_CON0               0x144
  48 #define RK3036_SDMMC_CON1               0x148
  49 #define RK3036_SDIO_CON0                0x14c
  50 #define RK3036_SDIO_CON1                0x150
  51 #define RK3036_EMMC_CON0                0x154
  52 #define RK3036_EMMC_CON1                0x158
  53
  54 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  55 #define RK3288_MODE_CON                 0x50
  56 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  57 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  58 #define RK3288_GLB_SRST_FST             0x1b0
  59 #define RK3288_GLB_SRST_SND             0x1b4
  60 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  61 #define RK3288_MISC_CON                 0x1e8
  62 #define RK3288_SDMMC_CON0               0x200
  63 #define RK3288_SDMMC_CON1               0x204
  64 #define RK3288_SDIO0_CON0               0x208
  65 #define RK3288_SDIO0_CON1               0x20c
  66 #define RK3288_SDIO1_CON0               0x210
  67 #define RK3288_SDIO1_CON1               0x214
  68 #define RK3288_EMMC_CON0                0x218
  69 #define RK3288_EMMC_CON1                0x21c
  70
  71 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  72 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  73 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  74 #define RK3368_GLB_SRST_FST             0x280
  75 #define RK3368_GLB_SRST_SND             0x284
  76 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  77 #define RK3368_MISC_CON                 0x380
  78 #define RK3368_SDMMC_CON0               0x400
  79 #define RK3368_SDMMC_CON1               0x404
  80 #define RK3368_SDIO0_CON0               0x408
  81 #define RK3368_SDIO0_CON1               0x40c
  82 #define RK3368_SDIO1_CON0               0x410
  83 #define RK3368_SDIO1_CON1               0x414
  84 #define RK3368_EMMC_CON0                0x418
  85 #define RK3368_EMMC_CON1                0x41c
  86
  87 enum rockchip_pll_type {
  88         pll_rk3036,
  89         pll_rk3066,
  90         pll_rk3366,
  91 };
  92
  93 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  94                         _postdiv2, _dsmpd, _frac)               \
  95 {                                                               \
  96         .rate   = _rate##U,                                     \
  97         .fbdiv = _fbdiv,                                        \
  98         .postdiv1 = _postdiv1,                                  \
  99         .refdiv = _refdiv,                                      \
 100         .postdiv2 = _postdiv2,                                  \
 101         .dsmpd = _dsmpd,                                        \
 102         .frac = _frac,                                          \
 103 }
 104
 105 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
 106 {                                               \
 107         .rate   = _rate##U,                     \
 108         .nr = _nr,                              \
 109         .nf = _nf,                              \
 110         .no = _no,                              \
 111         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 112 }
 113
 114 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 115 {                                                               \
 116         .rate   = _rate##U,                                     \
 117         .nr = _nr,                                              \
 118         .nf = _nf,                                              \
 119         .no = _no,                                              \
 120         .nb = _nb,                                              \
 121 }
 122
 123 /**
 124  * struct rockchip_clk_provider: information about clock provider
 125  * @reg_base: virtual address for the register base.
 126  * @clk_data: holds clock related data like clk* and number of clocks.
 127  * @cru_node: device-node of the clock-provider
 128  * @grf: regmap of the general-register-files syscon
 129  * @lock: maintains exclusion between callbacks for a given clock-provider.
 130  */
 131 struct rockchip_clk_provider {
 132         void __iomem *reg_base;
 133         struct clk_onecell_data clk_data;
 134         struct device_node *cru_node;
 135         struct regmap *grf;
 136         spinlock_t lock;
 137 };
 138
 139 struct rockchip_pll_rate_table {
 140         unsigned long rate;
 141         unsigned int nr;
 142         unsigned int nf;
 143         unsigned int no;
 144         unsigned int nb;
 145         /* for RK3036 */
 146         unsigned int fbdiv;
 147         unsigned int postdiv1;
 148         unsigned int refdiv;
 149         unsigned int postdiv2;
 150         unsigned int dsmpd;
 151         unsigned int frac;
 152 };
 153
 154 /**
 155  * struct rockchip_pll_clock: information about pll clock
 156  * @id: platform specific id of the clock.
 157  * @name: name of this pll clock.
 158  * @parent_name: name of the parent clock.
 159  * @flags: optional flags for basic clock.
 160  * @con_offset: offset of the register for configuring the PLL.
 161  * @mode_offset: offset of the register for configuring the PLL-mode.
 162  * @mode_shift: offset inside the mode-register for the mode of this pll.
 163  * @lock_shift: offset inside the lock register for the lock status.
 164  * @type: Type of PLL to be registered.
 165  * @pll_flags: hardware-specific flags
 166  * @rate_table: Table of usable pll rates
 167  *
 168  * Flags:
 169  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 170  *      rate_table parameters and ajust them if necessary.
 171  */
 172 struct rockchip_pll_clock {
 173         unsigned int            id;
 174         const char              *name;
 175         const char              *const *parent_names;
 176         u8                      num_parents;
 177         unsigned long           flags;
 178         int                     con_offset;
 179         int                     mode_offset;
 180         int                     mode_shift;
 181         int                     lock_shift;
 182         enum rockchip_pll_type  type;
 183         u8                      pll_flags;
 184         struct rockchip_pll_rate_table *rate_table;
 185 };
 186
 187 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 188
 189 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 190                 _lshift, _pflags, _rtable)                              \
 191         {                                                               \
 192                 .id             = _id,                                  \
 193                 .type           = _type,                                \
 194                 .name           = _name,                                \
 195                 .parent_names   = _pnames,                              \
 196                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 197                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 198                 .con_offset     = _con,                                 \
 199                 .mode_offset    = _mode,                                \
 200                 .mode_shift     = _mshift,                              \
 201                 .lock_shift     = _lshift,                              \
 202                 .pll_flags      = _pflags,                              \
 203                 .rate_table     = _rtable,                              \
 204         }
 205
 206 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 207                 enum rockchip_pll_type pll_type,
 208                 const char *name, const char *const *parent_names,
 209                 u8 num_parents, int con_offset, int grf_lock_offset,
 210                 int lock_shift, int mode_offset, int mode_shift,
 211                 struct rockchip_pll_rate_table *rate_table,
 212                 u8 clk_pll_flags);
 213
 214 struct rockchip_cpuclk_clksel {
 215         int reg;
 216         u32 val;
 217 };
 218
 219 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 220 struct rockchip_cpuclk_rate_table {
 221         unsigned long prate;
 222         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 223 };
 224
 225 /**
 226  * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
 227  * @core_reg:           register offset of the core settings register
 228  * @div_core_shift:     core divider offset used to divide the pll value
 229  * @div_core_mask:      core divider mask
 230  * @mux_core_alt:       mux value to select alternate parent
 231  * @mux_core_main:      mux value to select main parent of core
 232  * @mux_core_shift:     offset of the core multiplexer
 233  * @mux_core_mask:      core multiplexer mask
 234  */
 235 struct rockchip_cpuclk_reg_data {
 236         int             core_reg;
 237         u8              div_core_shift;
 238         u32             div_core_mask;
 239         u8              mux_core_alt;
 240         u8              mux_core_main;
 241         u8              mux_core_shift;
 242         u32             mux_core_mask;
 243 };
 244
 245 struct clk *rockchip_clk_register_cpuclk(const char *name,
 246                         const char *const *parent_names, u8 num_parents,
 247                         const struct rockchip_cpuclk_reg_data *reg_data,
 248                         const struct rockchip_cpuclk_rate_table *rates,
 249                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 250
 251 struct clk *rockchip_clk_register_mmc(const char *name,
 252                                 const char *const *parent_names, u8 num_parents,
 253                                 void __iomem *reg, int shift);
 254
 255 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 256
 257 struct clk *rockchip_clk_register_inverter(const char *name,
 258                                 const char *const *parent_names, u8 num_parents,
 259                                 void __iomem *reg, int shift, int flags,
 260                                 spinlock_t *lock);
 261
 262 #define PNAME(x) static const char *const x[] __initconst
 263
 264 enum rockchip_clk_branch_type {
 265         branch_composite,
 266         branch_mux,
 267         branch_divider,
 268         branch_fraction_divider,
 269         branch_gate,
 270         branch_mmc,
 271         branch_inverter,
 272         branch_factor,
 273 };
 274
 275 struct rockchip_clk_branch {
 276         unsigned int                    id;
 277         enum rockchip_clk_branch_type   branch_type;
 278         const char                      *name;
 279         const char                      *const *parent_names;
 280         u8                              num_parents;
 281         unsigned long                   flags;
 282         int                             muxdiv_offset;
 283         u8                              mux_shift;
 284         u8                              mux_width;
 285         u8                              mux_flags;
 286         u8                              div_shift;
 287         u8                              div_width;
 288         u8                              div_flags;
 289         struct clk_div_table            *div_table;
 290         int                             gate_offset;
 291         u8                              gate_shift;
 292         u8                              gate_flags;
 293         struct rockchip_clk_branch      *child;
 294 };
 295
 296 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 297                   df, go, gs, gf)                               \
 298         {                                                       \
 299                 .id             = _id,                          \
 300                 .branch_type    = branch_composite,             \
 301                 .name           = cname,                        \
 302                 .parent_names   = pnames,                       \
 303                 .num_parents    = ARRAY_SIZE(pnames),           \
 304                 .flags          = f,                            \
 305                 .muxdiv_offset  = mo,                           \
 306                 .mux_shift      = ms,                           \
 307                 .mux_width      = mw,                           \
 308                 .mux_flags      = mf,                           \
 309                 .div_shift      = ds,                           \
 310                 .div_width      = dw,                           \
 311                 .div_flags      = df,                           \
 312                 .gate_offset    = go,                           \
 313                 .gate_shift     = gs,                           \
 314                 .gate_flags     = gf,                           \
 315         }
 316
 317 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 318                         go, gs, gf)                             \
 319         {                                                       \
 320                 .id             = _id,                          \
 321                 .branch_type    = branch_composite,             \
 322                 .name           = cname,                        \
 323                 .parent_names   = (const char *[]){ pname },    \
 324                 .num_parents    = 1,                            \
 325                 .flags          = f,                            \
 326                 .muxdiv_offset  = mo,                           \
 327                 .div_shift      = ds,                           \
 328                 .div_width      = dw,                           \
 329                 .div_flags      = df,                           \
 330                 .gate_offset    = go,                           \
 331                 .gate_shift     = gs,                           \
 332                 .gate_flags     = gf,                           \
 333         }
 334
 335 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 336                                df, dt, go, gs, gf)              \
 337         {                                                       \
 338                 .id             = _id,                          \
 339                 .branch_type    = branch_composite,             \
 340                 .name           = cname,                        \
 341                 .parent_names   = (const char *[]){ pname },    \
 342                 .num_parents    = 1,                            \
 343                 .flags          = f,                            \
 344                 .muxdiv_offset  = mo,                           \
 345                 .div_shift      = ds,                           \
 346                 .div_width      = dw,                           \
 347                 .div_flags      = df,                           \
 348                 .div_table      = dt,                           \
 349                 .gate_offset    = go,                           \
 350                 .gate_shift     = gs,                           \
 351                 .gate_flags     = gf,                           \
 352         }
 353
 354 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 355                         go, gs, gf)                             \
 356         {                                                       \
 357                 .id             = _id,                          \
 358                 .branch_type    = branch_composite,             \
 359                 .name           = cname,                        \
 360                 .parent_names   = pnames,                       \
 361                 .num_parents    = ARRAY_SIZE(pnames),           \
 362                 .flags          = f,                            \
 363                 .muxdiv_offset  = mo,                           \
 364                 .mux_shift      = ms,                           \
 365                 .mux_width      = mw,                           \
 366                 .mux_flags      = mf,                           \
 367                 .gate_offset    = go,                           \
 368                 .gate_shift     = gs,                           \
 369                 .gate_flags     = gf,                           \
 370         }
 371
 372 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 373                          ds, dw, df)                            \
 374         {                                                       \
 375                 .id             = _id,                          \
 376                 .branch_type    = branch_composite,             \
 377                 .name           = cname,                        \
 378                 .parent_names   = pnames,                       \
 379                 .num_parents    = ARRAY_SIZE(pnames),           \
 380                 .flags          = f,                            \
 381                 .muxdiv_offset  = mo,                           \
 382                 .mux_shift      = ms,                           \
 383                 .mux_width      = mw,                           \
 384                 .mux_flags      = mf,                           \
 385                 .div_shift      = ds,                           \
 386                 .div_width      = dw,                           \
 387                 .div_flags      = df,                           \
 388                 .gate_offset    = -1,                           \
 389         }
 390
 391 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 392                                 mw, mf, ds, dw, df, dt)         \
 393         {                                                       \
 394                 .id             = _id,                          \
 395                 .branch_type    = branch_composite,             \
 396                 .name           = cname,                        \
 397                 .parent_names   = pnames,                       \
 398                 .num_parents    = ARRAY_SIZE(pnames),           \
 399                 .flags          = f,                            \
 400                 .muxdiv_offset  = mo,                           \
 401                 .mux_shift      = ms,                           \
 402                 .mux_width      = mw,                           \
 403                 .mux_flags      = mf,                           \
 404                 .div_shift      = ds,                           \
 405                 .div_width      = dw,                           \
 406                 .div_flags      = df,                           \
 407                 .div_table      = dt,                           \
 408                 .gate_offset    = -1,                           \
 409         }
 410
 411 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 412         {                                                       \
 413                 .id             = _id,                          \
 414                 .branch_type    = branch_fraction_divider,      \
 415                 .name           = cname,                        \
 416                 .parent_names   = (const char *[]){ pname },    \
 417                 .num_parents    = 1,                            \
 418                 .flags          = f,                            \
 419                 .muxdiv_offset  = mo,                           \
 420                 .div_shift      = 16,                           \
 421                 .div_width      = 16,                           \
 422                 .div_flags      = df,                           \
 423                 .gate_offset    = go,                           \
 424                 .gate_shift     = gs,                           \
 425                 .gate_flags     = gf,                           \
 426         }
 427
 428 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
 429         {                                                       \
 430                 .id             = _id,                          \
 431                 .branch_type    = branch_fraction_divider,      \
 432                 .name           = cname,                        \
 433                 .parent_names   = (const char *[]){ pname },    \
 434                 .num_parents    = 1,                            \
 435                 .flags          = f,                            \
 436                 .muxdiv_offset  = mo,                           \
 437                 .div_shift      = 16,                           \
 438                 .div_width      = 16,                           \
 439                 .div_flags      = df,                           \
 440                 .gate_offset    = go,                           \
 441                 .gate_shift     = gs,                           \
 442                 .gate_flags     = gf,                           \
 443                 .child          = ch,                           \
 444         }
 445
 446 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
 447         {                                                       \
 448                 .id             = _id,                          \
 449                 .branch_type    = branch_fraction_divider,      \
 450                 .name           = cname,                        \
 451                 .parent_names   = (const char *[]){ pname },    \
 452                 .num_parents    = 1,                            \
 453                 .flags          = f,                            \
 454                 .muxdiv_offset  = mo,                           \
 455                 .div_shift      = 16,                           \
 456                 .div_width      = 16,                           \
 457                 .div_flags      = df,                           \
 458                 .gate_offset    = -1,                           \
 459                 .child          = ch,                           \
 460         }
 461
 462 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 463         {                                                       \
 464                 .id             = _id,                          \
 465                 .branch_type    = branch_mux,                   \
 466                 .name           = cname,                        \
 467                 .parent_names   = pnames,                       \
 468                 .num_parents    = ARRAY_SIZE(pnames),           \
 469                 .flags          = f,                            \
 470                 .muxdiv_offset  = o,                            \
 471                 .mux_shift      = s,                            \
 472                 .mux_width      = w,                            \
 473                 .mux_flags      = mf,                           \
 474                 .gate_offset    = -1,                           \
 475         }
 476
 477 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 478         {                                                       \
 479                 .id             = _id,                          \
 480                 .branch_type    = branch_divider,               \
 481                 .name           = cname,                        \
 482                 .parent_names   = (const char *[]){ pname },    \
 483                 .num_parents    = 1,                            \
 484                 .flags          = f,                            \
 485                 .muxdiv_offset  = o,                            \
 486                 .div_shift      = s,                            \
 487                 .div_width      = w,                            \
 488                 .div_flags      = df,                           \
 489                 .gate_offset    = -1,                           \
 490         }
 491
 492 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 493         {                                                       \
 494                 .id             = _id,                          \
 495                 .branch_type    = branch_divider,               \
 496                 .name           = cname,                        \
 497                 .parent_names   = (const char *[]){ pname },    \
 498                 .num_parents    = 1,                            \
 499                 .flags          = f,                            \
 500                 .muxdiv_offset  = o,                            \
 501                 .div_shift      = s,                            \
 502                 .div_width      = w,                            \
 503                 .div_flags      = df,                           \
 504                 .div_table      = dt,                           \
 505         }
 506
 507 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 508         {                                                       \
 509                 .id             = _id,                          \
 510                 .branch_type    = branch_gate,                  \
 511                 .name           = cname,                        \
 512                 .parent_names   = (const char *[]){ pname },    \
 513                 .num_parents    = 1,                            \
 514                 .flags          = f,                            \
 515                 .gate_offset    = o,                            \
 516                 .gate_shift     = b,                            \
 517                 .gate_flags     = gf,                           \
 518         }
 519
 520 #define MMC(_id, cname, pname, offset, shift)                   \
 521         {                                                       \
 522                 .id             = _id,                          \
 523                 .branch_type    = branch_mmc,                   \
 524                 .name           = cname,                        \
 525                 .parent_names   = (const char *[]){ pname },    \
 526                 .num_parents    = 1,                            \
 527                 .muxdiv_offset  = offset,                       \
 528                 .div_shift      = shift,                        \
 529         }
 530
 531 #define INVERTER(_id, cname, pname, io, is, if)                 \
 532         {                                                       \
 533                 .id             = _id,                          \
 534                 .branch_type    = branch_inverter,              \
 535                 .name           = cname,                        \
 536                 .parent_names   = (const char *[]){ pname },    \
 537                 .num_parents    = 1,                            \
 538                 .muxdiv_offset  = io,                           \
 539                 .div_shift      = is,                           \
 540                 .div_flags      = if,                           \
 541         }
 542
 543 #define FACTOR(_id, cname, pname,  f, fm, fd)                   \
 544         {                                                       \
 545                 .id             = _id,                          \
 546                 .branch_type    = branch_factor,                \
 547                 .name           = cname,                        \
 548                 .parent_names   = (const char *[]){ pname },    \
 549                 .num_parents    = 1,                            \
 550                 .flags          = f,                            \
 551                 .div_shift      = fm,                           \
 552                 .div_width      = fd,                           \
 553         }
 554
 555 #define FACTOR_GATE(_id, cname, pname,  f, fm, fd, go, gb, gf)  \
 556         {                                                       \
 557                 .id             = _id,                          \
 558                 .branch_type    = branch_factor,                \
 559                 .name           = cname,                        \
 560                 .parent_names   = (const char *[]){ pname },    \
 561                 .num_parents    = 1,                            \
 562                 .flags          = f,                            \
 563                 .div_shift      = fm,                           \
 564                 .div_width      = fd,                           \
 565                 .gate_offset    = go,                           \
 566                 .gate_shift     = gb,                           \
 567                 .gate_flags     = gf,                           \
 568         }
 569
 570 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
 571                         void __iomem *base, unsigned long nr_clks);
 572 void rockchip_clk_of_add_provider(struct device_node *np,
 573                                 struct rockchip_clk_provider *ctx);
 574 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
 575 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 576                              struct clk *clk, unsigned int id);
 577 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
 578                                     struct rockchip_clk_branch *list,
 579                                     unsigned int nr_clk);
 580 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 581                                 struct rockchip_pll_clock *pll_list,
 582                                 unsigned int nr_pll, int grf_lock_offset);
 583 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 584                         unsigned int lookup_id, const char *name,
 585                         const char *const *parent_names, u8 num_parents,
 586                         const struct rockchip_cpuclk_reg_data *reg_data,
 587                         const struct rockchip_cpuclk_rate_table *rates,
 588                         int nrates);
 589 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 590 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 591                                         unsigned int reg, void (*cb)(void));
 592
 593 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 594
 595 #ifdef CONFIG_RESET_CONTROLLER
 596 void rockchip_register_softrst(struct device_node *np,
 597                                unsigned int num_regs,
 598                                void __iomem *base, u8 flags);
 599 #else
 600 static inline void rockchip_register_softrst(struct device_node *np,
 601                                unsigned int num_regs,
 602                                void __iomem *base, u8 flags)
 603 {
 604 }
 605 #endif
 606
 607 #endif