2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
28 enum rk3399_pmu_plls {
32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
103 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
104 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
105 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
106 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
107 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
108 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
112 static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
113 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
114 RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
115 RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
116 RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
117 RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
118 RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
119 RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
120 RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */
121 RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
122 RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
123 RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
124 RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
125 RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
126 RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
127 RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
132 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
134 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
135 "clk_core_l_bpll_src",
136 "clk_core_l_dpll_src",
137 "clk_core_l_gpll_src" };
138 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
139 "clk_core_b_bpll_src",
140 "clk_core_b_dpll_src",
141 "clk_core_b_gpll_src" };
142 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
145 "clk_ddrc_gpll_src" };
146 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
149 "vpll_aclk_cci_src" };
150 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
152 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
154 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
155 "gpll_aclk_perihp_src" };
157 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
158 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
159 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
160 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
161 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
162 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
164 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
166 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
168 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
170 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
172 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
173 "ppll", "upll", "xin24m" };
175 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
176 PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" };
178 * We hope to be able to HDMI/DP can obtain better signal quality,
179 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
180 * HDMI/DP phyclock can monopolize VPLL.
182 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
184 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll",
187 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
188 "dummy_dclk_vop0_frac" };
189 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
190 "dummy_dclk_vop1_frac" };
192 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
194 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
195 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
196 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
198 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
199 "clk_pcie_core_phy" };
201 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
202 "gpll_aclk_emmc_src" };
204 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
205 "gpll_aclk_perilp0_src" };
207 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
208 "gpll_fclk_cm0s_src" };
210 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
211 "gpll_hclk_perilp1_src" };
213 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
214 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
216 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
217 "clk_usbphy1_480m_src" };
218 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
219 "gpll_aclk_gmac_src" };
220 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
221 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
222 "clkin_i2s", "xin12m" };
223 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
224 "clkin_i2s", "xin12m" };
225 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
226 "clkin_i2s", "xin12m" };
227 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
228 "clkin_i2s", "xin12m" };
229 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
231 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
233 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
234 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
235 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
236 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
238 /* PMU CRU parents */
239 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
240 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
241 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
242 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
243 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
245 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
247 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
248 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
249 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
250 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
251 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
252 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
253 RK3399_PLL_CON(19), 8, 31, 0, NULL),
254 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
255 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
256 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
257 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
258 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
259 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
260 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
261 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
264 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
265 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
266 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
269 #define MFLAGS CLK_MUX_HIWORD_MASK
270 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
271 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
272 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
274 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
275 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
276 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
278 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
279 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
280 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
282 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
283 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
284 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
286 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
287 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
288 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
290 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
291 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
292 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
294 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
295 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
296 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
298 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
299 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
300 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
302 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
303 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
304 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
306 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
307 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
308 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
310 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
311 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
312 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
314 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
315 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
316 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
318 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
319 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
320 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
322 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
323 .core_reg = RK3399_CLKSEL_CON(0),
325 .div_core_mask = 0x1f,
329 .mux_core_mask = 0x3,
332 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
333 .core_reg = RK3399_CLKSEL_CON(2),
335 .div_core_mask = 0x1f,
339 .mux_core_mask = 0x3,
342 #define RK3399_DIV_ACLKM_MASK 0x1f
343 #define RK3399_DIV_ACLKM_SHIFT 8
344 #define RK3399_DIV_ATCLK_MASK 0x1f
345 #define RK3399_DIV_ATCLK_SHIFT 0
346 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
347 #define RK3399_DIV_PCLK_DBG_SHIFT 8
349 #define RK3399_CLKSEL0(_offs, _aclkm) \
351 .reg = RK3399_CLKSEL_CON(0 + _offs), \
352 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
353 RK3399_DIV_ACLKM_SHIFT), \
355 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
357 .reg = RK3399_CLKSEL_CON(1 + _offs), \
358 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
359 RK3399_DIV_ATCLK_SHIFT) | \
360 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
361 RK3399_DIV_PCLK_DBG_SHIFT), \
364 /* cluster_l: aclkm in clksel0, rest in clksel1 */
365 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
367 .prate = _prate##U, \
369 RK3399_CLKSEL0(0, _aclkm), \
370 RK3399_CLKSEL1(0, _atclk, _pdbg), \
374 /* cluster_b: aclkm in clksel2, rest in clksel3 */
375 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
377 .prate = _prate##U, \
379 RK3399_CLKSEL0(2, _aclkm), \
380 RK3399_CLKSEL1(2, _atclk, _pdbg), \
384 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
385 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
386 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
387 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
388 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
389 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
390 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
391 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
392 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
393 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
394 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
395 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
396 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
397 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
398 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
399 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
402 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
403 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
404 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
405 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
406 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
407 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
408 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
409 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
410 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
411 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
412 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
413 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
414 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
415 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
416 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
417 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
418 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
419 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
420 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
421 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
422 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
423 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
424 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
427 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
429 * CRU Clock-Architecture
433 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
434 RK3399_CLKGATE_CON(6), 5, GFLAGS),
435 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
436 RK3399_CLKGATE_CON(6), 6, GFLAGS),
438 GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
439 RK3399_CLKGATE_CON(13), 12, GFLAGS),
440 GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
441 RK3399_CLKGATE_CON(13), 12, GFLAGS),
442 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
443 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
445 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
446 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
448 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
449 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
450 RK3399_CLKGATE_CON(6), 4, GFLAGS),
452 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
453 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
454 RK3399_CLKGATE_CON(12), 0, GFLAGS),
455 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
456 RK3399_CLKGATE_CON(30), 0, GFLAGS),
457 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
458 RK3399_CLKGATE_CON(30), 1, GFLAGS),
459 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
460 RK3399_CLKGATE_CON(30), 2, GFLAGS),
461 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
462 RK3399_CLKGATE_CON(30), 3, GFLAGS),
463 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
464 RK3399_CLKGATE_CON(30), 4, GFLAGS),
466 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
467 RK3399_CLKGATE_CON(12), 1, GFLAGS),
468 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
469 RK3399_CLKGATE_CON(12), 2, GFLAGS),
471 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
472 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
473 RK3399_CLKGATE_CON(12), 3, GFLAGS),
475 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
476 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
477 RK3399_CLKGATE_CON(12), 4, GFLAGS),
479 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
480 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
481 RK3399_CLKGATE_CON(13), 4, GFLAGS),
483 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
484 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
485 RK3399_CLKGATE_CON(13), 5, GFLAGS),
487 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
488 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
489 RK3399_CLKGATE_CON(13), 6, GFLAGS),
491 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
492 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
493 RK3399_CLKGATE_CON(13), 7, GFLAGS),
496 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
497 RK3399_CLKGATE_CON(0), 0, GFLAGS),
498 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
499 RK3399_CLKGATE_CON(0), 1, GFLAGS),
500 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
501 RK3399_CLKGATE_CON(0), 2, GFLAGS),
502 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
503 RK3399_CLKGATE_CON(0), 3, GFLAGS),
505 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
506 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
507 RK3399_CLKGATE_CON(0), 4, GFLAGS),
508 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
509 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
510 RK3399_CLKGATE_CON(0), 5, GFLAGS),
511 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
512 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
513 RK3399_CLKGATE_CON(0), 6, GFLAGS),
515 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
516 RK3399_CLKGATE_CON(14), 12, GFLAGS),
517 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
518 RK3399_CLKGATE_CON(14), 13, GFLAGS),
520 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
521 RK3399_CLKGATE_CON(14), 9, GFLAGS),
522 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
523 RK3399_CLKGATE_CON(14), 10, GFLAGS),
524 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
525 RK3399_CLKGATE_CON(14), 11, GFLAGS),
526 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
527 RK3399_CLKGATE_CON(0), 7, GFLAGS),
530 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
531 RK3399_CLKGATE_CON(1), 0, GFLAGS),
532 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
533 RK3399_CLKGATE_CON(1), 1, GFLAGS),
534 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
535 RK3399_CLKGATE_CON(1), 2, GFLAGS),
536 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
537 RK3399_CLKGATE_CON(1), 3, GFLAGS),
539 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
540 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
541 RK3399_CLKGATE_CON(1), 4, GFLAGS),
542 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
543 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
544 RK3399_CLKGATE_CON(1), 5, GFLAGS),
545 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
546 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
547 RK3399_CLKGATE_CON(1), 6, GFLAGS),
549 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
550 RK3399_CLKGATE_CON(14), 5, GFLAGS),
551 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
552 RK3399_CLKGATE_CON(14), 6, GFLAGS),
554 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
555 RK3399_CLKGATE_CON(14), 1, GFLAGS),
556 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
557 RK3399_CLKGATE_CON(14), 3, GFLAGS),
558 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
559 RK3399_CLKGATE_CON(14), 4, GFLAGS),
561 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
562 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
564 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
565 RK3399_CLKGATE_CON(14), 2, GFLAGS),
567 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
568 RK3399_CLKGATE_CON(1), 7, GFLAGS),
571 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
572 RK3399_CLKGATE_CON(6), 9, GFLAGS),
573 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
574 RK3399_CLKGATE_CON(6), 8, GFLAGS),
575 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
576 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
577 RK3399_CLKGATE_CON(6), 10, GFLAGS),
579 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
580 RK3399_CLKGATE_CON(32), 0, GFLAGS),
581 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
582 RK3399_CLKGATE_CON(32), 1, GFLAGS),
583 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
584 RK3399_CLKGATE_CON(32), 4, GFLAGS),
586 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
587 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
588 RK3399_CLKGATE_CON(6), 11, GFLAGS),
589 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
590 RK3399_CLKGATE_CON(32), 2, GFLAGS),
591 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
592 RK3399_CLKGATE_CON(32), 3, GFLAGS),
594 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
595 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
596 RK3399_CLKGATE_CON(5), 5, GFLAGS),
598 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
599 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
600 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
601 RK3399_CLKGATE_CON(5), 6, GFLAGS),
602 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
603 RK3399_CLKGATE_CON(5), 7, GFLAGS),
604 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
605 RK3399_CLKGATE_CON(5), 8, GFLAGS),
606 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
607 RK3399_CLKGATE_CON(5), 9, GFLAGS),
610 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
611 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
612 RK3399_CLKGATE_CON(8), 13, GFLAGS),
613 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
614 RK3399_CLKSEL_CON(99), 0,
615 RK3399_CLKGATE_CON(8), 14, GFLAGS,
616 &rk3399_spdif_fracmux),
617 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
618 RK3399_CLKGATE_CON(8), 15, GFLAGS),
620 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
621 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
622 RK3399_CLKGATE_CON(10), 6, GFLAGS),
624 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
625 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
626 RK3399_CLKGATE_CON(8), 3, GFLAGS),
627 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
628 RK3399_CLKSEL_CON(96), 0,
629 RK3399_CLKGATE_CON(8), 4, GFLAGS,
630 &rk3399_i2s0_fracmux),
631 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
632 RK3399_CLKGATE_CON(8), 5, GFLAGS),
634 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
635 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
636 RK3399_CLKGATE_CON(8), 6, GFLAGS),
637 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
638 RK3399_CLKSEL_CON(97), 0,
639 RK3399_CLKGATE_CON(8), 7, GFLAGS,
640 &rk3399_i2s1_fracmux),
641 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
642 RK3399_CLKGATE_CON(8), 8, GFLAGS),
644 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
645 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
646 RK3399_CLKGATE_CON(8), 9, GFLAGS),
647 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
648 RK3399_CLKSEL_CON(98), 0,
649 RK3399_CLKGATE_CON(8), 10, GFLAGS,
650 &rk3399_i2s2_fracmux),
651 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
652 RK3399_CLKGATE_CON(8), 11, GFLAGS),
654 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
655 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
656 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
657 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
658 RK3399_CLKGATE_CON(8), 12, GFLAGS),
661 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
662 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
663 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
664 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
665 RK3399_CLKGATE_CON(9), 0, GFLAGS),
666 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
667 RK3399_CLKSEL_CON(100), 0,
668 RK3399_CLKGATE_CON(9), 1, GFLAGS,
669 &rk3399_uart0_fracmux),
671 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
672 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
673 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
674 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
675 RK3399_CLKGATE_CON(9), 2, GFLAGS),
676 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
677 RK3399_CLKSEL_CON(101), 0,
678 RK3399_CLKGATE_CON(9), 3, GFLAGS,
679 &rk3399_uart1_fracmux),
681 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
682 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
683 RK3399_CLKGATE_CON(9), 4, GFLAGS),
684 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
685 RK3399_CLKSEL_CON(102), 0,
686 RK3399_CLKGATE_CON(9), 5, GFLAGS,
687 &rk3399_uart2_fracmux),
689 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
690 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
691 RK3399_CLKGATE_CON(9), 6, GFLAGS),
692 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
693 RK3399_CLKSEL_CON(103), 0,
694 RK3399_CLKGATE_CON(9), 7, GFLAGS,
695 &rk3399_uart3_fracmux),
697 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
698 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
699 RK3399_CLKGATE_CON(3), 4, GFLAGS),
701 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
702 RK3399_CLKGATE_CON(18), 10, GFLAGS),
703 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
704 RK3399_CLKGATE_CON(18), 12, GFLAGS),
705 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
706 RK3399_CLKGATE_CON(18), 15, GFLAGS),
707 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
708 RK3399_CLKGATE_CON(19), 2, GFLAGS),
710 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
711 RK3399_CLKGATE_CON(4), 11, GFLAGS),
712 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
713 RK3399_CLKGATE_CON(3), 5, GFLAGS),
714 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
715 RK3399_CLKGATE_CON(3), 6, GFLAGS),
718 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
719 RK3399_CLKGATE_CON(2), 0, GFLAGS),
720 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
721 RK3399_CLKGATE_CON(2), 1, GFLAGS),
722 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
723 RK3399_CLKGATE_CON(2), 2, GFLAGS),
724 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
725 RK3399_CLKGATE_CON(2), 3, GFLAGS),
727 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
728 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
729 RK3399_CLKGATE_CON(2), 4, GFLAGS),
731 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
732 RK3399_CLKGATE_CON(15), 0, GFLAGS),
733 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
734 RK3399_CLKGATE_CON(15), 1, GFLAGS),
735 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
736 RK3399_CLKGATE_CON(15), 2, GFLAGS),
737 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
738 RK3399_CLKGATE_CON(15), 3, GFLAGS),
739 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
740 RK3399_CLKGATE_CON(15), 4, GFLAGS),
741 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
742 RK3399_CLKGATE_CON(15), 7, GFLAGS),
744 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
745 RK3399_CLKGATE_CON(2), 5, GFLAGS),
746 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
747 RK3399_CLKGATE_CON(2), 6, GFLAGS),
748 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
749 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
750 RK3399_CLKGATE_CON(2), 7, GFLAGS),
752 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
753 RK3399_CLKGATE_CON(2), 8, GFLAGS),
754 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
755 RK3399_CLKGATE_CON(2), 9, GFLAGS),
756 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
757 RK3399_CLKGATE_CON(2), 10, GFLAGS),
758 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
759 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
760 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
761 RK3399_CLKGATE_CON(15), 5, GFLAGS),
762 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
763 RK3399_CLKGATE_CON(15), 6, GFLAGS),
766 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
767 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
768 RK3399_CLKGATE_CON(4), 0, GFLAGS),
769 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
770 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
771 RK3399_CLKGATE_CON(4), 1, GFLAGS),
772 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
773 RK3399_CLKGATE_CON(17), 2, GFLAGS),
774 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
775 RK3399_CLKGATE_CON(17), 3, GFLAGS),
777 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
778 RK3399_CLKGATE_CON(17), 0, GFLAGS),
779 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
780 RK3399_CLKGATE_CON(17), 1, GFLAGS),
783 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
784 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
785 RK3399_CLKGATE_CON(4), 4, GFLAGS),
786 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
787 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
788 RK3399_CLKGATE_CON(4), 5, GFLAGS),
790 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
791 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
792 RK3399_CLKGATE_CON(4), 2, GFLAGS),
793 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
794 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
795 RK3399_CLKGATE_CON(4), 3, GFLAGS),
796 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
797 RK3399_CLKGATE_CON(17), 10, GFLAGS),
798 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
799 RK3399_CLKGATE_CON(17), 11, GFLAGS),
801 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
802 RK3399_CLKGATE_CON(17), 8, GFLAGS),
803 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
804 RK3399_CLKGATE_CON(17), 9, GFLAGS),
807 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
808 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
809 RK3399_CLKGATE_CON(4), 6, GFLAGS),
810 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
811 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
812 RK3399_CLKGATE_CON(4), 7, GFLAGS),
813 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
814 RK3399_CLKGATE_CON(16), 2, GFLAGS),
815 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
816 RK3399_CLKGATE_CON(16), 3, GFLAGS),
818 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
819 RK3399_CLKGATE_CON(16), 0, GFLAGS),
820 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
821 RK3399_CLKGATE_CON(16), 1, GFLAGS),
824 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
825 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
826 RK3399_CLKGATE_CON(4), 10, GFLAGS),
828 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
829 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
830 RK3399_CLKGATE_CON(4), 8, GFLAGS),
831 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
832 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
833 RK3399_CLKGATE_CON(4), 9, GFLAGS),
834 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
835 RK3399_CLKGATE_CON(16), 10, GFLAGS),
836 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
837 RK3399_CLKGATE_CON(16), 11, GFLAGS),
839 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
840 RK3399_CLKGATE_CON(16), 8, GFLAGS),
841 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
842 RK3399_CLKGATE_CON(16), 9, GFLAGS),
845 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
846 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
847 RK3399_CLKGATE_CON(3), 7, GFLAGS),
848 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
849 RK3399_CLKGATE_CON(19), 0, GFLAGS),
850 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
851 RK3399_CLKGATE_CON(19), 1, GFLAGS),
854 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
855 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
856 RK3399_CLKGATE_CON(13), 0, GFLAGS),
857 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
858 RK3399_CLKGATE_CON(30), 8, GFLAGS),
859 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
860 RK3399_CLKGATE_CON(30), 10, GFLAGS),
861 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
862 RK3399_CLKGATE_CON(30), 11, GFLAGS),
863 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
864 RK3399_CLKGATE_CON(13), 1, GFLAGS),
867 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
868 RK3399_CLKGATE_CON(5), 1, GFLAGS),
869 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
870 RK3399_CLKGATE_CON(5), 0, GFLAGS),
871 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
872 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
873 RK3399_CLKGATE_CON(5), 2, GFLAGS),
874 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
875 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
876 RK3399_CLKGATE_CON(5), 3, GFLAGS),
877 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
878 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
879 RK3399_CLKGATE_CON(5), 4, GFLAGS),
881 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
882 RK3399_CLKGATE_CON(20), 2, GFLAGS),
883 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
884 RK3399_CLKGATE_CON(20), 10, GFLAGS),
885 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
886 RK3399_CLKGATE_CON(20), 12, GFLAGS),
888 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
889 RK3399_CLKGATE_CON(20), 5, GFLAGS),
890 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
891 RK3399_CLKGATE_CON(20), 6, GFLAGS),
892 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
893 RK3399_CLKGATE_CON(20), 7, GFLAGS),
894 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
895 RK3399_CLKGATE_CON(20), 8, GFLAGS),
896 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
897 RK3399_CLKGATE_CON(20), 9, GFLAGS),
898 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
899 RK3399_CLKGATE_CON(20), 13, GFLAGS),
900 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
901 RK3399_CLKGATE_CON(20), 15, GFLAGS),
903 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
904 RK3399_CLKGATE_CON(20), 4, GFLAGS),
905 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
906 RK3399_CLKGATE_CON(20), 11, GFLAGS),
907 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
908 RK3399_CLKGATE_CON(20), 14, GFLAGS),
909 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
910 RK3399_CLKGATE_CON(31), 8, GFLAGS),
913 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
914 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
915 RK3399_CLKGATE_CON(12), 13, GFLAGS),
916 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
917 RK3399_CLKGATE_CON(33), 8, GFLAGS),
918 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
919 RK3399_CLKGATE_CON(33), 9, GFLAGS),
921 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
922 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
923 RK3399_CLKGATE_CON(6), 0, GFLAGS),
925 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
926 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
927 RK3399_CLKGATE_CON(6), 1, GFLAGS),
929 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
930 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
932 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
933 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
936 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
937 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
938 RK3399_CLKGATE_CON(6), 2, GFLAGS),
940 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
941 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
942 RK3399_CLKGATE_CON(12), 6, GFLAGS),
943 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
944 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
946 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
947 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
948 RK3399_CLKGATE_CON(6), 3, GFLAGS),
949 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
950 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
953 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
954 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
955 RK3399_CLKGATE_CON(6), 14, GFLAGS),
957 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
958 RK3399_CLKGATE_CON(6), 13, GFLAGS),
959 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
960 RK3399_CLKGATE_CON(6), 12, GFLAGS),
961 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
962 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
963 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
964 RK3399_CLKGATE_CON(32), 8, GFLAGS),
965 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
966 RK3399_CLKGATE_CON(32), 9, GFLAGS),
967 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
968 RK3399_CLKGATE_CON(32), 10, GFLAGS),
971 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
972 RK3399_CLKGATE_CON(7), 1, GFLAGS),
973 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
974 RK3399_CLKGATE_CON(7), 0, GFLAGS),
975 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
976 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
977 RK3399_CLKGATE_CON(7), 2, GFLAGS),
978 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
979 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
980 RK3399_CLKGATE_CON(7), 3, GFLAGS),
981 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
982 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
983 RK3399_CLKGATE_CON(7), 4, GFLAGS),
985 /* aclk_perilp0 gates */
986 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
987 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
988 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
989 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
990 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
991 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
992 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
993 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
994 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
995 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
996 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
997 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
999 /* hclk_perilp0 gates */
1000 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
1001 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
1002 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
1003 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
1004 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
1005 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
1007 /* pclk_perilp0 gates */
1008 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
1011 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
1012 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
1013 RK3399_CLKGATE_CON(7), 7, GFLAGS),
1015 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
1016 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
1017 RK3399_CLKGATE_CON(7), 8, GFLAGS),
1020 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
1021 RK3399_CLKGATE_CON(7), 6, GFLAGS),
1022 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
1023 RK3399_CLKGATE_CON(7), 5, GFLAGS),
1024 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1025 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
1026 RK3399_CLKGATE_CON(7), 9, GFLAGS),
1028 /* fclk_cm0s gates */
1029 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1030 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1031 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1032 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1033 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1036 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1037 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1038 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1039 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1040 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1041 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1042 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1043 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1044 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1046 /* hclk_perilp1 gates */
1047 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1048 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1049 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1050 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1051 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1052 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1053 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1054 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1055 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1057 /* pclk_perilp1 gates */
1058 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1059 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1060 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1061 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1062 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1063 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1064 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1065 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1066 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1067 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1068 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1069 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1070 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1071 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1072 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1073 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1074 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1075 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1076 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1077 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1078 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1081 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1082 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1083 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1086 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1087 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1088 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1091 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1092 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1093 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1094 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1095 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1097 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1098 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1099 COMPOSITE(SCLK_TESTOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1100 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1101 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1104 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1105 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1106 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1107 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
1108 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1109 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1111 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1112 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1114 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1115 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1116 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1117 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1118 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1119 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1122 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1123 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1124 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1125 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1126 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1127 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1128 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1129 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1130 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1132 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1133 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1134 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1135 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1137 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1138 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1139 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1140 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1142 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1143 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1144 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1145 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1146 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1147 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1148 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1149 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1150 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1151 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1154 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1155 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1156 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1158 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1159 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1160 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1161 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1162 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1163 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1164 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1167 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1168 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1170 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1171 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1172 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1175 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1176 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1177 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1178 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1179 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1180 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1182 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1183 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1184 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1185 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1187 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1188 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1189 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1190 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1192 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1193 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1194 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1196 /* The VOP0 is main screen, it is able to re-set parent rate. */
1197 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1198 RK3399_CLKSEL_CON(106), 0,
1199 &rk3399_dclk_vop0_fracmux),
1201 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1202 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1203 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1206 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1207 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1208 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1209 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1210 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1211 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1213 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1214 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1215 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1216 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1218 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1219 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1220 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1221 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1223 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1224 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
1225 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1226 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1228 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1229 RK3399_CLKSEL_CON(107), 0,
1230 &rk3399_dclk_vop1_fracmux),
1232 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1233 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1234 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1237 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1238 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1239 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1240 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1241 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1242 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1244 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1245 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1246 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1247 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1248 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1249 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1251 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1252 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1253 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1254 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1256 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1257 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1258 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1260 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1261 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1262 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1263 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1264 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1265 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1267 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1268 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1270 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1271 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1272 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1273 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1275 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1276 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1277 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1280 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1281 * so we ignore the mux and make clocks nodes as following,
1283 * pclkin_cifinv --|-------\
1284 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1285 * pclkin_cif --|-------/
1287 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1288 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1291 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1292 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1293 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1295 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1296 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1299 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1300 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1301 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1303 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1304 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1305 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1306 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1307 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1308 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1311 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1312 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1313 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1315 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1316 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1317 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1318 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1319 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1321 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1322 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1323 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1324 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1325 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1326 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1327 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1328 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1329 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1331 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1332 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1334 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1335 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1336 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1337 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1340 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1341 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1342 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1343 RK3399_CLKSEL_CON(105), 0,
1344 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1346 DIV(0, "clk_test_24m", "xin24m", 0,
1347 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1350 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1351 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1352 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1354 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1355 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1356 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1358 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1359 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1360 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1362 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1363 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1364 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1366 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1367 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1368 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1371 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1372 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1373 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1375 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1376 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1377 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1379 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1380 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1381 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1383 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1384 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1385 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1387 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1388 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1389 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1391 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1392 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1393 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1396 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1397 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1398 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1399 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1400 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1401 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1402 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1403 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1404 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1405 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1406 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1407 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1410 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1411 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1412 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1413 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1416 GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1418 GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1420 GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1422 GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1424 COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrclk_p, 0,
1425 RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1428 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1430 * PMU CRU Clock-Architecture
1433 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1434 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1436 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1437 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1439 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1440 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1441 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1443 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1444 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1445 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1447 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1448 RK3399_PMU_CLKSEL_CON(7), 0,
1449 &rk3399_pmuclk_wifi_fracmux),
1451 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1452 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1454 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1455 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1456 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1458 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1459 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1460 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1462 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1463 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1464 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1466 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1467 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1468 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1469 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1471 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1472 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1473 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1475 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1476 RK3399_PMU_CLKSEL_CON(6), 0,
1477 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1478 &rk3399_uart4_pmu_fracmux),
1480 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1481 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1483 /* pmu clock gates */
1484 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1485 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1487 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1489 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1490 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1491 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1492 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1493 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1494 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1495 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1496 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1497 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1498 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1499 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1500 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1501 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1502 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1503 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1504 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1506 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1507 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1508 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1509 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1510 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1513 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1515 * We need to declare that we enable all NOCs which are critical clocks
1516 * always and clearly and explicitly show that we have enabled them at
1522 "pclk_center_main_noc",
1534 "aclk_center_main_noc",
1535 "aclk_center_peri_noc",
1543 "hclk_m0_perilp_noc",
1546 "hclk_sdioaudio_noc",
1566 /* other critical clocks */
1576 "aclk_dmac1_perilp",
1577 "gpll_aclk_perilp0_src",
1578 "gpll_aclk_perihp_src",
1582 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1584 * We need to declare that we enable all NOCs which are critical clocks
1585 * always and clearly and explicitly show that we have enabled them at
1591 /* other critical clocks */
1594 "fclk_cm0s_src_pmu",
1595 "clk_timer_src_pmu",
1599 static void __iomem *rk3399_cru_base;
1600 static void __iomem *rk3399_pmucru_base;
1602 void rk3399_dump_cru(void)
1604 if (rk3399_cru_base) {
1606 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1607 32, 4, rk3399_cru_base,
1610 if (rk3399_pmucru_base) {
1611 pr_warn("PMU CRU:\n");
1612 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1613 32, 4, rk3399_pmucru_base,
1617 EXPORT_SYMBOL_GPL(rk3399_dump_cru);
1619 static int rk3399_clk_panic(struct notifier_block *this,
1620 unsigned long ev, void *ptr)
1626 static struct notifier_block rk3399_clk_panic_block = {
1627 .notifier_call = rk3399_clk_panic,
1630 static void __init rk3399_clk_init(struct device_node *np)
1632 struct rockchip_clk_provider *ctx;
1633 void __iomem *reg_base;
1636 reg_base = of_iomap(np, 0);
1638 pr_err("%s: could not map cru region\n", __func__);
1642 rk3399_cru_base = reg_base;
1644 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1646 pr_err("%s: rockchip clk init failed\n", __func__);
1650 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1651 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1653 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1654 __func__, PTR_ERR(clk));
1656 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1658 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1659 ARRAY_SIZE(rk3399_pll_clks), -1);
1661 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1662 ARRAY_SIZE(rk3399_clk_branches));
1664 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1665 ARRAY_SIZE(rk3399_cru_critical_clocks));
1667 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1668 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1669 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1670 ARRAY_SIZE(rk3399_cpuclkl_rates));
1672 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1673 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1674 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1675 ARRAY_SIZE(rk3399_cpuclkb_rates));
1677 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1678 ROCKCHIP_SOFTRST_HIWORD_MASK);
1680 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1682 rockchip_clk_of_add_provider(np, ctx);
1684 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1686 static void __init rk3399_pmu_clk_init(struct device_node *np)
1688 struct rockchip_clk_provider *ctx;
1689 void __iomem *reg_base;
1691 reg_base = of_iomap(np, 0);
1693 pr_err("%s: could not map cru pmu region\n", __func__);
1697 rk3399_pmucru_base = reg_base;
1699 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1701 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1705 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1706 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1708 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1709 ARRAY_SIZE(rk3399_clk_pmu_branches));
1711 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1712 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1714 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1715 ROCKCHIP_SOFTRST_HIWORD_MASK);
1717 rockchip_clk_of_add_provider(np, ctx);
1719 atomic_notifier_chain_register(&panic_notifier_list,
1720 &rk3399_clk_panic_block);
1722 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob