drivers/clk/rockchip/clk-rk3368.c

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/platform_device.h>
  19 #include <dt-bindings/clock/rk3368-cru.h>
  20 #include "clk.h"
  21
  22 #define RK3368_GRF_SOC_STATUS0  0x480
  23
  24 enum rk3368_plls {
  25         apllb, aplll, dpll, cpll, gpll, npll,
  26 };
  27
  28 static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
  29         RK3066_PLL_RATE(2208000000, 1, 92, 1),
  30         RK3066_PLL_RATE(2184000000, 1, 91, 1),
  31         RK3066_PLL_RATE(2160000000, 1, 90, 1),
  32         RK3066_PLL_RATE(2136000000, 1, 89, 1),
  33         RK3066_PLL_RATE(2112000000, 1, 88, 1),
  34         RK3066_PLL_RATE(2088000000, 1, 87, 1),
  35         RK3066_PLL_RATE(2064000000, 1, 86, 1),
  36         RK3066_PLL_RATE(2040000000, 1, 85, 1),
  37         RK3066_PLL_RATE(2016000000, 1, 84, 1),
  38         RK3066_PLL_RATE(1992000000, 1, 83, 1),
  39         RK3066_PLL_RATE(1968000000, 1, 82, 1),
  40         RK3066_PLL_RATE(1944000000, 1, 81, 1),
  41         RK3066_PLL_RATE(1920000000, 1, 80, 1),
  42         RK3066_PLL_RATE(1896000000, 1, 79, 1),
  43         RK3066_PLL_RATE(1872000000, 1, 78, 1),
  44         RK3066_PLL_RATE(1848000000, 1, 77, 1),
  45         RK3066_PLL_RATE(1824000000, 1, 76, 1),
  46         RK3066_PLL_RATE(1800000000, 1, 75, 1),
  47         RK3066_PLL_RATE(1776000000, 1, 74, 1),
  48         RK3066_PLL_RATE(1752000000, 1, 73, 1),
  49         RK3066_PLL_RATE(1728000000, 1, 72, 1),
  50         RK3066_PLL_RATE(1704000000, 1, 71, 1),
  51         RK3066_PLL_RATE(1680000000, 1, 70, 1),
  52         RK3066_PLL_RATE(1656000000, 1, 69, 1),
  53         RK3066_PLL_RATE(1632000000, 1, 68, 1),
  54         RK3066_PLL_RATE(1608000000, 1, 67, 1),
  55         RK3066_PLL_RATE(1560000000, 1, 65, 1),
  56         RK3066_PLL_RATE(1512000000, 1, 63, 1),
  57         RK3066_PLL_RATE(1488000000, 1, 62, 1),
  58         RK3066_PLL_RATE(1464000000, 1, 61, 1),
  59         RK3066_PLL_RATE(1440000000, 1, 60, 1),
  60         RK3066_PLL_RATE(1416000000, 1, 59, 1),
  61         RK3066_PLL_RATE(1392000000, 1, 58, 1),
  62         RK3066_PLL_RATE(1368000000, 1, 57, 1),
  63         RK3066_PLL_RATE(1344000000, 1, 56, 1),
  64         RK3066_PLL_RATE(1320000000, 1, 55, 1),
  65         RK3066_PLL_RATE(1296000000, 1, 54, 1),
  66         RK3066_PLL_RATE(1272000000, 1, 53, 1),
  67         RK3066_PLL_RATE(1248000000, 1, 52, 1),
  68         RK3066_PLL_RATE(1224000000, 1, 51, 1),
  69         RK3066_PLL_RATE(1200000000, 1, 50, 1),
  70         RK3066_PLL_RATE(1188000000, 2, 99, 1),
  71         RK3066_PLL_RATE(1176000000, 1, 49, 1),
  72         RK3066_PLL_RATE(1128000000, 1, 47, 1),
  73         RK3066_PLL_RATE(1104000000, 1, 46, 1),
  74         RK3066_PLL_RATE(1008000000, 1, 84, 2),
  75         RK3066_PLL_RATE( 912000000, 1, 76, 2),
  76         RK3066_PLL_RATE( 888000000, 1, 74, 2),
  77         RK3066_PLL_RATE( 816000000, 1, 68, 2),
  78         RK3066_PLL_RATE( 792000000, 1, 66, 2),
  79         RK3066_PLL_RATE( 696000000, 1, 58, 2),
  80         RK3066_PLL_RATE( 672000000, 1, 56, 2),
  81         RK3066_PLL_RATE( 648000000, 1, 54, 2),
  82         RK3066_PLL_RATE( 624000000, 1, 52, 2),
  83         RK3066_PLL_RATE( 600000000, 1, 50, 2),
  84         RK3066_PLL_RATE( 576000000, 1, 48, 2),
  85         RK3066_PLL_RATE( 552000000, 1, 46, 2),
  86         RK3066_PLL_RATE( 528000000, 1, 88, 4),
  87         RK3066_PLL_RATE( 504000000, 1, 84, 4),
  88         RK3066_PLL_RATE( 480000000, 1, 80, 4),
  89         RK3066_PLL_RATE( 456000000, 1, 76, 4),
  90         RK3066_PLL_RATE( 408000000, 1, 68, 4),
  91         RK3066_PLL_RATE( 312000000, 1, 52, 4),
  92         RK3066_PLL_RATE( 252000000, 1, 84, 8),
  93         RK3066_PLL_RATE( 216000000, 1, 72, 8),
  94         RK3066_PLL_RATE( 126000000, 2, 84, 8),
  95         RK3066_PLL_RATE(  48000000, 2, 32, 8),
  96         { /* sentinel */ },
  97 };
  98
  99 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
 100 PNAME(mux_armclkb_p)            = { "apllb_core", "gpllb_core" };
 101 PNAME(mux_armclkl_p)            = { "aplll_core", "gplll_core" };
 102 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 103 PNAME(mux_cs_src_p)             = { "apllb_cs", "aplll_cs", "gpll_cs"};
 104 PNAME(mux_aclk_bus_src_p)       = { "cpll_aclk_bus", "gpll_aclk_bus" };
 105
 106 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 107 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
 108 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 109 PNAME(mux_pll_src_cpll_gpll_usb_p)      = { "cpll", "gpll", "usbphy_480m" };
 110 PNAME(mux_pll_src_cpll_gpll_usb_usb_p)  = { "cpll", "gpll", "usbphy_480m",
 111                                             "usbphy_480m" };
 112 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
 113                                             "npll" };
 114 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
 115 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
 116                                             "usbphy_480m" };
 117
 118 PNAME(mux_i2s_8ch_pre_p)        = { "i2s_8ch_src", "i2s_8ch_frac",
 119                                     "ext_i2s", "xin12m" };
 120 PNAME(mux_i2s_8ch_clkout_p)     = { "i2s_8ch_pre", "xin12m" };
 121 PNAME(mux_i2s_2ch_p)            = { "i2s_2ch_src", "i2s_2ch_frac",
 122                                     "dummy", "xin12m" };
 123 PNAME(mux_spdif_8ch_p)          = { "spdif_8ch_pre", "spdif_8ch_frac",
 124                                     "ext_i2s", "xin12m" };
 125 PNAME(mux_edp_24m_p)            = { "xin24m", "dummy" };
 126 PNAME(mux_vip_out_p)            = { "vip_src", "xin24m" };
 127 PNAME(mux_usbphy480m_p)         = { "usbotg_out", "xin24m" };
 128 PNAME(mux_hsic_usbphy480m_p)    = { "usbotg_out", "dummy" };
 129 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy_480m" };
 130 PNAME(mux_uart0_p)              = { "uart0_src", "uart0_frac", "xin24m" };
 131 PNAME(mux_uart1_p)              = { "uart1_src", "uart1_frac", "xin24m" };
 132 PNAME(mux_uart2_p)              = { "uart2_src", "xin24m" };
 133 PNAME(mux_uart3_p)              = { "uart3_src", "uart3_frac", "xin24m" };
 134 PNAME(mux_uart4_p)              = { "uart4_src", "uart4_frac", "xin24m" };
 135 PNAME(mux_mac_p)                = { "mac_pll_src", "ext_gmac" };
 136 PNAME(mux_mmc_src_p)            = { "cpll", "gpll", "usbphy_480m", "xin24m" };
 137
 138 static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
 139         [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
 140                      RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
 141         [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
 142                      RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
 143         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
 144                      RK3368_PLL_CON(11), 8, 2, 0, NULL),
 145         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
 146                      RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
 147         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
 148                      RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
 149         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3368_PLL_CON(20),
 150                      RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
 151 };
 152
 153 static struct clk_div_table div_ddrphy_t[] = {
 154         { .val = 0, .div = 1 },
 155         { .val = 1, .div = 2 },
 156         { .val = 3, .div = 4 },
 157         { /* sentinel */ },
 158 };
 159
 160 #define MFLAGS CLK_MUX_HIWORD_MASK
 161 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 162 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 163 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 164
 165 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
 166         .core_reg = RK3368_CLKSEL_CON(0),
 167         .div_core_shift = 0,
 168         .div_core_mask = 0x1f,
 169         .mux_core_alt = 1,
 170         .mux_core_main = 0,
 171         .mux_core_shift = 7,
 172         .mux_core_mask = 0x1,
 173 };
 174
 175 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
 176         .core_reg = RK3368_CLKSEL_CON(2),
 177         .div_core_shift = 0,
 178         .mux_core_alt = 1,
 179         .mux_core_main = 0,
 180         .div_core_mask = 0x1f,
 181         .mux_core_shift = 7,
 182         .mux_core_mask = 0x1,
 183 };
 184
 185 #define RK3368_DIV_ACLKM_MASK           0x1f
 186 #define RK3368_DIV_ACLKM_SHIFT          8
 187 #define RK3368_DIV_ATCLK_MASK           0x1f
 188 #define RK3368_DIV_ATCLK_SHIFT          0
 189 #define RK3368_DIV_PCLK_DBG_MASK        0x1f
 190 #define RK3368_DIV_PCLK_DBG_SHIFT       8
 191
 192 #define RK3368_CLKSEL0(_offs, _aclkm)                                   \
 193         {                                                               \
 194                 .reg = RK3368_CLKSEL_CON(0 + _offs),                    \
 195                 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK,     \
 196                                 RK3368_DIV_ACLKM_SHIFT),                \
 197         }
 198 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg)                            \
 199         {                                                               \
 200                 .reg = RK3368_CLKSEL_CON(1 + _offs),                    \
 201                 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK,     \
 202                                 RK3368_DIV_ATCLK_SHIFT) |               \
 203                        HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,   \
 204                                 RK3368_DIV_PCLK_DBG_SHIFT),             \
 205         }
 206
 207 /* cluster_b: aclkm in clksel0, rest in clksel1 */
 208 #define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 209         {                                                               \
 210                 .prate = _prate,                                        \
 211                 .divs = {                                               \
 212                         RK3368_CLKSEL0(0, _aclkm),                      \
 213                         RK3368_CLKSEL1(0, _atclk, _pdbg),               \
 214                 },                                                      \
 215         }
 216
 217 /* cluster_l: aclkm in clksel2, rest in clksel3 */
 218 #define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 219         {                                                               \
 220                 .prate = _prate,                                        \
 221                 .divs = {                                               \
 222                         RK3368_CLKSEL0(2, _aclkm),                      \
 223                         RK3368_CLKSEL1(2, _atclk, _pdbg),               \
 224                 },                                                      \
 225         }
 226
 227 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
 228         RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
 229         RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
 230         RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
 231         RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
 232         RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
 233         RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
 234         RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
 235         RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
 236         RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
 237         RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
 238 };
 239
 240 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
 241         RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
 242         RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
 243         RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
 244         RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
 245         RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
 246         RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
 247         RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
 248         RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
 249         RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
 250         RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
 251 };
 252
 253 static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
 254         MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
 255             RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
 256
 257 static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
 258         MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 259             RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
 260
 261 static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
 262         MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
 263             RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
 264
 265 static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
 266         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 267             RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
 268
 269 static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
 270         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 271             RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
 272
 273 static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
 274         MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 275             RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
 276
 277 static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
 278         MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
 279             RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
 280
 281 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 282         /*
 283          * Clock-Architecture Diagram 2
 284          */
 285
 286         MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
 287                         RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
 288
 289         GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
 290                         RK3368_CLKGATE_CON(0), 0, GFLAGS),
 291         GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
 292                         RK3368_CLKGATE_CON(0), 1, GFLAGS),
 293
 294         GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
 295                         RK3368_CLKGATE_CON(0), 4, GFLAGS),
 296         GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
 297                         RK3368_CLKGATE_CON(0), 5, GFLAGS),
 298
 299         DIV(0, "aclkm_core_b", "armclkb", 0,
 300                         RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 301         DIV(0, "atclk_core_b", "armclkb", 0,
 302                         RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 303         DIV(0, "pclk_dbg_b", "armclkb", 0,
 304                         RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 305
 306         DIV(0, "aclkm_core_l", "armclkl", 0,
 307                         RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 308         DIV(0, "atclk_core_l", "armclkl", 0,
 309                         RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 310         DIV(0, "pclk_dbg_l", "armclkl", 0,
 311                         RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 312
 313         GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
 314                         RK3368_CLKGATE_CON(0), 9, GFLAGS),
 315         GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
 316                         RK3368_CLKGATE_CON(0), 10, GFLAGS),
 317         GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
 318                         RK3368_CLKGATE_CON(0), 8, GFLAGS),
 319         COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
 320                         RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
 321         COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
 322                         RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
 323                         RK3368_CLKGATE_CON(0), 13, GFLAGS),
 324
 325         COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
 326                         RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
 327                         RK3368_CLKGATE_CON(0), 12, GFLAGS),
 328         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
 329
 330         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 331                         RK3368_CLKGATE_CON(1), 8, GFLAGS),
 332         GATE(0, "gpll_ddr", "gpll", 0,
 333                         RK3368_CLKGATE_CON(1), 9, GFLAGS),
 334         COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 335                         RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
 336
 337         GATE(0, "sclk_ddr", "ddrphy_div4", CLK_IGNORE_UNUSED,
 338                         RK3368_CLKGATE_CON(6), 14, GFLAGS),
 339         GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
 340                         RK3368_CLKGATE_CON(6), 15, GFLAGS),
 341
 342         GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
 343                         RK3368_CLKGATE_CON(1), 10, GFLAGS),
 344         GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
 345                         RK3368_CLKGATE_CON(1), 11, GFLAGS),
 346         COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
 347                         RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
 348
 349         GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 350                         RK3368_CLKGATE_CON(1), 0, GFLAGS),
 351         COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 352                         RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
 353                         RK3368_CLKGATE_CON(1), 2, GFLAGS),
 354         COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 355                         RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
 356                         RK3368_CLKGATE_CON(1), 1, GFLAGS),
 357         COMPOSITE_NOMUX(SCLK_CRYPTO, "sclk_crypto", "aclk_bus_src", 0,
 358                         RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
 359                         RK3368_CLKGATE_CON(7), 2, GFLAGS),
 360
 361         COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 362                         RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
 363                         RK3368_CLKGATE_CON(1), 3, GFLAGS),
 364         /*
 365          * stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
 366          * but stclk_mcu has an additional own divider in diagram 2
 367          */
 368         COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", 0,
 369                         RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
 370                         RK3368_CLKGATE_CON(13), 13, GFLAGS),
 371
 372         COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
 373                         RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
 374                         RK3368_CLKGATE_CON(6), 1, GFLAGS),
 375         COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
 376                           RK3368_CLKSEL_CON(28), 0,
 377                           RK3368_CLKGATE_CON(6), 2, GFLAGS,
 378                           &rk3368_i2s_8ch_fracmux),
 379         COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
 380                         RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
 381                         RK3368_CLKGATE_CON(6), 0, GFLAGS),
 382         GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
 383                         RK3368_CLKGATE_CON(6), 3, GFLAGS),
 384         COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
 385                         RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
 386                         RK3368_CLKGATE_CON(6), 4, GFLAGS),
 387         COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
 388                           RK3368_CLKSEL_CON(32), 0,
 389                           RK3368_CLKGATE_CON(6), 5, GFLAGS,
 390                           &rk3368_spdif_8ch_fracmux),
 391         GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 392              RK3368_CLKGATE_CON(6), 6, GFLAGS),
 393         COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
 394                         RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
 395                         RK3368_CLKGATE_CON(5), 13, GFLAGS),
 396         COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
 397                           RK3368_CLKSEL_CON(54), 0,
 398                           RK3368_CLKGATE_CON(5), 14, GFLAGS,
 399                           &rk3368_i2s_2ch_fracmux),
 400         GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
 401              RK3368_CLKGATE_CON(5), 15, GFLAGS),
 402
 403         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
 404                         RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
 405                         RK3368_CLKGATE_CON(6), 12, GFLAGS),
 406         GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
 407                         RK3368_CLKGATE_CON(13), 7, GFLAGS),
 408
 409         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 410                         RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
 411         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 412                         RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
 413                         RK3368_CLKGATE_CON(2), 4, GFLAGS),
 414         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 415                         RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
 416
 417         /*
 418          * Clock-Architecture Diagram 3
 419          */
 420
 421         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 422                         RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
 423                         RK3368_CLKGATE_CON(4), 6, GFLAGS),
 424         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 425                         RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
 426                         RK3368_CLKGATE_CON(4), 7, GFLAGS),
 427
 428         /*
 429          * We introduce a virtual node of hclk_vodec_pre_v to split one clock
 430          * struct with a gate and a fix divider into two node in software.
 431          */
 432         GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
 433                 RK3368_CLKGATE_CON(4), 8, GFLAGS),
 434
 435         COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 436                         RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
 437                         RK3368_CLKGATE_CON(5), 1, GFLAGS),
 438         COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 439                         RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
 440                         RK3368_CLKGATE_CON(5), 2, GFLAGS),
 441
 442         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
 443                         RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
 444                         RK3368_CLKGATE_CON(4), 0, GFLAGS),
 445         DIV(0, "hclk_vio", "aclk_vio0", 0,
 446                         RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
 447
 448         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
 449                         RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
 450                         RK3368_CLKGATE_CON(4), 3, GFLAGS),
 451         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
 452                         RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
 453                         RK3368_CLKGATE_CON(4), 4, GFLAGS),
 454
 455         COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
 456                         RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
 457                         RK3368_CLKGATE_CON(4), 1, GFLAGS),
 458
 459         GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
 460                         RK3368_CLKGATE_CON(4), 2, GFLAGS),
 461
 462         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
 463                         RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
 464                         RK3368_CLKGATE_CON(4), 9, GFLAGS),
 465
 466         GATE(0, "pclk_isp_in", "ext_isp", 0,
 467                         RK3368_CLKGATE_CON(17), 2, GFLAGS),
 468         INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
 469                         RK3368_CLKSEL_CON(21), 6, IFLAGS),
 470
 471         GATE(0, "pclk_vip_in", "ext_vip", 0,
 472                         RK3368_CLKGATE_CON(16), 13, GFLAGS),
 473         INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
 474                         RK3368_CLKSEL_CON(21), 13, IFLAGS),
 475
 476         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 477                         RK3368_CLKGATE_CON(4), 13, GFLAGS),
 478         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 479                         RK3368_CLKGATE_CON(4), 12, GFLAGS),
 480
 481         COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 482                         RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
 483                         RK3368_CLKGATE_CON(4), 5, GFLAGS),
 484         COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
 485                         RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
 486
 487         COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
 488                         RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
 489                         RK3368_CLKGATE_CON(5), 4, GFLAGS),
 490         COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
 491                         RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
 492                         RK3368_CLKGATE_CON(5), 3, GFLAGS),
 493
 494         COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
 495                         RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
 496                         RK3368_CLKGATE_CON(5), 5, GFLAGS),
 497
 498         DIV(0, "pclk_pd_alive", "gpll", 0,
 499                         RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
 500
 501         /* sclk_timer has a gate in the sgrf */
 502
 503         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
 504                         RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
 505                         RK3368_CLKGATE_CON(7), 9, GFLAGS),
 506         GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
 507                         RK3368_CLKGATE_CON(7), 3, GFLAGS),
 508         COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
 509                         RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
 510                         RK3368_CLKGATE_CON(4), 11, GFLAGS),
 511         MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
 512                         RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
 513         COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
 514                         RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
 515                         RK3368_CLKGATE_CON(5), 8, GFLAGS),
 516         COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
 517                         RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
 518                         RK3368_CLKGATE_CON(5), 9, GFLAGS),
 519         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
 520                         RK3368_CLKGATE_CON(7), 11, GFLAGS),
 521
 522         COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 523                         RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
 524                         RK3368_CLKGATE_CON(3), 0, GFLAGS),
 525         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
 526                         RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 527                         RK3368_CLKGATE_CON(3), 3, GFLAGS),
 528         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 529                         RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 530                         RK3368_CLKGATE_CON(3), 2, GFLAGS),
 531         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 532                         RK3368_CLKGATE_CON(3), 1, GFLAGS),
 533
 534         GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
 535
 536         /*
 537          * Clock-Architecture Diagram 4
 538          */
 539
 540         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 541                         RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
 542                         RK3368_CLKGATE_CON(3), 7, GFLAGS),
 543         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 544                         RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
 545                         RK3368_CLKGATE_CON(3), 8, GFLAGS),
 546         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 547                         RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
 548                         RK3368_CLKGATE_CON(3), 9, GFLAGS),
 549
 550
 551         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 552                         RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
 553                         RK3368_CLKGATE_CON(7), 12, GFLAGS),
 554         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 555                         RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
 556                         RK3368_CLKGATE_CON(7), 13, GFLAGS),
 557         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 558                         RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
 559                         RK3368_CLKGATE_CON(7), 15, GFLAGS),
 560
 561         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
 562         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
 563
 564         MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3368_SDIO0_CON0, 1),
 565         MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
 566
 567         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3368_EMMC_CON0,  1),
 568         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3368_EMMC_CON1,  0),
 569
 570         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
 571                         RK3368_CLKGATE_CON(8), 1, GFLAGS),
 572
 573         /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
 574         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
 575                         RK3368_CLKGATE_CON(8), 4, GFLAGS),
 576
 577         /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
 578         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
 579                         RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
 580                         RK3368_CLKGATE_CON(3), 5, GFLAGS),
 581
 582         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 583                         RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
 584                         RK3368_CLKGATE_CON(3), 6, GFLAGS),
 585
 586         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 587                         RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
 588                         RK3368_CLKGATE_CON(7), 8, GFLAGS),
 589
 590         COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
 591                         RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
 592                         RK3368_CLKGATE_CON(6), 7, GFLAGS),
 593
 594         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
 595                         RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
 596                         RK3368_CLKGATE_CON(2), 0, GFLAGS),
 597         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 598                           RK3368_CLKSEL_CON(34), 0,
 599                           RK3368_CLKGATE_CON(2), 1, GFLAGS,
 600                           &rk3368_uart0_fracmux),
 601
 602         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
 603                         RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
 604                         RK3368_CLKGATE_CON(2), 2, GFLAGS),
 605         COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
 606                           RK3368_CLKSEL_CON(36), 0,
 607                           RK3368_CLKGATE_CON(2), 3, GFLAGS,
 608                           &rk3368_uart1_fracmux),
 609
 610         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 611                         RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
 612                         RK3368_CLKGATE_CON(2), 6, GFLAGS),
 613         COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
 614                           RK3368_CLKSEL_CON(40), 0,
 615                           RK3368_CLKGATE_CON(2), 7, GFLAGS,
 616                           &rk3368_uart3_fracmux),
 617
 618         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
 619                         RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
 620                         RK3368_CLKGATE_CON(2), 8, GFLAGS),
 621         COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
 622                           RK3368_CLKSEL_CON(42), 0,
 623                           RK3368_CLKGATE_CON(2), 9, GFLAGS,
 624                           &rk3368_uart4_fracmux),
 625
 626         COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
 627                         RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
 628                         RK3368_CLKGATE_CON(3), 4, GFLAGS),
 629         MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
 630                         RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
 631         GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
 632                         RK3368_CLKGATE_CON(7), 7, GFLAGS),
 633         GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
 634                         RK3368_CLKGATE_CON(7), 6, GFLAGS),
 635         GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
 636                         RK3368_CLKGATE_CON(7), 4, GFLAGS),
 637         GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 638                         RK3368_CLKGATE_CON(7), 5, GFLAGS),
 639
 640         GATE(0, "jtag", "ext_jtag", 0,
 641                         RK3368_CLKGATE_CON(7), 0, GFLAGS),
 642
 643         COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
 644                         RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
 645                         RK3368_CLKGATE_CON(8), 0, GFLAGS),
 646         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 647                         RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
 648                         RK3368_CLKGATE_CON(8), 7, GFLAGS),
 649         GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
 650                         RK3368_CLKGATE_CON(8), 6, GFLAGS),
 651
 652         /*
 653          * Clock-Architecture Diagram 5
 654          */
 655
 656         /* aclk_cci_pre gates */
 657         GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
 658         GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
 659         GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
 660         GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
 661         GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
 662
 663         /* aclkm_core_* gates */
 664         GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
 665         GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
 666
 667         /* armclk* gates */
 668         GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
 669         GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
 670
 671         /* sclk_cs_pre gates */
 672         GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
 673         GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
 674         GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
 675
 676         /* aclk_bus gates */
 677         GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
 678         GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
 679         GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
 680         GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
 681         GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
 682         GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
 683
 684         /* sclk_ddr gates */
 685         GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
 686
 687         /* clk_hsadc_tsp is part of diagram2 */
 688
 689         /* fclk_mcu_src gates */
 690         GATE(0, "hclk_noc_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 14, GFLAGS),
 691         GATE(0, "fclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 12, GFLAGS),
 692         GATE(0, "hclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 11, GFLAGS),
 693
 694         /* hclk_cpu gates */
 695         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
 696         GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
 697         GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
 698         GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
 699         GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
 700         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
 701         GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
 702
 703         /* pclk_cpu gates */
 704         GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
 705         GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
 706         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
 707         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
 708         GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
 709         GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
 710         GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
 711         GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
 712         GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
 713         GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
 714         GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
 715
 716         /*
 717          * video clk gates
 718          * aclk_video(_pre) can actually select between parents of aclk_vdpu
 719          * and aclk_vepu by setting bit GRF_SOC_CON0[7].
 720          */
 721         GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
 722         GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
 723         GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
 724         GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
 725
 726         /* aclk_rga_pre gates */
 727         GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
 728         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
 729         GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
 730
 731         /* aclk_vio0 gates */
 732         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
 733         GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
 734         GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
 735         GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
 736         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
 737
 738         /* sclk_isp gates */
 739         GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
 740         GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
 741
 742         /* hclk_vio gates */
 743         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
 744         GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
 745         GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
 746         GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
 747         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
 748         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
 749         GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
 750         GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
 751
 752         /*
 753          * pclk_vio gates
 754          * pclk_vio comes from the exactly same source as hclk_vio
 755          */
 756         GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
 757         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
 758         GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
 759         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
 760         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
 761         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
 762
 763         /* ext_vip gates in diagram3 */
 764
 765         /* gpu gates */
 766         GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
 767         GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
 768         GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
 769
 770         /* aclk_peri gates */
 771         GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
 772         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
 773         GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
 774         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
 775         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
 776         GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
 777
 778         /* hclk_peri gates */
 779         GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
 780         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
 781         GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
 782         GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
 783         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
 784         GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 6, GFLAGS),
 785         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
 786         GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
 787         GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
 788         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
 789         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 1, GFLAGS),
 790         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
 791         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
 792         GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
 793         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
 794
 795         /* pclk_peri gates */
 796         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
 797         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
 798         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
 799         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
 800         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
 801         GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
 802         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
 803         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
 804         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
 805         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
 806         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
 807         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
 808         GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
 809         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
 810         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
 811
 812         /* pclk_pd_alive gates */
 813         GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
 814         GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
 815         GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
 816         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
 817         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
 818         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
 819         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
 820
 821         /*
 822          * pclk_vio gates
 823          * pclk_vio comes from the exactly same source as hclk_vio
 824          */
 825         GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
 826         GATE(PCLK_DPHYTX0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
 827
 828         /* pclk_pd_pmu gates */
 829         GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
 830         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
 831         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
 832         GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
 833         GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
 834         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
 835
 836         /* timer gates */
 837         GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
 838         GATE(0, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
 839         GATE(0, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
 840         GATE(0, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
 841         GATE(0, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
 842         GATE(0, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
 843         GATE(0, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
 844         GATE(0, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
 845         GATE(0, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
 846         GATE(0, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
 847         GATE(0, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
 848         GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
 849 };
 850
 851 static const char *const rk3368_critical_clocks[] __initconst = {
 852         "aclk_bus",
 853         "aclk_peri",
 854         "pclk_pd_pmu",
 855 };
 856
 857 static void __init rk3368_clk_init(struct device_node *np)
 858 {
 859         struct rockchip_clk_provider *ctx;
 860         void __iomem *reg_base;
 861         struct clk *clk;
 862
 863         reg_base = of_iomap(np, 0);
 864         if (!reg_base) {
 865                 pr_err("%s: could not map cru region\n", __func__);
 866                 return;
 867         }
 868
 869         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 870         if (IS_ERR(ctx)) {
 871                 pr_err("%s: rockchip clk init failed\n", __func__);
 872                 iounmap(reg_base);
 873                 return;
 874         }
 875
 876         /* xin12m is created by a cru-internal divider */
 877         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 878         if (IS_ERR(clk))
 879                 pr_warn("%s: could not register clock xin12m: %ld\n",
 880                         __func__, PTR_ERR(clk));
 881
 882         /* ddrphy_div4 is created by a cru-internal divider */
 883         clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
 884         if (IS_ERR(clk))
 885                 pr_warn("%s: could not register clock xin12m: %ld\n",
 886                         __func__, PTR_ERR(clk));
 887
 888         clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
 889                                         "hclk_video_pre_v", 0, 1, 4);
 890         if (IS_ERR(clk))
 891                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 892                         __func__, PTR_ERR(clk));
 893
 894         /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
 895         clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
 896         if (IS_ERR(clk))
 897                 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
 898                         __func__, PTR_ERR(clk));
 899         else
 900                 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
 901
 902         rockchip_clk_register_plls(ctx, rk3368_pll_clks,
 903                                    ARRAY_SIZE(rk3368_pll_clks),
 904                                    RK3368_GRF_SOC_STATUS0);
 905         rockchip_clk_register_branches(ctx, rk3368_clk_branches,
 906                                   ARRAY_SIZE(rk3368_clk_branches));
 907         rockchip_clk_protect_critical(rk3368_critical_clocks,
 908                                       ARRAY_SIZE(rk3368_critical_clocks));
 909
 910         rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
 911                         mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
 912                         &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
 913                         ARRAY_SIZE(rk3368_cpuclkb_rates));
 914
 915         rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
 916                         mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
 917                         &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
 918                         ARRAY_SIZE(rk3368_cpuclkl_rates));
 919
 920         rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
 921                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 922
 923         rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
 924
 925         rockchip_clk_of_add_provider(np, ctx);
 926 }
 927 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);