2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk-provider.h>
17 #include <linux/of_address.h>
18 #include <linux/platform_device.h>
19 #include <dt-bindings/clock/rk3368-cru.h>
22 #define RK3368_GRF_SOC_STATUS0 0x480
25 apllb, aplll, dpll, cpll, gpll, npll,
28 static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
29 RK3066_PLL_RATE(2208000000, 1, 92, 1),
30 RK3066_PLL_RATE(2184000000, 1, 91, 1),
31 RK3066_PLL_RATE(2160000000, 1, 90, 1),
32 RK3066_PLL_RATE(2136000000, 1, 89, 1),
33 RK3066_PLL_RATE(2112000000, 1, 88, 1),
34 RK3066_PLL_RATE(2088000000, 1, 87, 1),
35 RK3066_PLL_RATE(2064000000, 1, 86, 1),
36 RK3066_PLL_RATE(2040000000, 1, 85, 1),
37 RK3066_PLL_RATE(2016000000, 1, 84, 1),
38 RK3066_PLL_RATE(1992000000, 1, 83, 1),
39 RK3066_PLL_RATE(1968000000, 1, 82, 1),
40 RK3066_PLL_RATE(1944000000, 1, 81, 1),
41 RK3066_PLL_RATE(1920000000, 1, 80, 1),
42 RK3066_PLL_RATE(1896000000, 1, 79, 1),
43 RK3066_PLL_RATE(1872000000, 1, 78, 1),
44 RK3066_PLL_RATE(1848000000, 1, 77, 1),
45 RK3066_PLL_RATE(1824000000, 1, 76, 1),
46 RK3066_PLL_RATE(1800000000, 1, 75, 1),
47 RK3066_PLL_RATE(1776000000, 1, 74, 1),
48 RK3066_PLL_RATE(1752000000, 1, 73, 1),
49 RK3066_PLL_RATE(1728000000, 1, 72, 1),
50 RK3066_PLL_RATE(1704000000, 1, 71, 1),
51 RK3066_PLL_RATE(1680000000, 1, 70, 1),
52 RK3066_PLL_RATE(1656000000, 1, 69, 1),
53 RK3066_PLL_RATE(1632000000, 1, 68, 1),
54 RK3066_PLL_RATE(1608000000, 1, 67, 1),
55 RK3066_PLL_RATE(1560000000, 1, 65, 1),
56 RK3066_PLL_RATE(1512000000, 1, 63, 1),
57 RK3066_PLL_RATE(1488000000, 1, 62, 1),
58 RK3066_PLL_RATE(1464000000, 1, 61, 1),
59 RK3066_PLL_RATE(1440000000, 1, 60, 1),
60 RK3066_PLL_RATE(1416000000, 1, 59, 1),
61 RK3066_PLL_RATE(1392000000, 1, 58, 1),
62 RK3066_PLL_RATE(1368000000, 1, 57, 1),
63 RK3066_PLL_RATE(1344000000, 1, 56, 1),
64 RK3066_PLL_RATE(1320000000, 1, 55, 1),
65 RK3066_PLL_RATE(1296000000, 1, 54, 1),
66 RK3066_PLL_RATE(1272000000, 1, 53, 1),
67 RK3066_PLL_RATE(1248000000, 1, 52, 1),
68 RK3066_PLL_RATE(1224000000, 1, 51, 1),
69 RK3066_PLL_RATE(1200000000, 1, 50, 1),
70 RK3066_PLL_RATE(1188000000, 2, 99, 1),
71 RK3066_PLL_RATE(1176000000, 1, 49, 1),
72 RK3066_PLL_RATE(1128000000, 1, 47, 1),
73 RK3066_PLL_RATE(1104000000, 1, 46, 1),
74 RK3066_PLL_RATE(1008000000, 1, 84, 2),
75 RK3066_PLL_RATE( 912000000, 1, 76, 2),
76 RK3066_PLL_RATE( 888000000, 1, 74, 2),
77 RK3066_PLL_RATE( 816000000, 1, 68, 2),
78 RK3066_PLL_RATE( 792000000, 1, 66, 2),
79 RK3066_PLL_RATE( 696000000, 1, 58, 2),
80 RK3066_PLL_RATE( 672000000, 1, 56, 2),
81 RK3066_PLL_RATE( 648000000, 1, 54, 2),
82 RK3066_PLL_RATE( 624000000, 1, 52, 2),
83 RK3066_PLL_RATE( 600000000, 1, 50, 2),
84 RK3066_PLL_RATE( 576000000, 1, 48, 2),
85 RK3066_PLL_RATE( 552000000, 1, 46, 2),
86 RK3066_PLL_RATE( 528000000, 1, 88, 4),
87 RK3066_PLL_RATE( 504000000, 1, 84, 4),
88 RK3066_PLL_RATE( 480000000, 1, 80, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 312000000, 1, 52, 4),
92 RK3066_PLL_RATE( 252000000, 1, 84, 8),
93 RK3066_PLL_RATE( 216000000, 1, 72, 8),
94 RK3066_PLL_RATE( 126000000, 2, 84, 8),
95 RK3066_PLL_RATE( 48000000, 2, 32, 8),
99 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
100 PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
101 PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
102 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
103 PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
104 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
106 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
107 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
108 PNAME(mux_pll_src_dmycpll_dmygpll_npll_p) = { "dummy_cpll", "dummy_gpll", "npll" };
109 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
110 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
111 PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
113 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
115 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
116 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
119 PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac",
120 "ext_i2s", "xin12m" };
121 PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
122 PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
124 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
125 "ext_i2s", "xin12m" };
126 PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
127 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
128 PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
129 PNAME(mux_hsic_usbphy480m_p) = { "usbotg_out", "dummy" };
130 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
131 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
132 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
133 PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
134 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
135 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
136 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
137 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
139 static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
140 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
141 RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
142 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
143 RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
144 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
145 RK3368_PLL_CON(11), 8, 2, 0, NULL),
146 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
147 RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
148 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
149 RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
150 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
151 RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates),
154 static struct clk_div_table div_ddrphy_t[] = {
155 { .val = 0, .div = 1 },
156 { .val = 1, .div = 2 },
157 { .val = 3, .div = 4 },
161 #define MFLAGS CLK_MUX_HIWORD_MASK
162 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
163 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
164 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
166 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
167 .core_reg = RK3368_CLKSEL_CON(0),
169 .div_core_mask = 0x1f,
173 .mux_core_mask = 0x1,
176 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
177 .core_reg = RK3368_CLKSEL_CON(2),
181 .div_core_mask = 0x1f,
183 .mux_core_mask = 0x1,
186 #define RK3368_DIV_ACLKM_MASK 0x1f
187 #define RK3368_DIV_ACLKM_SHIFT 8
188 #define RK3368_DIV_ATCLK_MASK 0x1f
189 #define RK3368_DIV_ATCLK_SHIFT 0
190 #define RK3368_DIV_PCLK_DBG_MASK 0x1f
191 #define RK3368_DIV_PCLK_DBG_SHIFT 8
193 #define RK3368_CLKSEL0(_offs, _aclkm) \
195 .reg = RK3368_CLKSEL_CON(0 + _offs), \
196 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
197 RK3368_DIV_ACLKM_SHIFT), \
199 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
201 .reg = RK3368_CLKSEL_CON(1 + _offs), \
202 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
203 RK3368_DIV_ATCLK_SHIFT) | \
204 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
205 RK3368_DIV_PCLK_DBG_SHIFT), \
208 /* cluster_b: aclkm in clksel0, rest in clksel1 */
209 #define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
213 RK3368_CLKSEL0(0, _aclkm), \
214 RK3368_CLKSEL1(0, _atclk, _pdbg), \
218 /* cluster_l: aclkm in clksel2, rest in clksel3 */
219 #define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
223 RK3368_CLKSEL0(2, _aclkm), \
224 RK3368_CLKSEL1(2, _atclk, _pdbg), \
228 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
229 RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
230 RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
231 RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
232 RK3368_CPUCLKL_RATE(1296000000, 1, 4, 4),
233 RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
234 RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
235 RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
236 RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
237 RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
238 RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
239 RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
240 RK3368_CPUCLKB_RATE( 216000000, 1, 1, 1),
241 RK3368_CPUCLKB_RATE( 126000000, 1, 1, 1),
244 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
245 RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
246 RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
247 RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
248 RK3368_CPUCLKL_RATE(1296000000, 1, 5, 5),
249 RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
250 RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
251 RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
252 RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
253 RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
254 RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
255 RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
256 RK3368_CPUCLKL_RATE( 216000000, 1, 1, 1),
257 RK3368_CPUCLKL_RATE( 126000000, 1, 1, 1),
260 static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
261 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
262 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
264 static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
265 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
266 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
268 static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
269 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
270 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
272 static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
273 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
274 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
276 static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
277 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
278 RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
280 static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
281 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
282 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
284 static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
285 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
286 RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
288 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
290 * Clock-Architecture Diagram 2
293 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
294 RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
296 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
297 RK3368_CLKGATE_CON(0), 0, GFLAGS),
298 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
299 RK3368_CLKGATE_CON(0), 1, GFLAGS),
301 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
302 RK3368_CLKGATE_CON(0), 4, GFLAGS),
303 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
304 RK3368_CLKGATE_CON(0), 5, GFLAGS),
306 DIV(0, "aclkm_core_b", "armclkb", 0,
307 RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
308 DIV(0, "atclk_core_b", "armclkb", 0,
309 RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
310 DIV(0, "pclk_dbg_b", "armclkb", 0,
311 RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
313 DIV(0, "aclkm_core_l", "armclkl", 0,
314 RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
315 DIV(0, "atclk_core_l", "armclkl", 0,
316 RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
317 DIV(0, "pclk_dbg_l", "armclkl", 0,
318 RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
320 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
321 RK3368_CLKGATE_CON(0), 9, GFLAGS),
322 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
323 RK3368_CLKGATE_CON(0), 10, GFLAGS),
324 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
325 RK3368_CLKGATE_CON(0), 8, GFLAGS),
326 COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
327 RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
328 COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
329 RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
330 RK3368_CLKGATE_CON(0), 13, GFLAGS),
332 COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
333 RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
334 RK3368_CLKGATE_CON(0), 12, GFLAGS),
335 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
337 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
338 RK3368_CLKGATE_CON(1), 8, GFLAGS),
339 GATE(0, "gpll_ddr", "gpll", 0,
340 RK3368_CLKGATE_CON(1), 9, GFLAGS),
341 COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
342 RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
344 COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
345 RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
347 GATE(0, "sclk_ddr", "ddrphy_div4", CLK_IGNORE_UNUSED,
348 RK3368_CLKGATE_CON(6), 14, GFLAGS),
349 GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
350 RK3368_CLKGATE_CON(6), 15, GFLAGS),
352 GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
353 RK3368_CLKGATE_CON(1), 10, GFLAGS),
354 GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
355 RK3368_CLKGATE_CON(1), 11, GFLAGS),
356 COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
357 RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
359 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
360 RK3368_CLKGATE_CON(1), 0, GFLAGS),
361 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
362 RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
363 RK3368_CLKGATE_CON(1), 2, GFLAGS),
364 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
365 RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
366 RK3368_CLKGATE_CON(1), 1, GFLAGS),
367 COMPOSITE_NOMUX(SCLK_CRYPTO, "sclk_crypto", "aclk_bus_src", 0,
368 RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
369 RK3368_CLKGATE_CON(7), 2, GFLAGS),
371 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
372 RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
373 RK3368_CLKGATE_CON(1), 3, GFLAGS),
375 * stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
376 * but stclk_mcu has an additional own divider in diagram 2
378 COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED,
379 RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
380 RK3368_CLKGATE_CON(13), 13, GFLAGS),
382 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
383 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
384 RK3368_CLKGATE_CON(6), 1, GFLAGS),
385 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
386 RK3368_CLKSEL_CON(28), 0,
387 RK3368_CLKGATE_CON(6), 2, GFLAGS,
388 &rk3368_i2s_8ch_fracmux),
389 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
390 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
391 RK3368_CLKGATE_CON(6), 0, GFLAGS),
392 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
393 RK3368_CLKGATE_CON(6), 3, GFLAGS),
394 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
395 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
396 RK3368_CLKGATE_CON(6), 4, GFLAGS),
397 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
398 RK3368_CLKSEL_CON(32), 0,
399 RK3368_CLKGATE_CON(6), 5, GFLAGS,
400 &rk3368_spdif_8ch_fracmux),
401 GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
402 RK3368_CLKGATE_CON(6), 6, GFLAGS),
403 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
404 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
405 RK3368_CLKGATE_CON(5), 13, GFLAGS),
406 COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
407 RK3368_CLKSEL_CON(54), 0,
408 RK3368_CLKGATE_CON(5), 14, GFLAGS,
409 &rk3368_i2s_2ch_fracmux),
410 GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
411 RK3368_CLKGATE_CON(5), 15, GFLAGS),
413 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
414 RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
415 RK3368_CLKGATE_CON(6), 12, GFLAGS),
416 GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
417 RK3368_CLKGATE_CON(13), 7, GFLAGS),
419 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
420 RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
421 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
422 RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
423 RK3368_CLKGATE_CON(2), 4, GFLAGS),
424 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
425 RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
428 * Clock-Architecture Diagram 3
431 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
432 RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
433 RK3368_CLKGATE_CON(4), 6, GFLAGS),
434 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
435 RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
436 RK3368_CLKGATE_CON(4), 7, GFLAGS),
439 * We introduce a virtual node of hclk_vodec_pre_v to split one clock
440 * struct with a gate and a fix divider into two node in software.
442 GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
443 RK3368_CLKGATE_CON(4), 8, GFLAGS),
445 COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
446 RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
447 RK3368_CLKGATE_CON(5), 1, GFLAGS),
448 COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
449 RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
450 RK3368_CLKGATE_CON(5), 2, GFLAGS),
452 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
453 RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
454 RK3368_CLKGATE_CON(4), 0, GFLAGS),
455 DIV(0, "hclk_vio", "aclk_vio0", 0,
456 RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
458 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
459 RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
460 RK3368_CLKGATE_CON(4), 3, GFLAGS),
461 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
462 RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
463 RK3368_CLKGATE_CON(4), 4, GFLAGS),
465 COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
466 RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
467 RK3368_CLKGATE_CON(4), 1, GFLAGS),
469 GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
470 RK3368_CLKGATE_CON(4), 2, GFLAGS),
472 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
473 RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
474 RK3368_CLKGATE_CON(4), 9, GFLAGS),
476 GATE(0, "pclk_isp_in", "ext_isp", 0,
477 RK3368_CLKGATE_CON(17), 2, GFLAGS),
478 INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
479 RK3368_CLKSEL_CON(21), 6, IFLAGS),
481 GATE(0, "pclk_vip_in", "ext_vip", 0,
482 RK3368_CLKGATE_CON(16), 13, GFLAGS),
483 INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
484 RK3368_CLKSEL_CON(21), 13, IFLAGS),
486 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
487 RK3368_CLKGATE_CON(4), 13, GFLAGS),
488 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
489 RK3368_CLKGATE_CON(4), 12, GFLAGS),
491 COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
492 RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
493 RK3368_CLKGATE_CON(4), 5, GFLAGS),
494 COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
495 RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
497 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
498 RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
499 RK3368_CLKGATE_CON(5), 4, GFLAGS),
500 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
501 RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
502 RK3368_CLKGATE_CON(5), 3, GFLAGS),
504 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
505 RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
506 RK3368_CLKGATE_CON(5), 5, GFLAGS),
508 DIV(0, "pclk_pd_alive", "gpll", 0,
509 RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
511 /* sclk_timer has a gate in the sgrf */
513 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
514 RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
515 RK3368_CLKGATE_CON(7), 9, GFLAGS),
516 GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
517 RK3368_CLKGATE_CON(7), 3, GFLAGS),
518 COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
519 RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
520 RK3368_CLKGATE_CON(4), 11, GFLAGS),
521 MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
522 RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
523 COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
524 RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
525 RK3368_CLKGATE_CON(5), 8, GFLAGS),
526 COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
527 RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
528 RK3368_CLKGATE_CON(5), 9, GFLAGS),
529 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
530 RK3368_CLKGATE_CON(7), 11, GFLAGS),
532 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
533 RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
534 RK3368_CLKGATE_CON(3), 0, GFLAGS),
535 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
536 RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
537 RK3368_CLKGATE_CON(3), 3, GFLAGS),
538 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
539 RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
540 RK3368_CLKGATE_CON(3), 2, GFLAGS),
541 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
542 RK3368_CLKGATE_CON(3), 1, GFLAGS),
544 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", CLK_IGNORE_UNUSED,
545 RK3368_CLKGATE_CON(4), 14, GFLAGS),
548 * Clock-Architecture Diagram 4
551 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
552 RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
553 RK3368_CLKGATE_CON(3), 7, GFLAGS),
554 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
555 RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
556 RK3368_CLKGATE_CON(3), 8, GFLAGS),
557 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
558 RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
559 RK3368_CLKGATE_CON(3), 9, GFLAGS),
562 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
563 RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
564 RK3368_CLKGATE_CON(7), 12, GFLAGS),
565 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
566 RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
567 RK3368_CLKGATE_CON(7), 13, GFLAGS),
568 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
569 RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
570 RK3368_CLKGATE_CON(7), 15, GFLAGS),
572 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
573 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
575 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1),
576 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
578 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
579 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
581 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
582 RK3368_CLKGATE_CON(8), 1, GFLAGS),
584 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
585 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
586 RK3368_CLKGATE_CON(8), 4, GFLAGS),
588 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
589 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
590 RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
591 RK3368_CLKGATE_CON(3), 5, GFLAGS),
593 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
594 RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
595 RK3368_CLKGATE_CON(3), 6, GFLAGS),
597 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
598 RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
599 RK3368_CLKGATE_CON(7), 8, GFLAGS),
601 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
602 RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
603 RK3368_CLKGATE_CON(6), 7, GFLAGS),
605 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
606 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
607 RK3368_CLKGATE_CON(2), 0, GFLAGS),
608 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
609 RK3368_CLKSEL_CON(34), 0,
610 RK3368_CLKGATE_CON(2), 1, GFLAGS,
611 &rk3368_uart0_fracmux),
613 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
614 RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
615 RK3368_CLKGATE_CON(2), 2, GFLAGS),
616 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
617 RK3368_CLKSEL_CON(36), 0,
618 RK3368_CLKGATE_CON(2), 3, GFLAGS,
619 &rk3368_uart1_fracmux),
621 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
622 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
623 RK3368_CLKGATE_CON(2), 6, GFLAGS),
624 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
625 RK3368_CLKSEL_CON(40), 0,
626 RK3368_CLKGATE_CON(2), 7, GFLAGS,
627 &rk3368_uart3_fracmux),
629 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
630 RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
631 RK3368_CLKGATE_CON(2), 8, GFLAGS),
632 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
633 RK3368_CLKSEL_CON(42), 0,
634 RK3368_CLKGATE_CON(2), 9, GFLAGS,
635 &rk3368_uart4_fracmux),
637 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
638 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
639 RK3368_CLKGATE_CON(3), 4, GFLAGS),
640 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
641 RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
642 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
643 RK3368_CLKGATE_CON(7), 7, GFLAGS),
644 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
645 RK3368_CLKGATE_CON(7), 6, GFLAGS),
646 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
647 RK3368_CLKGATE_CON(7), 4, GFLAGS),
648 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
649 RK3368_CLKGATE_CON(7), 5, GFLAGS),
651 GATE(0, "jtag", "ext_jtag", 0,
652 RK3368_CLKGATE_CON(7), 0, GFLAGS),
654 COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
655 RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
656 RK3368_CLKGATE_CON(8), 0, GFLAGS),
657 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
658 RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
659 RK3368_CLKGATE_CON(8), 7, GFLAGS),
660 GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
661 RK3368_CLKGATE_CON(8), 6, GFLAGS),
664 * Clock-Architecture Diagram 5
667 /* aclk_cci_pre gates */
668 GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
669 GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
670 GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
671 GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
672 GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
674 /* aclkm_core_* gates */
675 GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
676 GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
679 GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
680 GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
682 /* sclk_cs_pre gates */
683 GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
684 GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
685 GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
688 GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
689 GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
690 GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
691 GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
692 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
693 GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
696 GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
698 /* clk_hsadc_tsp is part of diagram2 */
700 /* fclk_mcu_src gates */
701 GATE(0, "hclk_noc_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 14, GFLAGS),
702 GATE(0, "fclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 12, GFLAGS),
703 GATE(0, "hclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 11, GFLAGS),
706 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
707 GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
708 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
709 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
710 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
711 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
712 GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
715 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
716 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
717 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
718 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
719 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
720 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
721 GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
722 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
723 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
724 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
725 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
729 * aclk_video(_pre) can actually select between parents of aclk_vdpu
730 * and aclk_vepu by setting bit GRF_SOC_CON0[7].
732 GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
733 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
734 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
735 GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
737 /* aclk_rga_pre gates */
738 GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
739 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
740 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
742 /* aclk_vio0 gates */
743 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
744 GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
745 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
746 GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
747 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
750 GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
751 GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
754 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
755 GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
756 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
757 GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
758 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
759 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
760 GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
761 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
765 * pclk_vio comes from the exactly same source as hclk_vio
767 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
768 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
769 GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
770 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
771 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
772 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
774 /* ext_vip gates in diagram3 */
777 GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
778 GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
779 GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
781 /* aclk_peri gates */
782 GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
783 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
784 GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
785 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
786 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
787 GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
789 /* hclk_peri gates */
790 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
791 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
792 GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
793 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
794 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
795 GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 6, GFLAGS),
796 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
797 GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
798 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
799 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
800 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 1, GFLAGS),
801 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
802 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
803 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
804 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
806 /* pclk_peri gates */
807 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
808 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
809 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
810 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
811 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
812 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
813 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
814 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
815 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
816 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
817 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
818 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
819 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
820 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
821 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
823 /* pclk_pd_alive gates */
824 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
825 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
826 GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
827 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
828 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
829 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
830 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
834 * pclk_vio comes from the exactly same source as hclk_vio
836 GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
837 GATE(PCLK_DPHYTX0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
839 /* pclk_pd_pmu gates */
840 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
841 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
842 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
843 GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
844 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
845 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
848 GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
849 GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
850 GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
851 GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
852 GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
853 GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
854 GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
855 GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
856 GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
857 GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
858 GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
859 GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
862 static const char *const rk3368_critical_clocks[] __initconst = {
869 static void __init rk3368_clk_init(struct device_node *np)
871 struct rockchip_clk_provider *ctx;
872 void __iomem *reg_base;
875 reg_base = of_iomap(np, 0);
877 pr_err("%s: could not map cru region\n", __func__);
881 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
883 pr_err("%s: rockchip clk init failed\n", __func__);
888 /* xin12m is created by a cru-internal divider */
889 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
891 pr_warn("%s: could not register clock xin12m: %ld\n",
892 __func__, PTR_ERR(clk));
894 /* ddrphy_div4 is created by a cru-internal divider */
895 clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
897 pr_warn("%s: could not register clock xin12m: %ld\n",
898 __func__, PTR_ERR(clk));
900 clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
901 "hclk_video_pre_v", 0, 1, 4);
903 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
904 __func__, PTR_ERR(clk));
906 /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
907 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
909 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
910 __func__, PTR_ERR(clk));
912 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
914 rockchip_clk_register_plls(ctx, rk3368_pll_clks,
915 ARRAY_SIZE(rk3368_pll_clks),
916 RK3368_GRF_SOC_STATUS0);
917 rockchip_clk_register_branches(ctx, rk3368_clk_branches,
918 ARRAY_SIZE(rk3368_clk_branches));
919 rockchip_clk_protect_critical(rk3368_critical_clocks,
920 ARRAY_SIZE(rk3368_critical_clocks));
922 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
923 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
924 &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
925 ARRAY_SIZE(rk3368_cpuclkb_rates));
927 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
928 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
929 &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
930 ARRAY_SIZE(rk3368_cpuclkl_rates));
932 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
933 ROCKCHIP_SOFTRST_HIWORD_MASK);
935 rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
937 rockchip_clk_of_add_provider(np, ctx);
939 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob