drivers/clk/rockchip/clk-rk3366.c

   1 /*
   2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   3  * Author: Xiao Feng <xf@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <dt-bindings/clock/rk3366-cru.h>
  21 #include "clk.h"
  22
  23 #define RK3366_GRF_SOC_STATUS0  0x480
  24
  25 enum rk3366_plls {
  26         apll, dpll, cpll, gpll, npll, mpll, wpll, bpll,
  27 };
  28
  29 static struct rockchip_pll_rate_table rk3366_pll_rates[] = {
  30         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  31         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  32         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  33         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  34         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  36         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  37         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  38         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  39         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  40         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  45         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  46         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  47         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  48         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  49         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  50         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  51         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  52         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  53         RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
  54         RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
  55         RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
  56         RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
  57         RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
  58         RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
  59         RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
  60         RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
  61         RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
  62         RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
  63         RK3036_PLL_RATE( 750000000, 2, 125, 2, 1, 1, 0),
  64         RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
  65         RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
  66         RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
  67         RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
  68         RK3036_PLL_RATE( 576000000, 1, 96, 4, 1, 1, 0),
  69         RK3036_PLL_RATE( 520000000, 1, 65, 3, 1, 1, 0),
  70         RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
  71         RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
  72         RK3036_PLL_RATE( 480000000, 1, 80, 4, 1, 1, 0),
  73         RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
  74         RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
  75         RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
  76         RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
  77
  78         { /* sentinel */ },
  79 };
  80
  81 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
  82 PNAME(mux_armclk_p)             = { "apll_core", "gpll_core", "dpll_core" };
  83 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
  84 PNAME(mux_aclk_bus_src_p)       = { "cpll_aclk_bus", "gpll_aclk_bus" };
  85 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
  86 PNAME(mux_pll_src_dmynpll_cpll_gpll_gpll_p)     = { "dummy_npll", "cpll", "gpll", "gpll" };
  87 PNAME(mux_pll_src_cpll_gpll_usb_p)      = { "cpll", "gpll", "usbphy_480m" };
  88 PNAME(mux_pll_src_cpll_gpll_usb_usb_p)  = { "cpll", "gpll", "usbphy_480m",
  89                                             "usbphy_480m" };
  90 PNAME(mux_pll_src_cpll_gpll_usb_dmynpll_p)      = { "cpll", "gpll", "usbphy_480m",
  91                                             "dummy_npll" };
  92 PNAME(mux_pll_src_cpll_gpll_dmynpll_dmynpll_p) = { "cpll", "gpll", "dummy_npll", "dummy_npll" };
  93 PNAME(mux_pll_src_cpll_gpll_dmynpll_usb_p) = { "cpll", "gpll", "dummy_npll",
  94                                             "usbphy_480m" };
  95 PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll_src" };
  96 PNAME(mux_vop_full_pwm_p) = { "xin24m", "cpll", "gpll", "dummy_npll" };
  97 PNAME(mux_clk_32k_p)            = { "xin32k", "clk_32k_intr" };
  98 PNAME(mux_i2s_8ch_pre_p)        = { "i2s_8ch_src", "i2s_8ch_frac",
  99                                     "ext_i2s", "xin12m" };
 100 PNAME(mux_i2s_8ch_clkout_p)     = { "i2s_8ch_pre", "xin12m" };
 101 PNAME(mux_i2s_2ch_p)            = { "i2s_2ch_src", "i2s_2ch_frac",
 102                                     "dummy", "xin12m" };
 103 PNAME(mux_spdif_8ch_p)          = { "spdif_8ch_pre", "spdif_8ch_frac",
 104                                     "ext_i2s", "xin12m" };
 105 PNAME(mux_vip_out_p)            = { "vip_src", "xin24m" };
 106 PNAME(mux_usb3_suspend_p)       = { "clk_32k", "xin24m" };
 107 PNAME(mux_usbphy480m_p)         = { "xin24m", "sclk_otgphy0_480m" };
 108 PNAME(mux_uart0_p)              = { "uart0_src", "uart0_frac", "xin24m", "xin24m" };
 109 PNAME(mux_uart2_p)              = { "uart2_src", "xin24m" };
 110 PNAME(mux_uart3_p)              = { "uart3_src", "uart3_frac", "xin24m", "xin24m"  };
 111 PNAME(mux_mac_p)                = { "mac_pll_src", "ext_gmac" };
 112 PNAME(mux_mmc_src_p)            = { "cpll", "gpll", "usbphy_480m", "xin24m" };
 113 PNAME(mux_bt_p)                 = { "bpll", "btclk520_pll" };
 114 PNAME(mux_wifi_pll_p)           = { "wpll_wiff", "usbphy_480m_wifi" };
 115
 116 static struct rockchip_pll_clock rk3366_pll_clks[] __initdata = {
 117         [apll] = PLL(pll_rk3366, PLL_APLL, "apll", mux_pll_p, 0, RK3368_PLL_CON(0),
 118                      RK3368_PLL_CON(3), 8, 0, 0, rk3366_pll_rates),
 119         [dpll] = PLL(pll_rk3366, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
 120                      RK3368_PLL_CON(11), 8, 1, 0, NULL),
 121         [cpll] = PLL(pll_rk3366, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
 122                      RK3368_PLL_CON(15), 8, 2, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 123         [gpll] = PLL(pll_rk3366, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
 124                      RK3368_PLL_CON(19), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 125         [npll] = PLL(pll_rk3366, PLL_NPLL, "npll",  mux_pll_p, 0, RK3368_PLL_CON(20),
 126                      RK3368_PLL_CON(23), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 127         [mpll] = PLL(pll_rk3366, PLL_MPLL, "mpll",  mux_pll_p, 0, RK3368_PLL_CON(24),
 128                      RK3368_PLL_CON(27), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 129         [wpll] = PLL(pll_rk3366, PLL_WPLL, "wpll",  mux_pll_p, 0, RK3368_PLL_CON(28),
 130                      RK3368_PLL_CON(31), 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 131         [bpll] = PLL(pll_rk3366, PLL_BPLL, "bpll",  mux_pll_p, 0, RK3368_PLL_CON(32),
 132                      RK3368_PLL_CON(35), 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
 133 };
 134
 135 static struct clk_div_table div_ddrphy_t[] = {
 136         { .val = 0, .div = 1 },
 137         { .val = 1, .div = 2 },
 138         { .val = 3, .div = 4 },
 139         { /* sentinel */ },
 140 };
 141
 142 #define MFLAGS CLK_MUX_HIWORD_MASK
 143 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 144 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 145 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 146
 147 static const struct rockchip_cpuclk_reg_data rk3366_cpuclk_data = {
 148         .core_reg = RK3368_CLKSEL_CON(0),
 149         .div_core_shift = 0,
 150         .div_core_mask = 0x1f,
 151         .mux_core_alt = 1,
 152         .mux_core_main = 0,
 153         .mux_core_shift = 6,
 154         .mux_core_mask = 0x1,
 155 };
 156
 157 #define RK3366_DIV_ACLKM_MASK           0x1f
 158 #define RK3366_DIV_ACLKM_SHIFT          8
 159 #define RK3366_DIV_ATCLK_MASK           0x1f
 160 #define RK3366_DIV_ATCLK_SHIFT          0
 161 #define RK3366_DIV_PCLK_DBG_MASK        0x1f
 162 #define RK3366_DIV_PCLK_DBG_SHIFT       8
 163
 164 #define RK3366_CLKSEL0(_offs, _aclkm)                                   \
 165         {                                                               \
 166                 .reg = RK3368_CLKSEL_CON(0 + _offs),                    \
 167                 .val = HIWORD_UPDATE(_aclkm, RK3366_DIV_ACLKM_MASK,     \
 168                                 RK3366_DIV_ACLKM_SHIFT),                \
 169         }
 170 #define RK3366_CLKSEL1(_offs, _atclk, _pdbg)                            \
 171         {                                                               \
 172                 .reg = RK3368_CLKSEL_CON(1 + _offs),                    \
 173                 .val = HIWORD_UPDATE(_atclk, RK3366_DIV_ATCLK_MASK,     \
 174                                 RK3366_DIV_ATCLK_SHIFT) |               \
 175                        HIWORD_UPDATE(_pdbg, RK3366_DIV_PCLK_DBG_MASK,   \
 176                                 RK3366_DIV_PCLK_DBG_SHIFT),             \
 177         }
 178
 179 /* cluster_b: aclkm in clksel0, rest in clksel1 */
 180 #define RK3366_CPUCLK_RATE(_prate, _aclkm, _atclk, _pdbg)               \
 181         {                                                               \
 182                 .prate = _prate,                                        \
 183                 .divs = {                                               \
 184                         RK3366_CLKSEL0(0, _aclkm),                      \
 185                         RK3366_CLKSEL1(0, _atclk, _pdbg),               \
 186                 },                                                      \
 187         }
 188
 189 static struct rockchip_cpuclk_rate_table rk3366_cpuclk_rates[] __initdata = {
 190         RK3366_CPUCLK_RATE(1512000000, 1, 5, 5),
 191         RK3366_CPUCLK_RATE(1488000000, 1, 4, 4),
 192         RK3366_CPUCLK_RATE(1416000000, 1, 4, 4),
 193         RK3366_CPUCLK_RATE(1296000000, 1, 4, 4),
 194         RK3366_CPUCLK_RATE(1200000000, 1, 3, 3),
 195         RK3366_CPUCLK_RATE(1104000000, 1, 3, 3),
 196         RK3366_CPUCLK_RATE(1008000000, 1, 3, 3),
 197         RK3366_CPUCLK_RATE( 816000000, 1, 2, 2),
 198         RK3366_CPUCLK_RATE( 696000000, 1, 2, 2),
 199         RK3366_CPUCLK_RATE( 600000000, 1, 1, 1),
 200         RK3366_CPUCLK_RATE( 408000000, 1, 1, 1),
 201         RK3366_CPUCLK_RATE( 312000000, 1, 1, 1),
 202         RK3366_CPUCLK_RATE( 216000000, 1, 1, 1),
 203 };
 204
 205 static struct rockchip_clk_branch rk3366_i2s_8ch_fracmux __initdata =
 206         MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
 207                         RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
 208
 209 static struct rockchip_clk_branch rk3366_spdif_8ch_fracmux __initdata =
 210         MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 211                         RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
 212
 213 static struct rockchip_clk_branch rk3366_i2s_2ch_fracmux __initdata =
 214         MUX(0, "i2s_2ch_mux", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
 215                         RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
 216
 217 static struct rockchip_clk_branch rk3366_uart0_fracmux __initdata =
 218         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 219                         RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
 220
 221 static struct rockchip_clk_branch rk3366_uart3_fracmux __initdata =
 222         MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 223                         RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
 224
 225 static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
 226         /*
 227          * Clock-Architecture Diagram 1
 228          */
 229
 230         GATE(SCLK_MPLL_SRC, "mpll_src", "mpll", CLK_IGNORE_UNUSED,
 231                         RK3368_CLKGATE_CON(2), 11, GFLAGS),
 232
 233         /*
 234          * Clock-Architecture Diagram 2
 235          */
 236
 237         MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, 0,
 238                         RK3368_CLKSEL_CON(13), 6, 1, MFLAGS),
 239
 240         DIV(SCLK_32K_INTR, "clk_32k_intr", "xin24m", 0,
 241                         RK3368_CLKSEL_CON(7), 0, 10, DFLAGS),
 242         MUX(SCLK_32K, "clk_32k", mux_clk_32k_p, CLK_SET_RATE_PARENT,
 243                         RK3368_CLKSEL_CON(7), 15, 1, MFLAGS),
 244
 245         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 246                         RK3368_CLKGATE_CON(0), 0, GFLAGS),
 247         GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
 248                         RK3368_CLKGATE_CON(0), 1, GFLAGS),
 249         GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
 250                         RK3368_CLKGATE_CON(0), 2, GFLAGS),
 251
 252         DIV(0, "aclkm_core", "armclk", 0,
 253                         RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 254         DIV(0, "atclk_core", "armclk", 0,
 255                         RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 256         DIV(0, "pclk_dbg", "armclk", 0,
 257                         RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
 258
 259         COMPOSITE_NOMUX(0, "sclk_cs_pre", "armclk", CLK_IGNORE_UNUSED,
 260                         RK3368_CLKSEL_CON(4), 0, 5, DFLAGS,
 261                         RK3368_CLKGATE_CON(0), 11, GFLAGS),
 262         COMPOSITE_NOMUX(0, "clkin_trace", "armclk", CLK_IGNORE_UNUSED,
 263                         RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
 264                         RK3368_CLKGATE_CON(0), 13, GFLAGS),
 265
 266         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0,
 267                         RK3368_CLKGATE_CON(7), 10, GFLAGS),
 268
 269         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 270                         RK3368_CLKGATE_CON(1), 8, GFLAGS),
 271         GATE(0, "gpll_ddr", "gpll", 0,
 272                         RK3368_CLKGATE_CON(1), 9, GFLAGS),
 273         GATE(0, "apll_ddr", "apll", 0,
 274                         RK3368_CLKGATE_CON(1), 7, GFLAGS),
 275         COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 276                         RK3368_CLKSEL_CON(13), 4, 2, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
 277
 278         GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
 279                         RK3368_CLKGATE_CON(1), 10, GFLAGS),
 280         GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
 281                         RK3368_CLKGATE_CON(1), 11, GFLAGS),
 282         COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
 283                         RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
 284
 285         GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 286                         RK3368_CLKGATE_CON(1), 0, GFLAGS),
 287         COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 288                         RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
 289                         RK3368_CLKGATE_CON(1), 2, GFLAGS),
 290         COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
 291                         RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
 292                         RK3368_CLKGATE_CON(1), 1, GFLAGS),
 293
 294         COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_cpll_gpll_p, 0,
 295                         RK3368_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 5, DFLAGS,
 296                         RK3368_CLKGATE_CON(7), 2, GFLAGS),
 297
 298         COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 299                         RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
 300                         RK3368_CLKGATE_CON(1), 3, GFLAGS),
 301
 302         COMPOSITE(SCLK_I2S_8CH_SRC, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
 303                         RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
 304                         RK3368_CLKGATE_CON(6), 1, GFLAGS),
 305         COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
 306                         RK3368_CLKSEL_CON(28), 0,
 307                         RK3368_CLKGATE_CON(6), 2, GFLAGS,
 308                         &rk3366_i2s_8ch_fracmux),
 309         COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
 310                         RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
 311                         RK3368_CLKGATE_CON(6), 0, GFLAGS),
 312         GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
 313                         RK3368_CLKGATE_CON(6), 3, GFLAGS),
 314
 315         COMPOSITE(SCLK_SPDIF_8CH_SRC, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
 316                         RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
 317                         RK3368_CLKGATE_CON(6), 4, GFLAGS),
 318         COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
 319                         RK3368_CLKSEL_CON(32), 0,
 320                         RK3368_CLKGATE_CON(6), 5, GFLAGS,
 321                         &rk3366_spdif_8ch_fracmux),
 322         GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 323                         RK3368_CLKGATE_CON(6), 6, GFLAGS),
 324
 325         COMPOSITE(SCLK_I2S_2CH_SRC, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
 326                         RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
 327                         RK3368_CLKGATE_CON(5), 13, GFLAGS),
 328         COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
 329                         RK3368_CLKSEL_CON(54), 0,
 330                         RK3368_CLKGATE_CON(5), 14, GFLAGS,
 331                         &rk3366_i2s_2ch_fracmux),
 332         GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_mux", CLK_SET_RATE_PARENT,
 333                         RK3368_CLKGATE_CON(5), 15, GFLAGS),
 334
 335         /*
 336          * Clock-Architecture Diagram 3
 337          */
 338
 339         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 340                         RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
 341         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 342                         RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
 343                         RK3368_CLKGATE_CON(2), 4, GFLAGS),
 344         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 345                         RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
 346
 347         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0,
 348                         RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
 349                         RK3368_CLKGATE_CON(4), 6, GFLAGS),
 350         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0,
 351                         RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
 352                         RK3368_CLKGATE_CON(4), 7, GFLAGS),
 353
 354         /*
 355          * We introduce a virtual node of hclk_vodec_pre_v to split one clock
 356          * struct with a gate and a fix divider into two node in software.
 357          */
 358         GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
 359                         RK3368_CLKGATE_CON(4), 8, GFLAGS),
 360
 361         COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0,
 362                         RK3368_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 5, DFLAGS,
 363                         RK3368_CLKGATE_CON(5), 8, GFLAGS),
 364
 365         /*
 366          * We introduce a virtual node of hclk_rkvdec_pre_v to split one clock
 367          * struct with a gate and a fix divider into two node in software.
 368          */
 369         GATE(0, "hclk_rkvdec_pre_v", "aclk_rkvdec_pre", 0,
 370                         RK3368_CLKGATE_CON(5), 9, GFLAGS),
 371
 372         COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0,
 373                         RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
 374                         RK3368_CLKGATE_CON(5), 1, GFLAGS),
 375         COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0,
 376                         RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
 377                         RK3368_CLKGATE_CON(5), 2, GFLAGS),
 378
 379         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
 380                         RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
 381                         RK3368_CLKGATE_CON(4), 0, GFLAGS),
 382         DIV(0, "hclk_vio", "aclk_vio0", 0,
 383                         RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
 384
 385         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
 386                         RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
 387                         RK3368_CLKGATE_CON(4), 3, GFLAGS),
 388         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
 389                         RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
 390                         RK3368_CLKGATE_CON(4), 4, GFLAGS),
 391
 392         COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_cpll_gpll_usb_p, 0,
 393                         RK3368_CLKSEL_CON(16), 6, 2, MFLAGS, 0, 5, DFLAGS,
 394                         RK3368_CLKGATE_CON(4), 15, GFLAGS),
 395
 396         COMPOSITE(DCLK_VOP_FULL, "dclk_vop_full", mux_pll_src_cpll_gpll_npll_mpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 397                         RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
 398                         RK3368_CLKGATE_CON(4), 1, GFLAGS),
 399
 400         COMPOSITE(SCLK_VOP_FULL_PWM, "sclk_vop_full_pwm", mux_vop_full_pwm_p, 0,
 401                         RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
 402                         RK3368_CLKGATE_CON(4), 2, GFLAGS),
 403
 404         COMPOSITE(DCLK_VOP_LITE, "dclk_vop_lite", mux_pll_src_cpll_gpll_npll_mpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 405                         RK3368_CLKSEL_CON(24), 8, 2, MFLAGS, 0, 8, DFLAGS,
 406                         RK3368_CLKGATE_CON(5), 6, GFLAGS),
 407
 408         COMPOSITE_NOMUX(DCLK_HDMIPHY, "dclk_hdmiphy", "mpll_src", 0,
 409                         RK3368_CLKSEL_CON(16), 8, 8, DFLAGS,
 410                         RK3368_CLKGATE_CON(5), 7, GFLAGS),
 411
 412         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0,
 413                         RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
 414                         RK3368_CLKGATE_CON(4), 9, GFLAGS),
 415
 416         GATE(PCLK_ISP, "pclk_isp", "ext_isp", 0,
 417                         RK3368_CLKGATE_CON(17), 2, GFLAGS),
 418
 419         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 420                         RK3368_CLKGATE_CON(4), 13, GFLAGS),
 421         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "clk_32k", 0,
 422                         RK3368_CLKGATE_CON(4), 12, GFLAGS),
 423
 424         MUX(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 425                         RK3368_CLKSEL_CON(21), 15, 1, MFLAGS),
 426         COMPOSITE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
 427                         RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS,
 428                         RK3368_CLKGATE_CON(4), 5, GFLAGS),
 429
 430         GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
 431
 432         /*
 433          * Clock-Architecture Diagram 4
 434          */
 435
 436         COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0,
 437                         RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
 438                         RK3368_CLKGATE_CON(5), 5, GFLAGS),
 439
 440         DIV(0, "pclk_pd_alive", "gpll", 0,
 441                         RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
 442
 443         /* sclk_timer has a gate in the sgrf */
 444
 445         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
 446                         RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
 447                         RK3368_CLKGATE_CON(7), 9, GFLAGS),
 448         GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
 449                         RK3368_CLKGATE_CON(7), 3, GFLAGS),
 450
 451         COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_dmynpll_p, 0,
 452                         RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
 453                         RK3368_CLKGATE_CON(4), 11, GFLAGS),
 454         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
 455                         RK3368_CLKGATE_CON(7), 11, GFLAGS),
 456
 457         COMPOSITE(0, "aclk_peri0_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 458                         RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
 459                         RK3368_CLKGATE_CON(3), 0, GFLAGS),
 460         COMPOSITE_NOMUX(PCLK_PERI0, "pclk_peri0", "aclk_peri0_src", 0,
 461                         RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 462                         RK3368_CLKGATE_CON(3), 3, GFLAGS),
 463         COMPOSITE_NOMUX(HCLK_PERI0, "hclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED,
 464                         RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 465                         RK3368_CLKGATE_CON(3), 2, GFLAGS),
 466         GATE(ACLK_PERI0, "aclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED,
 467                         RK3368_CLKGATE_CON(3), 1, GFLAGS),
 468
 469         COMPOSITE(0, "aclk_peri1_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 470                         RK3368_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
 471                         RK3368_CLKGATE_CON(3), 10, GFLAGS),
 472         COMPOSITE_NOMUX(PCLK_PERI1, "pclk_peri1", "aclk_peri1_src", 0,
 473                         RK3368_CLKSEL_CON(11), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 474                         RK3368_CLKGATE_CON(3), 13, GFLAGS),
 475         COMPOSITE_NOMUX(HCLK_PERI1, "hclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED,
 476                         RK3368_CLKSEL_CON(11), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 477                         RK3368_CLKGATE_CON(3), 12, GFLAGS),
 478         GATE(ACLK_PERI1, "aclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED,
 479                         RK3368_CLKGATE_CON(3), 11, GFLAGS),
 480
 481         GATE(SCLK_USB3_REF, "sclk_usb3_ref", "xin24m", 0,
 482                         RK3368_CLKGATE_CON(3), 15, GFLAGS),
 483
 484         COMPOSITE(SCLK_USB3_SUSPEND, "sclk_usb3_suspend", mux_usb3_suspend_p, 0,
 485                         RK3368_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 8, DFLAGS,
 486                         RK3368_CLKGATE_CON(3), 14, GFLAGS),
 487
 488         /* ref_alt_clk_p has a mux in the grf */
 489
 490         /*
 491          * Clock-Architecture Diagram 5
 492          */
 493
 494         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 495                         RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
 496                         RK3368_CLKGATE_CON(3), 7, GFLAGS),
 497         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 498                         RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
 499                         RK3368_CLKGATE_CON(3), 8, GFLAGS),
 500         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 501                         RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
 502                         RK3368_CLKGATE_CON(3), 9, GFLAGS),
 503
 504         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 505                         RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
 506                         RK3368_CLKGATE_CON(7), 12, GFLAGS),
 507         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 508                         RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
 509                         RK3368_CLKGATE_CON(7), 13, GFLAGS),
 510         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 511                         RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
 512                         RK3368_CLKGATE_CON(7), 15, GFLAGS),
 513
 514         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
 515         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
 516
 517         MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3368_SDIO0_CON0, 1),
 518         MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
 519
 520         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3368_EMMC_CON0,  1),
 521         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3368_EMMC_CON1,  0),
 522
 523         GATE(SCLK_OTG_PHY0, "sclk_otg_phy0", "xin24m", CLK_IGNORE_UNUSED,
 524                         RK3368_CLKGATE_CON(8), 1, GFLAGS),
 525
 526         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "clk_32k", CLK_IGNORE_UNUSED,
 527                         RK3368_CLKGATE_CON(8), 4, GFLAGS),
 528
 529         GATE(SCLK_TSADC, "sclk_tsadc", "clk_32k", 0,
 530                         RK3368_CLKGATE_CON(3), 5, GFLAGS),
 531
 532         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 533                         RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
 534                         RK3368_CLKGATE_CON(3), 6, GFLAGS),
 535
 536         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 537                         RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
 538                         RK3368_CLKGATE_CON(7), 8, GFLAGS),
 539
 540         COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
 541                         RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
 542                         RK3368_CLKGATE_CON(6), 7, GFLAGS),
 543
 544         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
 545                         RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
 546                         RK3368_CLKGATE_CON(2), 0, GFLAGS),
 547         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 548                         RK3368_CLKSEL_CON(34), 0,
 549                         RK3368_CLKGATE_CON(2), 1, GFLAGS,
 550                         &rk3366_uart0_fracmux),
 551
 552         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 553                         RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
 554                         RK3368_CLKGATE_CON(2), 6, GFLAGS),
 555         COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
 556                         RK3368_CLKSEL_CON(40), 0,
 557                         RK3368_CLKGATE_CON(2), 7, GFLAGS,
 558                         &rk3366_uart3_fracmux),
 559
 560         /*
 561          * Clock-Architecture Diagram 6
 562          */
 563
 564         COMPOSITE(0, "mac_pll_src", mux_pll_src_dmynpll_cpll_gpll_gpll_p, 0,
 565                         RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
 566                         RK3368_CLKGATE_CON(3), 4, GFLAGS),
 567         MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
 568                         RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
 569         GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
 570                         RK3368_CLKGATE_CON(7), 7, GFLAGS),
 571         GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
 572                         RK3368_CLKGATE_CON(7), 6, GFLAGS),
 573         GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
 574                         RK3368_CLKGATE_CON(7), 4, GFLAGS),
 575         GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 576                         RK3368_CLKGATE_CON(7), 5, GFLAGS),
 577
 578         GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 579                         RK3368_CLKGATE_CON(7), 0, GFLAGS),
 580
 581         /*
 582          * Clock-Architecture Diagram 7
 583          */
 584
 585         COMPOSITE_NODIV(0, "btclk520_pll", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0,
 586                         RK3368_CLKSEL_CON(5), 13, 2, MFLAGS,
 587                         RK3368_CLKGATE_CON(2), 10, GFLAGS),
 588         MUX(0, "clk_bt_pll", mux_bt_p, 0,
 589                         RK3368_CLKSEL_CON(5), 15, 1, MFLAGS),
 590         COMPOSITE_NOMUX(SCLK_BT_52, "sclk_bt_520", "clk_bt_pll", 0,
 591                         RK3368_CLKSEL_CON(5), 0, 5, DFLAGS,
 592                         RK3368_CLKGATE_CON(8), 13, GFLAGS),
 593         DIV(0, "pclk_btbb", "sclk_bt_520", 0,
 594                         RK3368_CLKSEL_CON(5), 10, 3, DFLAGS),
 595         COMPOSITE_NOMUX(SCLK_BT_M0, "sclk_bt_m0", "clk_bt_pll", 0,
 596                         RK3368_CLKSEL_CON(5), 5, 5, DFLAGS,
 597                         RK3368_CLKGATE_CON(8), 14, GFLAGS),
 598
 599         GATE(SCLK_WIFI_WPLL, "wpll_wiff", "wpll", 0,
 600                         RK3368_CLKGATE_CON(8), 11, GFLAGS),
 601         GATE(SCLK_WIFI_USBPHY480M, "usbphy_480m_wifi", "usbphy_480m", 0,
 602                         RK3368_CLKGATE_CON(8), 11, GFLAGS),
 603         COMPOSITE(SCLK_WIFIDSP, "sclk_wifidsp", mux_wifi_pll_p, 0,
 604                         RK3368_CLKSEL_CON(13), 15, 1, MFLAGS, 10, 5, DFLAGS,
 605                         RK3368_CLKGATE_CON(8), 12, GFLAGS),
 606         DIV(0, "hclk_wifi", "sclk_wifidsp", CLK_SET_RATE_PARENT,
 607                         RK3368_CLKSEL_CON(13), 7, 3, DFLAGS),
 608
 609         /*
 610          * Clock-Architecture Diagram 8
 611          */
 612
 613         /* pclk_pd_pmu gates*/
 614         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
 615         GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
 616         GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
 617         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
 618         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 4, GFLAGS),
 619         GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
 620         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 6, GFLAGS),
 621
 622         /* fclk_mcu_src gates */
 623         GATE(0, "fclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 7, GFLAGS),
 624         GATE(0, "hclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 8, GFLAGS),
 625         GATE(0, "hclk_mcu_noc", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 9, GFLAGS),
 626
 627         /* pclk_pd_alive gates */
 628         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
 629         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
 630         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
 631         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 4, GFLAGS),
 632         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 5, GFLAGS),
 633         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
 634         GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
 635         GATE(PCLK_DPHYTX, "pclk_dphytx", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
 636         GATE(PCLK_DPHYRX, "pclk_dphyrx", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
 637         GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
 638
 639         /* pclk_cpu gates */
 640         GATE(PCLK_DMFIMON, "pclk_dmfimon", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 0, GFLAGS),
 641         GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
 642         GATE(PCLK_DFC, "pclk_dfc", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
 643         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
 644         GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
 645         GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
 646         GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
 647         GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
 648         GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
 649         GATE(PCLK_RKPWM, "pclk_rk_pwm", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
 650         GATE(0, "pclk_ddrnoc", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 10, GFLAGS),
 651         GATE(0, "pclk_ddr_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 11, GFLAGS),
 652
 653         /* hclk_cpu gates */
 654         GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
 655         GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
 656         GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
 657         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
 658         GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
 659         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
 660
 661         /* aclk_bus gates */
 662         GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
 663         GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
 664         GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
 665         GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
 666         GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
 667         GATE(ACLK_DFC, "aclk_dfc", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 15, GFLAGS),
 668         GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
 669
 670         /* clk_ddrphy gates */
 671         GATE(0, "clk_ddrupctl", "ddrphy_div4", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
 672
 673         /* clk_cs_pre gates */
 674         GATE(0, "sclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
 675         GATE(0, "hclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
 676         GATE(0, "pclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 2, GFLAGS),
 677
 678         /* armclk gates */
 679         GATE(0, "clk_core_cxcs", "armclk", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 3, GFLAGS),
 680
 681         /* aclkm_core gates */
 682         GATE(0, "aclk_core_noc", "aclkm_core", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 4, GFLAGS),
 683
 684         /* gpu gates */
 685         GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
 686         GATE(ACLK_GPU_NOC, "aclk_gpu_noc", "sclk_gpu_core_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(18), 1, GFLAGS),
 687
 688         /* aclk_peri0 gates */
 689         GATE(0, "aclk_peri0_axi_matrix", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
 690         GATE(ACLK_USB3, "aclk_usb3", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
 691         GATE(0, "aclk_peri0_noc", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
 692         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri0", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
 693
 694         /* hclk_peri0 gates */
 695         GATE(HCLK_OTG, "hclk_otg", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
 696         GATE(HCLK_HOST, "hclk_host", "hclk_peri0", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
 697         GATE(0, "hclk_host_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
 698         GATE(0, "hclk_peri0_ahb_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
 699         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
 700         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
 701         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
 702
 703         /* pclk_peri0 gates */
 704         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri0", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
 705
 706         /* aclk_peri1 gates */
 707         GATE(0, "aclk_peri1_axi_matrix", "aclk_peri1", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
 708         GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri1", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
 709
 710         /* hclk_peri1 gates */
 711         GATE(0, "hclk_peri1_ahb_arbiter", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 8, GFLAGS),
 712         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
 713         GATE(HCLK_SFC, "hclk_sfc", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
 714
 715         /* pclk_peri1 gates */
 716         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
 717         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
 718         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
 719         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
 720         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
 721         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
 722         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
 723         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
 724         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
 725         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri1", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
 726         GATE(PCLK_SIM, "pclk_sim", "pclk_peri1", 0, RK3368_CLKGATE_CON(21), 7, GFLAGS),
 727
 728         /*
 729          * video clk gates
 730          * aclk_video(_pre) can actually select between parents of aclk_vdpu
 731          * and aclk_vepu by setting bit GRF_SOC_CON0[7].
 732          */
 733         GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
 734         GATE(0, "aclk_video_noc", "aclk_vdpu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 4, GFLAGS),
 735         GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
 736         GATE(0, "hclk_video_noc", "hclk_video_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 5, GFLAGS),
 737
 738         GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 6, GFLAGS),
 739         GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 2, GFLAGS),
 740         GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 3, GFLAGS),
 741         GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 7, GFLAGS),
 742
 743         /* aclk_rga_pre gates */
 744         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
 745         GATE(0, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
 746         GATE(ACLK_VOP_LITE, "aclk_vop_lite", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 13, GFLAGS),
 747
 748         /* aclk_vio0 gates */
 749         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
 750         GATE(ACLK_VOP_FULL, "aclk_vop_full", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
 751         GATE(0, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
 752         GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
 753
 754         /* sclk_isp gates */
 755         GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
 756         GATE(0, "hclk_isp_noc", "sclk_isp", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS),
 757         GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
 758
 759         /* aclk_hdcp_pre gates */
 760         GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
 761         GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 15, GFLAGS),
 762
 763         /* hclk_vio gates */
 764         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
 765         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
 766         GATE(HCLK_VOP_FULL, "hclk_vop_full", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
 767         GATE(HCLK_VIO_AHB_ARBITER, "hclk_vio_ahb_arbiter", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
 768         GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
 769         GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
 770         GATE(HCLK_VOP_LITE, "hclk_vop_lite", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 14, GFLAGS),
 771         GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
 772         GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
 773         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
 774         GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
 775         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
 776
 777         /* timer gates */
 778         GATE(SCLK_TIMER5, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
 779         GATE(SCLK_TIMER4, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
 780         GATE(SCLK_TIMER3, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
 781         GATE(SCLK_TIMER2, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
 782         GATE(SCLK_TIMER1, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
 783         GATE(SCLK_TIMER0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
 784 };
 785
 786 static const char *const rk3366_critical_clocks[] __initconst = {
 787         "aclk_bus",
 788         "aclk_peri0",
 789         "aclk_peri1",
 790         "aclk_video_noc",
 791         "aclk_rkvdec_noc",
 792         "hclk_peri0",
 793         "hclk_peri1",
 794         "hclk_video_noc",
 795         "hclk_rkvdec_noc",
 796         "pclk_peri0",
 797         "pclk_peri1",
 798         "pclk_rk_pwm",
 799         "pclk_pd_pmu",
 800 };
 801
 802 static void __init rk3366_clk_init(struct device_node *np)
 803 {
 804         struct rockchip_clk_provider *ctx;
 805         void __iomem *reg_base;
 806         struct clk *clk;
 807
 808         reg_base = of_iomap(np, 0);
 809         if (!reg_base) {
 810                 pr_err("%s: could not map cru region\n", __func__);
 811                 return;
 812         }
 813
 814         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 815         if (IS_ERR(ctx)) {
 816                 pr_err("%s: rockchip clk init failed\n", __func__);
 817                 iounmap(reg_base);
 818                 return;
 819         }
 820
 821         /* xin12m is created by a cru-internal divider */
 822         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 823         if (IS_ERR(clk))
 824                 pr_warn("%s: could not register clock xin12m: %ld\n",
 825                         __func__, PTR_ERR(clk));
 826
 827         /* ddrphy_div4 is created by a cru-internal divider */
 828         clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
 829         if (IS_ERR(clk))
 830                 pr_warn("%s: could not register clock xin12m: %ld\n",
 831                         __func__, PTR_ERR(clk));
 832
 833         clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
 834                                         "hclk_video_pre_v", 0, 1, 4);
 835         if (IS_ERR(clk))
 836                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 837                         __func__, PTR_ERR(clk));
 838
 839         clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
 840                                         "hclk_rkvdec_pre_v", 0, 1, 4);
 841         if (IS_ERR(clk))
 842                 pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
 843                         __func__, PTR_ERR(clk));
 844
 845         /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
 846         clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
 847         if (IS_ERR(clk))
 848                 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
 849                         __func__, PTR_ERR(clk));
 850         else
 851                 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
 852
 853         rockchip_clk_register_plls(ctx, rk3366_pll_clks,
 854                                    ARRAY_SIZE(rk3366_pll_clks),
 855                                    RK3366_GRF_SOC_STATUS0);
 856         rockchip_clk_register_branches(ctx, rk3366_clk_branches,
 857                                   ARRAY_SIZE(rk3366_clk_branches));
 858         rockchip_clk_protect_critical(rk3366_critical_clocks,
 859                                       ARRAY_SIZE(rk3366_critical_clocks));
 860
 861         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 862                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 863                         &rk3366_cpuclk_data, rk3366_cpuclk_rates,
 864                         ARRAY_SIZE(rk3366_cpuclk_rates));
 865
 866         rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
 867                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 868
 869         rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
 870
 871         rockchip_clk_of_add_provider(np, ctx);
 872 }
 873 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3366-cru", rk3366_clk_init);