drivers/clk/rockchip/clk-rk3036.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/syscore_ops.h>
  23 #include <dt-bindings/clock/rk3036-cru.h>
  24 #include "clk.h"
  25
  26 #define RK3036_GRF_SOC_STATUS0  0x14c
  27
  28 enum rk3036_plls {
  29         apll, dpll, gpll,
  30 };
  31
  32 static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
  33         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  34         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  36         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  37         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  38         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  39         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  40         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  45         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  46         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  47         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  48         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  49         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  50         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  51         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  52         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  53         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  54         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  55         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  56         RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
  57         RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
  58         RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
  59         RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
  60         RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
  61         RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
  62         RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
  63         RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
  64         RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
  65         RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
  66         RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
  67         RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
  68         RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
  69         RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
  70         RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
  71         RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
  72         RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
  73         RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
  74         RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
  75         RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
  76         { /* sentinel */ },
  77 };
  78
  79 #define RK3036_DIV_CPU_MASK             0x1f
  80 #define RK3036_DIV_CPU_SHIFT            8
  81
  82 #define RK3036_DIV_PERI_MASK            0xf
  83 #define RK3036_DIV_PERI_SHIFT           0
  84 #define RK3036_DIV_ACLK_MASK            0x7
  85 #define RK3036_DIV_ACLK_SHIFT           4
  86 #define RK3036_DIV_HCLK_MASK            0x3
  87 #define RK3036_DIV_HCLK_SHIFT           8
  88 #define RK3036_DIV_PCLK_MASK            0x7
  89 #define RK3036_DIV_PCLK_SHIFT           12
  90
  91 #define RK3036_CLKSEL1(_core_periph_div)                                        \
  92         {                                                                       \
  93                 .reg = RK2928_CLKSEL_CON(1),                                    \
  94                 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK,    \
  95                                 RK3036_DIV_PERI_SHIFT)                          \
  96         }
  97
  98 #define RK3036_CPUCLK_RATE(_prate, _core_periph_div)                    \
  99         {                                                               \
 100                 .prate = _prate,                                        \
 101                 .divs = {                                               \
 102                         RK3036_CLKSEL1(_core_periph_div),               \
 103                 },                                                      \
 104         }
 105
 106 static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
 107         RK3036_CPUCLK_RATE(816000000, 4),
 108         RK3036_CPUCLK_RATE(600000000, 4),
 109         RK3036_CPUCLK_RATE(312000000, 4),
 110 };
 111
 112 static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
 113         .core_reg = RK2928_CLKSEL_CON(0),
 114         .div_core_shift = 0,
 115         .div_core_mask = 0x1f,
 116         .mux_core_alt = 1,
 117         .mux_core_main = 0,
 118         .mux_core_shift = 7,
 119         .mux_core_mask = 0x1,
 120 };
 121
 122 PNAME(mux_pll_p)                = { "xin24m", "xin24m" };
 123
 124 PNAME(mux_armclk_p)             = { "apll", "gpll_armclk" };
 125 PNAME(mux_busclk_p)             = { "apll", "dpll_cpu", "gpll_cpu" };
 126 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 127 PNAME(mux_pll_src_3plls_p)      = { "apll", "dpll", "gpll" };
 128 PNAME(mux_timer_p)              = { "xin24m", "pclk_peri_src" };
 129
 130 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)     = { "apll", "dpll", "gpll" "usb480m" };
 131
 132 PNAME(mux_mmc_src_p)    = { "apll", "dpll", "gpll", "xin24m" };
 133 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 134 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 135 PNAME(mux_spdif_p)      = { "spdif_src", "spdif_frac", "xin12m" };
 136 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 137 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 138 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
 139 PNAME(mux_mac_p)        = { "mac_pll_src", "rmii_clkin" };
 140 PNAME(mux_dclk_p)       = { "dclk_lcdc", "dclk_cru" };
 141
 142 static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
 143         [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
 144                      RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
 145         [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
 146                      RK2928_MODE_CON, 4, 4, 0, NULL),
 147         [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
 148                      RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
 149 };
 150
 151 #define MFLAGS CLK_MUX_HIWORD_MASK
 152 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 153 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 154
 155 static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata =
 156         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 157                         RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
 158
 159 static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata =
 160         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 161                         RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
 162
 163 static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata =
 164         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 165                         RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
 166
 167 static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata =
 168         MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 169                         RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
 170
 171 static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata =
 172         MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
 173                         RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
 174
 175 static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 176         /*
 177          * Clock-Architecture Diagram 1
 178          */
 179
 180         GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
 181                         RK2928_CLKGATE_CON(0), 6, GFLAGS),
 182
 183         /*
 184          * Clock-Architecture Diagram 2
 185          */
 186
 187         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 188                         RK2928_CLKGATE_CON(0), 2, GFLAGS),
 189         GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
 190                         RK2928_CLKGATE_CON(0), 8, GFLAGS),
 191         COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 192                         RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 193
 194         COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
 195                         RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 196                         RK2928_CLKGATE_CON(0), 7, GFLAGS),
 197         COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
 198                         RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 199                         RK2928_CLKGATE_CON(0), 7, GFLAGS),
 200
 201         GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
 202         GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
 203         COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
 204                         RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
 205         GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
 206                         RK2928_CLKGATE_CON(0), 3, GFLAGS),
 207         COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
 208                         RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 209                         RK2928_CLKGATE_CON(0), 5, GFLAGS),
 210         COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
 211                         RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
 212                         RK2928_CLKGATE_CON(0), 4, GFLAGS),
 213
 214         COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
 215                         RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
 216                         RK2928_CLKGATE_CON(2), 0, GFLAGS),
 217
 218         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
 219                         RK2928_CLKGATE_CON(2), 1, GFLAGS),
 220         DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
 221                         RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 222         GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
 223                         RK2928_CLKGATE_CON(2), 3, GFLAGS),
 224         DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
 225                         RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 226         GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
 227                         RK2928_CLKGATE_CON(2), 2, GFLAGS),
 228
 229         COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
 230                         RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
 231                         RK2928_CLKGATE_CON(1), 0, GFLAGS),
 232         COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
 233                         RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
 234                         RK2928_CLKGATE_CON(1), 1, GFLAGS),
 235         COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
 236                         RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
 237                         RK2928_CLKGATE_CON(2), 4, GFLAGS),
 238         COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
 239                         RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
 240                         RK2928_CLKGATE_CON(2), 5, GFLAGS),
 241
 242         MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
 243                         RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
 244         COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
 245                         RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
 246                         RK2928_CLKGATE_CON(1), 8, GFLAGS),
 247         COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
 248                         RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
 249                         RK2928_CLKGATE_CON(1), 10, GFLAGS),
 250         COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
 251                         RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
 252                         RK2928_CLKGATE_CON(1), 12, GFLAGS),
 253         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 254                         RK2928_CLKSEL_CON(17), 0,
 255                         RK2928_CLKGATE_CON(1), 9, GFLAGS,
 256                         &rk3036_uart0_fracmux),
 257         COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
 258                         RK2928_CLKSEL_CON(18), 0,
 259                         RK2928_CLKGATE_CON(1), 11, GFLAGS,
 260                         &rk3036_uart1_fracmux),
 261         COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
 262                         RK2928_CLKSEL_CON(19), 0,
 263                         RK2928_CLKGATE_CON(1), 13, GFLAGS,
 264                         &rk3036_uart2_fracmux),
 265
 266         COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
 267                         RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 268                         RK2928_CLKGATE_CON(3), 11, GFLAGS),
 269
 270         COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
 271                         RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
 272                         RK2928_CLKGATE_CON(10), 6, GFLAGS),
 273
 274         COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
 275                         RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 276                         RK2928_CLKGATE_CON(1), 4, GFLAGS),
 277         COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
 278                         RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 279                         RK2928_CLKGATE_CON(0), 11, GFLAGS),
 280         COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
 281                         RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
 282                         RK2928_CLKGATE_CON(3), 2, GFLAGS),
 283
 284         COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
 285                         RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
 286                         RK2928_CLKGATE_CON(2), 11, GFLAGS),
 287         DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
 288                         RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
 289
 290         COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
 291                         RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
 292                         RK2928_CLKGATE_CON(2), 13, GFLAGS),
 293         DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
 294                         RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
 295
 296         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 297                         RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
 298                         RK2928_CLKGATE_CON(2), 14, GFLAGS),
 299
 300         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
 301         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
 302
 303         MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3036_SDIO_CON0, 1),
 304         MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3036_SDIO_CON1, 0),
 305
 306         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3036_EMMC_CON0,  1),
 307         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3036_EMMC_CON1,  0),
 308
 309         COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
 310                         RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
 311                         RK2928_CLKGATE_CON(0), 9, GFLAGS),
 312         COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
 313                         RK2928_CLKSEL_CON(7), 0,
 314                         RK2928_CLKGATE_CON(0), 10, GFLAGS,
 315                         &rk3036_i2s_fracmux),
 316         COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
 317                         RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
 318                         RK2928_CLKGATE_CON(0), 13, GFLAGS),
 319         GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
 320                         RK2928_CLKGATE_CON(0), 14, GFLAGS),
 321
 322         COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
 323                         RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
 324                         RK2928_CLKGATE_CON(2), 10, GFLAGS),
 325         COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
 326                         RK2928_CLKSEL_CON(9), 0,
 327                         RK2928_CLKGATE_CON(2), 12, GFLAGS,
 328                         &rk3036_spdif_fracmux),
 329
 330         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
 331                         RK2928_CLKGATE_CON(1), 5, GFLAGS),
 332
 333         COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
 334                         RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
 335                         RK2928_CLKGATE_CON(3), 13, GFLAGS),
 336
 337         COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
 338                         RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
 339                         RK2928_CLKGATE_CON(2), 9, GFLAGS),
 340
 341         COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
 342                         RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
 343                         RK2928_CLKGATE_CON(10), 4, GFLAGS),
 344
 345         COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
 346                         RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
 347                         RK2928_CLKGATE_CON(10), 5, GFLAGS),
 348
 349         COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
 350                         RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
 351         MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
 352                         RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
 353
 354         COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
 355                         RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
 356                         RK2928_CLKGATE_CON(2), 6, GFLAGS),
 357
 358         MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
 359                         RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
 360
 361         /*
 362          * Clock-Architecture Diagram 3
 363          */
 364
 365         /* aclk_cpu gates */
 366         GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
 367         GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
 368
 369         /* hclk_cpu gates */
 370         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
 371
 372         /* pclk_cpu gates */
 373         GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
 374         GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
 375         GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
 376         GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
 377
 378         /* aclk_vio gates */
 379         GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
 380         GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
 381
 382         GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
 383         GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
 384
 385         /* hclk_video gates */
 386         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
 387
 388         /* xin24m gates */
 389         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
 390         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
 391
 392         /* aclk_peri gates */
 393         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
 394         GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
 395         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
 396         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
 397
 398         /* hclk_peri gates */
 399         GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
 400         GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
 401         GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
 402         GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
 403         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
 404         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
 405         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
 406         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
 407         GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
 408         GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
 409         GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
 410         GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
 411
 412         /* pclk_peri gates */
 413         GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
 414         GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
 415         GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
 416         GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
 417         GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
 418         GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
 419         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
 420         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
 421         GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
 422         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
 423         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
 424         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
 425         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
 426         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
 427         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
 428 };
 429
 430 static const char *const rk3036_critical_clocks[] __initconst = {
 431         "aclk_cpu",
 432         "aclk_peri",
 433         "hclk_peri",
 434         "pclk_peri",
 435 };
 436
 437 static void __init rk3036_clk_init(struct device_node *np)
 438 {
 439         struct rockchip_clk_provider *ctx;
 440         void __iomem *reg_base;
 441         struct clk *clk;
 442
 443         reg_base = of_iomap(np, 0);
 444         if (!reg_base) {
 445                 pr_err("%s: could not map cru region\n", __func__);
 446                 return;
 447         }
 448
 449         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 450         if (IS_ERR(ctx)) {
 451                 pr_err("%s: rockchip clk init failed\n", __func__);
 452                 iounmap(reg_base);
 453                 return;
 454         }
 455
 456         /* xin12m is created by an cru-internal divider */
 457         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 458         if (IS_ERR(clk))
 459                 pr_warn("%s: could not register clock xin12m: %ld\n",
 460                         __func__, PTR_ERR(clk));
 461
 462         clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
 463         if (IS_ERR(clk))
 464                 pr_warn("%s: could not register clock usb480m: %ld\n",
 465                         __func__, PTR_ERR(clk));
 466
 467         clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
 468         if (IS_ERR(clk))
 469                 pr_warn("%s: could not register clock ddrphy: %ld\n",
 470                         __func__, PTR_ERR(clk));
 471
 472         clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
 473                                         "aclk_vcodec", 0, 1, 4);
 474         if (IS_ERR(clk))
 475                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 476                         __func__, PTR_ERR(clk));
 477
 478         clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
 479                                         "hclk_peri_src", 0, 1, 2);
 480         if (IS_ERR(clk))
 481                 pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
 482                         __func__, PTR_ERR(clk));
 483
 484         rockchip_clk_register_plls(ctx, rk3036_pll_clks,
 485                                    ARRAY_SIZE(rk3036_pll_clks),
 486                                    RK3036_GRF_SOC_STATUS0);
 487         rockchip_clk_register_branches(ctx, rk3036_clk_branches,
 488                                   ARRAY_SIZE(rk3036_clk_branches));
 489         rockchip_clk_protect_critical(rk3036_critical_clocks,
 490                                       ARRAY_SIZE(rk3036_critical_clocks));
 491
 492         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 493                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 494                         &rk3036_cpuclk_data, rk3036_cpuclk_rates,
 495                         ARRAY_SIZE(rk3036_cpuclk_rates));
 496
 497         rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
 498                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 499
 500         rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
 501
 502         rockchip_clk_of_add_provider(np, ctx);
 503 }
 504 CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);