drivers/clk/rockchip/clk-ddr.c

   1 /*
   2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/arm-smccc.h>
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/slab.h>
  22 #include <soc/rockchip/rockchip_sip.h>
  23 #include <soc/rockchip/scpi.h>
  24
  25 #include "clk.h"
  26
  27 #define MHZ             (1000000)
  28
  29 struct rockchip_ddrclk {
  30         struct clk_hw   hw;
  31         void __iomem    *reg_base;
  32         int             mux_offset;
  33         int             mux_shift;
  34         int             mux_width;
  35         int             div_shift;
  36         int             div_width;
  37         int             ddr_flag;
  38         spinlock_t      *lock;
  39 };
  40
  41 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
  42
  43 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
  44                                         unsigned long prate)
  45 {
  46         struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
  47         unsigned long flags;
  48         struct arm_smccc_res res;
  49
  50         spin_lock_irqsave(ddrclk->lock, flags);
  51         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
  52                       ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
  53                       0, 0, 0, 0, &res);
  54         spin_unlock_irqrestore(ddrclk->lock, flags);
  55
  56         return res.a0;
  57 }
  58
  59 static unsigned long
  60 rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
  61                                 unsigned long parent_rate)
  62 {
  63         struct arm_smccc_res res;
  64
  65         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
  66                       ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
  67                       0, 0, 0, 0, &res);
  68
  69         return res.a0;
  70 }
  71
  72 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
  73                                            unsigned long rate,
  74                                            unsigned long *prate)
  75 {
  76         struct arm_smccc_res res;
  77
  78         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0,
  79                       ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
  80                       0, 0, 0, 0, &res);
  81
  82         return res.a0;
  83 }
  84
  85 static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
  86 {
  87         struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
  88         int num_parents = clk_hw_get_num_parents(hw);
  89         u32 val;
  90
  91         val = clk_readl(ddrclk->reg_base +
  92                         ddrclk->mux_offset) >> ddrclk->mux_shift;
  93         val &= GENMASK(ddrclk->mux_width - 1, 0);
  94
  95         if (val >= num_parents)
  96                 return -EINVAL;
  97
  98         return val;
  99 }
 100
 101 static const struct clk_ops rockchip_ddrclk_sip_ops = {
 102         .recalc_rate = rockchip_ddrclk_sip_recalc_rate,
 103         .set_rate = rockchip_ddrclk_sip_set_rate,
 104         .round_rate = rockchip_ddrclk_sip_round_rate,
 105         .get_parent = rockchip_ddrclk_get_parent,
 106 };
 107
 108 static u32 ddr_clk_cached;
 109
 110 static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
 111                                          unsigned long prate)
 112 {
 113         u32 ret;
 114         u32 lcdc_type = 7;
 115
 116         ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
 117         if (ret) {
 118                 ddr_clk_cached = ret;
 119                 ret = 0;
 120         } else {
 121                 ddr_clk_cached = 0;
 122                 ret = -1;
 123         }
 124
 125         return ret;
 126 }
 127
 128 static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
 129                                                       unsigned long parent_rate)
 130 {
 131         if (ddr_clk_cached)
 132                 return (MHZ * ddr_clk_cached);
 133         else
 134                 return (MHZ * scpi_ddr_get_clk_rate());
 135 }
 136
 137 static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,
 138                                             unsigned long rate,
 139                                             unsigned long *prate)
 140 {
 141         rate = rate / MHZ;
 142         rate = (rate / 12) * 12;
 143
 144         return (rate * MHZ);
 145 }
 146
 147 static const struct clk_ops rockchip_ddrclk_scpi_ops = {
 148         .recalc_rate = rockchip_ddrclk_scpi_recalc_rate,
 149         .set_rate = rockchip_ddrclk_scpi_set_rate,
 150         .round_rate = rockchip_ddrclk_scpi_round_rate,
 151         .get_parent = rockchip_ddrclk_get_parent,
 152 };
 153
 154 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
 155                                          const char *const *parent_names,
 156                                          u8 num_parents, int mux_offset,
 157                                          int mux_shift, int mux_width,
 158                                          int div_shift, int div_width,
 159                                          int ddr_flag, void __iomem *reg_base,
 160                                          spinlock_t *lock)
 161 {
 162         struct rockchip_ddrclk *ddrclk;
 163         struct clk_init_data init;
 164         struct clk *clk;
 165
 166         ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
 167         if (!ddrclk)
 168                 return ERR_PTR(-ENOMEM);
 169
 170         init.name = name;
 171         init.parent_names = parent_names;
 172         init.num_parents = num_parents;
 173
 174         init.flags = flags;
 175         init.flags |= CLK_SET_RATE_NO_REPARENT;
 176         init.flags |= CLK_GET_RATE_NOCACHE;
 177
 178         switch (ddr_flag) {
 179         case ROCKCHIP_DDRCLK_SIP:
 180                 init.ops = &rockchip_ddrclk_sip_ops;
 181                 break;
 182         case ROCKCHIP_DDRCLK_SCPI:
 183                 init.ops = &rockchip_ddrclk_scpi_ops;
 184                 break;
 185         default:
 186                 pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
 187                 kfree(ddrclk);
 188                 return ERR_PTR(-EINVAL);
 189         }
 190
 191         ddrclk->reg_base = reg_base;
 192         ddrclk->lock = lock;
 193         ddrclk->hw.init = &init;
 194         ddrclk->mux_offset = mux_offset;
 195         ddrclk->mux_shift = mux_shift;
 196         ddrclk->mux_width = mux_width;
 197         ddrclk->div_shift = div_shift;
 198         ddrclk->div_width = div_width;
 199         ddrclk->ddr_flag = ddr_flag;
 200
 201         clk = clk_register(NULL, &ddrclk->hw);
 202         if (IS_ERR(clk)) {
 203                 pr_err("%s: could not register ddrclk %s\n", __func__,  name);
 204                 kfree(ddrclk);
 205                 return NULL;
 206         }
 207
 208         return clk;
 209 }