drm/rockchip: vop: support CRTC_STEREO_DOUBLE mode
[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-ddr.c
1 /*
2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3  * Author: Lin Huang <hl@rock-chips.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/arm-smccc.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/io.h>
20 #include <linux/of.h>
21 #include <linux/slab.h>
22 #include <soc/rockchip/rockchip_sip.h>
23
24 #include "clk.h"
25
26 struct rockchip_ddrclk {
27         struct clk_hw   hw;
28         void __iomem    *reg_base;
29         int             mux_offset;
30         int             mux_shift;
31         int             mux_width;
32         int             div_shift;
33         int             div_width;
34         int             ddr_flag;
35         spinlock_t      *lock;
36 };
37
38 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
39
40 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
41                                         unsigned long prate)
42 {
43         struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
44         unsigned long flags;
45         struct arm_smccc_res res;
46
47         spin_lock_irqsave(ddrclk->lock, flags);
48         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
49                       ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
50                       0, 0, 0, 0, &res);
51         spin_unlock_irqrestore(ddrclk->lock, flags);
52
53         return res.a0;
54 }
55
56 static unsigned long
57 rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
58                                 unsigned long parent_rate)
59 {
60         struct arm_smccc_res res;
61
62         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
63                       ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
64                       0, 0, 0, 0, &res);
65
66         return res.a0;
67 }
68
69 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
70                                            unsigned long rate,
71                                            unsigned long *prate)
72 {
73         struct arm_smccc_res res;
74
75         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0,
76                       ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
77                       0, 0, 0, 0, &res);
78
79         return res.a0;
80 }
81
82 static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
83 {
84         struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
85         int num_parents = clk_hw_get_num_parents(hw);
86         u32 val;
87
88         val = clk_readl(ddrclk->reg_base +
89                         ddrclk->mux_offset) >> ddrclk->mux_shift;
90         val &= GENMASK(ddrclk->mux_width - 1, 0);
91
92         if (val >= num_parents)
93                 return -EINVAL;
94
95         return val;
96 }
97
98 static const struct clk_ops rockchip_ddrclk_sip_ops = {
99         .recalc_rate = rockchip_ddrclk_sip_recalc_rate,
100         .set_rate = rockchip_ddrclk_sip_set_rate,
101         .round_rate = rockchip_ddrclk_sip_round_rate,
102         .get_parent = rockchip_ddrclk_get_parent,
103 };
104
105 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
106                                          const char *const *parent_names,
107                                          u8 num_parents, int mux_offset,
108                                          int mux_shift, int mux_width,
109                                          int div_shift, int div_width,
110                                          int ddr_flag, void __iomem *reg_base,
111                                          spinlock_t *lock)
112 {
113         struct rockchip_ddrclk *ddrclk;
114         struct clk_init_data init;
115         struct clk *clk;
116
117         ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
118         if (!ddrclk)
119                 return ERR_PTR(-ENOMEM);
120
121         init.name = name;
122         init.parent_names = parent_names;
123         init.num_parents = num_parents;
124
125         init.flags = flags;
126         init.flags |= CLK_SET_RATE_NO_REPARENT;
127         init.flags |= CLK_GET_RATE_NOCACHE;
128
129         switch (ddr_flag) {
130         case ROCKCHIP_DDRCLK_SIP:
131                 init.ops = &rockchip_ddrclk_sip_ops;
132                 break;
133         default:
134                 pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
135                 kfree(ddrclk);
136                 return ERR_PTR(-EINVAL);
137         }
138
139         ddrclk->reg_base = reg_base;
140         ddrclk->lock = lock;
141         ddrclk->hw.init = &init;
142         ddrclk->mux_offset = mux_offset;
143         ddrclk->mux_shift = mux_shift;
144         ddrclk->mux_width = mux_width;
145         ddrclk->div_shift = div_shift;
146         ddrclk->div_width = div_width;
147         ddrclk->ddr_flag = ddr_flag;
148
149         clk = clk_register(NULL, &ddrclk->hw);
150         if (IS_ERR(clk)) {
151                 pr_err("%s: could not register ddrclk %s\n", __func__,  name);
152                 kfree(ddrclk);
153                 return NULL;
154         }
155
156         return clk;
157 }