arch/arm64/kernel/cpuinfo.c

   1 /*
   2  * Record and handle CPU attributes.
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <asm/arch_timer.h>
  18 #include <asm/cachetype.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cputype.h>
  21 #include <asm/cpufeature.h>
  22
  23 #include <linux/bitops.h>
  24 #include <linux/bug.h>
  25 #include <linux/compat.h>
  26 #include <linux/elf.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/personality.h>
  30 #include <linux/preempt.h>
  31 #include <linux/printk.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/sched.h>
  34 #include <linux/smp.h>
  35 #include <linux/delay.h>
  36
  37 unsigned int system_serial_low;
  38 EXPORT_SYMBOL(system_serial_low);
  39
  40 unsigned int system_serial_high;
  41 EXPORT_SYMBOL(system_serial_high);
  42
  43 /*
  44  * In case the boot CPU is hotpluggable, we record its initial state and
  45  * current state separately. Certain system registers may contain different
  46  * values depending on configuration at or after reset.
  47  */
  48 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  49 static struct cpuinfo_arm64 boot_cpu_data;
  50
  51 static char *icache_policy_str[] = {
  52         [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
  53         [ICACHE_POLICY_AIVIVT] = "AIVIVT",
  54         [ICACHE_POLICY_VIPT] = "VIPT",
  55         [ICACHE_POLICY_PIPT] = "PIPT",
  56 };
  57
  58 unsigned long __icache_flags;
  59
  60 static const char *const hwcap_str[] = {
  61         "fp",
  62         "asimd",
  63         "evtstrm",
  64         "aes",
  65         "pmull",
  66         "sha1",
  67         "sha2",
  68         "crc32",
  69         "atomics",
  70         NULL
  71 };
  72
  73 #ifdef CONFIG_COMPAT
  74 static const char *const compat_hwcap_str[] = {
  75         "swp",
  76         "half",
  77         "thumb",
  78         "26bit",
  79         "fastmult",
  80         "fpa",
  81         "vfp",
  82         "edsp",
  83         "java",
  84         "iwmmxt",
  85         "crunch",
  86         "thumbee",
  87         "neon",
  88         "vfpv3",
  89         "vfpv3d16",
  90         "tls",
  91         "vfpv4",
  92         "idiva",
  93         "idivt",
  94         "vfpd32",
  95         "lpae",
  96         "evtstrm",
  97         NULL
  98 };
  99
 100 static const char *const compat_hwcap2_str[] = {
 101         "aes",
 102         "pmull",
 103         "sha1",
 104         "sha2",
 105         "crc32",
 106         NULL
 107 };
 108 #endif /* CONFIG_COMPAT */
 109
 110 static int c_show(struct seq_file *m, void *v)
 111 {
 112         int i, j;
 113         bool compat = personality(current->personality) == PER_LINUX32 ||
 114                       is_compat_task();
 115
 116         for_each_online_cpu(i) {
 117                 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
 118                 u32 midr = cpuinfo->reg_midr;
 119
 120                 /*
 121                  * glibc reads /proc/cpuinfo to determine the number of
 122                  * online processors, looking for lines beginning with
 123                  * "processor".  Give glibc what it expects.
 124                  */
 125                 seq_printf(m, "processor\t: %d\n", i);
 126                 if (compat)
 127                         seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
 128                                    MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
 129
 130                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 131                            loops_per_jiffy / (500000UL/HZ),
 132                            loops_per_jiffy / (5000UL/HZ) % 100);
 133
 134                 /*
 135                  * Dump out the common processor features in a single line.
 136                  * Userspace should read the hwcaps with getauxval(AT_HWCAP)
 137                  * rather than attempting to parse this, but there's a body of
 138                  * software which does already (at least for 32-bit).
 139                  */
 140                 seq_puts(m, "Features\t:");
 141                 if (compat) {
 142 #ifdef CONFIG_COMPAT
 143                         for (j = 0; compat_hwcap_str[j]; j++)
 144                                 if (compat_elf_hwcap & (1 << j))
 145                                         seq_printf(m, " %s", compat_hwcap_str[j]);
 146
 147                         for (j = 0; compat_hwcap2_str[j]; j++)
 148                                 if (compat_elf_hwcap2 & (1 << j))
 149                                         seq_printf(m, " %s", compat_hwcap2_str[j]);
 150 #endif /* CONFIG_COMPAT */
 151                 } else {
 152                         for (j = 0; hwcap_str[j]; j++)
 153                                 if (elf_hwcap & (1 << j))
 154                                         seq_printf(m, " %s", hwcap_str[j]);
 155                 }
 156                 seq_puts(m, "\n");
 157
 158                 seq_printf(m, "CPU implementer\t: 0x%02x\n",
 159                            MIDR_IMPLEMENTOR(midr));
 160                 seq_printf(m, "CPU architecture: 8\n");
 161                 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
 162                 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
 163                 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
 164         }
 165
 166         seq_printf(m, "Serial\t\t: %08x%08x\n",
 167                    system_serial_high, system_serial_low);
 168
 169         return 0;
 170 }
 171
 172 static void *c_start(struct seq_file *m, loff_t *pos)
 173 {
 174         return *pos < 1 ? (void *)1 : NULL;
 175 }
 176
 177 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 178 {
 179         ++*pos;
 180         return NULL;
 181 }
 182
 183 static void c_stop(struct seq_file *m, void *v)
 184 {
 185 }
 186
 187 const struct seq_operations cpuinfo_op = {
 188         .start  = c_start,
 189         .next   = c_next,
 190         .stop   = c_stop,
 191         .show   = c_show
 192 };
 193
 194 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 195 {
 196         unsigned int cpu = smp_processor_id();
 197         u32 l1ip = CTR_L1IP(info->reg_ctr);
 198
 199         if (l1ip != ICACHE_POLICY_PIPT) {
 200                 /*
 201                  * VIPT caches are non-aliasing if the VA always equals the PA
 202                  * in all bit positions that are covered by the index. This is
 203                  * the case if the size of a way (# of sets * line size) does
 204                  * not exceed PAGE_SIZE.
 205                  */
 206                 u32 waysize = icache_get_numsets() * icache_get_linesize();
 207
 208                 if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
 209                         set_bit(ICACHEF_ALIASING, &__icache_flags);
 210         }
 211         if (l1ip == ICACHE_POLICY_AIVIVT)
 212                 set_bit(ICACHEF_AIVIVT, &__icache_flags);
 213
 214         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
 215 }
 216
 217 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 218 {
 219         info->reg_cntfrq = arch_timer_get_cntfrq();
 220         info->reg_ctr = read_cpuid_cachetype();
 221         info->reg_dczid = read_cpuid(SYS_DCZID_EL0);
 222         info->reg_midr = read_cpuid_id();
 223
 224         info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1);
 225         info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1);
 226         info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1);
 227         info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1);
 228         info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1);
 229         info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1);
 230         info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1);
 231         info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1);
 232         info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1);
 233
 234         info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1);
 235         info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1);
 236         info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1);
 237         info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1);
 238         info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1);
 239         info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1);
 240         info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1);
 241         info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1);
 242         info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1);
 243         info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1);
 244         info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1);
 245         info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1);
 246         info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1);
 247
 248         info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1);
 249         info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1);
 250         info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1);
 251
 252         cpuinfo_detect_icache_policy(info);
 253
 254         check_local_cpu_errata();
 255 }
 256
 257 void cpuinfo_store_cpu(void)
 258 {
 259         struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
 260         __cpuinfo_store_cpu(info);
 261         update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
 262 }
 263
 264 void __init cpuinfo_store_boot_cpu(void)
 265 {
 266         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
 267         __cpuinfo_store_cpu(info);
 268
 269         boot_cpu_data = *info;
 270         init_cpu_features(&boot_cpu_data);
 271 }