arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb_host0_ehci: usb@fe380000 {
 373                 compatible = "generic-ehci";
 374                 reg = <0x0 0xfe380000 0x0 0x20000>;
 375                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 377                          <&cru SCLK_USBPHY0_480M_SRC>;
 378                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 379                 phys = <&u2phy0_host>;
 380                 phy-names = "usb";
 381                 status = "disabled";
 382         };
 383
 384         usb_host0_ohci: usb@fe3a0000 {
 385                 compatible = "generic-ohci";
 386                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 387                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 389                          <&cru SCLK_USBPHY0_480M_SRC>;
 390                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 391                 phys = <&u2phy0_host>;
 392                 phy-names = "usb";
 393                 status = "disabled";
 394         };
 395
 396         usb_host1_ehci: usb@fe3c0000 {
 397                 compatible = "generic-ehci";
 398                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 399                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 401                          <&cru SCLK_USBPHY1_480M_SRC>;
 402                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 403                 phys = <&u2phy1_host>;
 404                 phy-names = "usb";
 405                 status = "disabled";
 406         };
 407
 408         usb_host1_ohci: usb@fe3e0000 {
 409                 compatible = "generic-ohci";
 410                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 411                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 413                          <&cru SCLK_USBPHY1_480M_SRC>;
 414                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 415                 phys = <&u2phy1_host>;
 416                 phy-names = "usb";
 417                 status = "disabled";
 418         };
 419
 420         usbdrd3_0: usb@fe800000 {
 421                 compatible = "rockchip,dwc3";
 422                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 423                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 424                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 425                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 426                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 427                               "aclk_usb3", "aclk_usb3_grf";
 428                 #address-cells = <2>;
 429                 #size-cells = <2>;
 430                 ranges;
 431                 status = "disabled";
 432                 usbdrd_dwc3_0: dwc3@fe800000 {
 433                         compatible = "snps,dwc3";
 434                         reg = <0x0 0xfe800000 0x0 0x100000>;
 435                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 436                         dr_mode = "otg";
 437                         snps,dis_enblslpm_quirk;
 438                         snps,phyif_utmi_16_bits;
 439                         snps,dis_u2_freeclk_exists_quirk;
 440                         snps,dis_del_phy_power_chg_quirk;
 441                         snps,xhci_slow_suspend_quirk;
 442                         status = "disabled";
 443                 };
 444         };
 445
 446         usbdrd3_1: usb@fe900000 {
 447                 compatible = "rockchip,dwc3";
 448                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 449                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 450                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 451                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 452                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 453                               "aclk_usb3", "aclk_usb3_grf";
 454                 #address-cells = <2>;
 455                 #size-cells = <2>;
 456                 ranges;
 457                 status = "disabled";
 458                 usbdrd_dwc3_1: dwc3@fe900000 {
 459                         compatible = "snps,dwc3";
 460                         reg = <0x0 0xfe900000 0x0 0x100000>;
 461                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 462                         dr_mode = "otg";
 463                         snps,dis_enblslpm_quirk;
 464                         snps,phyif_utmi_16_bits;
 465                         snps,dis_u2_freeclk_exists_quirk;
 466                         snps,dis_del_phy_power_chg_quirk;
 467                         snps,xhci_slow_suspend_quirk;
 468                         status = "disabled";
 469                 };
 470         };
 471
 472         gic: interrupt-controller@fee00000 {
 473                 compatible = "arm,gic-v3";
 474                 #interrupt-cells = <3>;
 475                 #address-cells = <2>;
 476                 #size-cells = <2>;
 477                 ranges;
 478                 interrupt-controller;
 479
 480                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 481                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 482                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 483                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 484                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 485                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 486                 its: interrupt-controller@fee20000 {
 487                         compatible = "arm,gic-v3-its";
 488                         msi-controller;
 489                         reg = <0x0 0xfee20000 0x0 0x20000>;
 490                 };
 491         };
 492
 493         saradc: saradc@ff100000 {
 494                 compatible = "rockchip,rk3399-saradc";
 495                 reg = <0x0 0xff100000 0x0 0x100>;
 496                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 497                 #io-channel-cells = <1>;
 498                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 499                 clock-names = "saradc", "apb_pclk";
 500                 status = "disabled";
 501         };
 502
 503         i2c0: i2c@ff3c0000 {
 504                 compatible = "rockchip,rk3399-i2c";
 505                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 506                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 507                 clock-names = "i2c", "pclk";
 508                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&i2c0_xfer>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 status = "disabled";
 514         };
 515
 516         i2c1: i2c@ff110000 {
 517                 compatible = "rockchip,rk3399-i2c";
 518                 reg = <0x0 0xff110000 0x0 0x1000>;
 519                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 520                 clock-names = "i2c", "pclk";
 521                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&i2c1_xfer>;
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 status = "disabled";
 527         };
 528
 529         i2c2: i2c@ff120000 {
 530                 compatible = "rockchip,rk3399-i2c";
 531                 reg = <0x0 0xff120000 0x0 0x1000>;
 532                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c2_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c3: i2c@ff130000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff130000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 546                 clock-names = "i2c", "pclk";
 547                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c3_xfer>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         i2c5: i2c@ff140000 {
 556                 compatible = "rockchip,rk3399-i2c";
 557                 reg = <0x0 0xff140000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c5_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c6: i2c@ff150000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff150000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c6_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c7: i2c@ff160000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff160000 0x0 0x1000>;
 584                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c7_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         uart0: serial@ff180000 {
 595                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 596                 reg = <0x0 0xff180000 0x0 0x100>;
 597                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 598                 clock-names = "baudclk", "apb_pclk";
 599                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 600                 reg-shift = <2>;
 601                 reg-io-width = <4>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 604                 status = "disabled";
 605         };
 606
 607         uart1: serial@ff190000 {
 608                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 609                 reg = <0x0 0xff190000 0x0 0x100>;
 610                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 611                 clock-names = "baudclk", "apb_pclk";
 612                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 613                 reg-shift = <2>;
 614                 reg-io-width = <4>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart1_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         uart2: serial@ff1a0000 {
 621                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff1a0000 0x0 0x100>;
 623                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 624                 clock-names = "baudclk", "apb_pclk";
 625                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 626                 reg-shift = <2>;
 627                 reg-io-width = <4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&uart2c_xfer>;
 630                 status = "disabled";
 631         };
 632
 633         uart3: serial@ff1b0000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff1b0000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 643                 status = "disabled";
 644         };
 645
 646         spi0: spi@ff1c0000 {
 647                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 648                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 649                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 650                 clock-names = "spiclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 status = "disabled";
 657         };
 658
 659         spi1: spi@ff1d0000 {
 660                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 661                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 662                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 663                 clock-names = "spiclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 status = "disabled";
 670         };
 671
 672         spi2: spi@ff1e0000 {
 673                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 674                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 675                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 676                 clock-names = "spiclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         spi4: spi@ff1f0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         spi5: spi@ff200000 {
 699                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 700                 reg = <0x0 0xff200000 0x0 0x1000>;
 701                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 702                 clock-names = "spiclk", "apb_pclk";
 703                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 status = "disabled";
 709         };
 710
 711         thermal-zones {
 712                 soc_thermal: soc-thermal {
 713                         polling-delay-passive = <20>; /* milliseconds */
 714                         polling-delay = <1000>; /* milliseconds */
 715                         sustainable-power = <1600>; /* milliwatts */
 716
 717                         thermal-sensors = <&tsadc 0>;
 718
 719                         trips {
 720                                 threshold: trip-point@0 {
 721                                         temperature = <70000>; /* millicelsius */
 722                                         hysteresis = <2000>; /* millicelsius */
 723                                         type = "passive";
 724                                 };
 725                                 target: trip-point@1 {
 726                                         temperature = <85000>; /* millicelsius */
 727                                         hysteresis = <2000>; /* millicelsius */
 728                                         type = "passive";
 729                                 };
 730                                 soc_crit: soc-crit {
 731                                         temperature = <95000>; /* millicelsius */
 732                                         hysteresis = <2000>; /* millicelsius */
 733                                         type = "critical";
 734                                 };
 735                         };
 736
 737                         cooling-maps {
 738                                 map0 {
 739                                         trip = <&target>;
 740                                         cooling-device =
 741                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 742                                         contribution = <10240>;
 743                                 };
 744                                 map1 {
 745                                         trip = <&target>;
 746                                         cooling-device =
 747                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 748                                         contribution = <1024>;
 749                                 };
 750                                 map2 {
 751                                         trip = <&target>;
 752                                         cooling-device =
 753                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 754                                         contribution = <10240>;
 755                                 };
 756                         };
 757                 };
 758
 759                 gpu_thermal: gpu-thermal {
 760                         polling-delay-passive = <100>; /* milliseconds */
 761                         polling-delay = <1000>; /* milliseconds */
 762
 763                         thermal-sensors = <&tsadc 1>;
 764                 };
 765         };
 766
 767         tsadc: tsadc@ff260000 {
 768                 compatible = "rockchip,rk3399-tsadc";
 769                 reg = <0x0 0xff260000 0x0 0x100>;
 770                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 771                 rockchip,grf = <&grf>;
 772                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 773                 clock-names = "tsadc", "apb_pclk";
 774                 assigned-clocks = <&cru SCLK_TSADC>;
 775                 assigned-clock-rates = <750000>;
 776                 resets = <&cru SRST_TSADC>;
 777                 reset-names = "tsadc-apb";
 778                 pinctrl-names = "init", "default", "sleep";
 779                 pinctrl-0 = <&otp_gpio>;
 780                 pinctrl-1 = <&otp_out>;
 781                 pinctrl-2 = <&otp_gpio>;
 782                 #thermal-sensor-cells = <1>;
 783                 rockchip,hw-tshut-temp = <95000>;
 784                 status = "disabled";
 785         };
 786
 787         qos_hdcp: qos@ffa90000 {
 788                 compatible = "syscon";
 789                 reg = <0x0 0xffa90000 0x0 0x20>;
 790         };
 791
 792         qos_iep: qos@ffa98000 {
 793                 compatible = "syscon";
 794                 reg = <0x0 0xffa98000 0x0 0x20>;
 795         };
 796
 797         qos_isp0_m0: qos@ffaa0000 {
 798                 compatible = "syscon";
 799                 reg = <0x0 0xffaa0000 0x0 0x20>;
 800         };
 801
 802         qos_isp0_m1: qos@ffaa0080 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffaa0080 0x0 0x20>;
 805         };
 806
 807         qos_isp1_m0: qos@ffaa8000 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffaa8000 0x0 0x20>;
 810         };
 811
 812         qos_isp1_m1: qos@ffaa8080 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffaa8080 0x0 0x20>;
 815         };
 816
 817         qos_rga_r: qos@ffab0000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffab0000 0x0 0x20>;
 820         };
 821
 822         qos_rga_w: qos@ffab0080 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffab0080 0x0 0x20>;
 825         };
 826
 827         qos_video_m0: qos@ffab8000 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffab8000 0x0 0x20>;
 830         };
 831
 832         qos_video_m1_r: qos@ffac0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffac0000 0x0 0x20>;
 835         };
 836
 837         qos_video_m1_w: qos@ffac0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffac0080 0x0 0x20>;
 840         };
 841
 842         qos_vop_big_r: qos@ffac8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffac8000 0x0 0x20>;
 845         };
 846
 847         qos_vop_big_w: qos@ffac8080 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffac8080 0x0 0x20>;
 850         };
 851
 852         qos_vop_little: qos@ffad0000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffad0000 0x0 0x20>;
 855         };
 856
 857         qos_gpu: qos@ffae0000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffae0000 0x0 0x20>;
 860         };
 861
 862         pmu: power-management@ff310000 {
 863                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 864                 reg = <0x0 0xff310000 0x0 0x1000>;
 865
 866                 /*
 867                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 868                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 869                  * Some of the power domains are grouped together for every
 870                  * voltage domain.
 871                  * The detail contents as below.
 872                  */
 873                 power: power-controller {
 874                         compatible = "rockchip,rk3399-power-controller";
 875                         #power-domain-cells = <1>;
 876                         #address-cells = <1>;
 877                         #size-cells = <0>;
 878
 879                         /* These power domains are grouped by VD_CENTER */
 880                         pd_iep@RK3399_PD_IEP {
 881                                 reg = <RK3399_PD_IEP>;
 882                                 clocks = <&cru ACLK_IEP>,
 883                                          <&cru HCLK_IEP>;
 884                                 pm_qos = <&qos_iep>;
 885                         };
 886                         pd_rga@RK3399_PD_RGA {
 887                                 reg = <RK3399_PD_RGA>;
 888                                 clocks = <&cru ACLK_RGA>,
 889                                          <&cru HCLK_RGA>;
 890                                 pm_qos = <&qos_rga_r>,
 891                                          <&qos_rga_w>;
 892                         };
 893                         pd_vcodec@RK3399_PD_VCODEC {
 894                                 reg = <RK3399_PD_VCODEC>;
 895                                 clocks = <&cru ACLK_VCODEC>,
 896                                          <&cru HCLK_VCODEC>;
 897                                 pm_qos = <&qos_video_m0>;
 898                         };
 899                         pd_vdu@RK3399_PD_VDU {
 900                                 reg = <RK3399_PD_VDU>;
 901                                 clocks = <&cru ACLK_VDU>,
 902                                          <&cru HCLK_VDU>;
 903                                 pm_qos = <&qos_video_m1_r>,
 904                                          <&qos_video_m1_w>;
 905                         };
 906
 907                         /* These power domains are grouped by VD_GPU */
 908                         pd_gpu@RK3399_PD_GPU {
 909                                 reg = <RK3399_PD_GPU>;
 910                                 clocks = <&cru ACLK_GPU>;
 911                                 pm_qos = <&qos_gpu>;
 912                         };
 913
 914                         /* These power domains are grouped by VD_LOGIC */
 915                         pd_vio@RK3399_PD_VIO {
 916                                 reg = <RK3399_PD_VIO>;
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919
 920                                 pd_hdcp@RK3399_PD_HDCP {
 921                                         reg = <RK3399_PD_HDCP>;
 922                                         clocks = <&cru ACLK_HDCP>,
 923                                                  <&cru HCLK_HDCP>,
 924                                                  <&cru PCLK_HDCP>;
 925                                         pm_qos = <&qos_hdcp>;
 926                                 };
 927                                 pd_isp0@RK3399_PD_ISP0 {
 928                                         reg = <RK3399_PD_ISP0>;
 929                                         clocks = <&cru ACLK_ISP0>,
 930                                                  <&cru HCLK_ISP0>;
 931                                         pm_qos = <&qos_isp0_m0>,
 932                                                  <&qos_isp0_m1>;
 933                                 };
 934                                 pd_isp1@RK3399_PD_ISP1 {
 935                                         reg = <RK3399_PD_ISP1>;
 936                                         clocks = <&cru ACLK_ISP1>,
 937                                                  <&cru HCLK_ISP1>;
 938                                         pm_qos = <&qos_isp1_m0>,
 939                                                  <&qos_isp1_m1>;
 940                                 };
 941                                 pd_vo@RK3399_PD_VO {
 942                                         reg = <RK3399_PD_VO>;
 943                                         #address-cells = <1>;
 944                                         #size-cells = <0>;
 945
 946                                         pd_vopb@RK3399_PD_VOPB {
 947                                                 reg = <RK3399_PD_VOPB>;
 948                                                 clocks = <&cru ACLK_VOP0>,
 949                                                          <&cru HCLK_VOP0>;
 950                                                 pm_qos = <&qos_vop_big_r>,
 951                                                          <&qos_vop_big_w>;
 952                                         };
 953                                         pd_vopl@RK3399_PD_VOPL {
 954                                                 reg = <RK3399_PD_VOPL>;
 955                                                 clocks = <&cru ACLK_VOP1>,
 956                                                          <&cru HCLK_VOP1>;
 957                                                 pm_qos = <&qos_vop_little>;
 958                                         };
 959                                 };
 960                         };
 961                 };
 962         };
 963
 964         pmugrf: syscon@ff320000 {
 965                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 966                 reg = <0x0 0xff320000 0x0 0x1000>;
 967
 968                 reboot-mode {
 969                         compatible = "syscon-reboot-mode";
 970                         offset = <0x300>;
 971                         mode-normal = <BOOT_NORMAL>;
 972                         mode-recovery = <BOOT_RECOVERY>;
 973                         mode-bootloader = <BOOT_FASTBOOT>;
 974                         mode-loader = <BOOT_LOADER>;
 975                 };
 976         };
 977
 978         spi3: spi@ff350000 {
 979                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 980                 reg = <0x0 0xff350000 0x0 0x1000>;
 981                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 982                 clock-names = "spiclk", "apb_pclk";
 983                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 984                 pinctrl-names = "default";
 985                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 986                 #address-cells = <1>;
 987                 #size-cells = <0>;
 988                 status = "disabled";
 989         };
 990
 991         uart4: serial@ff370000 {
 992                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 993                 reg = <0x0 0xff370000 0x0 0x100>;
 994                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 995                 clock-names = "baudclk", "apb_pclk";
 996                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 997                 reg-shift = <2>;
 998                 reg-io-width = <4>;
 999                 pinctrl-names = "default";
1000                 pinctrl-0 = <&uart4_xfer>;
1001                 status = "disabled";
1002         };
1003
1004         i2c4: i2c@ff3d0000 {
1005                 compatible = "rockchip,rk3399-i2c";
1006                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1007                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1008                 clock-names = "i2c", "pclk";
1009                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1010                 pinctrl-names = "default";
1011                 pinctrl-0 = <&i2c4_xfer>;
1012                 #address-cells = <1>;
1013                 #size-cells = <0>;
1014                 status = "disabled";
1015         };
1016
1017         i2c8: i2c@ff3e0000 {
1018                 compatible = "rockchip,rk3399-i2c";
1019                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1020                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1021                 clock-names = "i2c", "pclk";
1022                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1023                 pinctrl-names = "default";
1024                 pinctrl-0 = <&i2c8_xfer>;
1025                 #address-cells = <1>;
1026                 #size-cells = <0>;
1027                 status = "disabled";
1028         };
1029
1030         pcie0: pcie@f8000000 {
1031                 compatible = "rockchip,rk3399-pcie";
1032                 #address-cells = <3>;
1033                 #size-cells = <2>;
1034                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1035                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1036                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1037                               "hclk_pcie", "clk_pciephy_ref";
1038                 bus-range = <0x0 0x1>;
1039                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1041                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1042                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1043                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1044                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1045                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1046                       < 0x0 0xfd000000 0x0 0x1000000 >;
1047                 reg-name = "axi-base", "apb-base";
1048                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1049                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1050                          <&cru SRST_PCIE_PIPE>;
1051                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1052                               "mgmt-sticky-rst", "pipe-rst";
1053                 rockchip,grf = <&grf>;
1054                 pcie-conf = <0xe220>;
1055                 pcie-status = <0xe2a4>;
1056                 pcie-laneoff = <0xe214>;
1057                 msi-parent = <&its>;
1058                 #interrupt-cells = <1>;
1059                 interrupt-map-mask = <0 0 0 7>;
1060                 interrupt-map = <0 0 0 1 &pcie0 1>,
1061                                 <0 0 0 2 &pcie0 2>,
1062                                 <0 0 0 3 &pcie0 3>,
1063                                 <0 0 0 4 &pcie0 4>;
1064                 status = "disabled";
1065                 pcie_intc: interrupt-controller {
1066                         interrupt-controller;
1067                         #address-cells = <0>;
1068                         #interrupt-cells = <1>;
1069                 };
1070         };
1071
1072         pwm0: pwm@ff420000 {
1073                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1074                 reg = <0x0 0xff420000 0x0 0x10>;
1075                 #pwm-cells = <3>;
1076                 pinctrl-names = "default";
1077                 pinctrl-0 = <&pwm0_pin>;
1078                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1079                 clock-names = "pwm";
1080                 status = "disabled";
1081         };
1082
1083         pwm1: pwm@ff420010 {
1084                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1085                 reg = <0x0 0xff420010 0x0 0x10>;
1086                 #pwm-cells = <3>;
1087                 pinctrl-names = "default";
1088                 pinctrl-0 = <&pwm1_pin>;
1089                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1090                 clock-names = "pwm";
1091                 status = "disabled";
1092         };
1093
1094         pwm2: pwm@ff420020 {
1095                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1096                 reg = <0x0 0xff420020 0x0 0x10>;
1097                 #pwm-cells = <3>;
1098                 pinctrl-names = "default";
1099                 pinctrl-0 = <&pwm2_pin>;
1100                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1101                 clock-names = "pwm";
1102                 status = "disabled";
1103         };
1104
1105         pwm3: pwm@ff420030 {
1106                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1107                 reg = <0x0 0xff420030 0x0 0x10>;
1108                 #pwm-cells = <3>;
1109                 pinctrl-names = "default";
1110                 pinctrl-0 = <&pwm3a_pin>;
1111                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1112                 clock-names = "pwm";
1113                 status = "disabled";
1114         };
1115
1116         rga: rga@ff680000 {
1117                 compatible = "rockchip,rk3399-rga";
1118                 reg = <0x0 0xff680000 0x0 0x10000>;
1119                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1120                 interrupt-names = "rga";
1121                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1122                 clock-names = "aclk", "hclk", "sclk";
1123                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1124                 reset-names = "core", "axi", "ahb";
1125                 status = "disabled";
1126         };
1127
1128         pmucru: pmu-clock-controller@ff750000 {
1129                 compatible = "rockchip,rk3399-pmucru";
1130                 reg = <0x0 0xff750000 0x0 0x1000>;
1131                 #clock-cells = <1>;
1132                 #reset-cells = <1>;
1133                 assigned-clocks = <&pmucru PLL_PPLL>;
1134                 assigned-clock-rates = <676000000>;
1135         };
1136
1137         cru: clock-controller@ff760000 {
1138                 compatible = "rockchip,rk3399-cru";
1139                 reg = <0x0 0xff760000 0x0 0x1000>;
1140                 #clock-cells = <1>;
1141                 #reset-cells = <1>;
1142                 assigned-clocks =
1143                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1144                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1145                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1146                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1147                         <&cru PLL_NPLL>,
1148                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1149                         <&cru PCLK_PERIHP>,
1150                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1151                         <&cru PCLK_PERILP0>,
1152                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1153                 assigned-clock-rates =
1154                          <400000000>,  <200000000>,
1155                          <400000000>,  <200000000>,
1156                          <816000000>, <816000000>,
1157                          <594000000>,  <800000000>,
1158                         <1000000000>,
1159                          <150000000>,   <75000000>,
1160                           <37500000>,
1161                          <100000000>,  <100000000>,
1162                           <50000000>,
1163                          <100000000>,   <50000000>;
1164         };
1165
1166         grf: syscon@ff770000 {
1167                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1168                 reg = <0x0 0xff770000 0x0 0x10000>;
1169                 #address-cells = <1>;
1170                 #size-cells = <1>;
1171
1172                 u2phy0: usb2-phy@e450 {
1173                         compatible = "rockchip,rk3399-usb2phy";
1174                         reg = <0xe450 0x10>;
1175                         clocks = <&cru SCLK_USB2PHY0_REF>;
1176                         clock-names = "phyclk";
1177                         #clock-cells = <0>;
1178                         clock-output-names = "clk_usbphy0_480m";
1179                         status = "disabled";
1180
1181                         u2phy0_otg: otg-port {
1182                                 #phy-cells = <0>;
1183                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1184                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1185                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1186                                 interrupt-names = "otg-bvalid", "otg-id",
1187                                                   "linestate";
1188                                 status = "disabled";
1189                         };
1190
1191                         u2phy0_host: host-port {
1192                                 #phy-cells = <0>;
1193                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1194                                 interrupt-names = "linestate";
1195                                 status = "disabled";
1196                         };
1197                 };
1198
1199                 u2phy1: usb2-phy@e460 {
1200                         compatible = "rockchip,rk3399-usb2phy";
1201                         reg = <0xe460 0x10>;
1202                         clocks = <&cru SCLK_USB2PHY1_REF>;
1203                         clock-names = "phyclk";
1204                         #clock-cells = <0>;
1205                         clock-output-names = "clk_usbphy1_480m";
1206                         status = "disabled";
1207
1208                         u2phy1_host: host-port {
1209                                 #phy-cells = <0>;
1210                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1211                                 interrupt-names = "linestate";
1212                                 status = "disabled";
1213                         };
1214                 };
1215         };
1216
1217         tcphy0: phy@ff7c0000 {
1218                 compatible = "rockchip,rk3399-typec-phy";
1219                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1220                 rockchip,grf = <&grf>;
1221                 #phy-cells = <0>;
1222                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1223                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1224                 clock-names = "tcpdcore", "tcpdphy-ref";
1225                 resets = <&cru SRST_UPHY0>,
1226                          <&cru SRST_UPHY0_PIPE_L00>,
1227                          <&cru SRST_P_UPHY0_TCPHY>;
1228                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1229                 rockchip,typec-conn-dir = <0xe580 0 16>;
1230                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1231                 rockchip,external-psm = <0xe588 14 30>;
1232                 rockchip,pipe-status = <0xe5c0 0 0>;
1233                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1234                 status = "disabled";
1235         };
1236
1237         tcphy1: phy@ff800000 {
1238                 compatible = "rockchip,rk3399-typec-phy";
1239                 reg = <0x0 0xff800000 0x0 0x40000>;
1240                 rockchip,grf = <&grf>;
1241                 #phy-cells = <0>;
1242                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1243                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1244                 clock-names = "tcpdcore", "tcpdphy-ref";
1245                 resets = <&cru SRST_UPHY1>,
1246                          <&cru SRST_UPHY1_PIPE_L00>,
1247                          <&cru SRST_P_UPHY1_TCPHY>;
1248                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1249                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1250                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1251                 rockchip,external-psm = <0xe594 14 30>;
1252                 rockchip,pipe-status = <0xe5c0 16 16>;
1253                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1254                 status = "disabled";
1255         };
1256
1257         watchdog@ff840000 {
1258                 compatible = "snps,dw-wdt";
1259                 reg = <0x0 0xff840000 0x0 0x100>;
1260                 clocks = <&cru PCLK_WDT>;
1261                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1262         };
1263
1264         rktimer: rktimer@ff850000 {
1265                 compatible = "rockchip,rk3399-timer";
1266                 reg = <0x0 0xff850000 0x0 0x1000>;
1267                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1268                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1269                 clock-names = "pclk", "timer";
1270         };
1271
1272         spdif: spdif@ff870000 {
1273                 compatible = "rockchip,rk3399-spdif";
1274                 reg = <0x0 0xff870000 0x0 0x1000>;
1275                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1276                 dmas = <&dmac_bus 7>;
1277                 dma-names = "tx";
1278                 clock-names = "mclk", "hclk";
1279                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1280                 pinctrl-names = "default";
1281                 pinctrl-0 = <&spdif_bus>;
1282                 status = "disabled";
1283         };
1284
1285         i2s0: i2s@ff880000 {
1286                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1287                 reg = <0x0 0xff880000 0x0 0x1000>;
1288                 rockchip,grf = <&grf>;
1289                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1290                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1291                 dma-names = "tx", "rx";
1292                 clock-names = "i2s_clk", "i2s_hclk";
1293                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1294                 pinctrl-names = "default";
1295                 pinctrl-0 = <&i2s0_8ch_bus>;
1296                 status = "disabled";
1297         };
1298
1299         i2s1: i2s@ff890000 {
1300                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1301                 reg = <0x0 0xff890000 0x0 0x1000>;
1302                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1303                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1304                 dma-names = "tx", "rx";
1305                 clock-names = "i2s_clk", "i2s_hclk";
1306                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1307                 pinctrl-names = "default";
1308                 pinctrl-0 = <&i2s1_2ch_bus>;
1309                 status = "disabled";
1310         };
1311
1312         i2s2: i2s@ff8a0000 {
1313                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1314                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1315                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1316                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1317                 dma-names = "tx", "rx";
1318                 clock-names = "i2s_clk", "i2s_hclk";
1319                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1320                 status = "disabled";
1321         };
1322
1323         gpu: gpu@ff9a0000 {
1324                 compatible = "arm,malit860",
1325                              "arm,malit86x",
1326                              "arm,malit8xx",
1327                              "arm,mali-midgard";
1328
1329                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1330
1331                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1332                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1333                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1334                 interrupt-names = "GPU", "JOB", "MMU";
1335
1336                 clocks = <&cru ACLK_GPU>;
1337                 clock-names = "clk_mali";
1338                 #cooling-cells = <2>; /* min followed by max */
1339                 operating-points-v2 = <&gpu_opp_table>;
1340                 power-domains = <&power RK3399_PD_GPU>;
1341                 power-off-delay-ms = <200>;
1342                 status = "disabled";
1343
1344                 power_model {
1345                         compatible = "arm,mali-simple-power-model";
1346                         voltage = <900>;
1347                         frequency = <500>;
1348                         static-power = <300>;
1349                         dynamic-power = <1780>;
1350                         ts = <32000 4700 (-80) 2>;
1351                         thermal-zone = "gpu-thermal";
1352                 };
1353         };
1354
1355         gpu_opp_table: gpu_opp_table {
1356                 compatible = "operating-points-v2";
1357                 opp-shared;
1358
1359                 opp@200000000 {
1360                         opp-hz = /bits/ 64 <200000000>;
1361                         opp-microvolt = <900000>;
1362                 };
1363                 opp@300000000 {
1364                         opp-hz = /bits/ 64 <300000000>;
1365                         opp-microvolt = <900000>;
1366                 };
1367                 opp@400000000 {
1368                         opp-hz = /bits/ 64 <400000000>;
1369                         opp-microvolt = <900000>;
1370                 };
1371
1372         };
1373
1374         vopl: vop@ff8f0000 {
1375                 compatible = "rockchip,rk3399-vop-lit";
1376                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1377                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1378                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1379                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1380                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1381                 reset-names = "axi", "ahb", "dclk";
1382                 power-domains = <&power RK3399_PD_VOPL>;
1383                 iommus = <&vopl_mmu>;
1384                 status = "disabled";
1385
1386                 vopl_out: port {
1387                         #address-cells = <1>;
1388                         #size-cells = <0>;
1389
1390                         vopl_out_mipi: endpoint@0 {
1391                                 reg = <0>;
1392                                 remote-endpoint = <&mipi_in_vopl>;
1393                         };
1394
1395                         vopl_out_edp: endpoint@1 {
1396                                 reg = <1>;
1397                                 remote-endpoint = <&edp_in_vopl>;
1398                         };
1399
1400                         vopl_out_hdmi: endpoint@2 {
1401                                 reg = <2>;
1402                                 remote-endpoint = <&hdmi_in_vopl>;
1403                         };
1404                 };
1405         };
1406
1407         vopl_mmu: iommu@ff8f3f00 {
1408                 compatible = "rockchip,iommu";
1409                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1410                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1411                 interrupt-names = "vopl_mmu";
1412                 #iommu-cells = <0>;
1413                 status = "disabled";
1414         };
1415
1416         vopb: vop@ff900000 {
1417                 compatible = "rockchip,rk3399-vop-big";
1418                 reg = <0x0 0xff900000 0x0 0x3efc>;
1419                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1420                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1421                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1422                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1423                 reset-names = "axi", "ahb", "dclk";
1424                 power-domains = <&power RK3399_PD_VOPB>;
1425                 iommus = <&vopb_mmu>;
1426                 status = "disabled";
1427
1428                 vopb_out: port {
1429                         #address-cells = <1>;
1430                         #size-cells = <0>;
1431
1432                         vopb_out_edp: endpoint@0 {
1433                                 reg = <0>;
1434                                 remote-endpoint = <&edp_in_vopb>;
1435                         };
1436
1437                         vopb_out_mipi: endpoint@1 {
1438                                 reg = <1>;
1439                                 remote-endpoint = <&mipi_in_vopb>;
1440                         };
1441
1442                         vopb_out_hdmi: endpoint@2 {
1443                                 reg = <2>;
1444                                 remote-endpoint = <&hdmi_in_vopb>;
1445                         };
1446                 };
1447         };
1448
1449         vopb_mmu: iommu@ff903f00 {
1450                 compatible = "rockchip,iommu";
1451                 reg = <0x0 0xff903f00 0x0 0x100>;
1452                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1453                 interrupt-names = "vopb_mmu";
1454                 #iommu-cells = <0>;
1455                 status = "disabled";
1456         };
1457
1458         hdmi: hdmi@ff940000 {
1459                 compatible = "rockchip,rk3399-dw-hdmi";
1460                 reg = <0x0 0xff940000 0x0 0x20000>;
1461                 reg-io-width = <4>;
1462                 rockchip,grf = <&grf>;
1463                 power-domains = <&power RK3399_PD_HDCP>;
1464                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1465                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1466                 clock-names = "iahb", "isfr", "vpll", "grf";
1467                 status = "disabled";
1468
1469                 ports {
1470                         hdmi_in: port {
1471                                 #address-cells = <1>;
1472                                 #size-cells = <0>;
1473                                 hdmi_in_vopb: endpoint@0 {
1474                                         reg = <0>;
1475                                         remote-endpoint = <&vopb_out_hdmi>;
1476                                 };
1477                                 hdmi_in_vopl: endpoint@1 {
1478                                         reg = <1>;
1479                                         remote-endpoint = <&vopl_out_hdmi>;
1480                                 };
1481                         };
1482                 };
1483         };
1484
1485         mipi_dsi: mipi@ff960000 {
1486                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1487                 reg = <0x0 0xff960000 0x0 0x8000>;
1488                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1489                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1490                          <&cru SCLK_DPHY_TX0_CFG>;
1491                 clock-names = "ref", "pclk", "phy_cfg";
1492                 power-domains = <&power RK3399_PD_VIO>;
1493                 rockchip,grf = <&grf>;
1494                 #address-cells = <1>;
1495                 #size-cells = <0>;
1496                 status = "disabled";
1497
1498                 ports {
1499                         #address-cells = <1>;
1500                         #size-cells = <0>;
1501                         reg = <1>;
1502
1503                         mipi_in: port {
1504                                 #address-cells = <1>;
1505                                 #size-cells = <0>;
1506
1507                                 mipi_in_vopb: endpoint@0 {
1508                                         reg = <0>;
1509                                         remote-endpoint = <&vopb_out_mipi>;
1510                                 };
1511                                 mipi_in_vopl: endpoint@1 {
1512                                         reg = <1>;
1513                                         remote-endpoint = <&vopl_out_mipi>;
1514                                 };
1515                         };
1516                 };
1517         };
1518
1519         edp: edp@ff970000 {
1520                 compatible = "rockchip,rk3399-edp";
1521                 reg = <0x0 0xff970000 0x0 0x8000>;
1522                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1523                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1524                 clock-names = "dp", "pclk";
1525                 resets = <&cru SRST_P_EDP_CTRL>;
1526                 reset-names = "dp";
1527                 rockchip,grf = <&grf>;
1528                 status = "disabled";
1529                 pinctrl-names = "default";
1530                 pinctrl-0 = <&edp_hpd>;
1531
1532                 ports {
1533                         #address-cells = <1>;
1534                         #size-cells = <0>;
1535
1536                         edp_in: port@0 {
1537                                 reg = <0>;
1538                                 #address-cells = <1>;
1539                                 #size-cells = <0>;
1540
1541                                 edp_in_vopb: endpoint@0 {
1542                                         reg = <0>;
1543                                         remote-endpoint = <&vopb_out_edp>;
1544                                 };
1545
1546                                 edp_in_vopl: endpoint@1 {
1547                                         reg = <1>;
1548                                         remote-endpoint = <&vopl_out_edp>;
1549                                 };
1550                         };
1551                 };
1552         };
1553
1554         display_subsystem: display-subsystem {
1555                 compatible = "rockchip,display-subsystem";
1556                 ports = <&vopl_out>, <&vopb_out>;
1557                 status = "disabled";
1558         };
1559
1560         pinctrl: pinctrl {
1561                 compatible = "rockchip,rk3399-pinctrl";
1562                 rockchip,grf = <&grf>;
1563                 rockchip,pmu = <&pmugrf>;
1564                 #address-cells = <0x2>;
1565                 #size-cells = <0x2>;
1566                 ranges;
1567
1568                 gpio0: gpio0@ff720000 {
1569                         compatible = "rockchip,gpio-bank";
1570                         reg = <0x0 0xff720000 0x0 0x100>;
1571                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1572                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1573
1574                         gpio-controller;
1575                         #gpio-cells = <0x2>;
1576
1577                         interrupt-controller;
1578                         #interrupt-cells = <0x2>;
1579                 };
1580
1581                 gpio1: gpio1@ff730000 {
1582                         compatible = "rockchip,gpio-bank";
1583                         reg = <0x0 0xff730000 0x0 0x100>;
1584                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1585                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1586
1587                         gpio-controller;
1588                         #gpio-cells = <0x2>;
1589
1590                         interrupt-controller;
1591                         #interrupt-cells = <0x2>;
1592                 };
1593
1594                 gpio2: gpio2@ff780000 {
1595                         compatible = "rockchip,gpio-bank";
1596                         reg = <0x0 0xff780000 0x0 0x100>;
1597                         clocks = <&cru PCLK_GPIO2>;
1598                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1599
1600                         gpio-controller;
1601                         #gpio-cells = <0x2>;
1602
1603                         interrupt-controller;
1604                         #interrupt-cells = <0x2>;
1605                 };
1606
1607                 gpio3: gpio3@ff788000 {
1608                         compatible = "rockchip,gpio-bank";
1609                         reg = <0x0 0xff788000 0x0 0x100>;
1610                         clocks = <&cru PCLK_GPIO3>;
1611                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1612
1613                         gpio-controller;
1614                         #gpio-cells = <0x2>;
1615
1616                         interrupt-controller;
1617                         #interrupt-cells = <0x2>;
1618                 };
1619
1620                 gpio4: gpio4@ff790000 {
1621                         compatible = "rockchip,gpio-bank";
1622                         reg = <0x0 0xff790000 0x0 0x100>;
1623                         clocks = <&cru PCLK_GPIO4>;
1624                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1625
1626                         gpio-controller;
1627                         #gpio-cells = <0x2>;
1628
1629                         interrupt-controller;
1630                         #interrupt-cells = <0x2>;
1631                 };
1632
1633                 pcfg_pull_up: pcfg-pull-up {
1634                         bias-pull-up;
1635                 };
1636
1637                 pcfg_pull_down: pcfg-pull-down {
1638                         bias-pull-down;
1639                 };
1640
1641                 pcfg_pull_none: pcfg-pull-none {
1642                         bias-disable;
1643                 };
1644
1645                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1646                         bias-disable;
1647                         drive-strength = <12>;
1648                 };
1649
1650                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1651                         bias-pull-up;
1652                         drive-strength = <8>;
1653                 };
1654
1655                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1656                         bias-pull-down;
1657                         drive-strength = <4>;
1658                 };
1659
1660                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1661                         bias-pull-up;
1662                         drive-strength = <2>;
1663                 };
1664
1665                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1666                         bias-pull-down;
1667                         drive-strength = <12>;
1668                 };
1669
1670                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1671                         bias-disable;
1672                         drive-strength = <13>;
1673                 };
1674
1675                 emmc {
1676                         emmc_pwr: emmc-pwr {
1677                                 rockchip,pins =
1678                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1679                         };
1680                 };
1681
1682                 gmac {
1683                         rgmii_pins: rgmii-pins {
1684                                 rockchip,pins =
1685                                         /* mac_txclk */
1686                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1687                                         /* mac_rxclk */
1688                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1689                                         /* mac_mdio */
1690                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1691                                         /* mac_txen */
1692                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1693                                         /* mac_clk */
1694                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1695                                         /* mac_rxdv */
1696                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1697                                         /* mac_mdc */
1698                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1699                                         /* mac_rxd1 */
1700                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1701                                         /* mac_rxd0 */
1702                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1703                                         /* mac_txd1 */
1704                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1705                                         /* mac_txd0 */
1706                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1707                                         /* mac_rxd3 */
1708                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1709                                         /* mac_rxd2 */
1710                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1711                                         /* mac_txd3 */
1712                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1713                                         /* mac_txd2 */
1714                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1715                         };
1716
1717                         rmii_pins: rmii-pins {
1718                                 rockchip,pins =
1719                                         /* mac_mdio */
1720                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1721                                         /* mac_txen */
1722                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1723                                         /* mac_clk */
1724                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1725                                         /* mac_rxer */
1726                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1727                                         /* mac_rxdv */
1728                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1729                                         /* mac_mdc */
1730                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1731                                         /* mac_rxd1 */
1732                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1733                                         /* mac_rxd0 */
1734                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1735                                         /* mac_txd1 */
1736                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1737                                         /* mac_txd0 */
1738                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1739                         };
1740                 };
1741
1742                 i2c0 {
1743                         i2c0_xfer: i2c0-xfer {
1744                                 rockchip,pins =
1745                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1746                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 i2c1 {
1751                         i2c1_xfer: i2c1-xfer {
1752                                 rockchip,pins =
1753                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1754                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1755                         };
1756                 };
1757
1758                 i2c2 {
1759                         i2c2_xfer: i2c2-xfer {
1760                                 rockchip,pins =
1761                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1762                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1763                         };
1764                 };
1765
1766                 i2c3 {
1767                         i2c3_xfer: i2c3-xfer {
1768                                 rockchip,pins =
1769                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1770                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1771                         };
1772
1773                         i2c3_gpio: i2c3_gpio {
1774                                 rockchip,pins =
1775                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1776                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1777                         };
1778
1779                 };
1780
1781                 i2c4 {
1782                         i2c4_xfer: i2c4-xfer {
1783                                 rockchip,pins =
1784                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1785                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1786                         };
1787                 };
1788
1789                 i2c5 {
1790                         i2c5_xfer: i2c5-xfer {
1791                                 rockchip,pins =
1792                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1793                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 i2c6 {
1798                         i2c6_xfer: i2c6-xfer {
1799                                 rockchip,pins =
1800                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1801                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 i2c7 {
1806                         i2c7_xfer: i2c7-xfer {
1807                                 rockchip,pins =
1808                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1809                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1810                         };
1811                 };
1812
1813                 i2c8 {
1814                         i2c8_xfer: i2c8-xfer {
1815                                 rockchip,pins =
1816                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1817                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1818                         };
1819                 };
1820
1821                 i2s0 {
1822                         i2s0_8ch_bus: i2s0-8ch-bus {
1823                                 rockchip,pins =
1824                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1825                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1826                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1827                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1828                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1829                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1830                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1831                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1832                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 i2s1 {
1837                         i2s1_2ch_bus: i2s1-2ch-bus {
1838                                 rockchip,pins =
1839                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1840                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1841                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1842                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1843                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1844                         };
1845                 };
1846
1847                 sdio0 {
1848                         sdio0_bus1: sdio0-bus1 {
1849                                 rockchip,pins =
1850                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852
1853                         sdio0_bus4: sdio0-bus4 {
1854                                 rockchip,pins =
1855                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1856                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1857                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1858                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1859                         };
1860
1861                         sdio0_cmd: sdio0-cmd {
1862                                 rockchip,pins =
1863                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1864                         };
1865
1866                         sdio0_clk: sdio0-clk {
1867                                 rockchip,pins =
1868                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1869                         };
1870
1871                         sdio0_cd: sdio0-cd {
1872                                 rockchip,pins =
1873                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1874                         };
1875
1876                         sdio0_pwr: sdio0-pwr {
1877                                 rockchip,pins =
1878                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1879                         };
1880
1881                         sdio0_bkpwr: sdio0-bkpwr {
1882                                 rockchip,pins =
1883                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1884                         };
1885
1886                         sdio0_wp: sdio0-wp {
1887                                 rockchip,pins =
1888                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1889                         };
1890
1891                         sdio0_int: sdio0-int {
1892                                 rockchip,pins =
1893                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1894                         };
1895                 };
1896
1897                 sdmmc {
1898                         sdmmc_bus1: sdmmc-bus1 {
1899                                 rockchip,pins =
1900                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1901                         };
1902
1903                         sdmmc_bus4: sdmmc-bus4 {
1904                                 rockchip,pins =
1905                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1906                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1907                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1908                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1909                         };
1910
1911                         sdmmc_clk: sdmmc-clk {
1912                                 rockchip,pins =
1913                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1914                         };
1915
1916                         sdmmc_cmd: sdmmc-cmd {
1917                                 rockchip,pins =
1918                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1919                         };
1920
1921                         sdmmc_cd: sdmcc-cd {
1922                                 rockchip,pins =
1923                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1924                         };
1925
1926                         sdmmc_wp: sdmmc-wp {
1927                                 rockchip,pins =
1928                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1929                         };
1930                 };
1931
1932                 spdif {
1933                         spdif_bus: spdif-bus {
1934                                 rockchip,pins =
1935                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1936                         };
1937
1938                         spdif_bus_1: spdif-bus-1 {
1939                                 rockchip,pins =
1940                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 spi0 {
1945                         spi0_clk: spi0-clk {
1946                                 rockchip,pins =
1947                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1948                         };
1949                         spi0_cs0: spi0-cs0 {
1950                                 rockchip,pins =
1951                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1952                         };
1953                         spi0_cs1: spi0-cs1 {
1954                                 rockchip,pins =
1955                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1956                         };
1957                         spi0_tx: spi0-tx {
1958                                 rockchip,pins =
1959                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1960                         };
1961                         spi0_rx: spi0-rx {
1962                                 rockchip,pins =
1963                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1964                         };
1965                 };
1966
1967                 spi1 {
1968                         spi1_clk: spi1-clk {
1969                                 rockchip,pins =
1970                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1971                         };
1972                         spi1_cs0: spi1-cs0 {
1973                                 rockchip,pins =
1974                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1975                         };
1976                         spi1_rx: spi1-rx {
1977                                 rockchip,pins =
1978                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1979                         };
1980                         spi1_tx: spi1-tx {
1981                                 rockchip,pins =
1982                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1983                         };
1984                 };
1985
1986                 spi2 {
1987                         spi2_clk: spi2-clk {
1988                                 rockchip,pins =
1989                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1990                         };
1991                         spi2_cs0: spi2-cs0 {
1992                                 rockchip,pins =
1993                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1994                         };
1995                         spi2_rx: spi2-rx {
1996                                 rockchip,pins =
1997                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1998                         };
1999                         spi2_tx: spi2-tx {
2000                                 rockchip,pins =
2001                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2002                         };
2003                 };
2004
2005                 spi3 {
2006                         spi3_clk: spi3-clk {
2007                                 rockchip,pins =
2008                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010                         spi3_cs0: spi3-cs0 {
2011                                 rockchip,pins =
2012                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2013                         };
2014                         spi3_rx: spi3-rx {
2015                                 rockchip,pins =
2016                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2017                         };
2018                         spi3_tx: spi3-tx {
2019                                 rockchip,pins =
2020                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2021                         };
2022                 };
2023
2024                 spi4 {
2025                         spi4_clk: spi4-clk {
2026                                 rockchip,pins =
2027                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2028                         };
2029                         spi4_cs0: spi4-cs0 {
2030                                 rockchip,pins =
2031                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2032                         };
2033                         spi4_rx: spi4-rx {
2034                                 rockchip,pins =
2035                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2036                         };
2037                         spi4_tx: spi4-tx {
2038                                 rockchip,pins =
2039                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2040                         };
2041                 };
2042
2043                 spi5 {
2044                         spi5_clk: spi5-clk {
2045                                 rockchip,pins =
2046                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2047                         };
2048                         spi5_cs0: spi5-cs0 {
2049                                 rockchip,pins =
2050                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2051                         };
2052                         spi5_rx: spi5-rx {
2053                                 rockchip,pins =
2054                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2055                         };
2056                         spi5_tx: spi5-tx {
2057                                 rockchip,pins =
2058                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2059                         };
2060                 };
2061
2062                 tsadc {
2063                         otp_gpio: otp-gpio {
2064                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2065                         };
2066
2067                         otp_out: otp-out {
2068                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2069                         };
2070                 };
2071
2072                 uart0 {
2073                         uart0_xfer: uart0-xfer {
2074                                 rockchip,pins =
2075                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2076                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2077                         };
2078
2079                         uart0_cts: uart0-cts {
2080                                 rockchip,pins =
2081                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2082                         };
2083
2084                         uart0_rts: uart0-rts {
2085                                 rockchip,pins =
2086                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2087                         };
2088                 };
2089
2090                 uart1 {
2091                         uart1_xfer: uart1-xfer {
2092                                 rockchip,pins =
2093                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2094                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2095                         };
2096                 };
2097
2098                 uart2a {
2099                         uart2a_xfer: uart2a-xfer {
2100                                 rockchip,pins =
2101                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2102                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2103                         };
2104                 };
2105
2106                 uart2b {
2107                         uart2b_xfer: uart2b-xfer {
2108                                 rockchip,pins =
2109                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2110                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2111                         };
2112                 };
2113
2114                 uart2c {
2115                         uart2c_xfer: uart2c-xfer {
2116                                 rockchip,pins =
2117                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2118                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2119                         };
2120                 };
2121
2122                 uart3 {
2123                         uart3_xfer: uart3-xfer {
2124                                 rockchip,pins =
2125                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2126                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2127                         };
2128
2129                         uart3_cts: uart3-cts {
2130                                 rockchip,pins =
2131                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2132                         };
2133
2134                         uart3_rts: uart3-rts {
2135                                 rockchip,pins =
2136                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 uart4 {
2141                         uart4_xfer: uart4-xfer {
2142                                 rockchip,pins =
2143                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2144                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2145                         };
2146                 };
2147
2148                 uarthdcp {
2149                         uarthdcp_xfer: uarthdcp-xfer {
2150                                 rockchip,pins =
2151                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2152                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2153                         };
2154                 };
2155
2156                 pwm0 {
2157                         pwm0_pin: pwm0-pin {
2158                                 rockchip,pins =
2159                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2160                         };
2161
2162                         vop0_pwm_pin: vop0-pwm-pin {
2163                                 rockchip,pins =
2164                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2165                         };
2166                 };
2167
2168                 pwm1 {
2169                         pwm1_pin: pwm1-pin {
2170                                 rockchip,pins =
2171                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2172                         };
2173
2174                         vop1_pwm_pin: vop1-pwm-pin {
2175                                 rockchip,pins =
2176                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2177                         };
2178                 };
2179
2180                 pwm2 {
2181                         pwm2_pin: pwm2-pin {
2182                                 rockchip,pins =
2183                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2184                         };
2185                 };
2186
2187                 pwm3a {
2188                         pwm3a_pin: pwm3a-pin {
2189                                 rockchip,pins =
2190                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2191                         };
2192                 };
2193
2194                 pwm3b {
2195                         pwm3b_pin: pwm3b-pin {
2196                                 rockchip,pins =
2197                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2198                         };
2199                 };
2200
2201                 edp {
2202                         edp_hpd: edp-hpd {
2203                                 rockchip,pins =
2204                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2205                         };
2206                 };
2207
2208                 hdmi {
2209                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2210                                 rockchip,pins =
2211                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2212                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2213                         };
2214
2215                         hdmi_cec: hdmi-cec {
2216                                 rockchip,pins =
2217                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2218                         };
2219                 };
2220
2221                 pcie {
2222                         pcie_clkreqn: pci-clkreqn {
2223                                 rockchip,pins =
2224                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2225                         };
2226
2227                         pcie_clkreqnb: pci-clkreqnb {
2228                                 rockchip,pins =
2229                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2230                         };
2231                 };
2232         };
2233 };