arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <1000000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <1000000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <1000000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <1000000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <1000000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <1000000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <1000000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <1000000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <1000000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         pmu_a53 {
 225                 compatible = "arm,cortex-a53-pmu";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227                 interrupt-affinity = <&cpu_l0>,
 228                                      <&cpu_l1>,
 229                                      <&cpu_l2>,
 230                                      <&cpu_l3>;
 231         };
 232
 233         pmu_a72 {
 234                 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 235                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu_b0>,
 237                                      <&cpu_b1>;
 238         };
 239
 240         xin24m: xin24m {
 241                 compatible = "fixed-clock";
 242                 #clock-cells = <0>;
 243                 clock-frequency = <24000000>;
 244                 clock-output-names = "xin24m";
 245         };
 246
 247         amba {
 248                 compatible = "arm,amba-bus";
 249                 #address-cells = <2>;
 250                 #size-cells = <2>;
 251                 ranges;
 252
 253                 dmac_bus: dma-controller@ff6d0000 {
 254                         compatible = "arm,pl330", "arm,primecell";
 255                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 256                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 258                         #dma-cells = <1>;
 259                         clocks = <&cru ACLK_DMAC0_PERILP>;
 260                         clock-names = "apb_pclk";
 261                 };
 262
 263                 dmac_peri: dma-controller@ff6e0000 {
 264                         compatible = "arm,pl330", "arm,primecell";
 265                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 266                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 268                         #dma-cells = <1>;
 269                         clocks = <&cru ACLK_DMAC1_PERILP>;
 270                         clock-names = "apb_pclk";
 271                 };
 272         };
 273
 274         emmc_phy: phy {
 275                 compatible = "rockchip,rk3399-emmc-phy";
 276                 reg-offset = <0xf780>;
 277                 #phy-cells = <0>;
 278                 rockchip,grf = <&grf>;
 279                 status = "disabled";
 280         };
 281
 282         sdio0: dwmmc@fe310000 {
 283                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 284                 reg = <0x0 0xfe310000 0x0 0x4000>;
 285                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 286                 clock-freq-min-max = <400000 150000000>;
 287                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 288                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 289                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 290                 fifo-depth = <0x100>;
 291                 status = "disabled";
 292         };
 293
 294         sdmmc: dwmmc@fe320000 {
 295                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 296                 reg = <0x0 0xfe320000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 300                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 status = "disabled";
 304         };
 305
 306         sdhci: sdhci@fe330000 {
 307                 compatible = "arasan,sdhci-5.1";
 308                 reg = <0x0 0xfe330000 0x0 0x10000>;
 309                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 311                 clock-names = "clk_xin", "clk_ahb";
 312                 phys = <&emmc_phy>;
 313                 phy-names = "phy_arasan";
 314                 status = "disabled";
 315         };
 316
 317         usb_host0_echi: usb@fe380000 {
 318                 compatible = "generic-ehci";
 319                 reg = <0x0 0xfe380000 0x0 0x20000>;
 320                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&cru HCLK_HOST0>;
 322                 clock-names = "hclk_host0";
 323                 status = "disabled";
 324         };
 325
 326         usb_host0_ohci: usb@fe3a0000 {
 327                 compatible = "generic-ohci";
 328                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 329                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&cru HCLK_HOST0>;
 331                 clock-names = "hclk_host0";
 332                 status = "disabled";
 333         };
 334
 335         usb_host1_echi: usb@fe3c0000 {
 336                 compatible = "generic-ehci";
 337                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 338                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&cru HCLK_HOST1>;
 340                 clock-names = "hclk_host1";
 341                 status = "disabled";
 342         };
 343
 344         usb_host1_ohci: usb@fe3e0000 {
 345                 compatible = "generic-ohci";
 346                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 347                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru HCLK_HOST1>;
 349                 clock-names = "hclk_host1";
 350                 status = "disabled";
 351         };
 352
 353         gic: interrupt-controller@fee00000 {
 354                 compatible = "arm,gic-v3";
 355                 #interrupt-cells = <3>;
 356                 #address-cells = <2>;
 357                 #size-cells = <2>;
 358                 ranges;
 359                 interrupt-controller;
 360
 361                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 362                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 363                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 364                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 365                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 366                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 367                 its: interrupt-controller@fee20000 {
 368                         compatible = "arm,gic-v3-its";
 369                         msi-controller;
 370                         reg = <0x0 0xfee20000 0x0 0x20000>;
 371                 };
 372         };
 373
 374         saradc: saradc@ff100000 {
 375                 compatible = "rockchip,rk3399-saradc";
 376                 reg = <0x0 0xff100000 0x0 0x100>;
 377                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 378                 #io-channel-cells = <1>;
 379                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 380                 clock-names = "saradc", "apb_pclk";
 381                 status = "disabled";
 382         };
 383
 384         i2c0: i2c@ff3c0000 {
 385                 compatible = "rockchip,rk3399-i2c";
 386                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 387                 clocks =  <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
 388                 clock-names = "i2c", "pclk";
 389                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c0_xfer>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 status = "disabled";
 395         };
 396
 397         i2c1: i2c@ff110000 {
 398                 compatible = "rockchip,rk3399-i2c";
 399                 reg = <0x0 0xff110000 0x0 0x1000>;
 400                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 401                 clock-names = "i2c", "pclk";
 402                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&i2c1_xfer>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 status = "disabled";
 408         };
 409
 410         i2c2: i2c@ff120000 {
 411                 compatible = "rockchip,rk3399-i2c";
 412                 reg = <0x0 0xff120000 0x0 0x1000>;
 413                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 414                 clock-names = "i2c", "pclk";
 415                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&i2c2_xfer>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 status = "disabled";
 421         };
 422
 423         i2c3: i2c@ff130000 {
 424                 compatible = "rockchip,rk3399-i2c";
 425                 reg = <0x0 0xff130000 0x0 0x1000>;
 426                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 427                 clock-names = "i2c", "pclk";
 428                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&i2c3_xfer>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 status = "disabled";
 434         };
 435
 436         i2c5: i2c@ff140000 {
 437                 compatible = "rockchip,rk3399-i2c";
 438                 reg = <0x0 0xff140000 0x0 0x1000>;
 439                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 440                 clock-names = "i2c", "pclk";
 441                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&i2c5_xfer>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 status = "disabled";
 447         };
 448
 449         i2c6: i2c@ff150000 {
 450                 compatible = "rockchip,rk3399-i2c";
 451                 reg = <0x0 0xff150000 0x0 0x1000>;
 452                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 453                 clock-names = "i2c", "pclk";
 454                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&i2c6_xfer>;
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 status = "disabled";
 460         };
 461
 462         i2c7: i2c@ff160000 {
 463                 compatible = "rockchip,rk3399-i2c";
 464                 reg = <0x0 0xff160000 0x0 0x1000>;
 465                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 466                 clock-names = "i2c", "pclk";
 467                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&i2c7_xfer>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 status = "disabled";
 473         };
 474
 475         uart0: serial@ff180000 {
 476                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 477                 reg = <0x0 0xff180000 0x0 0x100>;
 478                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 479                 clock-names = "baudclk", "apb_pclk";
 480                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 481                 reg-shift = <2>;
 482                 reg-io-width = <4>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 485                 status = "disabled";
 486         };
 487
 488         uart1: serial@ff190000 {
 489                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 490                 reg = <0x0 0xff190000 0x0 0x100>;
 491                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 492                 clock-names = "baudclk", "apb_pclk";
 493                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 494                 reg-shift = <2>;
 495                 reg-io-width = <4>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&uart1_xfer>;
 498                 status = "disabled";
 499         };
 500
 501         uart2: serial@ff1a0000 {
 502                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 503                 reg = <0x0 0xff1a0000 0x0 0x100>;
 504                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 505                 clock-names = "baudclk", "apb_pclk";
 506                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 507                 reg-shift = <2>;
 508                 reg-io-width = <4>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&uart2c_xfer>;
 511                 status = "disabled";
 512         };
 513
 514         uart3: serial@ff1b0000 {
 515                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 516                 reg = <0x0 0xff1b0000 0x0 0x100>;
 517                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 518                 clock-names = "baudclk", "apb_pclk";
 519                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 520                 reg-shift = <2>;
 521                 reg-io-width = <4>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 524                 status = "disabled";
 525         };
 526
 527         spi0: spi@ff1c0000 {
 528                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 529                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 531                 clock-names = "spiclk", "apb_pclk";
 532                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         spi1: spi@ff1d0000 {
 541                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 542                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 544                 clock-names = "spiclk", "apb_pclk";
 545                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         spi2: spi@ff1e0000 {
 554                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 555                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 557                 clock-names = "spiclk", "apb_pclk";
 558                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         spi4: spi@ff1f0000 {
 567                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 568                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 570                 clock-names = "spiclk", "apb_pclk";
 571                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         spi5: spi@ff200000 {
 580                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 581                 reg = <0x0 0xff200000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 583                 clock-names = "spiclk", "apb_pclk";
 584                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         thermal-zones {
 593                 #include "rk3368-thermal.dtsi"
 594         };
 595
 596         tsadc: tsadc@ff260000 {
 597                 compatible = "rockchip,rk3399-tsadc";
 598                 reg = <0x0 0xff260000 0x0 0x100>;
 599                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 601                 clock-names = "tsadc", "apb_pclk";
 602                 resets = <&cru SRST_TSADC>;
 603                 reset-names = "tsadc-apb";
 604                 pinctrl-names = "init", "default", "sleep";
 605                 pinctrl-0 = <&otp_gpio>;
 606                 pinctrl-1 = <&otp_out>;
 607                 pinctrl-2 = <&otp_gpio>;
 608                 #thermal-sensor-cells = <1>;
 609                 rockchip,hw-tshut-temp = <95000>;
 610                 status = "disabled";
 611         };
 612
 613         pmu: power-management@ff31000 {
 614                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 615                 reg = <0x0 0xff310000 0x0 0x1000>;
 616
 617                 power: power-controller {
 618                         status = "disabled";
 619                         compatible = "rockchip,rk3399-power-controller";
 620                         #power-domain-cells = <1>;
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623
 624                         pd_center {
 625                                 reg = <RK3399_PD_CENTER>;
 626                                 #address-cells = <1>;
 627                                 #size-cells = <0>;
 628
 629                                 pd_vdu {
 630                                         reg = <RK3399_PD_VDU>;
 631                                 };
 632                                 pd_vcodec {
 633                                         reg = <RK3399_PD_VCODEC>;
 634                                 };
 635                                 pd_iep {
 636                                         reg = <RK3399_PD_IEP>;
 637                                 };
 638                                 pd_rga {
 639                                         reg = <RK3399_PD_RGA>;
 640                                 };
 641                         };
 642                         pd_vio {
 643                                 reg = <RK3399_PD_VIO>;
 644                                 #address-cells = <1>;
 645                                 #size-cells = <0>;
 646
 647                                 pd_isp0 {
 648                                         reg = <RK3399_PD_ISP0>;
 649                                 };
 650                                 pd_isp1 {
 651                                         reg = <RK3399_PD_ISP1>;
 652                                 };
 653                                 pd_hdcp {
 654                                         reg = <RK3399_PD_HDCP>;
 655                                 };
 656                                 pd_vo {
 657                                         reg = <RK3399_PD_VO>;
 658                                         #address-cells = <1>;
 659                                         #size-cells = <0>;
 660
 661                                         pd_vopb {
 662                                                 reg = <RK3399_PD_VOPB>;
 663                                         };
 664                                         pd_vopl {
 665                                                 reg = <RK3399_PD_VOPL>;
 666                                         };
 667                                 };
 668                         };
 669                         pd_gpu {
 670                                 reg = <RK3399_PD_GPU>;
 671                         };
 672                 };
 673         };
 674
 675         pmugrf: syscon@ff320000 {
 676                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 677                 reg = <0x0 0xff320000 0x0 0x1000>;
 678         };
 679
 680         spi3: spi@ff350000 {
 681                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 682                 reg = <0x0 0xff350000 0x0 0x1000>;
 683                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 684                 clock-names = "spiclk", "apb_pclk";
 685                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 status = "disabled";
 691         };
 692
 693         uart4: serial@ff370000 {
 694                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 695                 reg = <0x0 0xff370000 0x0 0x100>;
 696                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 697                 clock-names = "baudclk", "apb_pclk";
 698                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 699                 reg-shift = <2>;
 700                 reg-io-width = <4>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&uart4_xfer>;
 703                 status = "disabled";
 704         };
 705
 706         i2c4: i2c@ff3d0000 {
 707                 compatible = "rockchip,rk3399-i2c";
 708                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 709                 clocks = <&cru SCLK_I2C4_PMU>, <&cru PCLK_I2C4_PMU>;
 710                 clock-names = "i2c", "pclk";
 711                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 712                 pinctrl-names = "default";
 713                 pinctrl-0 = <&i2c4_xfer>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 status = "disabled";
 717         };
 718
 719         i2c8: i2c@ff3e0000 {
 720                 compatible = "rockchip,rk3399-i2c";
 721                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 722                 clocks = <&cru SCLK_I2C8_PMU>, <&cru PCLK_I2C8_PMU>;
 723                 clock-names = "i2c", "pclk";
 724                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 725                 pinctrl-names = "default";
 726                 pinctrl-0 = <&i2c8_xfer>;
 727                 #address-cells = <1>;
 728                 #size-cells = <0>;
 729                 status = "disabled";
 730         };
 731
 732         pwm0: pwm@ff420000 {
 733                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 734                 reg = <0x0 0xff420000 0x0 0x10>;
 735                 #pwm-cells = <3>;
 736                 pinctrl-names = "default";
 737                 pinctrl-0 = <&pwm0_pin>;
 738                 clocks = <&cru PCLK_RKPWM_PMU>;
 739                 clock-names = "pwm";
 740                 status = "disabled";
 741         };
 742
 743         pwm1: pwm@ff420010 {
 744                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 745                 reg = <0x0 0xff420010 0x0 0x10>;
 746                 #pwm-cells = <3>;
 747                 pinctrl-names = "default";
 748                 pinctrl-0 = <&pwm1_pin>;
 749                 clocks = <&cru PCLK_RKPWM_PMU>;
 750                 clock-names = "pwm";
 751                 status = "disabled";
 752         };
 753
 754         pwm2: pwm@ff420020 {
 755                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 756                 reg = <0x0 0xff420020 0x0 0x10>;
 757                 #pwm-cells = <3>;
 758                 pinctrl-names = "default";
 759                 pinctrl-0 = <&pwm2_pin>;
 760                 clocks = <&cru PCLK_RKPWM_PMU>;
 761                 clock-names = "pwm";
 762                 status = "disabled";
 763         };
 764
 765         pwm3: pwm@ff420030 {
 766                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 767                 reg = <0x0 0xff420030 0x0 0x10>;
 768                 #pwm-cells = <3>;
 769                 pinctrl-names = "default";
 770                 pinctrl-0 = <&pwm3a_pin>;
 771                 clocks = <&cru PCLK_RKPWM_PMU>;
 772                 clock-names = "pwm";
 773                 status = "disabled";
 774         };
 775
 776         pmucru: pmu-clock-controller@ff750000 {
 777                 compatible = "rockchip,rk3399-pmucru";
 778                 reg = <0x0 0xff750000 0x0 0x1000>;
 779                 rockchip,grf = <&pmugrf>;
 780                 #clock-cells = <1>;
 781                 #reset-cells = <1>;
 782                 assigned-clocks = <&cru PLL_PPLL>;
 783                 assigned-clock-rates = <676000000>;
 784         };
 785
 786         cru: clock-controller@ff760000 {
 787                 compatible = "rockchip,rk3399-cru";
 788                 reg = <0x0 0xff760000 0x0 0x1000>;
 789                 rockchip,grf = <&grf>;
 790                 #clock-cells = <1>;
 791                 #reset-cells = <1>;
 792                 assigned-clocks =
 793                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 794                         <&cru PLL_NPLL>,
 795                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 796                         <&cru PCLK_PERIHP>,
 797                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 798                         <&cru PCLK_PERILP0>,
 799                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 800                 assigned-clock-rates =
 801                          <594000000>,  <800000000>,
 802                         <1000000000>,
 803                          <150000000>,   <75000000>,
 804                           <37500000>,
 805                          <100000000>,  <100000000>,
 806                           <50000000>,
 807                          <100000000>,   <50000000>;
 808         };
 809
 810         grf: syscon@ff770000 {
 811                 compatible = "rockchip,rk3399-grf", "syscon";
 812                 reg = <0x0 0xff770000 0x0 0x10000>;
 813         };
 814
 815         wdt0: watchdog@ff840000 {
 816                 compatible = "snps,dw-wdt";
 817                 reg = <0x0 0xff840000 0x0 0x100>;
 818                 clocks = <&cru PCLK_WDT>;
 819                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 820                 status = "disabled";
 821         };
 822
 823         spdif: spdif@ff870000 {
 824                 compatible = "rockchip,rk3399-spdif";
 825                 reg = <0x0 0xff870000 0x0 0x1000>;
 826                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 827                 dmas = <&dmac_bus 7>;
 828                 dma-names = "tx";
 829                 clock-names = "hclk", "mclk";
 830                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 831                 pinctrl-names = "default";
 832                 pinctrl-0 = <&spdif_bus>;
 833                 status = "disabled";
 834         };
 835
 836         i2s0: i2s@ff880000 {
 837                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 838                 reg = <0x0 0xff880000 0x0 0x1000>;
 839                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 840                 #address-cells = <1>;
 841                 #size-cells = <0>;
 842                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 843                 dma-names = "tx", "rx";
 844                 clock-names = "i2s_hclk", "i2s_clk";
 845                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&i2s0_8ch_bus>;
 848                 status = "disabled";
 849         };
 850
 851         i2s1: i2s@ff890000 {
 852                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 853                 reg = <0x0 0xff890000 0x0 0x1000>;
 854                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 855                 #address-cells = <1>;
 856                 #size-cells = <0>;
 857                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 858                 dma-names = "tx", "rx";
 859                 clock-names = "i2s_hclk", "i2s_clk";
 860                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 861                 pinctrl-names = "default";
 862                 pinctrl-0 = <&i2s1_2ch_bus>;
 863                 status = "disabled";
 864         };
 865
 866         i2s2: i2s@ff8a0000 {
 867                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 868                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 869                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 870                 #address-cells = <1>;
 871                 #size-cells = <0>;
 872                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 873                 dma-names = "tx", "rx";
 874                 clock-names = "i2s_hclk", "i2s_clk";
 875                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 876                 status = "disabled";
 877         };
 878
 879         pinctrl: pinctrl {
 880                 compatible = "rockchip,rk3399-pinctrl";
 881                 rockchip,grf = <&grf>;
 882                 rockchip,pmu = <&pmugrf>;
 883                 #address-cells = <0x2>;
 884                 #size-cells = <0x2>;
 885                 ranges;
 886
 887                 gpio0: gpio0@ff720000 {
 888                         compatible = "rockchip,gpio-bank";
 889                         reg = <0x0 0xff720000 0x0 0x100>;
 890                         clocks = <&cru PCLK_GPIO0_PMU>;
 891                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 892
 893                         gpio-controller;
 894                         #gpio-cells = <0x2>;
 895
 896                         interrupt-controller;
 897                         #interrupt-cells = <0x2>;
 898                 };
 899
 900                 gpio1: gpio1@ff730000 {
 901                         compatible = "rockchip,gpio-bank";
 902                         reg = <0x0 0xff730000 0x0 0x100>;
 903                         clocks = <&cru PCLK_GPIO1_PMU>;
 904                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 905
 906                         gpio-controller;
 907                         #gpio-cells = <0x2>;
 908
 909                         interrupt-controller;
 910                         #interrupt-cells = <0x2>;
 911                 };
 912
 913                 gpio2: gpio2@ff780000 {
 914                         compatible = "rockchip,gpio-bank";
 915                         reg = <0x0 0xff780000 0x0 0x100>;
 916                         clocks = <&cru PCLK_GPIO2>;
 917                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 918
 919                         gpio-controller;
 920                         #gpio-cells = <0x2>;
 921
 922                         interrupt-controller;
 923                         #interrupt-cells = <0x2>;
 924                 };
 925
 926                 gpio3: gpio3@ff788000 {
 927                         compatible = "rockchip,gpio-bank";
 928                         reg = <0x0 0xff788000 0x0 0x100>;
 929                         clocks = <&cru PCLK_GPIO3>;
 930                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 931
 932                         gpio-controller;
 933                         #gpio-cells = <0x2>;
 934
 935                         interrupt-controller;
 936                         #interrupt-cells = <0x2>;
 937                 };
 938
 939                 gpio4: gpio4@ff790000 {
 940                         compatible = "rockchip,gpio-bank";
 941                         reg = <0x0 0xff790000 0x0 0x100>;
 942                         clocks = <&cru PCLK_GPIO4>;
 943                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 944
 945                         gpio-controller;
 946                         #gpio-cells = <0x2>;
 947
 948                         interrupt-controller;
 949                         #interrupt-cells = <0x2>;
 950                 };
 951
 952                 pcfg_pull_up: pcfg-pull-up {
 953                         bias-pull-up;
 954                 };
 955
 956                 pcfg_pull_down: pcfg-pull-down {
 957                         bias-pull-down;
 958                 };
 959
 960                 pcfg_pull_none: pcfg-pull-none {
 961                         bias-disable;
 962                 };
 963
 964                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 965                         bias-disable;
 966                         drive-strength = <12>;
 967                 };
 968
 969                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 970                         bias-pull-up;
 971                         drive-strength = <8>;
 972                 };
 973
 974                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 975                         bias-pull-down;
 976                         drive-strength = <4>;
 977                 };
 978
 979                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 980                         bias-pull-up;
 981                         drive-strength = <2>;
 982                 };
 983
 984                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 985                         bias-pull-down;
 986                         drive-strength = <12>;
 987                 };
 988
 989                 emmc {
 990                         emmc_pwr: emmc-pwr {
 991                                 rockchip,pins =
 992                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 993                         };
 994                 };
 995
 996                 gmac {
 997                         rgmii_pins: rgmii-pins {
 998                                 rockchip,pins =
 999                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1001                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1002                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1003                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1004                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
1005                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1006                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1007                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1008                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1009                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1010                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1011                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1012                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1013                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1014                         };
1015
1016                         rmii_pins: rmii-pins {
1017                                 rockchip,pins =
1018                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1019                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1020                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1021                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1024                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1025                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1026                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1027                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1028                         };
1029                 };
1030
1031                 i2c0 {
1032                         i2c0_xfer: i2c0-xfer {
1033                                 rockchip,pins =
1034                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1035                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1036                         };
1037                 };
1038
1039                 i2c1 {
1040                         i2c1_xfer: i2c1-xfer {
1041                                 rockchip,pins =
1042                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1043                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1044                         };
1045                 };
1046
1047                 i2c2 {
1048                         i2c2_xfer: i2c2-xfer {
1049                                 rockchip,pins =
1050                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1051                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1052                         };
1053                 };
1054
1055                 i2c3 {
1056                         i2c3_xfer: i2c3-xfer {
1057                                 rockchip,pins =
1058                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1059                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1060                         };
1061                 };
1062
1063                 i2c4 {
1064                         i2c4_xfer: i2c4-xfer {
1065                                 rockchip,pins =
1066                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1067                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069                 };
1070
1071                 i2c5 {
1072                         i2c5_xfer: i2c5-xfer {
1073                                 rockchip,pins =
1074                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1075                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 i2c6 {
1080                         i2c6_xfer: i2c6-xfer {
1081                                 rockchip,pins =
1082                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1083                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1084                         };
1085                 };
1086
1087                 i2c7 {
1088                         i2c7_xfer: i2c7-xfer {
1089                                 rockchip,pins =
1090                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1091                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1092                         };
1093                 };
1094
1095                 i2c8 {
1096                         i2c8_xfer: i2c8-xfer {
1097                                 rockchip,pins =
1098                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1099                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 i2s0 {
1104                         i2s0_8ch_bus: i2s0-8ch-bus {
1105                                 rockchip,pins =
1106                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1107                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1108                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1109                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1110                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1111                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1112                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1113                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1114                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116                 };
1117
1118                 i2s1 {
1119                         i2s1_2ch_bus: i2s1-2ch-bus {
1120                                 rockchip,pins =
1121                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1122                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1123                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1124                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1125                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1126                         };
1127                 };
1128
1129                 sdio0 {
1130                         sdio0_bus1: sdio0-bus1 {
1131                                 rockchip,pins =
1132                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1133                         };
1134
1135                         sdio0_bus4: sdio0-bus4 {
1136                                 rockchip,pins =
1137                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1138                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1139                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1140                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1141                         };
1142
1143                         sdio0_cmd: sdio0-cmd {
1144                                 rockchip,pins =
1145                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1146                         };
1147
1148                         sdio0_clk: sdio0-clk {
1149                                 rockchip,pins =
1150                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1151                         };
1152
1153                         sdio0_cd: sdio0-cd {
1154                                 rockchip,pins =
1155                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1156                         };
1157
1158                         sdio0_pwr: sdio0-pwr {
1159                                 rockchip,pins =
1160                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1161                         };
1162
1163                         sdio0_bkpwr: sdio0-bkpwr {
1164                                 rockchip,pins =
1165                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1166                         };
1167
1168                         sdio0_wp: sdio0-wp {
1169                                 rockchip,pins =
1170                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1171                         };
1172
1173                         sdio0_int: sdio0-int {
1174                                 rockchip,pins =
1175                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1176                         };
1177                 };
1178
1179                 sdmmc {
1180                         sdmmc_bus1: sdmmc-bus1 {
1181                                 rockchip,pins =
1182                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1183                         };
1184
1185                         sdmmc_bus4: sdmmc-bus4 {
1186                                 rockchip,pins =
1187                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1188                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1189                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1190                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1191                         };
1192
1193                         sdmmc_clk: sdmmc-clk {
1194                                 rockchip,pins =
1195                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197
1198                         sdmmc_cmd: sdmmc-cmd {
1199                                 rockchip,pins =
1200                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1201                         };
1202
1203                         sdmmc_cd: sdmcc-cd {
1204                                 rockchip,pins =
1205                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1206                         };
1207
1208                         sdmmc_wp: sdmmc-wp {
1209                                 rockchip,pins =
1210                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1211                         };
1212                 };
1213
1214                 spdif {
1215                         spdif_bus: spdif-bus {
1216                                 rockchip,pins =
1217                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 spi0 {
1222                         spi0_clk: spi0-clk {
1223                                 rockchip,pins =
1224                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1225                         };
1226                         spi0_cs0: spi0-cs0 {
1227                                 rockchip,pins =
1228                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1229                         };
1230                         spi0_cs1: spi0-cs1 {
1231                                 rockchip,pins =
1232                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1233                         };
1234                         spi0_tx: spi0-tx {
1235                                 rockchip,pins =
1236                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1237                         };
1238                         spi0_rx: spi0-rx {
1239                                 rockchip,pins =
1240                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1241                         };
1242                 };
1243
1244                 spi1 {
1245                         spi1_clk: spi1-clk {
1246                                 rockchip,pins =
1247                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1248                         };
1249                         spi1_cs0: spi1-cs0 {
1250                                 rockchip,pins =
1251                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1252                         };
1253                         spi1_rx: spi1-rx {
1254                                 rockchip,pins =
1255                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1256                         };
1257                         spi1_tx: spi1-tx {
1258                                 rockchip,pins =
1259                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1260                         };
1261                 };
1262
1263                 spi2 {
1264                         spi2_clk: spi2-clk {
1265                                 rockchip,pins =
1266                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1267                         };
1268                         spi2_cs0: spi2-cs0 {
1269                                 rockchip,pins =
1270                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1271                         };
1272                         spi2_rx: spi2-rx {
1273                                 rockchip,pins =
1274                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1275                         };
1276                         spi2_tx: spi2-tx {
1277                                 rockchip,pins =
1278                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1279                         };
1280                 };
1281
1282                 spi3 {
1283                         spi3_clk: spi3-clk {
1284                                 rockchip,pins =
1285                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287                         spi3_cs0: spi3-cs0 {
1288                                 rockchip,pins =
1289                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1290                         };
1291                         spi3_rx: spi3-rx {
1292                                 rockchip,pins =
1293                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1294                         };
1295                         spi3_tx: spi3-tx {
1296                                 rockchip,pins =
1297                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1298                         };
1299                 };
1300
1301                 spi4 {
1302                         spi4_clk: spi4-clk {
1303                                 rockchip,pins =
1304                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1305                         };
1306                         spi4_cs0: spi4-cs0 {
1307                                 rockchip,pins =
1308                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1309                         };
1310                         spi4_rx: spi4-rx {
1311                                 rockchip,pins =
1312                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1313                         };
1314                         spi4_tx: spi4-tx {
1315                                 rockchip,pins =
1316                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1317                         };
1318                 };
1319
1320                 spi5 {
1321                         spi5_clk: spi5-clk {
1322                                 rockchip,pins =
1323                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1324                         };
1325                         spi5_cs0: spi5-cs0 {
1326                                 rockchip,pins =
1327                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1328                         };
1329                         spi5_rx: spi5-rx {
1330                                 rockchip,pins =
1331                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1332                         };
1333                         spi5_tx: spi5-tx {
1334                                 rockchip,pins =
1335                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1336                         };
1337                 };
1338
1339                 tsadc {
1340                         otp_gpio: otp-gpio {
1341                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1342                         };
1343
1344                         otp_out: otp-out {
1345                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1346                         };
1347                 };
1348
1349                 uart0 {
1350                         uart0_xfer: uart0-xfer {
1351                                 rockchip,pins =
1352                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1353                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1354                         };
1355
1356                         uart0_cts: uart0-cts {
1357                                 rockchip,pins =
1358                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360
1361                         uart0_rts: uart0-rts {
1362                                 rockchip,pins =
1363                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1364                         };
1365                 };
1366
1367                 uart1 {
1368                         uart1_xfer: uart1-xfer {
1369                                 rockchip,pins =
1370                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1371                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1372                         };
1373                 };
1374
1375                 uart2a {
1376                         uart2a_xfer: uart2a-xfer {
1377                                 rockchip,pins =
1378                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1379                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1380                         };
1381                 };
1382
1383                 uart2b {
1384                         uart2b_xfer: uart2b-xfer {
1385                                 rockchip,pins =
1386                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1387                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1388                         };
1389                 };
1390
1391                 uart2c {
1392                         uart2c_xfer: uart2c-xfer {
1393                                 rockchip,pins =
1394                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1395                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1396                         };
1397                 };
1398
1399                 uart3 {
1400                         uart3_xfer: uart3-xfer {
1401                                 rockchip,pins =
1402                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1403                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1404                         };
1405
1406                         uart3_cts: uart3-cts {
1407                                 rockchip,pins =
1408                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1409                         };
1410
1411                         uart3_rts: uart3-rts {
1412                                 rockchip,pins =
1413                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1414                         };
1415                 };
1416
1417                 uart4 {
1418                         uart4_xfer: uart4-xfer {
1419                                 rockchip,pins =
1420                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1421                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1422                         };
1423                 };
1424
1425                 uarthdcp {
1426                         uarthdcp_xfer: uarthdcp-xfer {
1427                                 rockchip,pins =
1428                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1429                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1430                         };
1431                 };
1432
1433                 pwm0 {
1434                         pwm0_pin: pwm0-pin {
1435                                 rockchip,pins =
1436                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         vop0_pwm_pin: vop0-pwm-pin {
1440                                 rockchip,pins =
1441                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1442                         };
1443                 };
1444
1445                 pwm1 {
1446                         pwm1_pin: pwm1-pin {
1447                                 rockchip,pins =
1448                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1449                         };
1450
1451                         vop1_pwm_pin: vop1-pwm-pin {
1452                                 rockchip,pins =
1453                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1454                         };
1455                 };
1456
1457                 pwm2 {
1458                         pwm2_pin: pwm2-pin {
1459                                 rockchip,pins =
1460                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 pwm3a {
1465                         pwm3a_pin: pwm3a-pin {
1466                                 rockchip,pins =
1467                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1468                         };
1469                 };
1470
1471                 pwm3b {
1472                         pwm3b_pin: pwm3b-pin {
1473                                 rockchip,pins =
1474                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1475                         };
1476                 };
1477
1478                 pmic {
1479                         pmic_int_l: pmic-int-l {
1480                                 rockchip,pins =
1481                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1482                         };
1483                 };
1484         };
1485 };