arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci-1.0";
  77                 method = "smc";
  78         };
  79
  80         cpus {
  81                 #address-cells = <2>;
  82                 #size-cells = <0>;
  83
  84                 cpu-map {
  85                         cluster0 {
  86                                 core0 {
  87                                         cpu = <&cpu_l0>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&cpu_l1>;
  91                                 };
  92                                 core2 {
  93                                         cpu = <&cpu_l2>;
  94                                 };
  95                                 core3 {
  96                                         cpu = <&cpu_l3>;
  97                                 };
  98                         };
  99
 100                         cluster1 {
 101                                 core0 {
 102                                         cpu = <&cpu_b0>;
 103                                 };
 104                                 core1 {
 105                                         cpu = <&cpu_b1>;
 106                                 };
 107                         };
 108                 };
 109
 110                 cpu_l0: cpu@0 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         reg = <0x0 0x0>;
 114                         enable-method = "psci";
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&cpu_sleep>;
 118                         operating-points-v2 = <&cluster0_opp>;
 119                 };
 120
 121                 cpu_l1: cpu@1 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x1>;
 125                         enable-method = "psci";
 126                         clocks = <&cru ARMCLKL>;
 127                         cpu-idle-states = <&cpu_sleep>;
 128                         operating-points-v2 = <&cluster0_opp>;
 129                 };
 130
 131                 cpu_l2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x0 0x2>;
 135                         enable-method = "psci";
 136                         clocks = <&cru ARMCLKL>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         operating-points-v2 = <&cluster0_opp>;
 139                 };
 140
 141                 cpu_l3: cpu@3 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x0 0x3>;
 145                         enable-method = "psci";
 146                         clocks = <&cru ARMCLKL>;
 147                         cpu-idle-states = <&cpu_sleep>;
 148                         operating-points-v2 = <&cluster0_opp>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         clocks = <&cru ARMCLKB>;
 158                         cpu-idle-states = <&cpu_sleep>;
 159                         operating-points-v2 = <&cluster1_opp>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&cpu_sleep>;
 169                         operating-points-v2 = <&cluster1_opp>;
 170                 };
 171
 172                 idle-states {
 173                         entry-method = "psci";
 174                         cpu_sleep: cpu-sleep-0 {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <350>;
 179                                 exit-latency-us = <600>;
 180                                 min-residency-us = <1150>;
 181                         };
 182                 };
 183         };
 184
 185         cluster0_opp: opp_table0 {
 186                 compatible = "operating-points-v2";
 187                 opp-shared;
 188
 189                 opp00 {
 190                         opp-hz = /bits/ 64 <408000000>;
 191                         opp-microvolt = <800000>;
 192                         clock-latency-ns = <40000>;
 193                 };
 194                 opp01 {
 195                         opp-hz = /bits/ 64 <600000000>;
 196                         opp-microvolt = <800000>;
 197                 };
 198                 opp02 {
 199                         opp-hz = /bits/ 64 <816000000>;
 200                         opp-microvolt = <800000>;
 201                 };
 202                 opp03 {
 203                         opp-hz = /bits/ 64 <1008000000>;
 204                         opp-microvolt = <875000>;
 205                 };
 206                 opp04 {
 207                         opp-hz = /bits/ 64 <1200000000>;
 208                         opp-microvolt = <925000>;
 209                 };
 210                 opp05 {
 211                         opp-hz = /bits/ 64 <1416000000>;
 212                         opp-microvolt = <1025000>;
 213                 };
 214         };
 215
 216         cluster1_opp: opp_table1 {
 217                 compatible = "operating-points-v2";
 218                 opp-shared;
 219
 220                 opp00 {
 221                         opp-hz = /bits/ 64 <408000000>;
 222                         opp-microvolt = <800000>;
 223                         clock-latency-ns = <40000>;
 224                 };
 225                 opp01 {
 226                         opp-hz = /bits/ 64 <600000000>;
 227                         opp-microvolt = <800000>;
 228                 };
 229                 opp02 {
 230                         opp-hz = /bits/ 64 <816000000>;
 231                         opp-microvolt = <800000>;
 232                 };
 233                 opp03 {
 234                         opp-hz = /bits/ 64 <1008000000>;
 235                         opp-microvolt = <850000>;
 236                 };
 237                 opp04 {
 238                         opp-hz = /bits/ 64 <1200000000>;
 239                         opp-microvolt = <925000>;
 240                 };
 241         };
 242
 243         timer {
 244                 compatible = "arm,armv8-timer";
 245                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 249         };
 250
 251         arm-pmu {
 252                 compatible = "arm,armv8-pmuv3";
 253                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 254         };
 255
 256         xin24m: xin24m {
 257                 compatible = "fixed-clock";
 258                 #clock-cells = <0>;
 259                 clock-frequency = <24000000>;
 260                 clock-output-names = "xin24m";
 261         };
 262
 263         amba {
 264                 compatible = "arm,amba-bus";
 265                 #address-cells = <2>;
 266                 #size-cells = <2>;
 267                 ranges;
 268
 269                 dmac_bus: dma-controller@ff6d0000 {
 270                         compatible = "arm,pl330", "arm,primecell";
 271                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 272                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 274                         #dma-cells = <1>;
 275                         clocks = <&cru ACLK_DMAC0_PERILP>;
 276                         clock-names = "apb_pclk";
 277                 };
 278
 279                 dmac_peri: dma-controller@ff6e0000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 282                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         clocks = <&cru ACLK_DMAC1_PERILP>;
 286                         clock-names = "apb_pclk";
 287                 };
 288         };
 289
 290         gmac: eth@fe300000 {
 291                 compatible = "rockchip,rk3399-gmac";
 292                 reg = <0x0 0xfe300000 0x0 0x10000>;
 293                 rockchip,grf = <&grf>;
 294                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 295                 interrupt-names = "macirq";
 296                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 297                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 298                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 299                          <&cru PCLK_GMAC>;
 300                 clock-names = "stmmaceth", "mac_clk_rx",
 301                               "mac_clk_tx", "clk_mac_ref",
 302                               "clk_mac_refout", "aclk_mac",
 303                               "pclk_mac";
 304                 resets = <&cru SRST_A_GMAC>;
 305                 reset-names = "stmmaceth";
 306                 status = "disabled";
 307         };
 308
 309         emmc_phy: phy {
 310                 compatible = "rockchip,rk3399-emmc-phy";
 311                 reg-offset = <0xf780>;
 312                 #phy-cells = <0>;
 313                 rockchip,grf = <&grf>;
 314                 status = "disabled";
 315         };
 316
 317         sdio0: dwmmc@fe310000 {
 318                 compatible = "rockchip,rk3399-dw-mshc",
 319                              "rockchip,rk3288-dw-mshc";
 320                 reg = <0x0 0xfe310000 0x0 0x4000>;
 321                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 322                 clock-freq-min-max = <400000 150000000>;
 323                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 324                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 325                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 326                 fifo-depth = <0x100>;
 327                 status = "disabled";
 328         };
 329
 330         sdmmc: dwmmc@fe320000 {
 331                 compatible = "rockchip,rk3399-dw-mshc",
 332                              "rockchip,rk3288-dw-mshc";
 333                 reg = <0x0 0xfe320000 0x0 0x4000>;
 334                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 335                 clock-freq-min-max = <400000 150000000>;
 336                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 337                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 338                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 339                 fifo-depth = <0x100>;
 340                 status = "disabled";
 341         };
 342
 343         sdhci: sdhci@fe330000 {
 344                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 345                 reg = <0x0 0xfe330000 0x0 0x10000>;
 346                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 348                 clock-names = "clk_xin", "clk_ahb";
 349                 assigned-clocks = <&cru SCLK_EMMC>;
 350                 assigned-clock-parents = <&cru PLL_CPLL>;
 351                 assigned-clock-rates = <200000000>;
 352                 phys = <&emmc_phy>;
 353                 phy-names = "phy_arasan";
 354                 status = "disabled";
 355         };
 356
 357         usb2phy: usb2phy {
 358                 compatible = "rockchip,rk3399-usb-phy";
 359                 rockchip,grf = <&grf>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362
 363                 usb2phy0: usb2-phy0 {
 364                         #phy-cells = <0>;
 365                         #clock-cells = <0>;
 366                         reg = <0xe458>;
 367                 };
 368
 369                 usb2phy1: usb2-phy1 {
 370                         #phy-cells = <0>;
 371                         #clock-cells = <0>;
 372                         reg = <0xe468>;
 373                 };
 374         };
 375
 376         usb_host0_ehci: usb@fe380000 {
 377                 compatible = "generic-ehci";
 378                 reg = <0x0 0xfe380000 0x0 0x20000>;
 379                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 381                 clock-names = "hclk_host0", "hclk_host0_arb";
 382                 phys = <&usb2phy0>;
 383                 phy-names = "usb2_phy0";
 384                 status = "disabled";
 385         };
 386
 387         usb_host0_ohci: usb@fe3a0000 {
 388                 compatible = "generic-ohci";
 389                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 390                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 392                 clock-names = "hclk_host0", "hclk_host0_arb";
 393                 status = "disabled";
 394         };
 395
 396         usb_host1_ehci: usb@fe3c0000 {
 397                 compatible = "generic-ehci";
 398                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 399                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 401                 clock-names = "hclk_host1", "hclk_host1_arb";
 402                 phys = <&usb2phy1>;
 403                 phy-names = "usb2_phy1";
 404                 status = "disabled";
 405         };
 406
 407         usb_host1_ohci: usb@fe3e0000 {
 408                 compatible = "generic-ohci";
 409                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 410                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 412                 clock-names = "hclk_host1", "hclk_host1_arb";
 413                 status = "disabled";
 414         };
 415
 416         usbdrd3_0: usb@fe800000 {
 417                 compatible = "rockchip,dwc3";
 418                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 419                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 420                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 421                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 422                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 423                               "aclk_usb3", "aclk_usb3_grf";
 424                 #address-cells = <2>;
 425                 #size-cells = <2>;
 426                 ranges;
 427                 status = "disabled";
 428                 usbdrd_dwc3_0: dwc3 {
 429                         compatible = "snps,dwc3";
 430                         reg = <0x0 0xfe800000 0x0 0x100000>;
 431                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 432                         dr_mode = "otg";
 433                         tx-fifo-resize;
 434                         snps,dis_enblslpm_quirk;
 435                         snps,phyif_utmi_16_bits;
 436                         snps,dis_u2_freeclk_exists_quirk;
 437                         snps,dis_del_phy_power_chg_quirk;
 438                         status = "disabled";
 439                 };
 440         };
 441
 442         usbdrd3_1: usb@fe900000 {
 443                 compatible = "rockchip,dwc3";
 444                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 445                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 446                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 447                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 448                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 449                               "aclk_usb3", "aclk_usb3_grf";
 450                 #address-cells = <2>;
 451                 #size-cells = <2>;
 452                 ranges;
 453                 status = "disabled";
 454                 usbdrd_dwc3_1: dwc3 {
 455                         compatible = "snps,dwc3";
 456                         reg = <0x0 0xfe900000 0x0 0x100000>;
 457                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 458                         dr_mode = "otg";
 459                         tx-fifo-resize;
 460                         snps,dis_enblslpm_quirk;
 461                         snps,phyif_utmi_16_bits;
 462                         snps,dis_u2_freeclk_exists_quirk;
 463                         snps,dis_del_phy_power_chg_quirk;
 464                         status = "disabled";
 465                 };
 466         };
 467
 468         gic: interrupt-controller@fee00000 {
 469                 compatible = "arm,gic-v3";
 470                 #interrupt-cells = <3>;
 471                 #address-cells = <2>;
 472                 #size-cells = <2>;
 473                 ranges;
 474                 interrupt-controller;
 475
 476                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 477                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 478                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 479                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 480                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 481                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 482                 its: interrupt-controller@fee20000 {
 483                         compatible = "arm,gic-v3-its";
 484                         msi-controller;
 485                         reg = <0x0 0xfee20000 0x0 0x20000>;
 486                 };
 487         };
 488
 489         saradc: saradc@ff100000 {
 490                 compatible = "rockchip,rk3399-saradc";
 491                 reg = <0x0 0xff100000 0x0 0x100>;
 492                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 493                 #io-channel-cells = <1>;
 494                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 495                 clock-names = "saradc", "apb_pclk";
 496                 status = "disabled";
 497         };
 498
 499         i2c0: i2c@ff3c0000 {
 500                 compatible = "rockchip,rk3399-i2c";
 501                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 502                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 503                 clock-names = "i2c", "pclk";
 504                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&i2c0_xfer>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 status = "disabled";
 510         };
 511
 512         i2c1: i2c@ff110000 {
 513                 compatible = "rockchip,rk3399-i2c";
 514                 reg = <0x0 0xff110000 0x0 0x1000>;
 515                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 516                 clock-names = "i2c", "pclk";
 517                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&i2c1_xfer>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 status = "disabled";
 523         };
 524
 525         i2c2: i2c@ff120000 {
 526                 compatible = "rockchip,rk3399-i2c";
 527                 reg = <0x0 0xff120000 0x0 0x1000>;
 528                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c2_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c3: i2c@ff130000 {
 539                 compatible = "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff130000 0x0 0x1000>;
 541                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c3_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c5: i2c@ff140000 {
 552                 compatible = "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff140000 0x0 0x1000>;
 554                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 555                 clock-names = "i2c", "pclk";
 556                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c5_xfer>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         i2c6: i2c@ff150000 {
 565                 compatible = "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff150000 0x0 0x1000>;
 567                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 568                 clock-names = "i2c", "pclk";
 569                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&i2c6_xfer>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         i2c7: i2c@ff160000 {
 578                 compatible = "rockchip,rk3399-i2c";
 579                 reg = <0x0 0xff160000 0x0 0x1000>;
 580                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 581                 clock-names = "i2c", "pclk";
 582                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&i2c7_xfer>;
 585                 #address-cells = <1>;
 586                 #size-cells = <0>;
 587                 status = "disabled";
 588         };
 589
 590         uart0: serial@ff180000 {
 591                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 592                 reg = <0x0 0xff180000 0x0 0x100>;
 593                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 594                 clock-names = "baudclk", "apb_pclk";
 595                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 596                 reg-shift = <2>;
 597                 reg-io-width = <4>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 600                 status = "disabled";
 601         };
 602
 603         uart1: serial@ff190000 {
 604                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 605                 reg = <0x0 0xff190000 0x0 0x100>;
 606                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 607                 clock-names = "baudclk", "apb_pclk";
 608                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 609                 reg-shift = <2>;
 610                 reg-io-width = <4>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&uart1_xfer>;
 613                 status = "disabled";
 614         };
 615
 616         uart2: serial@ff1a0000 {
 617                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 618                 reg = <0x0 0xff1a0000 0x0 0x100>;
 619                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 620                 clock-names = "baudclk", "apb_pclk";
 621                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 622                 reg-shift = <2>;
 623                 reg-io-width = <4>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&uart2c_xfer>;
 626                 status = "disabled";
 627         };
 628
 629         uart3: serial@ff1b0000 {
 630                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 631                 reg = <0x0 0xff1b0000 0x0 0x100>;
 632                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 633                 clock-names = "baudclk", "apb_pclk";
 634                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 635                 reg-shift = <2>;
 636                 reg-io-width = <4>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 639                 status = "disabled";
 640         };
 641
 642         spi0: spi@ff1c0000 {
 643                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 644                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 645                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 646                 clock-names = "spiclk", "apb_pclk";
 647                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 648                 pinctrl-names = "default";
 649                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 650                 #address-cells = <1>;
 651                 #size-cells = <0>;
 652                 status = "disabled";
 653         };
 654
 655         spi1: spi@ff1d0000 {
 656                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 657                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 658                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 659                 clock-names = "spiclk", "apb_pclk";
 660                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 status = "disabled";
 666         };
 667
 668         spi2: spi@ff1e0000 {
 669                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 670                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 671                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 672                 clock-names = "spiclk", "apb_pclk";
 673                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 status = "disabled";
 679         };
 680
 681         spi4: spi@ff1f0000 {
 682                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 683                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 684                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 685                 clock-names = "spiclk", "apb_pclk";
 686                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 status = "disabled";
 692         };
 693
 694         spi5: spi@ff200000 {
 695                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 696                 reg = <0x0 0xff200000 0x0 0x1000>;
 697                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 698                 clock-names = "spiclk", "apb_pclk";
 699                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         thermal-zones {
 708                 cpu {
 709                         polling-delay-passive = <100>; /* milliseconds */
 710                         polling-delay = <1000>; /* milliseconds */
 711
 712                         thermal-sensors = <&tsadc 0>;
 713
 714                         trips {
 715                                 cpu_alert0: cpu_alert0 {
 716                                         temperature = <70000>; /* millicelsius */
 717                                         hysteresis = <2000>; /* millicelsius */
 718                                         type = "passive";
 719                                 };
 720                                 cpu_alert1: cpu_alert1 {
 721                                         temperature = <75000>; /* millicelsius */
 722                                         hysteresis = <2000>; /* millicelsius */
 723                                         type = "passive";
 724                                 };
 725                                 cpu_crit: cpu_crit {
 726                                         temperature = <95000>; /* millicelsius */
 727                                         hysteresis = <2000>; /* millicelsius */
 728                                         type = "critical";
 729                                 };
 730                         };
 731
 732                         cooling-maps {
 733                                 map0 {
 734                                         trip = <&cpu_alert0>;
 735                                         cooling-device =
 736                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 737                                 };
 738                                 map1 {
 739                                         trip = <&cpu_alert1>;
 740                                         cooling-device =
 741                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 742                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 743                                 };
 744                         };
 745                 };
 746
 747                 gpu {
 748                         polling-delay-passive = <100>; /* milliseconds */
 749                         polling-delay = <1000>; /* milliseconds */
 750
 751                         thermal-sensors = <&tsadc 1>;
 752
 753                         trips {
 754                                 gpu_alert0: gpu_alert0 {
 755                                         temperature = <75000>; /* millicelsius */
 756                                         hysteresis = <2000>; /* millicelsius */
 757                                         type = "passive";
 758                                 };
 759                                 gpu_crit: gpu_crit {
 760                                         temperature = <95000>; /* millicelsius */
 761                                         hysteresis = <2000>; /* millicelsius */
 762                                         type = "critical";
 763                                 };
 764                         };
 765
 766                         cooling-maps {
 767                                 map0 {
 768                                         trip = <&gpu_alert0>;
 769                                         cooling-device =
 770                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 771                                 };
 772                         };
 773                 };
 774         };
 775
 776         tsadc: tsadc@ff260000 {
 777                 compatible = "rockchip,rk3399-tsadc";
 778                 reg = <0x0 0xff260000 0x0 0x100>;
 779                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 780                 rockchip,grf = <&grf>;
 781                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 782                 clock-names = "tsadc", "apb_pclk";
 783                 assigned-clocks = <&cru SCLK_TSADC>;
 784                 assigned-clock-rates = <750000>;
 785                 resets = <&cru SRST_TSADC>;
 786                 reset-names = "tsadc-apb";
 787                 pinctrl-names = "init", "default", "sleep";
 788                 pinctrl-0 = <&otp_gpio>;
 789                 pinctrl-1 = <&otp_out>;
 790                 pinctrl-2 = <&otp_gpio>;
 791                 #thermal-sensor-cells = <1>;
 792                 rockchip,hw-tshut-temp = <95000>;
 793                 status = "disabled";
 794         };
 795
 796         pmu: power-management@ff310000 {
 797                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 798                 reg = <0x0 0xff310000 0x0 0x1000>;
 799
 800                 power: power-controller {
 801                         status = "disabled";
 802                         compatible = "rockchip,rk3399-power-controller";
 803                         #power-domain-cells = <1>;
 804                         #address-cells = <1>;
 805                         #size-cells = <0>;
 806
 807                         pd_center {
 808                                 reg = <RK3399_PD_CENTER>;
 809                                 #address-cells = <1>;
 810                                 #size-cells = <0>;
 811
 812                                 pd_vdu {
 813                                         reg = <RK3399_PD_VDU>;
 814                                 };
 815                                 pd_vcodec {
 816                                         reg = <RK3399_PD_VCODEC>;
 817                                 };
 818                                 pd_iep {
 819                                         reg = <RK3399_PD_IEP>;
 820                                 };
 821                                 pd_rga {
 822                                         reg = <RK3399_PD_RGA>;
 823                                 };
 824                         };
 825                         pd_vio {
 826                                 reg = <RK3399_PD_VIO>;
 827                                 #address-cells = <1>;
 828                                 #size-cells = <0>;
 829
 830                                 pd_isp0 {
 831                                         reg = <RK3399_PD_ISP0>;
 832                                 };
 833                                 pd_isp1 {
 834                                         reg = <RK3399_PD_ISP1>;
 835                                 };
 836                                 pd_hdcp {
 837                                         reg = <RK3399_PD_HDCP>;
 838                                 };
 839                                 pd_vo {
 840                                         reg = <RK3399_PD_VO>;
 841                                         #address-cells = <1>;
 842                                         #size-cells = <0>;
 843
 844                                         pd_vopb {
 845                                                 reg = <RK3399_PD_VOPB>;
 846                                         };
 847                                         pd_vopl {
 848                                                 reg = <RK3399_PD_VOPL>;
 849                                         };
 850                                 };
 851                         };
 852                         pd_gpu {
 853                                 reg = <RK3399_PD_GPU>;
 854                         };
 855                 };
 856         };
 857
 858         pmugrf: syscon@ff320000 {
 859                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 860                 reg = <0x0 0xff320000 0x0 0x1000>;
 861         };
 862
 863         spi3: spi@ff350000 {
 864                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 865                 reg = <0x0 0xff350000 0x0 0x1000>;
 866                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 867                 clock-names = "spiclk", "apb_pclk";
 868                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 869                 pinctrl-names = "default";
 870                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 871                 #address-cells = <1>;
 872                 #size-cells = <0>;
 873                 status = "disabled";
 874         };
 875
 876         uart4: serial@ff370000 {
 877                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 878                 reg = <0x0 0xff370000 0x0 0x100>;
 879                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 880                 clock-names = "baudclk", "apb_pclk";
 881                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 882                 reg-shift = <2>;
 883                 reg-io-width = <4>;
 884                 pinctrl-names = "default";
 885                 pinctrl-0 = <&uart4_xfer>;
 886                 status = "disabled";
 887         };
 888
 889         i2c4: i2c@ff3d0000 {
 890                 compatible = "rockchip,rk3399-i2c";
 891                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 892                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 893                 clock-names = "i2c", "pclk";
 894                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 895                 pinctrl-names = "default";
 896                 pinctrl-0 = <&i2c4_xfer>;
 897                 #address-cells = <1>;
 898                 #size-cells = <0>;
 899                 status = "disabled";
 900         };
 901
 902         i2c8: i2c@ff3e0000 {
 903                 compatible = "rockchip,rk3399-i2c";
 904                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 905                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 906                 clock-names = "i2c", "pclk";
 907                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 908                 pinctrl-names = "default";
 909                 pinctrl-0 = <&i2c8_xfer>;
 910                 #address-cells = <1>;
 911                 #size-cells = <0>;
 912                 status = "disabled";
 913         };
 914
 915         pwm0: pwm@ff420000 {
 916                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 917                 reg = <0x0 0xff420000 0x0 0x10>;
 918                 #pwm-cells = <3>;
 919                 pinctrl-names = "default";
 920                 pinctrl-0 = <&pwm0_pin>;
 921                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 922                 clock-names = "pwm";
 923                 status = "disabled";
 924         };
 925
 926         pwm1: pwm@ff420010 {
 927                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 928                 reg = <0x0 0xff420010 0x0 0x10>;
 929                 #pwm-cells = <3>;
 930                 pinctrl-names = "default";
 931                 pinctrl-0 = <&pwm1_pin>;
 932                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 933                 clock-names = "pwm";
 934                 status = "disabled";
 935         };
 936
 937         pwm2: pwm@ff420020 {
 938                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 939                 reg = <0x0 0xff420020 0x0 0x10>;
 940                 #pwm-cells = <3>;
 941                 pinctrl-names = "default";
 942                 pinctrl-0 = <&pwm2_pin>;
 943                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 944                 clock-names = "pwm";
 945                 status = "disabled";
 946         };
 947
 948         pwm3: pwm@ff420030 {
 949                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 950                 reg = <0x0 0xff420030 0x0 0x10>;
 951                 #pwm-cells = <3>;
 952                 pinctrl-names = "default";
 953                 pinctrl-0 = <&pwm3a_pin>;
 954                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 955                 clock-names = "pwm";
 956                 status = "disabled";
 957         };
 958
 959         rga: rga@ff680000 {
 960                 compatible = "rockchip,rk3399-rga";
 961                 reg = <0x0 0xff680000 0x0 0x10000>;
 962                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 963                 interrupt-names = "rga";
 964                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 965                 clock-names = "aclk", "hclk", "sclk";
 966                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 967                 reset-names = "core", "axi", "ahb";
 968                 status = "disabled";
 969         };
 970
 971         pmucru: pmu-clock-controller@ff750000 {
 972                 compatible = "rockchip,rk3399-pmucru";
 973                 reg = <0x0 0xff750000 0x0 0x1000>;
 974                 #clock-cells = <1>;
 975                 #reset-cells = <1>;
 976                 assigned-clocks = <&pmucru PLL_PPLL>;
 977                 assigned-clock-rates = <676000000>;
 978         };
 979
 980         cru: clock-controller@ff760000 {
 981                 compatible = "rockchip,rk3399-cru";
 982                 reg = <0x0 0xff760000 0x0 0x1000>;
 983                 #clock-cells = <1>;
 984                 #reset-cells = <1>;
 985                 assigned-clocks =
 986                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 987                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 988                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 989                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 990                         <&cru PLL_NPLL>,
 991                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 992                         <&cru PCLK_PERIHP>,
 993                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 994                         <&cru PCLK_PERILP0>,
 995                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 996                 assigned-clock-rates =
 997                          <400000000>,  <200000000>,
 998                          <400000000>,  <200000000>,
 999                          <816000000>, <1008000000>,
1000                          <594000000>,  <800000000>,
1001                         <1000000000>,
1002                          <150000000>,   <75000000>,
1003                           <37500000>,
1004                          <100000000>,  <100000000>,
1005                           <50000000>,
1006                          <100000000>,   <50000000>;
1007         };
1008
1009         grf: syscon@ff770000 {
1010                 compatible = "rockchip,rk3399-grf", "syscon";
1011                 reg = <0x0 0xff770000 0x0 0x10000>;
1012         };
1013
1014         watchdog@ff840000 {
1015                 compatible = "snps,dw-wdt";
1016                 reg = <0x0 0xff840000 0x0 0x100>;
1017                 clocks = <&cru PCLK_WDT>;
1018                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1019         };
1020
1021         spdif: spdif@ff870000 {
1022                 compatible = "rockchip,rk3399-spdif";
1023                 reg = <0x0 0xff870000 0x0 0x1000>;
1024                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1025                 dmas = <&dmac_bus 7>;
1026                 dma-names = "tx";
1027                 clock-names = "mclk", "hclk";
1028                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1029                 pinctrl-names = "default";
1030                 pinctrl-0 = <&spdif_bus>;
1031                 status = "disabled";
1032         };
1033
1034         i2s0: i2s@ff880000 {
1035                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1036                 reg = <0x0 0xff880000 0x0 0x1000>;
1037                 rockchip,grf = <&grf>;
1038                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1039                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1040                 dma-names = "tx", "rx";
1041                 clock-names = "i2s_clk", "i2s_hclk";
1042                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1043                 pinctrl-names = "default";
1044                 pinctrl-0 = <&i2s0_8ch_bus>;
1045                 status = "disabled";
1046         };
1047
1048         i2s1: i2s@ff890000 {
1049                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1050                 reg = <0x0 0xff890000 0x0 0x1000>;
1051                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1052                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1053                 dma-names = "tx", "rx";
1054                 clock-names = "i2s_clk", "i2s_hclk";
1055                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1056                 pinctrl-names = "default";
1057                 pinctrl-0 = <&i2s1_2ch_bus>;
1058                 status = "disabled";
1059         };
1060
1061         i2s2: i2s@ff8a0000 {
1062                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1063                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1064                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1065                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1066                 dma-names = "tx", "rx";
1067                 clock-names = "i2s_clk", "i2s_hclk";
1068                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1069                 status = "disabled";
1070         };
1071
1072         gpu: gpu@ff9a0000 {
1073                 compatible = "arm,malit860",
1074                              "arm,malit86x",
1075                              "arm,malit8xx",
1076                              "arm,mali-midgard";
1077
1078                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1079
1080                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1081                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1082                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1083                 interrupt-names = "GPU", "JOB", "MMU";
1084
1085                 clocks = <&cru ACLK_GPU>;
1086                 clock-names = "clk_mali";
1087                 #cooling-cells = <2>; /* min followed by max */
1088                 operating-points-v2 = <&gpu_opp_table>;
1089
1090                 status = "disabled";
1091
1092                 power_model {
1093                         compatible = "arm,mali-simple-power-model";
1094                         voltage = <900>;
1095                         frequency = <500>;
1096                         static-power = <500>;
1097                         dynamic-power = <1500>;
1098                         ts = <20000 2000 (-20) 2>;
1099                         thermal-zone = "gpu";
1100                 };
1101         };
1102
1103         gpu_opp_table: gpu_opp_table {
1104                 compatible = "operating-points-v2";
1105                 opp-shared;
1106
1107                 opp00 {
1108                         opp-hz = /bits/ 64 <200000000>;
1109                         opp-microvolt = <900000>;
1110                 };
1111                 opp01 {
1112                         opp-hz = /bits/ 64 <300000000>;
1113                         opp-microvolt = <900000>;
1114                 };
1115                 opp02 {
1116                         opp-hz = /bits/ 64 <400000000>;
1117                         opp-microvolt = <900000>;
1118                 };
1119
1120         };
1121
1122         vopl: vop@ff8f0000 {
1123                 compatible = "rockchip,rk3399-vop-lit";
1124                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1125                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1126                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1127                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1128                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1129                 reset-names = "axi", "ahb", "dclk";
1130                 iommus = <&vopl_mmu>;
1131                 status = "disabled";
1132
1133                 vopl_out: port {
1134                         #address-cells = <1>;
1135                         #size-cells = <0>;
1136
1137                         vopl_out_mipi: endpoint@0 {
1138                                 reg = <0>;
1139                                 remote-endpoint = <&mipi_in_vopl>;
1140                         };
1141
1142                         vopl_out_edp: endpoint@1 {
1143                                 reg = <1>;
1144                                 remote-endpoint = <&edp_in_vopl>;
1145                         };
1146                 };
1147         };
1148
1149         vopl_mmu: iommu@ff8f3f00 {
1150                 compatible = "rockchip,iommu";
1151                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1152                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1153                 interrupt-names = "vopl_mmu";
1154                 #iommu-cells = <0>;
1155                 status = "disabled";
1156         };
1157
1158         vopb: vop@ff900000 {
1159                 compatible = "rockchip,rk3399-vop-big";
1160                 reg = <0x0 0xff900000 0x0 0x3efc>;
1161                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1162                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1163                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1164                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1165                 reset-names = "axi", "ahb", "dclk";
1166                 iommus = <&vopb_mmu>;
1167                 status = "disabled";
1168
1169                 vopb_out: port {
1170                         #address-cells = <1>;
1171                         #size-cells = <0>;
1172
1173                         vopb_out_edp: endpoint@0 {
1174                                 reg = <0>;
1175                                 remote-endpoint = <&edp_in_vopb>;
1176                         };
1177
1178                         vopb_out_mipi: endpoint@1 {
1179                                 reg = <1>;
1180                                 remote-endpoint = <&mipi_in_vopb>;
1181                         };
1182                 };
1183         };
1184
1185         vopb_mmu: iommu@ff903f00 {
1186                 compatible = "rockchip,iommu";
1187                 reg = <0x0 0xff903f00 0x0 0x100>;
1188                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1189                 interrupt-names = "vopb_mmu";
1190                 #iommu-cells = <0>;
1191                 status = "disabled";
1192         };
1193
1194         mipi_dsi: mipi@ff960000 {
1195                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1196                 reg = <0x0 0xff960000 0x0 0x8000>;
1197                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1198                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1199                          <&cru SCLK_DPHY_TX0_CFG>;
1200                 clock-names = "ref", "pclk", "phy_cfg";
1201                 rockchip,grf = <&grf>;
1202                 #address-cells = <1>;
1203                 #size-cells = <0>;
1204                 status = "disabled";
1205
1206                 ports {
1207                         #address-cells = <1>;
1208                         #size-cells = <0>;
1209                         reg = <1>;
1210
1211                         mipi_in: port {
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214
1215                                 mipi_in_vopb: endpoint@0 {
1216                                         reg = <0>;
1217                                         remote-endpoint = <&vopb_out_mipi>;
1218                                 };
1219                                 mipi_in_vopl: endpoint@1 {
1220                                         reg = <1>;
1221                                         remote-endpoint = <&vopl_out_mipi>;
1222                                 };
1223                         };
1224                 };
1225         };
1226
1227         edp: edp@ff970000 {
1228                 compatible = "rockchip,rk3399-edp";
1229                 reg = <0x0 0xff970000 0x0 0x8000>;
1230                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1231                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1232                 clock-names = "dp", "pclk";
1233                 resets = <&cru SRST_P_EDP_CTRL>;
1234                 reset-names = "dp";
1235                 rockchip,grf = <&grf>;
1236                 status = "disabled";
1237                 pinctrl-names = "default";
1238                 pinctrl-0 = <&edp_hpd>;
1239
1240                 ports {
1241                         #address-cells = <1>;
1242                         #size-cells = <0>;
1243
1244                         edp_in: port@0 {
1245                                 reg = <0>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248
1249                                 edp_in_vopb: endpoint@0 {
1250                                         reg = <0>;
1251                                         remote-endpoint = <&vopb_out_edp>;
1252                                 };
1253
1254                                 edp_in_vopl: endpoint@1 {
1255                                         reg = <1>;
1256                                         remote-endpoint = <&vopl_out_edp>;
1257                                 };
1258                         };
1259                 };
1260         };
1261
1262         display_subsystem: display-subsystem {
1263                 compatible = "rockchip,display-subsystem";
1264                 ports = <&vopl_out>, <&vopb_out>;
1265                 status = "disabled";
1266         };
1267
1268         pinctrl: pinctrl {
1269                 compatible = "rockchip,rk3399-pinctrl";
1270                 rockchip,grf = <&grf>;
1271                 rockchip,pmu = <&pmugrf>;
1272                 #address-cells = <0x2>;
1273                 #size-cells = <0x2>;
1274                 ranges;
1275
1276                 gpio0: gpio0@ff720000 {
1277                         compatible = "rockchip,gpio-bank";
1278                         reg = <0x0 0xff720000 0x0 0x100>;
1279                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1280                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1281
1282                         gpio-controller;
1283                         #gpio-cells = <0x2>;
1284
1285                         interrupt-controller;
1286                         #interrupt-cells = <0x2>;
1287                 };
1288
1289                 gpio1: gpio1@ff730000 {
1290                         compatible = "rockchip,gpio-bank";
1291                         reg = <0x0 0xff730000 0x0 0x100>;
1292                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1293                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1294
1295                         gpio-controller;
1296                         #gpio-cells = <0x2>;
1297
1298                         interrupt-controller;
1299                         #interrupt-cells = <0x2>;
1300                 };
1301
1302                 gpio2: gpio2@ff780000 {
1303                         compatible = "rockchip,gpio-bank";
1304                         reg = <0x0 0xff780000 0x0 0x100>;
1305                         clocks = <&cru PCLK_GPIO2>;
1306                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1307
1308                         gpio-controller;
1309                         #gpio-cells = <0x2>;
1310
1311                         interrupt-controller;
1312                         #interrupt-cells = <0x2>;
1313                 };
1314
1315                 gpio3: gpio3@ff788000 {
1316                         compatible = "rockchip,gpio-bank";
1317                         reg = <0x0 0xff788000 0x0 0x100>;
1318                         clocks = <&cru PCLK_GPIO3>;
1319                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1320
1321                         gpio-controller;
1322                         #gpio-cells = <0x2>;
1323
1324                         interrupt-controller;
1325                         #interrupt-cells = <0x2>;
1326                 };
1327
1328                 gpio4: gpio4@ff790000 {
1329                         compatible = "rockchip,gpio-bank";
1330                         reg = <0x0 0xff790000 0x0 0x100>;
1331                         clocks = <&cru PCLK_GPIO4>;
1332                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1333
1334                         gpio-controller;
1335                         #gpio-cells = <0x2>;
1336
1337                         interrupt-controller;
1338                         #interrupt-cells = <0x2>;
1339                 };
1340
1341                 pcfg_pull_up: pcfg-pull-up {
1342                         bias-pull-up;
1343                 };
1344
1345                 pcfg_pull_down: pcfg-pull-down {
1346                         bias-pull-down;
1347                 };
1348
1349                 pcfg_pull_none: pcfg-pull-none {
1350                         bias-disable;
1351                 };
1352
1353                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1354                         bias-disable;
1355                         drive-strength = <12>;
1356                 };
1357
1358                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1359                         bias-pull-up;
1360                         drive-strength = <8>;
1361                 };
1362
1363                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1364                         bias-pull-down;
1365                         drive-strength = <4>;
1366                 };
1367
1368                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1369                         bias-pull-up;
1370                         drive-strength = <2>;
1371                 };
1372
1373                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1374                         bias-pull-down;
1375                         drive-strength = <12>;
1376                 };
1377
1378                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1379                         bias-disable;
1380                         drive-strength = <13>;
1381                 };
1382
1383                 emmc {
1384                         emmc_pwr: emmc-pwr {
1385                                 rockchip,pins =
1386                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1387                         };
1388                 };
1389
1390                 gmac {
1391                         rgmii_pins: rgmii-pins {
1392                                 rockchip,pins =
1393                                         /* mac_txclk */
1394                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1395                                         /* mac_rxclk */
1396                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1397                                         /* mac_mdio */
1398                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1399                                         /* mac_txen */
1400                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1401                                         /* mac_clk */
1402                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1403                                         /* mac_rxdv */
1404                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1405                                         /* mac_mdc */
1406                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1407                                         /* mac_rxd1 */
1408                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1409                                         /* mac_rxd0 */
1410                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1411                                         /* mac_txd1 */
1412                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1413                                         /* mac_txd0 */
1414                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1415                                         /* mac_rxd3 */
1416                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1417                                         /* mac_rxd2 */
1418                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1419                                         /* mac_txd3 */
1420                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1421                                         /* mac_txd2 */
1422                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1423                         };
1424
1425                         rmii_pins: rmii-pins {
1426                                 rockchip,pins =
1427                                         /* mac_mdio */
1428                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1429                                         /* mac_txen */
1430                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1431                                         /* mac_clk */
1432                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1433                                         /* mac_rxer */
1434                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1435                                         /* mac_rxdv */
1436                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1437                                         /* mac_mdc */
1438                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1439                                         /* mac_rxd1 */
1440                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1441                                         /* mac_rxd0 */
1442                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1443                                         /* mac_txd1 */
1444                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1445                                         /* mac_txd0 */
1446                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1447                         };
1448                 };
1449
1450                 i2c0 {
1451                         i2c0_xfer: i2c0-xfer {
1452                                 rockchip,pins =
1453                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1454                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 i2c1 {
1459                         i2c1_xfer: i2c1-xfer {
1460                                 rockchip,pins =
1461                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1462                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 i2c2 {
1467                         i2c2_xfer: i2c2-xfer {
1468                                 rockchip,pins =
1469                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1470                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1471                         };
1472                 };
1473
1474                 i2c3 {
1475                         i2c3_xfer: i2c3-xfer {
1476                                 rockchip,pins =
1477                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1478                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 i2c4 {
1483                         i2c4_xfer: i2c4-xfer {
1484                                 rockchip,pins =
1485                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1486                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 i2c5 {
1491                         i2c5_xfer: i2c5-xfer {
1492                                 rockchip,pins =
1493                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1494                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1495                         };
1496                 };
1497
1498                 i2c6 {
1499                         i2c6_xfer: i2c6-xfer {
1500                                 rockchip,pins =
1501                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1502                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1503                         };
1504                 };
1505
1506                 i2c7 {
1507                         i2c7_xfer: i2c7-xfer {
1508                                 rockchip,pins =
1509                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1510                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1511                         };
1512                 };
1513
1514                 i2c8 {
1515                         i2c8_xfer: i2c8-xfer {
1516                                 rockchip,pins =
1517                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1518                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1519                         };
1520                 };
1521
1522                 i2s0 {
1523                         i2s0_8ch_bus: i2s0-8ch-bus {
1524                                 rockchip,pins =
1525                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1526                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1527                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1528                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1529                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1530                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1531                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1532                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1533                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1534                         };
1535                 };
1536
1537                 i2s1 {
1538                         i2s1_2ch_bus: i2s1-2ch-bus {
1539                                 rockchip,pins =
1540                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1541                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1542                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1543                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1544                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1545                         };
1546                 };
1547
1548                 sdio0 {
1549                         sdio0_bus1: sdio0-bus1 {
1550                                 rockchip,pins =
1551                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1552                         };
1553
1554                         sdio0_bus4: sdio0-bus4 {
1555                                 rockchip,pins =
1556                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1557                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1558                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1559                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561
1562                         sdio0_cmd: sdio0-cmd {
1563                                 rockchip,pins =
1564                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1565                         };
1566
1567                         sdio0_clk: sdio0-clk {
1568                                 rockchip,pins =
1569                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1570                         };
1571
1572                         sdio0_cd: sdio0-cd {
1573                                 rockchip,pins =
1574                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1575                         };
1576
1577                         sdio0_pwr: sdio0-pwr {
1578                                 rockchip,pins =
1579                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1580                         };
1581
1582                         sdio0_bkpwr: sdio0-bkpwr {
1583                                 rockchip,pins =
1584                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1585                         };
1586
1587                         sdio0_wp: sdio0-wp {
1588                                 rockchip,pins =
1589                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1590                         };
1591
1592                         sdio0_int: sdio0-int {
1593                                 rockchip,pins =
1594                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1595                         };
1596                 };
1597
1598                 sdmmc {
1599                         sdmmc_bus1: sdmmc-bus1 {
1600                                 rockchip,pins =
1601                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1602                         };
1603
1604                         sdmmc_bus4: sdmmc-bus4 {
1605                                 rockchip,pins =
1606                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1607                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1608                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1609                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1610                         };
1611
1612                         sdmmc_clk: sdmmc-clk {
1613                                 rockchip,pins =
1614                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1615                         };
1616
1617                         sdmmc_cmd: sdmmc-cmd {
1618                                 rockchip,pins =
1619                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1620                         };
1621
1622                         sdmmc_cd: sdmcc-cd {
1623                                 rockchip,pins =
1624                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1625                         };
1626
1627                         sdmmc_wp: sdmmc-wp {
1628                                 rockchip,pins =
1629                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1630                         };
1631                 };
1632
1633                 spdif {
1634                         spdif_bus: spdif-bus {
1635                                 rockchip,pins =
1636                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640                 spi0 {
1641                         spi0_clk: spi0-clk {
1642                                 rockchip,pins =
1643                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1644                         };
1645                         spi0_cs0: spi0-cs0 {
1646                                 rockchip,pins =
1647                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1648                         };
1649                         spi0_cs1: spi0-cs1 {
1650                                 rockchip,pins =
1651                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1652                         };
1653                         spi0_tx: spi0-tx {
1654                                 rockchip,pins =
1655                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1656                         };
1657                         spi0_rx: spi0-rx {
1658                                 rockchip,pins =
1659                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1660                         };
1661                 };
1662
1663                 spi1 {
1664                         spi1_clk: spi1-clk {
1665                                 rockchip,pins =
1666                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1667                         };
1668                         spi1_cs0: spi1-cs0 {
1669                                 rockchip,pins =
1670                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1671                         };
1672                         spi1_rx: spi1-rx {
1673                                 rockchip,pins =
1674                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1675                         };
1676                         spi1_tx: spi1-tx {
1677                                 rockchip,pins =
1678                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1679                         };
1680                 };
1681
1682                 spi2 {
1683                         spi2_clk: spi2-clk {
1684                                 rockchip,pins =
1685                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1686                         };
1687                         spi2_cs0: spi2-cs0 {
1688                                 rockchip,pins =
1689                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1690                         };
1691                         spi2_rx: spi2-rx {
1692                                 rockchip,pins =
1693                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695                         spi2_tx: spi2-tx {
1696                                 rockchip,pins =
1697                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1698                         };
1699                 };
1700
1701                 spi3 {
1702                         spi3_clk: spi3-clk {
1703                                 rockchip,pins =
1704                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706                         spi3_cs0: spi3-cs0 {
1707                                 rockchip,pins =
1708                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710                         spi3_rx: spi3-rx {
1711                                 rockchip,pins =
1712                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1713                         };
1714                         spi3_tx: spi3-tx {
1715                                 rockchip,pins =
1716                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718                 };
1719
1720                 spi4 {
1721                         spi4_clk: spi4-clk {
1722                                 rockchip,pins =
1723                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1724                         };
1725                         spi4_cs0: spi4-cs0 {
1726                                 rockchip,pins =
1727                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1728                         };
1729                         spi4_rx: spi4-rx {
1730                                 rockchip,pins =
1731                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1732                         };
1733                         spi4_tx: spi4-tx {
1734                                 rockchip,pins =
1735                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1736                         };
1737                 };
1738
1739                 spi5 {
1740                         spi5_clk: spi5-clk {
1741                                 rockchip,pins =
1742                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1743                         };
1744                         spi5_cs0: spi5-cs0 {
1745                                 rockchip,pins =
1746                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1747                         };
1748                         spi5_rx: spi5-rx {
1749                                 rockchip,pins =
1750                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1751                         };
1752                         spi5_tx: spi5-tx {
1753                                 rockchip,pins =
1754                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1755                         };
1756                 };
1757
1758                 tsadc {
1759                         otp_gpio: otp-gpio {
1760                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1761                         };
1762
1763                         otp_out: otp-out {
1764                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1765                         };
1766                 };
1767
1768                 uart0 {
1769                         uart0_xfer: uart0-xfer {
1770                                 rockchip,pins =
1771                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1772                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774
1775                         uart0_cts: uart0-cts {
1776                                 rockchip,pins =
1777                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1778                         };
1779
1780                         uart0_rts: uart0-rts {
1781                                 rockchip,pins =
1782                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1783                         };
1784                 };
1785
1786                 uart1 {
1787                         uart1_xfer: uart1-xfer {
1788                                 rockchip,pins =
1789                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1790                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1791                         };
1792                 };
1793
1794                 uart2a {
1795                         uart2a_xfer: uart2a-xfer {
1796                                 rockchip,pins =
1797                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1798                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1799                         };
1800                 };
1801
1802                 uart2b {
1803                         uart2b_xfer: uart2b-xfer {
1804                                 rockchip,pins =
1805                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1806                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1807                         };
1808                 };
1809
1810                 uart2c {
1811                         uart2c_xfer: uart2c-xfer {
1812                                 rockchip,pins =
1813                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1814                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1815                         };
1816                 };
1817
1818                 uart3 {
1819                         uart3_xfer: uart3-xfer {
1820                                 rockchip,pins =
1821                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1822                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1823                         };
1824
1825                         uart3_cts: uart3-cts {
1826                                 rockchip,pins =
1827                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1828                         };
1829
1830                         uart3_rts: uart3-rts {
1831                                 rockchip,pins =
1832                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 uart4 {
1837                         uart4_xfer: uart4-xfer {
1838                                 rockchip,pins =
1839                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1840                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1841                         };
1842                 };
1843
1844                 uarthdcp {
1845                         uarthdcp_xfer: uarthdcp-xfer {
1846                                 rockchip,pins =
1847                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1848                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1849                         };
1850                 };
1851
1852                 pwm0 {
1853                         pwm0_pin: pwm0-pin {
1854                                 rockchip,pins =
1855                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1856                         };
1857
1858                         vop0_pwm_pin: vop0-pwm-pin {
1859                                 rockchip,pins =
1860                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1861                         };
1862                 };
1863
1864                 pwm1 {
1865                         pwm1_pin: pwm1-pin {
1866                                 rockchip,pins =
1867                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1868                         };
1869
1870                         vop1_pwm_pin: vop1-pwm-pin {
1871                                 rockchip,pins =
1872                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1873                         };
1874                 };
1875
1876                 pwm2 {
1877                         pwm2_pin: pwm2-pin {
1878                                 rockchip,pins =
1879                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1880                         };
1881                 };
1882
1883                 pwm3a {
1884                         pwm3a_pin: pwm3a-pin {
1885                                 rockchip,pins =
1886                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1887                         };
1888                 };
1889
1890                 pwm3b {
1891                         pwm3b_pin: pwm3b-pin {
1892                                 rockchip,pins =
1893                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1894                         };
1895                 };
1896
1897                 edp {
1898                         edp_hpd: edp-hpd {
1899                                 rockchip,pins =
1900                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1901                         };
1902                 };
1903         };
1904 };