2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/clock/rk3399-cru.h>
43 #include <dt-bindings/gpio/gpio.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pinctrl/rockchip.h>
49 compatible = "rockchip,rk3399";
50 interrupt-parent = <&gic>;
93 compatible = "arm,cortex-a53", "arm,armv8";
99 compatible = "arm,cortex-a53", "arm,armv8";
105 compatible = "arm,cortex-a53", "arm,armv8";
111 compatible = "arm,cortex-a53", "arm,armv8";
117 compatible = "arm,cortex-a72", "arm,armv8";
123 compatible = "arm,cortex-a72", "arm,armv8";
129 compatible = "arm,armv8-timer";
130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
137 compatible = "fixed-clock";
139 clock-frequency = <24000000>;
140 clock-output-names = "xin24m";
143 gic: interrupt-controller@fee00000 {
144 compatible = "arm,gic-v3";
145 #interrupt-cells = <3>;
146 #address-cells = <2>;
149 interrupt-controller;
151 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
152 <0x0 0xfef00000 0 0xc0000>, /* GICR */
153 <0x0 0xfff00000 0 0x10000>, /* GICC */
154 <0x0 0xfff10000 0 0x10000>, /* GICH */
155 <0x0 0xfff20000 0 0x10000>; /* GICV */
156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
157 its: interrupt-controller@fee20000 {
158 compatible = "arm,gic-v3-its";
160 reg = <0x0 0xfee20000 0x0 0x20000>;
165 compatible = "arm,amba-bus";
166 #address-cells = <2>;
170 dmac_bus: dma-controller@ff6d0000 {
171 compatible = "arm,pl330", "arm,primecell";
172 reg = <0x0 0xff6d0000 0x0 0x4000>;
173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cru ACLK_DMAC0_PERILP>;
177 clock-names = "apb_pclk";
180 dmac_peri: dma-controller@ff6e0000 {
181 compatible = "arm,pl330", "arm,primecell";
182 reg = <0x0 0xff6e0000 0x0 0x4000>;
183 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cru ACLK_DMAC1_PERILP>;
187 clock-names = "apb_pclk";
192 compatible = "rockchip,rk3399-emmc-phy";
195 rockchip,grf = <&grf>;
199 sdio0: dwmmc@fe310000 {
200 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
201 reg = <0x0 0xfe310000 0x0 0x4000>;
202 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
203 clock-freq-min-max = <400000 150000000>;
204 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
205 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
206 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
207 fifo-depth = <0x100>;
211 sdmmc: dwmmc@fe320000 {
212 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
213 reg = <0x0 0xfe320000 0x0 0x4000>;
214 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
215 clock-freq-min-max = <400000 150000000>;
216 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
217 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
218 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
219 fifo-depth = <0x100>;
223 sdhci: sdhci@fe330000 {
224 compatible = "arasan,sdhci-5.1";
225 reg = <0x0 0xfe330000 0x0 0x10000>;
226 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
228 clock-names = "clk_xin", "clk_ahb";
230 phy-names = "phy_arasan";
234 uart0: serial@ff180000 {
235 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
236 reg = <0x0 0xff180000 0x0 0x100>;
237 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
238 clock-names = "baudclk", "apb_pclk";
239 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
245 uart1: serial@ff190000 {
246 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
247 reg = <0x0 0xff190000 0x0 0x100>;
248 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
249 clock-names = "baudclk", "apb_pclk";
250 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
256 uart2: serial@ff1a0000 {
257 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
258 reg = <0x0 0xff1a0000 0x0 0x100>;
259 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
260 clock-names = "baudclk", "apb_pclk";
261 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
267 uart3: serial@ff1b0000 {
268 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
269 reg = <0x0 0xff1b0000 0x0 0x100>;
270 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
271 clock-names = "baudclk", "apb_pclk";
272 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
279 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
280 reg = <0x0 0xff110000 0x0 0x1000>;
281 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
282 clock-names = "spiclk", "apb_pclk";
283 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
286 #address-cells = <1>;
292 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
293 reg = <0x0 0xff120000 0x0 0x1000>;
294 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
295 clock-names = "spiclk", "apb_pclk";
296 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
299 #address-cells = <1>;
305 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
306 reg = <0x0 0xff130000 0x0 0x1000>;
307 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
308 clock-names = "spiclk", "apb_pclk";
309 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
312 #address-cells = <1>;
318 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
319 reg = <0x0 0xff120000 0x0 0x1000>;
320 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
321 clock-names = "spiclk", "apb_pclk";
322 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
325 #address-cells = <1>;
331 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
332 reg = <0x0 0xff130000 0x0 0x1000>;
333 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
334 clock-names = "spiclk", "apb_pclk";
335 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
338 #address-cells = <1>;
343 pmugrf: syscon@ff320000 {
344 compatible = "rockchip,rk3399-pmugrf", "syscon";
345 reg = <0x0 0xff320000 0x0 0x1000>;
349 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
350 reg = <0x0 0xff110000 0x0 0x1000>;
351 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
352 clock-names = "spiclk", "apb_pclk";
353 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
356 #address-cells = <1>;
361 uart4: serial@ff370000 {
362 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
363 reg = <0x0 0xff370000 0x0 0x100>;
364 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
365 clock-names = "baudclk", "apb_pclk";
366 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
372 pmucru: pmu-clock-controller@ff750000 {
373 compatible = "rockchip,rk3399-pmucru";
374 reg = <0x0 0xff750000 0x0 0x1000>;
375 rockchip,grf = <&pmugrf>;
380 cru: clock-controller@ff760000 {
381 compatible = "rockchip,rk3399-cru";
382 reg = <0x0 0xff760000 0x0 0x1000>;
383 rockchip,grf = <&grf>;
388 grf: syscon@ff770000 {
389 compatible = "rockchip,rk3399-grf", "syscon";
390 reg = <0x0 0xff770000 0x0 0x10000>;
394 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
395 reg = <0x0 0xff880000 0x0 0x1000>;
396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
399 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
400 dma-names = "tx", "rx";
401 clock-names = "i2s_hclk", "i2s_clk";
402 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
407 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
408 reg = <0x0 0xff890000 0x0 0x1000>;
409 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>;
412 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
413 dma-names = "tx", "rx";
414 clock-names = "i2s_hclk", "i2s_clk";
415 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
420 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
421 reg = <0x0 0xff8a0000 0x0 0x1000>;
422 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
425 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
426 dma-names = "tx", "rx";
427 clock-names = "i2s_hclk", "i2s_clk";
428 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
433 compatible = "rockchip,rk3399-pinctrl";
434 rockchip,grf = <&grf>;
435 rockchip,pmu = <&pmugrf>;
436 #address-cells = <0x2>;
440 gpio0: gpio0@ff720000 {
441 compatible = "rockchip,gpio-bank";
442 reg = <0x0 0xff720000 0x0 0x100>;
444 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-controller;
450 #interrupt-cells = <0x2>;
453 gpio1: gpio1@ff730000 {
454 compatible = "rockchip,gpio-bank";
455 reg = <0x0 0xff730000 0x0 0x100>;
457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-controller;
463 #interrupt-cells = <0x2>;
466 gpio2: gpio2@ff780000 {
467 compatible = "rockchip,gpio-bank";
468 reg = <0x0 0xff780000 0x0 0x100>;
470 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
475 interrupt-controller;
476 #interrupt-cells = <0x2>;
479 gpio3: gpio3@ff788000 {
480 compatible = "rockchip,gpio-bank";
481 reg = <0x0 0xff788000 0x0 0x100>;
483 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-controller;
489 #interrupt-cells = <0x2>;
492 gpio4: gpio4@ff790000 {
493 compatible = "rockchip,gpio-bank";
494 reg = <0x0 0xff790000 0x0 0x100>;
496 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
501 interrupt-controller;
502 #interrupt-cells = <0x2>;
505 pcfg_pull_up: pcfg-pull-up {
509 pcfg_pull_down: pcfg-pull-down {
513 pcfg_pull_none: pcfg-pull-none {
517 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
519 drive-strength = <12>;
522 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
524 drive-strength = <8>;
527 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
529 drive-strength = <4>;
532 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
534 drive-strength = <2>;
537 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
539 drive-strength = <12>;
545 <0 5 RK_FUNC_1 &pcfg_pull_up>;
550 rgmii_pins: rgmii-pins {
552 <3 11 RK_FUNC_1 &pcfg_pull_none>,
553 <3 13 RK_FUNC_1 &pcfg_pull_none>,
554 <3 8 RK_FUNC_1 &pcfg_pull_none>,
555 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
556 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
557 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
558 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
559 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
560 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
561 <3 6 RK_FUNC_1 &pcfg_pull_none>,
562 <3 7 RK_FUNC_1 &pcfg_pull_none>,
563 <3 2 RK_FUNC_1 &pcfg_pull_none>,
564 <3 3 RK_FUNC_1 &pcfg_pull_none>,
565 <3 14 RK_FUNC_1 &pcfg_pull_none>,
566 <3 9 RK_FUNC_1 &pcfg_pull_none>;
569 rmii_pins: rmii-pins {
571 <3 11 RK_FUNC_1 &pcfg_pull_none>,
572 <3 13 RK_FUNC_1 &pcfg_pull_none>,
573 <3 8 RK_FUNC_1 &pcfg_pull_none>,
574 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
575 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
576 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
577 <3 6 RK_FUNC_1 &pcfg_pull_none>,
578 <3 7 RK_FUNC_1 &pcfg_pull_none>,
579 <3 9 RK_FUNC_1 &pcfg_pull_none>,
580 <3 10 RK_FUNC_1 &pcfg_pull_none>;
585 i2c0_xfer: i2c0-xfer {
587 <1 15 RK_FUNC_2 &pcfg_pull_none>,
588 <1 16 RK_FUNC_2 &pcfg_pull_none>;
593 i2c1_xfer: i2c1-xfer {
595 <4 2 RK_FUNC_1 &pcfg_pull_none>,
596 <4 1 RK_FUNC_1 &pcfg_pull_none>;
601 i2c2_xfer: i2c2-xfer {
603 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
604 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
609 i2c3_xfer: i2c3-xfer {
611 <4 17 RK_FUNC_1 &pcfg_pull_none>,
612 <4 16 RK_FUNC_1 &pcfg_pull_none>;
617 i2c4_xfer: i2c4-xfer {
619 <1 12 RK_FUNC_1 &pcfg_pull_none>,
620 <1 11 RK_FUNC_1 &pcfg_pull_none>;
625 i2c5_xfer: i2c5-xfer {
627 <3 11 RK_FUNC_2 &pcfg_pull_none>,
628 <3 10 RK_FUNC_2 &pcfg_pull_none>;
633 i2c6_xfer: i2c6-xfer {
635 <2 10 RK_FUNC_2 &pcfg_pull_none>,
636 <2 9 RK_FUNC_2 &pcfg_pull_none>;
641 i2c7_xfer: i2c7-xfer {
643 <2 8 RK_FUNC_2 &pcfg_pull_none>,
644 <2 7 RK_FUNC_2 &pcfg_pull_none>;
649 i2c8_xfer: i2c8-xfer {
651 <1 21 RK_FUNC_1 &pcfg_pull_none>,
652 <1 20 RK_FUNC_1 &pcfg_pull_none>;
657 i2s0_8ch_bus: i2s0-8ch-bus {
659 <3 24 RK_FUNC_1 &pcfg_pull_none>,
660 <3 25 RK_FUNC_1 &pcfg_pull_none>,
661 <3 26 RK_FUNC_1 &pcfg_pull_none>,
662 <3 27 RK_FUNC_1 &pcfg_pull_none>,
663 <3 28 RK_FUNC_1 &pcfg_pull_none>,
664 <3 29 RK_FUNC_1 &pcfg_pull_none>,
665 <3 30 RK_FUNC_1 &pcfg_pull_none>,
666 <3 31 RK_FUNC_1 &pcfg_pull_none>,
667 <4 0 RK_FUNC_1 &pcfg_pull_none>;
672 i2s1_2ch_bus: i2s1-2ch-bus {
674 <4 3 RK_FUNC_1 &pcfg_pull_none>,
675 <4 4 RK_FUNC_1 &pcfg_pull_none>,
676 <4 5 RK_FUNC_1 &pcfg_pull_none>,
677 <4 6 RK_FUNC_1 &pcfg_pull_none>,
678 <4 7 RK_FUNC_1 &pcfg_pull_none>;
683 sdio0_bus1: sdio0-bus1 {
685 <2 20 RK_FUNC_1 &pcfg_pull_up>;
688 sdio0_bus4: sdio0-bus4 {
690 <2 20 RK_FUNC_1 &pcfg_pull_up>,
691 <2 21 RK_FUNC_1 &pcfg_pull_up>,
692 <2 22 RK_FUNC_1 &pcfg_pull_up>,
693 <2 23 RK_FUNC_1 &pcfg_pull_up>;
696 sdio0_cmd: sdio0-cmd {
698 <2 24 RK_FUNC_1 &pcfg_pull_up>;
701 sdio0_clk: sdio0-clk {
703 <2 25 RK_FUNC_1 &pcfg_pull_none>;
708 <2 26 RK_FUNC_1 &pcfg_pull_up>;
711 sdio0_pwr: sdio0-pwr {
713 <2 27 RK_FUNC_1 &pcfg_pull_up>;
716 sdio0_bkpwr: sdio0-bkpwr {
718 <2 28 RK_FUNC_1 &pcfg_pull_up>;
723 <0 3 RK_FUNC_1 &pcfg_pull_up>;
726 sdio0_int: sdio0-int {
728 <0 4 RK_FUNC_1 &pcfg_pull_up>;
733 sdmmc_bus1: sdmmc-bus1 {
735 <4 8 RK_FUNC_1 &pcfg_pull_up>;
738 sdmmc_bus4: sdmmc-bus4 {
740 <4 8 RK_FUNC_1 &pcfg_pull_up>,
741 <4 9 RK_FUNC_1 &pcfg_pull_up>,
742 <4 10 RK_FUNC_1 &pcfg_pull_up>,
743 <4 11 RK_FUNC_1 &pcfg_pull_up>;
746 sdmmc_clk: sdmmc-clk {
748 <4 12 RK_FUNC_1 &pcfg_pull_none>;
751 sdmmc_cmd: sdmmc-cmd {
753 <4 13 RK_FUNC_1 &pcfg_pull_up>;
758 <0 7 RK_FUNC_1 &pcfg_pull_up>;
763 <0 8 RK_FUNC_1 &pcfg_pull_up>;
770 <3 6 RK_FUNC_2 &pcfg_pull_up>;
774 <3 7 RK_FUNC_2 &pcfg_pull_up>;
778 <3 8 RK_FUNC_2 &pcfg_pull_up>;
782 <3 5 RK_FUNC_2 &pcfg_pull_up>;
786 <3 4 RK_FUNC_2 &pcfg_pull_up>;
793 <1 9 RK_FUNC_2 &pcfg_pull_up>;
797 <1 10 RK_FUNC_2 &pcfg_pull_up>;
801 <1 7 RK_FUNC_2 &pcfg_pull_up>;
805 <1 8 RK_FUNC_2 &pcfg_pull_up>;
812 <2 11 RK_FUNC_1 &pcfg_pull_up>;
816 <2 12 RK_FUNC_1 &pcfg_pull_up>;
820 <2 9 RK_FUNC_1 &pcfg_pull_up>;
824 <2 10 RK_FUNC_1 &pcfg_pull_up>;
831 <1 17 RK_FUNC_1 &pcfg_pull_up>;
835 <1 18 RK_FUNC_1 &pcfg_pull_up>;
839 <1 15 RK_FUNC_1 &pcfg_pull_up>;
843 <1 16 RK_FUNC_1 &pcfg_pull_up>;
850 <3 2 RK_FUNC_2 &pcfg_pull_up>;
854 <3 3 RK_FUNC_2 &pcfg_pull_up>;
858 <3 0 RK_FUNC_2 &pcfg_pull_up>;
862 <3 1 RK_FUNC_2 &pcfg_pull_up>;
869 <2 22 RK_FUNC_2 &pcfg_pull_up>;
873 <2 23 RK_FUNC_2 &pcfg_pull_up>;
877 <2 20 RK_FUNC_2 &pcfg_pull_up>;
881 <2 21 RK_FUNC_2 &pcfg_pull_up>;
886 uart0_xfer: uart0-xfer {
888 <2 16 RK_FUNC_1 &pcfg_pull_up>,
889 <2 17 RK_FUNC_1 &pcfg_pull_none>;
892 uart0_cts: uart0-cts {
894 <2 18 RK_FUNC_1 &pcfg_pull_none>;
897 uart0_rts: uart0-rts {
899 <2 19 RK_FUNC_1 &pcfg_pull_none>;
904 uart1_xfer: uart1-xfer {
906 <3 12 RK_FUNC_2 &pcfg_pull_up>,
907 <3 13 RK_FUNC_2 &pcfg_pull_none>;
912 uart2a_xfer: uart2a-xfer {
914 <4 8 RK_FUNC_2 &pcfg_pull_up>,
915 <4 9 RK_FUNC_2 &pcfg_pull_none>;
920 uart2b_xfer: uart2b-xfer {
922 <4 16 RK_FUNC_2 &pcfg_pull_up>,
923 <4 17 RK_FUNC_2 &pcfg_pull_none>;
928 uart2c_xfer: uart2c-xfer {
930 <4 19 RK_FUNC_1 &pcfg_pull_up>,
931 <4 20 RK_FUNC_1 &pcfg_pull_none>;
936 uart3_xfer: uart3-xfer {
938 <3 14 RK_FUNC_2 &pcfg_pull_up>,
939 <3 15 RK_FUNC_2 &pcfg_pull_none>;
942 uart3_cts: uart3-cts {
944 <3 18 RK_FUNC_2 &pcfg_pull_none>;
947 uart3_rts: uart3-rts {
949 <3 19 RK_FUNC_2 &pcfg_pull_none>;
954 uart4_xfer: uart4-xfer {
956 <1 7 RK_FUNC_1 &pcfg_pull_up>,
957 <1 8 RK_FUNC_1 &pcfg_pull_none>;
962 uarthdcp_xfer: uarthdcp-xfer {
964 <4 21 RK_FUNC_2 &pcfg_pull_up>,
965 <4 22 RK_FUNC_2 &pcfg_pull_none>;
972 <4 18 RK_FUNC_1 &pcfg_pull_none>;
975 vop0_pwm_pin: vop0-pwm-pin {
977 <4 18 RK_FUNC_2 &pcfg_pull_none>;
984 <4 22 RK_FUNC_1 &pcfg_pull_none>;
987 vop1_pwm_pin: vop1-pwm-pin {
989 <4 18 RK_FUNC_3 &pcfg_pull_none>;