arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48
  49 / {
  50         compatible = "rockchip,rk3399";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 i2c6 = &i2c6;
  63                 i2c7 = &i2c7;
  64                 i2c8 = &i2c8;
  65                 serial0 = &uart0;
  66                 serial1 = &uart1;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69         };
  70
  71         cpus {
  72                 #address-cells = <2>;
  73                 #size-cells = <0>;
  74
  75                 cpu-map {
  76                         cluster0 {
  77                                 core0 {
  78                                         cpu = <&cpu_l0>;
  79                                 };
  80                                 core1 {
  81                                         cpu = <&cpu_l1>;
  82                                 };
  83                                 core2 {
  84                                         cpu = <&cpu_l2>;
  85                                 };
  86                                 core3 {
  87                                         cpu = <&cpu_l3>;
  88                                 };
  89                         };
  90
  91                         cluster1 {
  92                                 core0 {
  93                                         cpu = <&cpu_b0>;
  94                                 };
  95                                 core1 {
  96                                         cpu = <&cpu_b1>;
  97                                 };
  98                         };
  99                 };
 100
 101                 cpu_l0: cpu@0 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x0>;
 105
 106                         #cooling-cells = <2>; /* min followed by max */
 107                 };
 108
 109                 cpu_l1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x1>;
 113                 };
 114
 115                 cpu_l2: cpu@2 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x2>;
 119                 };
 120
 121                 cpu_l3: cpu@3 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x3>;
 125                 };
 126
 127                 cpu_b0: cpu@100 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a72", "arm,armv8";
 130                         reg = <0x0 0x100>;
 131
 132                         #cooling-cells = <2>; /* min followed by max */
 133                 };
 134
 135                 cpu_b1: cpu@101 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72", "arm,armv8";
 138                         reg = <0x0 0x101>;
 139                 };
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv8-timer";
 144                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 148         };
 149
 150         xin24m: xin24m {
 151                 compatible = "fixed-clock";
 152                 #clock-cells = <0>;
 153                 clock-frequency = <24000000>;
 154                 clock-output-names = "xin24m";
 155         };
 156
 157         gic: interrupt-controller@fee00000 {
 158                 compatible = "arm,gic-v3";
 159                 #interrupt-cells = <3>;
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163                 interrupt-controller;
 164
 165                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 166                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 167                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 168                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 169                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 170                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 171                 its: interrupt-controller@fee20000 {
 172                         compatible = "arm,gic-v3-its";
 173                         msi-controller;
 174                         reg = <0x0 0xfee20000 0x0 0x20000>;
 175                 };
 176         };
 177
 178         amba {
 179                 compatible = "arm,amba-bus";
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 ranges;
 183
 184                 dmac_bus: dma-controller@ff6d0000 {
 185                         compatible = "arm,pl330", "arm,primecell";
 186                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 187                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 189                         #dma-cells = <1>;
 190                         clocks = <&cru ACLK_DMAC0_PERILP>;
 191                         clock-names = "apb_pclk";
 192                 };
 193
 194                 dmac_peri: dma-controller@ff6e0000 {
 195                         compatible = "arm,pl330", "arm,primecell";
 196                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 197                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 199                         #dma-cells = <1>;
 200                         clocks = <&cru ACLK_DMAC1_PERILP>;
 201                         clock-names = "apb_pclk";
 202                 };
 203         };
 204
 205         saradc: saradc@ff100000 {
 206                 compatible = "rockchip,rk3399-saradc";
 207                 reg = <0x0 0xff100000 0x0 0x100>;
 208                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 209                 #io-channel-cells = <1>;
 210                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 211                 clock-names = "saradc", "apb_pclk";
 212                 status = "disabled";
 213         };
 214
 215         i2c0: i2c@ff3c0000 {
 216                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 217                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 218                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 219                 clock-names = "i2c", "i2c_sclk";
 220                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 221                 pinctrl-names = "default";
 222                 pinctrl-0 = <&i2c0_xfer>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 status = "disabled";
 226         };
 227
 228         i2c1: i2c@ff110000 {
 229                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 232                 clock-names = "i2c", "i2c_sclk";
 233                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&i2c1_xfer>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         i2c2: i2c@ff120000 {
 242                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 245                 clock-names = "i2c", "i2c_sclk";
 246                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&i2c2_xfer>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         i2c3: i2c@ff130000 {
 255                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 256                 reg = <0x0 0xff130000 0x0 0x1000>;
 257                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 258                 clock-names = "i2c", "i2c_sclk";
 259                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&i2c3_xfer>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 status = "disabled";
 265         };
 266
 267         i2c5: i2c@ff140000 {
 268                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 269                 reg = <0x0 0xff140000 0x0 0x1000>;
 270                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 271                 clock-names = "i2c", "i2c_sclk";
 272                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&i2c5_xfer>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 status = "disabled";
 278         };
 279
 280         i2c6: i2c@ff150000 {
 281                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 282                 reg = <0x0 0xff150000 0x0 0x1000>;
 283                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 284                 clock-names = "i2c", "i2c_sclk";
 285                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&i2c6_xfer>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 status = "disabled";
 291         };
 292
 293         i2c7: i2c@ff160000 {
 294                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 295                 reg = <0x0 0xff160000 0x0 0x1000>;
 296                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 297                 clock-names = "i2c", "i2c_sclk";
 298                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&i2c7_xfer>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         emmc_phy: phy {
 307                 compatible = "rockchip,rk3399-emmc-phy";
 308                 reg-offset = <0xf780>;
 309                 #phy-cells = <0>;
 310                 rockchip,grf = <&grf>;
 311                 status = "disabled";
 312         };
 313
 314         sdio0: dwmmc@fe310000 {
 315                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 316                 reg = <0x0 0xfe310000 0x0 0x4000>;
 317                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 318                 clock-freq-min-max = <400000 150000000>;
 319                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 320                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 321                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 322                 fifo-depth = <0x100>;
 323                 status = "disabled";
 324         };
 325
 326         sdmmc: dwmmc@fe320000 {
 327                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 328                 reg = <0x0 0xfe320000 0x0 0x4000>;
 329                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 330                 clock-freq-min-max = <400000 150000000>;
 331                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 332                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 333                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 334                 fifo-depth = <0x100>;
 335                 status = "disabled";
 336         };
 337
 338         sdhci: sdhci@fe330000 {
 339                 compatible = "arasan,sdhci-5.1";
 340                 reg = <0x0 0xfe330000 0x0 0x10000>;
 341                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 343                 clock-names = "clk_xin", "clk_ahb";
 344                 phys = <&emmc_phy>;
 345                 phy-names = "phy_arasan";
 346                 status = "disabled";
 347         };
 348
 349         uart0: serial@ff180000 {
 350                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 351                 reg = <0x0 0xff180000 0x0 0x100>;
 352                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 353                 clock-names = "baudclk", "apb_pclk";
 354                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 355                 reg-shift = <2>;
 356                 reg-io-width = <4>;
 357                 status = "disabled";
 358         };
 359
 360         uart1: serial@ff190000 {
 361                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 362                 reg = <0x0 0xff190000 0x0 0x100>;
 363                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 366                 reg-shift = <2>;
 367                 reg-io-width = <4>;
 368                 status = "disabled";
 369         };
 370
 371         uart2: serial@ff1a0000 {
 372                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 373                 reg = <0x0 0xff1a0000 0x0 0x100>;
 374                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 375                 clock-names = "baudclk", "apb_pclk";
 376                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 377                 reg-shift = <2>;
 378                 reg-io-width = <4>;
 379                 status = "disabled";
 380         };
 381
 382         uart3: serial@ff1b0000 {
 383                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 384                 reg = <0x0 0xff1b0000 0x0 0x100>;
 385                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 386                 clock-names = "baudclk", "apb_pclk";
 387                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 388                 reg-shift = <2>;
 389                 reg-io-width = <4>;
 390                 status = "disabled";
 391         };
 392
 393         spi0: spi@ff1c0000 {
 394                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 395                 reg = <0x0 0xff110000 0x0 0x1000>;
 396                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 397                 clock-names = "spiclk", "apb_pclk";
 398                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 status = "disabled";
 404         };
 405
 406         spi1: spi@ff1d0000 {
 407                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 408                 reg = <0x0 0xff120000 0x0 0x1000>;
 409                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 410                 clock-names = "spiclk", "apb_pclk";
 411                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 status = "disabled";
 417         };
 418
 419         spi2: spi@ff1e0000 {
 420                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 421                 reg = <0x0 0xff130000 0x0 0x1000>;
 422                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 423                 clock-names = "spiclk", "apb_pclk";
 424                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 status = "disabled";
 430         };
 431
 432         spi4: spi@ff1f0000 {
 433                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 434                 reg = <0x0 0xff120000 0x0 0x1000>;
 435                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 436                 clock-names = "spiclk", "apb_pclk";
 437                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 status = "disabled";
 443         };
 444
 445         spi5: spi@ff200000 {
 446                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 447                 reg = <0x0 0xff130000 0x0 0x1000>;
 448                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 449                 clock-names = "spiclk", "apb_pclk";
 450                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 status = "disabled";
 456         };
 457
 458         thermal-zones {
 459                 #include "rk3368-thermal.dtsi"
 460         };
 461
 462         tsadc: tsadc@ff260000 {
 463                 compatible = "rockchip,rk3399-tsadc";
 464                 reg = <0x0 0xff260000 0x0 0x100>;
 465                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 467                 clock-names = "tsadc", "apb_pclk";
 468                 resets = <&cru SRST_TSADC>;
 469                 reset-names = "tsadc-apb";
 470                 pinctrl-names = "init", "default", "sleep";
 471                 pinctrl-0 = <&otp_gpio>;
 472                 pinctrl-1 = <&otp_out>;
 473                 pinctrl-2 = <&otp_gpio>;
 474                 #thermal-sensor-cells = <1>;
 475                 rockchip,hw-tshut-temp = <95000>;
 476                 status = "disabled";
 477         };
 478
 479         pmugrf: syscon@ff320000 {
 480                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 481                 reg = <0x0 0xff320000 0x0 0x1000>;
 482         };
 483
 484         spi3: spi@ff350000 {
 485                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 486                 reg = <0x0 0xff110000 0x0 0x1000>;
 487                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 488                 clock-names = "spiclk", "apb_pclk";
 489                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 status = "disabled";
 495         };
 496
 497         uart4: serial@ff370000 {
 498                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 499                 reg = <0x0 0xff370000 0x0 0x100>;
 500                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 status = "disabled";
 506         };
 507
 508         i2c4: i2c@ff3d0000 {
 509                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 510                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 511                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 512                 clock-names = "i2c", "i2c_sclk";
 513                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c4_xfer>;
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 status = "disabled";
 519         };
 520
 521         i2c8: i2c@ff3e0000 {
 522                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 523                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 524                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 525                 clock-names = "i2c", "i2c_sclk";
 526                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c8_xfer>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 status = "disabled";
 532         };
 533
 534         pwm0: pwm@ff420000 {
 535                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 536                 reg = <0x0 0xff420000 0x0 0x10>;
 537                 #pwm-cells = <3>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&pwm0_pin>;
 540                 clocks = <&cru PCLK_RKPWM_PMU>;
 541                 clock-names = "pwm";
 542                 status = "disabled";
 543         };
 544
 545         pwm1: pwm@ff420010 {
 546                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 547                 reg = <0x0 0xff420010 0x0 0x10>;
 548                 #pwm-cells = <3>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&pwm1_pin>;
 551                 clocks = <&cru PCLK_RKPWM_PMU>;
 552                 clock-names = "pwm";
 553                 status = "disabled";
 554         };
 555
 556         pwm2: pwm@ff420020 {
 557                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 558                 reg = <0x0 0xff420020 0x0 0x10>;
 559                 #pwm-cells = <3>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&pwm2_pin>;
 562                 clocks = <&cru PCLK_RKPWM_PMU>;
 563                 clock-names = "pwm";
 564                 status = "disabled";
 565         };
 566
 567         pwm3: pwm@ff420030 {
 568                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 569                 reg = <0x0 0xff420030 0x0 0x10>;
 570                 #pwm-cells = <3>;
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&pwm3a_pin>;
 573                 clocks = <&cru PCLK_RKPWM_PMU>;
 574                 clock-names = "pwm";
 575                 status = "disabled";
 576         };
 577
 578         pmucru: pmu-clock-controller@ff750000 {
 579                 compatible = "rockchip,rk3399-pmucru";
 580                 reg = <0x0 0xff750000 0x0 0x1000>;
 581                 rockchip,grf = <&pmugrf>;
 582                 #clock-cells = <1>;
 583                 #reset-cells = <1>;
 584         };
 585
 586         cru: clock-controller@ff760000 {
 587                 compatible = "rockchip,rk3399-cru";
 588                 reg = <0x0 0xff760000 0x0 0x1000>;
 589                 rockchip,grf = <&grf>;
 590                 #clock-cells = <1>;
 591                 #reset-cells = <1>;
 592         };
 593
 594         grf: syscon@ff770000 {
 595                 compatible = "rockchip,rk3399-grf", "syscon";
 596                 reg = <0x0 0xff770000 0x0 0x10000>;
 597         };
 598
 599         spdif: spdif@ff870000 {
 600                 compatible = "rockchip,rk3399-spdif";
 601                 reg = <0x0 0xff870000 0x0 0x1000>;
 602                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 603                 dmas = <&dmac_bus 7>;
 604                 dma-names = "tx";
 605                 clock-names = "hclk", "mclk";
 606                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&spdif_bus>;
 609                 status = "disabled";
 610         };
 611
 612         i2s0: i2s@ff880000 {
 613                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 614                 reg = <0x0 0xff880000 0x0 0x1000>;
 615                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 616                 #address-cells = <1>;
 617                 #size-cells = <0>;
 618                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 619                 dma-names = "tx", "rx";
 620                 clock-names = "i2s_hclk", "i2s_clk";
 621                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&i2s0_8ch_bus>;
 624                 status = "disabled";
 625         };
 626
 627         i2s1: i2s@ff890000 {
 628                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 629                 reg = <0x0 0xff890000 0x0 0x1000>;
 630                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 634                 dma-names = "tx", "rx";
 635                 clock-names = "i2s_hclk", "i2s_clk";
 636                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&i2s1_2ch_bus>;
 639                 status = "disabled";
 640         };
 641
 642         i2s2: i2s@ff8a0000 {
 643                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 644                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 645                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 649                 dma-names = "tx", "rx";
 650                 clock-names = "i2s_hclk", "i2s_clk";
 651                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 652                 status = "disabled";
 653         };
 654
 655         pinctrl: pinctrl {
 656                 compatible = "rockchip,rk3399-pinctrl";
 657                 rockchip,grf = <&grf>;
 658                 rockchip,pmu = <&pmugrf>;
 659                 #address-cells = <0x2>;
 660                 #size-cells = <0x2>;
 661                 ranges;
 662
 663                 gpio0: gpio0@ff720000 {
 664                         compatible = "rockchip,gpio-bank";
 665                         reg = <0x0 0xff720000 0x0 0x100>;
 666                         clocks = <&xin24m>;
 667                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 668
 669                         gpio-controller;
 670                         #gpio-cells = <0x2>;
 671
 672                         interrupt-controller;
 673                         #interrupt-cells = <0x2>;
 674                 };
 675
 676                 gpio1: gpio1@ff730000 {
 677                         compatible = "rockchip,gpio-bank";
 678                         reg = <0x0 0xff730000 0x0 0x100>;
 679                         clocks = <&xin24m>;
 680                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 681
 682                         gpio-controller;
 683                         #gpio-cells = <0x2>;
 684
 685                         interrupt-controller;
 686                         #interrupt-cells = <0x2>;
 687                 };
 688
 689                 gpio2: gpio2@ff780000 {
 690                         compatible = "rockchip,gpio-bank";
 691                         reg = <0x0 0xff780000 0x0 0x100>;
 692                         clocks = <&xin24m>;
 693                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 694
 695                         gpio-controller;
 696                         #gpio-cells = <0x2>;
 697
 698                         interrupt-controller;
 699                         #interrupt-cells = <0x2>;
 700                 };
 701
 702                 gpio3: gpio3@ff788000 {
 703                         compatible = "rockchip,gpio-bank";
 704                         reg = <0x0 0xff788000 0x0 0x100>;
 705                         clocks = <&xin24m>;
 706                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 707
 708                         gpio-controller;
 709                         #gpio-cells = <0x2>;
 710
 711                         interrupt-controller;
 712                         #interrupt-cells = <0x2>;
 713                 };
 714
 715                 gpio4: gpio4@ff790000 {
 716                         compatible = "rockchip,gpio-bank";
 717                         reg = <0x0 0xff790000 0x0 0x100>;
 718                         clocks = <&xin24m>;
 719                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 720
 721                         gpio-controller;
 722                         #gpio-cells = <0x2>;
 723
 724                         interrupt-controller;
 725                         #interrupt-cells = <0x2>;
 726                 };
 727
 728                 pcfg_pull_up: pcfg-pull-up {
 729                         bias-pull-up;
 730                 };
 731
 732                 pcfg_pull_down: pcfg-pull-down {
 733                         bias-pull-down;
 734                 };
 735
 736                 pcfg_pull_none: pcfg-pull-none {
 737                         bias-disable;
 738                 };
 739
 740                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 741                         bias-disable;
 742                         drive-strength = <12>;
 743                 };
 744
 745                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 746                         bias-pull-up;
 747                         drive-strength = <8>;
 748                 };
 749
 750                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 751                         bias-pull-down;
 752                         drive-strength = <4>;
 753                 };
 754
 755                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 756                         bias-pull-up;
 757                         drive-strength = <2>;
 758                 };
 759
 760                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 761                         bias-pull-down;
 762                         drive-strength = <12>;
 763                 };
 764
 765                 emmc {
 766                         emmc_pwr: emmc-pwr {
 767                                 rockchip,pins =
 768                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 769                         };
 770                 };
 771
 772                 gmac {
 773                         rgmii_pins: rgmii-pins {
 774                                 rockchip,pins =
 775                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 776                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 777                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 778                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 779                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 780                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 781                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 782                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 783                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 784                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 785                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 786                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 787                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 788                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 789                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 790                         };
 791
 792                         rmii_pins: rmii-pins {
 793                                 rockchip,pins =
 794                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 795                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 796                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 797                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 798                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 799                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 800                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 801                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 802                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 803                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 804                         };
 805                 };
 806
 807                 i2c0 {
 808                         i2c0_xfer: i2c0-xfer {
 809                                 rockchip,pins =
 810                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 811                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 812                         };
 813                 };
 814
 815                 i2c1 {
 816                         i2c1_xfer: i2c1-xfer {
 817                                 rockchip,pins =
 818                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 819                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 820                         };
 821                 };
 822
 823                 i2c2 {
 824                         i2c2_xfer: i2c2-xfer {
 825                                 rockchip,pins =
 826                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 827                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 828                         };
 829                 };
 830
 831                 i2c3 {
 832                         i2c3_xfer: i2c3-xfer {
 833                                 rockchip,pins =
 834                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 835                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 836                         };
 837                 };
 838
 839                 i2c4 {
 840                         i2c4_xfer: i2c4-xfer {
 841                                 rockchip,pins =
 842                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 843                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 844                         };
 845                 };
 846
 847                 i2c5 {
 848                         i2c5_xfer: i2c5-xfer {
 849                                 rockchip,pins =
 850                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 851                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 852                         };
 853                 };
 854
 855                 i2c6 {
 856                         i2c6_xfer: i2c6-xfer {
 857                                 rockchip,pins =
 858                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 859                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 860                         };
 861                 };
 862
 863                 i2c7 {
 864                         i2c7_xfer: i2c7-xfer {
 865                                 rockchip,pins =
 866                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 867                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 868                         };
 869                 };
 870
 871                 i2c8 {
 872                         i2c8_xfer: i2c8-xfer {
 873                                 rockchip,pins =
 874                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 875                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 876                         };
 877                 };
 878
 879                 i2s0 {
 880                         i2s0_8ch_bus: i2s0-8ch-bus {
 881                                 rockchip,pins =
 882                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 883                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 884                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 885                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 886                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 887                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 888                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 889                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 890                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 891                         };
 892                 };
 893
 894                 i2s1 {
 895                         i2s1_2ch_bus: i2s1-2ch-bus {
 896                                 rockchip,pins =
 897                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 898                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 899                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 900                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 901                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 902                         };
 903                 };
 904
 905                 sdio0 {
 906                         sdio0_bus1: sdio0-bus1 {
 907                                 rockchip,pins =
 908                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 909                         };
 910
 911                         sdio0_bus4: sdio0-bus4 {
 912                                 rockchip,pins =
 913                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 914                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 915                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 916                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 917                         };
 918
 919                         sdio0_cmd: sdio0-cmd {
 920                                 rockchip,pins =
 921                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 922                         };
 923
 924                         sdio0_clk: sdio0-clk {
 925                                 rockchip,pins =
 926                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 927                         };
 928
 929                         sdio0_cd: sdio0-cd {
 930                                 rockchip,pins =
 931                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 932                         };
 933
 934                         sdio0_pwr: sdio0-pwr {
 935                                 rockchip,pins =
 936                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 937                         };
 938
 939                         sdio0_bkpwr: sdio0-bkpwr {
 940                                 rockchip,pins =
 941                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 942                         };
 943
 944                         sdio0_wp: sdio0-wp {
 945                                 rockchip,pins =
 946                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 947                         };
 948
 949                         sdio0_int: sdio0-int {
 950                                 rockchip,pins =
 951                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 952                         };
 953                 };
 954
 955                 sdmmc {
 956                         sdmmc_bus1: sdmmc-bus1 {
 957                                 rockchip,pins =
 958                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 959                         };
 960
 961                         sdmmc_bus4: sdmmc-bus4 {
 962                                 rockchip,pins =
 963                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 964                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 965                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 966                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 967                         };
 968
 969                         sdmmc_clk: sdmmc-clk {
 970                                 rockchip,pins =
 971                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 972                         };
 973
 974                         sdmmc_cmd: sdmmc-cmd {
 975                                 rockchip,pins =
 976                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 977                         };
 978
 979                         sdmmc_cd: sdmcc-cd {
 980                                 rockchip,pins =
 981                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 982                         };
 983
 984                         sdmmc_wp: sdmmc-wp {
 985                                 rockchip,pins =
 986                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 987                         };
 988                 };
 989
 990                 spdif {
 991                         spdif_bus: spdif-bus {
 992                                 rockchip,pins =
 993                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 994                         };
 995                 };
 996
 997                 spi0 {
 998                         spi0_clk: spi0-clk {
 999                                 rockchip,pins =
1000                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1001                         };
1002                         spi0_cs0: spi0-cs0 {
1003                                 rockchip,pins =
1004                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1005                         };
1006                         spi0_cs1: spi0-cs1 {
1007                                 rockchip,pins =
1008                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1009                         };
1010                         spi0_tx: spi0-tx {
1011                                 rockchip,pins =
1012                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1013                         };
1014                         spi0_rx: spi0-rx {
1015                                 rockchip,pins =
1016                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1017                         };
1018                 };
1019
1020                 spi1 {
1021                         spi1_clk: spi1-clk {
1022                                 rockchip,pins =
1023                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1024                         };
1025                         spi1_cs0: spi1-cs0 {
1026                                 rockchip,pins =
1027                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1028                         };
1029                         spi1_rx: spi1-rx {
1030                                 rockchip,pins =
1031                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1032                         };
1033                         spi1_tx: spi1-tx {
1034                                 rockchip,pins =
1035                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1036                         };
1037                 };
1038
1039                 spi2 {
1040                         spi2_clk: spi2-clk {
1041                                 rockchip,pins =
1042                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1043                         };
1044                         spi2_cs0: spi2-cs0 {
1045                                 rockchip,pins =
1046                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1047                         };
1048                         spi2_rx: spi2-rx {
1049                                 rockchip,pins =
1050                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1051                         };
1052                         spi2_tx: spi2-tx {
1053                                 rockchip,pins =
1054                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1055                         };
1056                 };
1057
1058                 spi3 {
1059                         spi3_clk: spi3-clk {
1060                                 rockchip,pins =
1061                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1062                         };
1063                         spi3_cs0: spi3-cs0 {
1064                                 rockchip,pins =
1065                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1066                         };
1067                         spi3_rx: spi3-rx {
1068                                 rockchip,pins =
1069                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1070                         };
1071                         spi3_tx: spi3-tx {
1072                                 rockchip,pins =
1073                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1074                         };
1075                 };
1076
1077                 spi4 {
1078                         spi4_clk: spi4-clk {
1079                                 rockchip,pins =
1080                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1081                         };
1082                         spi4_cs0: spi4-cs0 {
1083                                 rockchip,pins =
1084                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1085                         };
1086                         spi4_rx: spi4-rx {
1087                                 rockchip,pins =
1088                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1089                         };
1090                         spi4_tx: spi4-tx {
1091                                 rockchip,pins =
1092                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1093                         };
1094                 };
1095
1096                 spi5 {
1097                         spi5_clk: spi5-clk {
1098                                 rockchip,pins =
1099                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1100                         };
1101                         spi5_cs0: spi5-cs0 {
1102                                 rockchip,pins =
1103                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1104                         };
1105                         spi5_rx: spi5-rx {
1106                                 rockchip,pins =
1107                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1108                         };
1109                         spi5_tx: spi5-tx {
1110                                 rockchip,pins =
1111                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1112                         };
1113                 };
1114
1115                 tsadc {
1116                         otp_gpio: otp-gpio {
1117                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1118                         };
1119
1120                         otp_out: otp-out {
1121                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1122                         };
1123                 };
1124
1125                 uart0 {
1126                         uart0_xfer: uart0-xfer {
1127                                 rockchip,pins =
1128                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1129                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1130                         };
1131
1132                         uart0_cts: uart0-cts {
1133                                 rockchip,pins =
1134                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136
1137                         uart0_rts: uart0-rts {
1138                                 rockchip,pins =
1139                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141                 };
1142
1143                 uart1 {
1144                         uart1_xfer: uart1-xfer {
1145                                 rockchip,pins =
1146                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1147                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 uart2a {
1152                         uart2a_xfer: uart2a-xfer {
1153                                 rockchip,pins =
1154                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1155                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 uart2b {
1160                         uart2b_xfer: uart2b-xfer {
1161                                 rockchip,pins =
1162                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1163                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1164                         };
1165                 };
1166
1167                 uart2c {
1168                         uart2c_xfer: uart2c-xfer {
1169                                 rockchip,pins =
1170                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1171                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1172                         };
1173                 };
1174
1175                 uart3 {
1176                         uart3_xfer: uart3-xfer {
1177                                 rockchip,pins =
1178                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1179                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1180                         };
1181
1182                         uart3_cts: uart3-cts {
1183                                 rockchip,pins =
1184                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1185                         };
1186
1187                         uart3_rts: uart3-rts {
1188                                 rockchip,pins =
1189                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1190                         };
1191                 };
1192
1193                 uart4 {
1194                         uart4_xfer: uart4-xfer {
1195                                 rockchip,pins =
1196                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1197                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1198                         };
1199                 };
1200
1201                 uarthdcp {
1202                         uarthdcp_xfer: uarthdcp-xfer {
1203                                 rockchip,pins =
1204                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1205                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1206                         };
1207                 };
1208
1209                 pwm0 {
1210                         pwm0_pin: pwm0-pin {
1211                                 rockchip,pins =
1212                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1213                         };
1214
1215                         vop0_pwm_pin: vop0-pwm-pin {
1216                                 rockchip,pins =
1217                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 pwm1 {
1222                         pwm1_pin: pwm1-pin {
1223                                 rockchip,pins =
1224                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1225                         };
1226
1227                         vop1_pwm_pin: vop1-pwm-pin {
1228                                 rockchip,pins =
1229                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1230                         };
1231                 };
1232
1233                 pwm2 {
1234                         pwm2_pin: pwm2-pin {
1235                                 rockchip,pins =
1236                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 pwm3a {
1241                         pwm3a_pin: pwm3a-pin {
1242                                 rockchip,pins =
1243                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1244                         };
1245                 };
1246
1247                 pwm3b {
1248                         pwm3b_pin: pwm3b-pin {
1249                                 rockchip,pins =
1250                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1251                         };
1252                 };
1253         };
1254 };