arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 power-domains = <&power RK3399_PD_GMAC>;
 326                 status = "disabled";
 327         };
 328
 329         emmc_phy: phy {
 330                 compatible = "rockchip,rk3399-emmc-phy";
 331                 reg-offset = <0xf780>;
 332                 #phy-cells = <0>;
 333                 rockchip,grf = <&grf>;
 334                 ctrl-base = <0xfe330000>;
 335                 status = "disabled";
 336         };
 337
 338         sdio0: dwmmc@fe310000 {
 339                 compatible = "rockchip,rk3399-dw-mshc",
 340                              "rockchip,rk3288-dw-mshc";
 341                 reg = <0x0 0xfe310000 0x0 0x4000>;
 342                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 343                 clock-freq-min-max = <400000 150000000>;
 344                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 345                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 346                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 347                 fifo-depth = <0x100>;
 348                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 349                 status = "disabled";
 350         };
 351
 352         sdmmc: dwmmc@fe320000 {
 353                 compatible = "rockchip,rk3399-dw-mshc",
 354                              "rockchip,rk3288-dw-mshc";
 355                 reg = <0x0 0xfe320000 0x0 0x4000>;
 356                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 357                 clock-freq-min-max = <400000 150000000>;
 358                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 359                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 360                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 361                 fifo-depth = <0x100>;
 362                 power-domains = <&power RK3399_PD_SD>;
 363                 status = "disabled";
 364         };
 365
 366         sdhci: sdhci@fe330000 {
 367                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 368                 reg = <0x0 0xfe330000 0x0 0x10000>;
 369                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 370                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 371                 clock-names = "clk_xin", "clk_ahb";
 372                 assigned-clocks = <&cru SCLK_EMMC>;
 373                 assigned-clock-parents = <&cru PLL_CPLL>;
 374                 assigned-clock-rates = <200000000>;
 375                 phys = <&emmc_phy>;
 376                 phy-names = "phy_arasan";
 377                 power-domains = <&power RK3399_PD_EMMC>;
 378                 status = "disabled";
 379         };
 380
 381         usb_host0_ehci: usb@fe380000 {
 382                 compatible = "generic-ehci";
 383                 reg = <0x0 0xfe380000 0x0 0x20000>;
 384                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 386                          <&cru SCLK_USBPHY0_480M_SRC>;
 387                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 388                 phys = <&u2phy0_host>;
 389                 phy-names = "usb";
 390                 power-domains = <&power RK3399_PD_PERIHP>;
 391                 status = "disabled";
 392         };
 393
 394         usb_host0_ohci: usb@fe3a0000 {
 395                 compatible = "generic-ohci";
 396                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 397                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 399                          <&cru SCLK_USBPHY0_480M_SRC>;
 400                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 401                 phys = <&u2phy0_host>;
 402                 phy-names = "usb";
 403                 power-domains = <&power RK3399_PD_PERIHP>;
 404                 status = "disabled";
 405         };
 406
 407         usb_host1_ehci: usb@fe3c0000 {
 408                 compatible = "generic-ehci";
 409                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 410                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 411                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 412                          <&cru SCLK_USBPHY1_480M_SRC>;
 413                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 414                 phys = <&u2phy1_host>;
 415                 phy-names = "usb";
 416                 power-domains = <&power RK3399_PD_PERIHP>;
 417                 status = "disabled";
 418         };
 419
 420         usb_host1_ohci: usb@fe3e0000 {
 421                 compatible = "generic-ohci";
 422                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 423                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 424                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 425                          <&cru SCLK_USBPHY1_480M_SRC>;
 426                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 427                 phys = <&u2phy1_host>;
 428                 phy-names = "usb";
 429                 power-domains = <&power RK3399_PD_PERIHP>;
 430                 status = "disabled";
 431         };
 432
 433         usbdrd3_0: usb@fe800000 {
 434                 compatible = "rockchip,dwc3";
 435                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 436                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 437                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 438                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 439                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 440                               "aclk_usb3", "aclk_usb3_grf";
 441                 power-domains = <&power RK3399_PD_USB3>;
 442                 #address-cells = <2>;
 443                 #size-cells = <2>;
 444                 ranges;
 445                 status = "disabled";
 446                 usbdrd_dwc3_0: dwc3@fe800000 {
 447                         compatible = "snps,dwc3";
 448                         reg = <0x0 0xfe800000 0x0 0x100000>;
 449                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 450                         dr_mode = "otg";
 451                         phys = <&u2phy0_otg>;
 452                         phy-names = "usb2-phy";
 453                         snps,dis_enblslpm_quirk;
 454                         snps,phyif_utmi_16_bits;
 455                         snps,dis_u2_freeclk_exists_quirk;
 456                         snps,dis_del_phy_power_chg_quirk;
 457                         snps,xhci_slow_suspend_quirk;
 458                         status = "disabled";
 459                 };
 460         };
 461
 462         usbdrd3_1: usb@fe900000 {
 463                 compatible = "rockchip,dwc3";
 464                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 465                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 466                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 467                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 468                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 469                               "aclk_usb3", "aclk_usb3_grf";
 470                 power-domains = <&power RK3399_PD_USB3>;
 471                 #address-cells = <2>;
 472                 #size-cells = <2>;
 473                 ranges;
 474                 status = "disabled";
 475                 usbdrd_dwc3_1: dwc3@fe900000 {
 476                         compatible = "snps,dwc3";
 477                         reg = <0x0 0xfe900000 0x0 0x100000>;
 478                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 479                         dr_mode = "otg";
 480                         phys = <&u2phy1_otg>;
 481                         phy-names = "usb2-phy";
 482                         snps,dis_enblslpm_quirk;
 483                         snps,phyif_utmi_16_bits;
 484                         snps,dis_u2_freeclk_exists_quirk;
 485                         snps,dis_del_phy_power_chg_quirk;
 486                         snps,xhci_slow_suspend_quirk;
 487                         status = "disabled";
 488                 };
 489         };
 490
 491         gic: interrupt-controller@fee00000 {
 492                 compatible = "arm,gic-v3";
 493                 #interrupt-cells = <4>;
 494                 #address-cells = <2>;
 495                 #size-cells = <2>;
 496                 ranges;
 497                 interrupt-controller;
 498
 499                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 500                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 501                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 502                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 503                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 504                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 505                 its: interrupt-controller@fee20000 {
 506                         compatible = "arm,gic-v3-its";
 507                         msi-controller;
 508                         reg = <0x0 0xfee20000 0x0 0x20000>;
 509                 };
 510
 511                 ppi-partitions {
 512                         part0: interrupt-partition-0 {
 513                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 514                         };
 515
 516                         part1: interrupt-partition-1 {
 517                                 affinity = <&cpu_b0 &cpu_b1>;
 518                         };
 519                 };
 520         };
 521
 522         saradc: saradc@ff100000 {
 523                 compatible = "rockchip,rk3399-saradc";
 524                 reg = <0x0 0xff100000 0x0 0x100>;
 525                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 526                 #io-channel-cells = <1>;
 527                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 528                 clock-names = "saradc", "apb_pclk";
 529                 status = "disabled";
 530         };
 531
 532         i2c0: i2c@ff3c0000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 535                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c0_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c1: i2c@ff110000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff110000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c1_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         i2c2: i2c@ff120000 {
 559                 compatible = "rockchip,rk3399-i2c";
 560                 reg = <0x0 0xff120000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 562                 clock-names = "i2c", "pclk";
 563                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c2_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c3: i2c@ff130000 {
 572                 compatible = "rockchip,rk3399-i2c";
 573                 reg = <0x0 0xff130000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 575                 clock-names = "i2c", "pclk";
 576                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c3_xfer>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         i2c5: i2c@ff140000 {
 585                 compatible = "rockchip,rk3399-i2c";
 586                 reg = <0x0 0xff140000 0x0 0x1000>;
 587                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 588                 clock-names = "i2c", "pclk";
 589                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c5_xfer>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 status = "disabled";
 595         };
 596
 597         i2c6: i2c@ff150000 {
 598                 compatible = "rockchip,rk3399-i2c";
 599                 reg = <0x0 0xff150000 0x0 0x1000>;
 600                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 601                 clock-names = "i2c", "pclk";
 602                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&i2c6_xfer>;
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 status = "disabled";
 608         };
 609
 610         i2c7: i2c@ff160000 {
 611                 compatible = "rockchip,rk3399-i2c";
 612                 reg = <0x0 0xff160000 0x0 0x1000>;
 613                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 614                 clock-names = "i2c", "pclk";
 615                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&i2c7_xfer>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 status = "disabled";
 621         };
 622
 623         uart0: serial@ff180000 {
 624                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 625                 reg = <0x0 0xff180000 0x0 0x100>;
 626                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 627                 clock-names = "baudclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 629                 reg-shift = <2>;
 630                 reg-io-width = <4>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 633                 status = "disabled";
 634         };
 635
 636         uart1: serial@ff190000 {
 637                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 638                 reg = <0x0 0xff190000 0x0 0x100>;
 639                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 640                 clock-names = "baudclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 642                 reg-shift = <2>;
 643                 reg-io-width = <4>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&uart1_xfer>;
 646                 status = "disabled";
 647         };
 648
 649         uart2: serial@ff1a0000 {
 650                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 651                 reg = <0x0 0xff1a0000 0x0 0x100>;
 652                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 653                 clock-names = "baudclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 reg-shift = <2>;
 656                 reg-io-width = <4>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&uart2c_xfer>;
 659                 status = "disabled";
 660         };
 661
 662         uart3: serial@ff1b0000 {
 663                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 664                 reg = <0x0 0xff1b0000 0x0 0x100>;
 665                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 666                 clock-names = "baudclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 reg-shift = <2>;
 669                 reg-io-width = <4>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 672                 status = "disabled";
 673         };
 674
 675         spi0: spi@ff1c0000 {
 676                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 677                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 678                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 679                 clock-names = "spiclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "disabled";
 686         };
 687
 688         spi1: spi@ff1d0000 {
 689                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 690                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 691                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 692                 clock-names = "spiclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         spi2: spi@ff1e0000 {
 702                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 703                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 704                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 705                 clock-names = "spiclk", "apb_pclk";
 706                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 709                 #address-cells = <1>;
 710                 #size-cells = <0>;
 711                 status = "disabled";
 712         };
 713
 714         spi4: spi@ff1f0000 {
 715                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 716                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 717                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 718                 clock-names = "spiclk", "apb_pclk";
 719                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 722                 #address-cells = <1>;
 723                 #size-cells = <0>;
 724                 status = "disabled";
 725         };
 726
 727         spi5: spi@ff200000 {
 728                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 729                 reg = <0x0 0xff200000 0x0 0x1000>;
 730                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 731                 clock-names = "spiclk", "apb_pclk";
 732                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 735                 #address-cells = <1>;
 736                 #size-cells = <0>;
 737                 status = "disabled";
 738         };
 739
 740         thermal-zones {
 741                 soc_thermal: soc-thermal {
 742                         polling-delay-passive = <20>; /* milliseconds */
 743                         polling-delay = <1000>; /* milliseconds */
 744                         sustainable-power = <1000>; /* milliwatts */
 745
 746                         thermal-sensors = <&tsadc 0>;
 747
 748                         trips {
 749                                 threshold: trip-point@0 {
 750                                         temperature = <70000>; /* millicelsius */
 751                                         hysteresis = <2000>; /* millicelsius */
 752                                         type = "passive";
 753                                 };
 754                                 target: trip-point@1 {
 755                                         temperature = <85000>; /* millicelsius */
 756                                         hysteresis = <2000>; /* millicelsius */
 757                                         type = "passive";
 758                                 };
 759                                 soc_crit: soc-crit {
 760                                         temperature = <95000>; /* millicelsius */
 761                                         hysteresis = <2000>; /* millicelsius */
 762                                         type = "critical";
 763                                 };
 764                         };
 765
 766                         cooling-maps {
 767                                 map0 {
 768                                         trip = <&target>;
 769                                         cooling-device =
 770                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 771                                         contribution = <4096>;
 772                                 };
 773                                 map1 {
 774                                         trip = <&target>;
 775                                         cooling-device =
 776                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 777                                         contribution = <1024>;
 778                                 };
 779                                 map2 {
 780                                         trip = <&target>;
 781                                         cooling-device =
 782                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 783                                         contribution = <4096>;
 784                                 };
 785                         };
 786                 };
 787
 788                 gpu_thermal: gpu-thermal {
 789                         polling-delay-passive = <100>; /* milliseconds */
 790                         polling-delay = <1000>; /* milliseconds */
 791
 792                         thermal-sensors = <&tsadc 1>;
 793                 };
 794         };
 795
 796         tsadc: tsadc@ff260000 {
 797                 compatible = "rockchip,rk3399-tsadc";
 798                 reg = <0x0 0xff260000 0x0 0x100>;
 799                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 800                 rockchip,grf = <&grf>;
 801                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 802                 clock-names = "tsadc", "apb_pclk";
 803                 assigned-clocks = <&cru SCLK_TSADC>;
 804                 assigned-clock-rates = <750000>;
 805                 resets = <&cru SRST_TSADC>;
 806                 reset-names = "tsadc-apb";
 807                 pinctrl-names = "init", "default", "sleep";
 808                 pinctrl-0 = <&otp_gpio>;
 809                 pinctrl-1 = <&otp_out>;
 810                 pinctrl-2 = <&otp_gpio>;
 811                 #thermal-sensor-cells = <1>;
 812                 rockchip,hw-tshut-temp = <95000>;
 813                 status = "disabled";
 814         };
 815
 816         qos_emmc: qos@ffa58000 {
 817                 compatible = "syscon";
 818                 reg = <0x0 0xffa58000 0x0 0x20>;
 819         };
 820
 821         qos_gmac: qos@ffa5c000 {
 822                 compatible = "syscon";
 823                 reg = <0x0 0xffa5c000 0x0 0x20>;
 824         };
 825
 826         qos_pcie: qos@ffa60080 {
 827                 compatible = "syscon";
 828                 reg = <0x0 0xffa60080 0x0 0x20>;
 829         };
 830
 831         qos_usb_host0: qos@ffa60100 {
 832                 compatible = "syscon";
 833                 reg = <0x0 0xffa60100 0x0 0x20>;
 834         };
 835
 836         qos_usb_host1: qos@ffa60180 {
 837                 compatible = "syscon";
 838                 reg = <0x0 0xffa60180 0x0 0x20>;
 839         };
 840
 841         qos_usb_otg0: qos@ffa70000 {
 842                 compatible = "syscon";
 843                 reg = <0x0 0xffa70000 0x0 0x20>;
 844         };
 845
 846         qos_usb_otg1: qos@ffa70080 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffa70080 0x0 0x20>;
 849         };
 850
 851         qos_sd: qos@ffa74000 {
 852                 compatible = "syscon";
 853                 reg = <0x0 0xffa74000 0x0 0x20>;
 854         };
 855
 856         qos_sdioaudio: qos@ffa76000 {
 857                 compatible = "syscon";
 858                 reg = <0x0 0xffa76000 0x0 0x20>;
 859         };
 860
 861         qos_hdcp: qos@ffa90000 {
 862                 compatible = "syscon";
 863                 reg = <0x0 0xffa90000 0x0 0x20>;
 864         };
 865
 866         qos_iep: qos@ffa98000 {
 867                 compatible = "syscon";
 868                 reg = <0x0 0xffa98000 0x0 0x20>;
 869         };
 870
 871         qos_isp0_m0: qos@ffaa0000 {
 872                 compatible = "syscon";
 873                 reg = <0x0 0xffaa0000 0x0 0x20>;
 874         };
 875
 876         qos_isp0_m1: qos@ffaa0080 {
 877                 compatible = "syscon";
 878                 reg = <0x0 0xffaa0080 0x0 0x20>;
 879         };
 880
 881         qos_isp1_m0: qos@ffaa8000 {
 882                 compatible = "syscon";
 883                 reg = <0x0 0xffaa8000 0x0 0x20>;
 884         };
 885
 886         qos_isp1_m1: qos@ffaa8080 {
 887                 compatible = "syscon";
 888                 reg = <0x0 0xffaa8080 0x0 0x20>;
 889         };
 890
 891         qos_rga_r: qos@ffab0000 {
 892                 compatible = "syscon";
 893                 reg = <0x0 0xffab0000 0x0 0x20>;
 894         };
 895
 896         qos_rga_w: qos@ffab0080 {
 897                 compatible = "syscon";
 898                 reg = <0x0 0xffab0080 0x0 0x20>;
 899         };
 900
 901         qos_video_m0: qos@ffab8000 {
 902                 compatible = "syscon";
 903                 reg = <0x0 0xffab8000 0x0 0x20>;
 904         };
 905
 906         qos_video_m1_r: qos@ffac0000 {
 907                 compatible = "syscon";
 908                 reg = <0x0 0xffac0000 0x0 0x20>;
 909         };
 910
 911         qos_video_m1_w: qos@ffac0080 {
 912                 compatible = "syscon";
 913                 reg = <0x0 0xffac0080 0x0 0x20>;
 914         };
 915
 916         qos_vop_big_r: qos@ffac8000 {
 917                 compatible = "syscon";
 918                 reg = <0x0 0xffac8000 0x0 0x20>;
 919         };
 920
 921         qos_vop_big_w: qos@ffac8080 {
 922                 compatible = "syscon";
 923                 reg = <0x0 0xffac8080 0x0 0x20>;
 924         };
 925
 926         qos_vop_little: qos@ffad0000 {
 927                 compatible = "syscon";
 928                 reg = <0x0 0xffad0000 0x0 0x20>;
 929         };
 930
 931         qos_perihp: qos@ffad8080 {
 932                 compatible = "syscon";
 933                 reg = <0x0 0xffad8080 0x0 0x20>;
 934         };
 935
 936         qos_gpu: qos@ffae0000 {
 937                 compatible = "syscon";
 938                 reg = <0x0 0xffae0000 0x0 0x20>;
 939         };
 940
 941         pmu: power-management@ff310000 {
 942                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 943                 reg = <0x0 0xff310000 0x0 0x1000>;
 944
 945                 /*
 946                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 947                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 948                  * Some of the power domains are grouped together for every
 949                  * voltage domain.
 950                  * The detail contents as below.
 951                  */
 952                 power: power-controller {
 953                         compatible = "rockchip,rk3399-power-controller";
 954                         #power-domain-cells = <1>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957
 958                         /* These power domains are grouped by VD_CENTER */
 959                         pd_iep@RK3399_PD_IEP {
 960                                 reg = <RK3399_PD_IEP>;
 961                                 clocks = <&cru ACLK_IEP>,
 962                                          <&cru HCLK_IEP>;
 963                                 pm_qos = <&qos_iep>;
 964                         };
 965                         pd_rga@RK3399_PD_RGA {
 966                                 reg = <RK3399_PD_RGA>;
 967                                 clocks = <&cru ACLK_RGA>,
 968                                          <&cru HCLK_RGA>;
 969                                 pm_qos = <&qos_rga_r>,
 970                                          <&qos_rga_w>;
 971                         };
 972                         pd_vcodec@RK3399_PD_VCODEC {
 973                                 reg = <RK3399_PD_VCODEC>;
 974                                 clocks = <&cru ACLK_VCODEC>,
 975                                          <&cru HCLK_VCODEC>;
 976                                 pm_qos = <&qos_video_m0>;
 977                         };
 978                         pd_vdu@RK3399_PD_VDU {
 979                                 reg = <RK3399_PD_VDU>;
 980                                 clocks = <&cru ACLK_VDU>,
 981                                          <&cru HCLK_VDU>;
 982                                 pm_qos = <&qos_video_m1_r>,
 983                                          <&qos_video_m1_w>;
 984                         };
 985
 986                         /* These power domains are grouped by VD_GPU */
 987                         pd_gpu@RK3399_PD_GPU {
 988                                 reg = <RK3399_PD_GPU>;
 989                                 clocks = <&cru ACLK_GPU>;
 990                                 pm_qos = <&qos_gpu>;
 991                         };
 992
 993                         /* These power domains are grouped by VD_LOGIC */
 994                         pd_emmc@RK3399_PD_EMMC {
 995                                 reg = <RK3399_PD_EMMC>;
 996                                 clocks = <&cru ACLK_EMMC>;
 997                                 pm_qos = <&qos_emmc>;
 998                         };
 999                         pd_gmac@RK3399_PD_GMAC {
1000                                 reg = <RK3399_PD_GMAC>;
1001                                 clocks = <&cru ACLK_GMAC>;
1002                                 pm_qos = <&qos_gmac>;
1003                         };
1004                         pd_perihp@RK3399_PD_PERIHP {
1005                                 reg = <RK3399_PD_PERIHP>;
1006                                 clocks = <&cru ACLK_PERIHP>;
1007                                 pm_qos = <&qos_perihp>,
1008                                          <&qos_pcie>,
1009                                          <&qos_usb_host0>,
1010                                          <&qos_usb_host1>;
1011                         };
1012                         pd_sd@RK3399_PD_SD {
1013                                 reg = <RK3399_PD_SD>;
1014                                 clocks = <&cru HCLK_SDMMC>;
1015                                 pm_qos = <&qos_sd>;
1016                         };
1017                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1018                                 reg = <RK3399_PD_SDIOAUDIO>;
1019                                 clocks = <&cru HCLK_SDIO>;
1020                                 pm_qos = <&qos_sdioaudio>;
1021                         };
1022                         pd_usb3@RK3399_PD_USB3 {
1023                                 reg = <RK3399_PD_USB3>;
1024                                 clocks = <&cru ACLK_USB3>;
1025                                 pm_qos = <&qos_usb_otg0>,
1026                                          <&qos_usb_otg1>;
1027                         };
1028                         pd_vio@RK3399_PD_VIO {
1029                                 reg = <RK3399_PD_VIO>;
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032
1033                                 pd_hdcp@RK3399_PD_HDCP {
1034                                         reg = <RK3399_PD_HDCP>;
1035                                         clocks = <&cru ACLK_HDCP>,
1036                                                  <&cru HCLK_HDCP>,
1037                                                  <&cru PCLK_HDCP>;
1038                                         pm_qos = <&qos_hdcp>;
1039                                 };
1040                                 pd_isp0@RK3399_PD_ISP0 {
1041                                         reg = <RK3399_PD_ISP0>;
1042                                         clocks = <&cru ACLK_ISP0>,
1043                                                  <&cru HCLK_ISP0>;
1044                                         pm_qos = <&qos_isp0_m0>,
1045                                                  <&qos_isp0_m1>;
1046                                 };
1047                                 pd_isp1@RK3399_PD_ISP1 {
1048                                         reg = <RK3399_PD_ISP1>;
1049                                         clocks = <&cru ACLK_ISP1>,
1050                                                  <&cru HCLK_ISP1>;
1051                                         pm_qos = <&qos_isp1_m0>,
1052                                                  <&qos_isp1_m1>;
1053                                 };
1054                                 pd_vo@RK3399_PD_VO {
1055                                         reg = <RK3399_PD_VO>;
1056                                         #address-cells = <1>;
1057                                         #size-cells = <0>;
1058
1059                                         pd_vopb@RK3399_PD_VOPB {
1060                                                 reg = <RK3399_PD_VOPB>;
1061                                                 clocks = <&cru ACLK_VOP0>,
1062                                                          <&cru HCLK_VOP0>;
1063                                                 pm_qos = <&qos_vop_big_r>,
1064                                                          <&qos_vop_big_w>;
1065                                         };
1066                                         pd_vopl@RK3399_PD_VOPL {
1067                                                 reg = <RK3399_PD_VOPL>;
1068                                                 clocks = <&cru ACLK_VOP1>,
1069                                                          <&cru HCLK_VOP1>;
1070                                                 pm_qos = <&qos_vop_little>;
1071                                         };
1072                                 };
1073                         };
1074                 };
1075         };
1076
1077         pmugrf: syscon@ff320000 {
1078                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1079                 reg = <0x0 0xff320000 0x0 0x1000>;
1080
1081                 reboot-mode {
1082                         compatible = "syscon-reboot-mode";
1083                         offset = <0x300>;
1084                         mode-bootloader = <BOOT_LOADER>;
1085                         mode-charge = <BOOT_CHARGING>;
1086                         mode-fastboot = <BOOT_FASTBOOT>;
1087                         mode-loader = <BOOT_LOADER>;
1088                         mode-normal = <BOOT_NORMAL>;
1089                         mode-recovery = <BOOT_RECOVERY>;
1090                 };
1091         };
1092
1093         spi3: spi@ff350000 {
1094                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1095                 reg = <0x0 0xff350000 0x0 0x1000>;
1096                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1097                 clock-names = "spiclk", "apb_pclk";
1098                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1099                 pinctrl-names = "default";
1100                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1101                 #address-cells = <1>;
1102                 #size-cells = <0>;
1103                 status = "disabled";
1104         };
1105
1106         uart4: serial@ff370000 {
1107                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1108                 reg = <0x0 0xff370000 0x0 0x100>;
1109                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1110                 clock-names = "baudclk", "apb_pclk";
1111                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1112                 reg-shift = <2>;
1113                 reg-io-width = <4>;
1114                 pinctrl-names = "default";
1115                 pinctrl-0 = <&uart4_xfer>;
1116                 status = "disabled";
1117         };
1118
1119         i2c4: i2c@ff3d0000 {
1120                 compatible = "rockchip,rk3399-i2c";
1121                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1122                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1123                 clock-names = "i2c", "pclk";
1124                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1125                 pinctrl-names = "default";
1126                 pinctrl-0 = <&i2c4_xfer>;
1127                 #address-cells = <1>;
1128                 #size-cells = <0>;
1129                 status = "disabled";
1130         };
1131
1132         i2c8: i2c@ff3e0000 {
1133                 compatible = "rockchip,rk3399-i2c";
1134                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1135                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1136                 clock-names = "i2c", "pclk";
1137                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1138                 pinctrl-names = "default";
1139                 pinctrl-0 = <&i2c8_xfer>;
1140                 #address-cells = <1>;
1141                 #size-cells = <0>;
1142                 status = "disabled";
1143         };
1144
1145         pcie0: pcie@f8000000 {
1146                 compatible = "rockchip,rk3399-pcie";
1147                 #address-cells = <3>;
1148                 #size-cells = <2>;
1149                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1150                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1151                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1152                               "hclk_pcie", "clk_pciephy_ref";
1153                 bus-range = <0x0 0x1>;
1154                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1155                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1156                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1157                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1158                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1159                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1160                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1161                       < 0x0 0xfd000000 0x0 0x1000000 >;
1162                 reg-name = "axi-base", "apb-base";
1163                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1164                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1165                          <&cru SRST_PCIE_PIPE>;
1166                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1167                               "mgmt-sticky-rst", "pipe-rst";
1168                 rockchip,grf = <&grf>;
1169                 pcie-conf = <0xe220>;
1170                 pcie-status = <0xe2a4>;
1171                 pcie-laneoff = <0xe214>;
1172                 power-domains = <&power RK3399_PD_PERIHP>;
1173                 msi-parent = <&its>;
1174                 #interrupt-cells = <1>;
1175                 interrupt-map-mask = <0 0 0 7>;
1176                 interrupt-map = <0 0 0 1 &pcie0 1>,
1177                                 <0 0 0 2 &pcie0 2>,
1178                                 <0 0 0 3 &pcie0 3>,
1179                                 <0 0 0 4 &pcie0 4>;
1180                 status = "disabled";
1181                 pcie_intc: interrupt-controller {
1182                         interrupt-controller;
1183                         #address-cells = <0>;
1184                         #interrupt-cells = <1>;
1185                 };
1186         };
1187
1188         pwm0: pwm@ff420000 {
1189                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1190                 reg = <0x0 0xff420000 0x0 0x10>;
1191                 #pwm-cells = <3>;
1192                 pinctrl-names = "default";
1193                 pinctrl-0 = <&pwm0_pin>;
1194                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1195                 clock-names = "pwm";
1196                 status = "disabled";
1197         };
1198
1199         pwm1: pwm@ff420010 {
1200                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1201                 reg = <0x0 0xff420010 0x0 0x10>;
1202                 #pwm-cells = <3>;
1203                 pinctrl-names = "default";
1204                 pinctrl-0 = <&pwm1_pin>;
1205                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1206                 clock-names = "pwm";
1207                 status = "disabled";
1208         };
1209
1210         pwm2: pwm@ff420020 {
1211                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1212                 reg = <0x0 0xff420020 0x0 0x10>;
1213                 #pwm-cells = <3>;
1214                 pinctrl-names = "default";
1215                 pinctrl-0 = <&pwm2_pin>;
1216                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1217                 clock-names = "pwm";
1218                 status = "disabled";
1219         };
1220
1221         pwm3: pwm@ff420030 {
1222                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1223                 reg = <0x0 0xff420030 0x0 0x10>;
1224                 #pwm-cells = <3>;
1225                 pinctrl-names = "default";
1226                 pinctrl-0 = <&pwm3a_pin>;
1227                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1228                 clock-names = "pwm";
1229                 status = "disabled";
1230         };
1231
1232         rga: rga@ff680000 {
1233                 compatible = "rockchip,rk3399-rga";
1234                 reg = <0x0 0xff680000 0x0 0x10000>;
1235                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1236                 interrupt-names = "rga";
1237                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1238                 clock-names = "aclk", "hclk", "sclk";
1239                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1240                 reset-names = "core", "axi", "ahb";
1241                 power-domains = <&power RK3399_PD_RGA>;
1242                 status = "disabled";
1243         };
1244
1245         pmucru: pmu-clock-controller@ff750000 {
1246                 compatible = "rockchip,rk3399-pmucru";
1247                 reg = <0x0 0xff750000 0x0 0x1000>;
1248                 #clock-cells = <1>;
1249                 #reset-cells = <1>;
1250                 assigned-clocks = <&pmucru PLL_PPLL>;
1251                 assigned-clock-rates = <676000000>;
1252         };
1253
1254         cru: clock-controller@ff760000 {
1255                 compatible = "rockchip,rk3399-cru";
1256                 reg = <0x0 0xff760000 0x0 0x1000>;
1257                 #clock-cells = <1>;
1258                 #reset-cells = <1>;
1259                 assigned-clocks =
1260                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1261                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1262                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1263                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1264                         <&cru PLL_NPLL>,
1265                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1266                         <&cru PCLK_PERIHP>,
1267                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1268                         <&cru PCLK_PERILP0>,
1269                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1270                 assigned-clock-rates =
1271                          <400000000>,  <200000000>,
1272                          <400000000>,  <200000000>,
1273                          <816000000>, <816000000>,
1274                          <594000000>,  <800000000>,
1275                         <1000000000>,
1276                          <150000000>,   <75000000>,
1277                           <37500000>,
1278                          <100000000>,  <100000000>,
1279                           <50000000>,
1280                          <100000000>,   <50000000>;
1281         };
1282
1283         grf: syscon@ff770000 {
1284                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1285                 reg = <0x0 0xff770000 0x0 0x10000>;
1286                 #address-cells = <1>;
1287                 #size-cells = <1>;
1288
1289                 u2phy0: usb2-phy@e450 {
1290                         compatible = "rockchip,rk3399-usb2phy";
1291                         reg = <0xe450 0x10>;
1292                         clocks = <&cru SCLK_USB2PHY0_REF>;
1293                         clock-names = "phyclk";
1294                         #clock-cells = <0>;
1295                         clock-output-names = "clk_usbphy0_480m";
1296                         status = "disabled";
1297
1298                         u2phy0_otg: otg-port {
1299                                 #phy-cells = <0>;
1300                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1301                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1302                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1303                                 interrupt-names = "otg-bvalid", "otg-id",
1304                                                   "linestate";
1305                                 status = "disabled";
1306                         };
1307
1308                         u2phy0_host: host-port {
1309                                 #phy-cells = <0>;
1310                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1311                                 interrupt-names = "linestate";
1312                                 status = "disabled";
1313                         };
1314                 };
1315
1316                 u2phy1: usb2-phy@e460 {
1317                         compatible = "rockchip,rk3399-usb2phy";
1318                         reg = <0xe460 0x10>;
1319                         clocks = <&cru SCLK_USB2PHY1_REF>;
1320                         clock-names = "phyclk";
1321                         #clock-cells = <0>;
1322                         clock-output-names = "clk_usbphy1_480m";
1323                         status = "disabled";
1324
1325                         u2phy1_otg: otg-port {
1326                                 #phy-cells = <0>;
1327                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1328                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1329                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1330                                 interrupt-names = "otg-bvalid", "otg-id",
1331                                                   "linestate";
1332                                 status = "disabled";
1333                         };
1334
1335                         u2phy1_host: host-port {
1336                                 #phy-cells = <0>;
1337                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1338                                 interrupt-names = "linestate";
1339                                 status = "disabled";
1340                         };
1341                 };
1342         };
1343
1344         tcphy0: phy@ff7c0000 {
1345                 compatible = "rockchip,rk3399-typec-phy";
1346                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1347                 rockchip,grf = <&grf>;
1348                 #phy-cells = <0>;
1349                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1350                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1351                 clock-names = "tcpdcore", "tcpdphy-ref";
1352                 resets = <&cru SRST_UPHY0>,
1353                          <&cru SRST_UPHY0_PIPE_L00>,
1354                          <&cru SRST_P_UPHY0_TCPHY>;
1355                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1356                 rockchip,typec-conn-dir = <0xe580 0 16>;
1357                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1358                 rockchip,external-psm = <0xe588 14 30>;
1359                 rockchip,pipe-status = <0xe5c0 0 0>;
1360                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1361                 status = "disabled";
1362         };
1363
1364         tcphy1: phy@ff800000 {
1365                 compatible = "rockchip,rk3399-typec-phy";
1366                 reg = <0x0 0xff800000 0x0 0x40000>;
1367                 rockchip,grf = <&grf>;
1368                 #phy-cells = <0>;
1369                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1370                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1371                 clock-names = "tcpdcore", "tcpdphy-ref";
1372                 resets = <&cru SRST_UPHY1>,
1373                          <&cru SRST_UPHY1_PIPE_L00>,
1374                          <&cru SRST_P_UPHY1_TCPHY>;
1375                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1376                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1377                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1378                 rockchip,external-psm = <0xe594 14 30>;
1379                 rockchip,pipe-status = <0xe5c0 16 16>;
1380                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1381                 status = "disabled";
1382         };
1383
1384         watchdog@ff840000 {
1385                 compatible = "snps,dw-wdt";
1386                 reg = <0x0 0xff840000 0x0 0x100>;
1387                 clocks = <&cru PCLK_WDT>;
1388                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1389         };
1390
1391         rktimer: rktimer@ff850000 {
1392                 compatible = "rockchip,rk3399-timer";
1393                 reg = <0x0 0xff850000 0x0 0x1000>;
1394                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1395                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1396                 clock-names = "pclk", "timer";
1397         };
1398
1399         spdif: spdif@ff870000 {
1400                 compatible = "rockchip,rk3399-spdif";
1401                 reg = <0x0 0xff870000 0x0 0x1000>;
1402                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1403                 dmas = <&dmac_bus 7>;
1404                 dma-names = "tx";
1405                 clock-names = "mclk", "hclk";
1406                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1407                 pinctrl-names = "default";
1408                 pinctrl-0 = <&spdif_bus>;
1409                 status = "disabled";
1410         };
1411
1412         i2s0: i2s@ff880000 {
1413                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1414                 reg = <0x0 0xff880000 0x0 0x1000>;
1415                 rockchip,grf = <&grf>;
1416                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1417                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1418                 dma-names = "tx", "rx";
1419                 clock-names = "i2s_clk", "i2s_hclk";
1420                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1421                 pinctrl-names = "default";
1422                 pinctrl-0 = <&i2s0_8ch_bus>;
1423                 status = "disabled";
1424         };
1425
1426         i2s1: i2s@ff890000 {
1427                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1428                 reg = <0x0 0xff890000 0x0 0x1000>;
1429                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1430                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1431                 dma-names = "tx", "rx";
1432                 clock-names = "i2s_clk", "i2s_hclk";
1433                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1434                 pinctrl-names = "default";
1435                 pinctrl-0 = <&i2s1_2ch_bus>;
1436                 status = "disabled";
1437         };
1438
1439         i2s2: i2s@ff8a0000 {
1440                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1441                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1442                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1443                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1444                 dma-names = "tx", "rx";
1445                 clock-names = "i2s_clk", "i2s_hclk";
1446                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1447                 status = "disabled";
1448         };
1449
1450         gpu: gpu@ff9a0000 {
1451                 compatible = "arm,malit860",
1452                              "arm,malit86x",
1453                              "arm,malit8xx",
1454                              "arm,mali-midgard";
1455
1456                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1457
1458                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1459                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1460                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1461                 interrupt-names = "GPU", "JOB", "MMU";
1462
1463                 clocks = <&cru ACLK_GPU>;
1464                 clock-names = "clk_mali";
1465                 #cooling-cells = <2>; /* min followed by max */
1466                 operating-points-v2 = <&gpu_opp_table>;
1467                 power-domains = <&power RK3399_PD_GPU>;
1468                 power-off-delay-ms = <200>;
1469                 status = "disabled";
1470
1471                 gpu_power_model: power_model {
1472                         compatible = "arm,mali-simple-power-model";
1473                         voltage = <900>;
1474                         frequency = <500>;
1475                         static-power = <300>;
1476                         dynamic-power = <396>;
1477                         ts = <32000 4700 (-80) 2>;
1478                         thermal-zone = "gpu-thermal";
1479                 };
1480         };
1481
1482         gpu_opp_table: gpu_opp_table {
1483                 compatible = "operating-points-v2";
1484                 opp-shared;
1485
1486                 opp@200000000 {
1487                         opp-hz = /bits/ 64 <200000000>;
1488                         opp-microvolt = <900000>;
1489                 };
1490                 opp@300000000 {
1491                         opp-hz = /bits/ 64 <300000000>;
1492                         opp-microvolt = <900000>;
1493                 };
1494                 opp@400000000 {
1495                         opp-hz = /bits/ 64 <400000000>;
1496                         opp-microvolt = <900000>;
1497                 };
1498
1499         };
1500
1501         vopl: vop@ff8f0000 {
1502                 compatible = "rockchip,rk3399-vop-lit";
1503                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1504                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1505                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1506                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1507                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1508                 reset-names = "axi", "ahb", "dclk";
1509                 power-domains = <&power RK3399_PD_VOPL>;
1510                 iommus = <&vopl_mmu>;
1511                 status = "disabled";
1512
1513                 vopl_out: port {
1514                         #address-cells = <1>;
1515                         #size-cells = <0>;
1516
1517                         vopl_out_mipi: endpoint@0 {
1518                                 reg = <0>;
1519                                 remote-endpoint = <&mipi_in_vopl>;
1520                         };
1521
1522                         vopl_out_edp: endpoint@1 {
1523                                 reg = <1>;
1524                                 remote-endpoint = <&edp_in_vopl>;
1525                         };
1526
1527                         vopl_out_hdmi: endpoint@2 {
1528                                 reg = <2>;
1529                                 remote-endpoint = <&hdmi_in_vopl>;
1530                         };
1531                 };
1532         };
1533
1534         vopl_mmu: iommu@ff8f3f00 {
1535                 compatible = "rockchip,iommu";
1536                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1537                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1538                 interrupt-names = "vopl_mmu";
1539                 #iommu-cells = <0>;
1540                 status = "disabled";
1541         };
1542
1543         vopb: vop@ff900000 {
1544                 compatible = "rockchip,rk3399-vop-big";
1545                 reg = <0x0 0xff900000 0x0 0x3efc>;
1546                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1547                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1548                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1549                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1550                 reset-names = "axi", "ahb", "dclk";
1551                 power-domains = <&power RK3399_PD_VOPB>;
1552                 iommus = <&vopb_mmu>;
1553                 status = "disabled";
1554
1555                 vopb_out: port {
1556                         #address-cells = <1>;
1557                         #size-cells = <0>;
1558
1559                         vopb_out_edp: endpoint@0 {
1560                                 reg = <0>;
1561                                 remote-endpoint = <&edp_in_vopb>;
1562                         };
1563
1564                         vopb_out_mipi: endpoint@1 {
1565                                 reg = <1>;
1566                                 remote-endpoint = <&mipi_in_vopb>;
1567                         };
1568
1569                         vopb_out_hdmi: endpoint@2 {
1570                                 reg = <2>;
1571                                 remote-endpoint = <&hdmi_in_vopb>;
1572                         };
1573                 };
1574         };
1575
1576         vopb_mmu: iommu@ff903f00 {
1577                 compatible = "rockchip,iommu";
1578                 reg = <0x0 0xff903f00 0x0 0x100>;
1579                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1580                 interrupt-names = "vopb_mmu";
1581                 #iommu-cells = <0>;
1582                 status = "disabled";
1583         };
1584
1585         hdmi: hdmi@ff940000 {
1586                 compatible = "rockchip,rk3399-dw-hdmi";
1587                 reg = <0x0 0xff940000 0x0 0x20000>;
1588                 reg-io-width = <4>;
1589                 rockchip,grf = <&grf>;
1590                 power-domains = <&power RK3399_PD_HDCP>;
1591                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1592                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1593                 clock-names = "iahb", "isfr", "vpll", "grf";
1594                 status = "disabled";
1595
1596                 ports {
1597                         hdmi_in: port {
1598                                 #address-cells = <1>;
1599                                 #size-cells = <0>;
1600                                 hdmi_in_vopb: endpoint@0 {
1601                                         reg = <0>;
1602                                         remote-endpoint = <&vopb_out_hdmi>;
1603                                 };
1604                                 hdmi_in_vopl: endpoint@1 {
1605                                         reg = <1>;
1606                                         remote-endpoint = <&vopl_out_hdmi>;
1607                                 };
1608                         };
1609                 };
1610         };
1611
1612         mipi_dsi: mipi@ff960000 {
1613                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1614                 reg = <0x0 0xff960000 0x0 0x8000>;
1615                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1616                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1617                          <&cru SCLK_DPHY_TX0_CFG>;
1618                 clock-names = "ref", "pclk", "phy_cfg";
1619                 power-domains = <&power RK3399_PD_VIO>;
1620                 rockchip,grf = <&grf>;
1621                 #address-cells = <1>;
1622                 #size-cells = <0>;
1623                 status = "disabled";
1624
1625                 ports {
1626                         #address-cells = <1>;
1627                         #size-cells = <0>;
1628                         reg = <1>;
1629
1630                         mipi_in: port {
1631                                 #address-cells = <1>;
1632                                 #size-cells = <0>;
1633
1634                                 mipi_in_vopb: endpoint@0 {
1635                                         reg = <0>;
1636                                         remote-endpoint = <&vopb_out_mipi>;
1637                                 };
1638                                 mipi_in_vopl: endpoint@1 {
1639                                         reg = <1>;
1640                                         remote-endpoint = <&vopl_out_mipi>;
1641                                 };
1642                         };
1643                 };
1644         };
1645
1646         edp: edp@ff970000 {
1647                 compatible = "rockchip,rk3399-edp";
1648                 reg = <0x0 0xff970000 0x0 0x8000>;
1649                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1650                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1651                 clock-names = "dp", "pclk";
1652                 resets = <&cru SRST_P_EDP_CTRL>;
1653                 reset-names = "dp";
1654                 rockchip,grf = <&grf>;
1655                 status = "disabled";
1656                 pinctrl-names = "default";
1657                 pinctrl-0 = <&edp_hpd>;
1658
1659                 ports {
1660                         #address-cells = <1>;
1661                         #size-cells = <0>;
1662
1663                         edp_in: port@0 {
1664                                 reg = <0>;
1665                                 #address-cells = <1>;
1666                                 #size-cells = <0>;
1667
1668                                 edp_in_vopb: endpoint@0 {
1669                                         reg = <0>;
1670                                         remote-endpoint = <&vopb_out_edp>;
1671                                 };
1672
1673                                 edp_in_vopl: endpoint@1 {
1674                                         reg = <1>;
1675                                         remote-endpoint = <&vopl_out_edp>;
1676                                 };
1677                         };
1678                 };
1679         };
1680
1681         display_subsystem: display-subsystem {
1682                 compatible = "rockchip,display-subsystem";
1683                 ports = <&vopl_out>, <&vopb_out>;
1684                 status = "disabled";
1685         };
1686
1687         pinctrl: pinctrl {
1688                 compatible = "rockchip,rk3399-pinctrl";
1689                 rockchip,grf = <&grf>;
1690                 rockchip,pmu = <&pmugrf>;
1691                 #address-cells = <0x2>;
1692                 #size-cells = <0x2>;
1693                 ranges;
1694
1695                 gpio0: gpio0@ff720000 {
1696                         compatible = "rockchip,gpio-bank";
1697                         reg = <0x0 0xff720000 0x0 0x100>;
1698                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1699                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1700
1701                         gpio-controller;
1702                         #gpio-cells = <0x2>;
1703
1704                         interrupt-controller;
1705                         #interrupt-cells = <0x2>;
1706                 };
1707
1708                 gpio1: gpio1@ff730000 {
1709                         compatible = "rockchip,gpio-bank";
1710                         reg = <0x0 0xff730000 0x0 0x100>;
1711                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1712                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1713
1714                         gpio-controller;
1715                         #gpio-cells = <0x2>;
1716
1717                         interrupt-controller;
1718                         #interrupt-cells = <0x2>;
1719                 };
1720
1721                 gpio2: gpio2@ff780000 {
1722                         compatible = "rockchip,gpio-bank";
1723                         reg = <0x0 0xff780000 0x0 0x100>;
1724                         clocks = <&cru PCLK_GPIO2>;
1725                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1726
1727                         gpio-controller;
1728                         #gpio-cells = <0x2>;
1729
1730                         interrupt-controller;
1731                         #interrupt-cells = <0x2>;
1732                 };
1733
1734                 gpio3: gpio3@ff788000 {
1735                         compatible = "rockchip,gpio-bank";
1736                         reg = <0x0 0xff788000 0x0 0x100>;
1737                         clocks = <&cru PCLK_GPIO3>;
1738                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1739
1740                         gpio-controller;
1741                         #gpio-cells = <0x2>;
1742
1743                         interrupt-controller;
1744                         #interrupt-cells = <0x2>;
1745                 };
1746
1747                 gpio4: gpio4@ff790000 {
1748                         compatible = "rockchip,gpio-bank";
1749                         reg = <0x0 0xff790000 0x0 0x100>;
1750                         clocks = <&cru PCLK_GPIO4>;
1751                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1752
1753                         gpio-controller;
1754                         #gpio-cells = <0x2>;
1755
1756                         interrupt-controller;
1757                         #interrupt-cells = <0x2>;
1758                 };
1759
1760                 pcfg_pull_up: pcfg-pull-up {
1761                         bias-pull-up;
1762                 };
1763
1764                 pcfg_pull_down: pcfg-pull-down {
1765                         bias-pull-down;
1766                 };
1767
1768                 pcfg_pull_none: pcfg-pull-none {
1769                         bias-disable;
1770                 };
1771
1772                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1773                         bias-pull-up;
1774                         drive-strength = <20>;
1775                 };
1776
1777                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1778                         bias-disable;
1779                         drive-strength = <20>;
1780                 };
1781
1782                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1783                         bias-disable;
1784                         drive-strength = <18>;
1785                 };
1786
1787                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1788                         bias-disable;
1789                         drive-strength = <12>;
1790                 };
1791
1792                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1793                         bias-pull-up;
1794                         drive-strength = <8>;
1795                 };
1796
1797                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1798                         bias-pull-down;
1799                         drive-strength = <4>;
1800                 };
1801
1802                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1803                         bias-pull-up;
1804                         drive-strength = <2>;
1805                 };
1806
1807                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1808                         bias-pull-down;
1809                         drive-strength = <12>;
1810                 };
1811
1812                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1813                         bias-disable;
1814                         drive-strength = <13>;
1815                 };
1816
1817                 emmc {
1818                         emmc_pwr: emmc-pwr {
1819                                 rockchip,pins =
1820                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1821                         };
1822                 };
1823
1824                 gmac {
1825                         rgmii_pins: rgmii-pins {
1826                                 rockchip,pins =
1827                                         /* mac_txclk */
1828                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1829                                         /* mac_rxclk */
1830                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1831                                         /* mac_mdio */
1832                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1833                                         /* mac_txen */
1834                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1835                                         /* mac_clk */
1836                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1837                                         /* mac_rxdv */
1838                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1839                                         /* mac_mdc */
1840                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1841                                         /* mac_rxd1 */
1842                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1843                                         /* mac_rxd0 */
1844                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1845                                         /* mac_txd1 */
1846                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1847                                         /* mac_txd0 */
1848                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1849                                         /* mac_rxd3 */
1850                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1851                                         /* mac_rxd2 */
1852                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1853                                         /* mac_txd3 */
1854                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1855                                         /* mac_txd2 */
1856                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1857                         };
1858
1859                         rmii_pins: rmii-pins {
1860                                 rockchip,pins =
1861                                         /* mac_mdio */
1862                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1863                                         /* mac_txen */
1864                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1865                                         /* mac_clk */
1866                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1867                                         /* mac_rxer */
1868                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1869                                         /* mac_rxdv */
1870                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1871                                         /* mac_mdc */
1872                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1873                                         /* mac_rxd1 */
1874                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1875                                         /* mac_rxd0 */
1876                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1877                                         /* mac_txd1 */
1878                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1879                                         /* mac_txd0 */
1880                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1881                         };
1882                 };
1883
1884                 i2c0 {
1885                         i2c0_xfer: i2c0-xfer {
1886                                 rockchip,pins =
1887                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1888                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1889                         };
1890                 };
1891
1892                 i2c1 {
1893                         i2c1_xfer: i2c1-xfer {
1894                                 rockchip,pins =
1895                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1896                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1897                         };
1898                 };
1899
1900                 i2c2 {
1901                         i2c2_xfer: i2c2-xfer {
1902                                 rockchip,pins =
1903                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1904                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1905                         };
1906                 };
1907
1908                 i2c3 {
1909                         i2c3_xfer: i2c3-xfer {
1910                                 rockchip,pins =
1911                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1912                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1913                         };
1914
1915                         i2c3_gpio: i2c3_gpio {
1916                                 rockchip,pins =
1917                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1918                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1919                         };
1920
1921                 };
1922
1923                 i2c4 {
1924                         i2c4_xfer: i2c4-xfer {
1925                                 rockchip,pins =
1926                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1927                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1928                         };
1929                 };
1930
1931                 i2c5 {
1932                         i2c5_xfer: i2c5-xfer {
1933                                 rockchip,pins =
1934                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1935                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1936                         };
1937                 };
1938
1939                 i2c6 {
1940                         i2c6_xfer: i2c6-xfer {
1941                                 rockchip,pins =
1942                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1943                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1944                         };
1945                 };
1946
1947                 i2c7 {
1948                         i2c7_xfer: i2c7-xfer {
1949                                 rockchip,pins =
1950                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1951                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1952                         };
1953                 };
1954
1955                 i2c8 {
1956                         i2c8_xfer: i2c8-xfer {
1957                                 rockchip,pins =
1958                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1959                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1960                         };
1961                 };
1962
1963                 i2s0 {
1964                         i2s0_8ch_bus: i2s0-8ch-bus {
1965                                 rockchip,pins =
1966                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1967                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1968                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1969                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1970                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1971                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1972                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1973                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1974                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1975                         };
1976                 };
1977
1978                 i2s1 {
1979                         i2s1_2ch_bus: i2s1-2ch-bus {
1980                                 rockchip,pins =
1981                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1982                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1983                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1984                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1985                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1986                         };
1987                 };
1988
1989                 sdio0 {
1990                         sdio0_bus1: sdio0-bus1 {
1991                                 rockchip,pins =
1992                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1993                         };
1994
1995                         sdio0_bus4: sdio0-bus4 {
1996                                 rockchip,pins =
1997                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1998                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1999                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2000                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2001                         };
2002
2003                         sdio0_cmd: sdio0-cmd {
2004                                 rockchip,pins =
2005                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2006                         };
2007
2008                         sdio0_clk: sdio0-clk {
2009                                 rockchip,pins =
2010                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2011                         };
2012
2013                         sdio0_cd: sdio0-cd {
2014                                 rockchip,pins =
2015                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2016                         };
2017
2018                         sdio0_pwr: sdio0-pwr {
2019                                 rockchip,pins =
2020                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2021                         };
2022
2023                         sdio0_bkpwr: sdio0-bkpwr {
2024                                 rockchip,pins =
2025                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2026                         };
2027
2028                         sdio0_wp: sdio0-wp {
2029                                 rockchip,pins =
2030                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2031                         };
2032
2033                         sdio0_int: sdio0-int {
2034                                 rockchip,pins =
2035                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2036                         };
2037                 };
2038
2039                 sdmmc {
2040                         sdmmc_bus1: sdmmc-bus1 {
2041                                 rockchip,pins =
2042                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2043                         };
2044
2045                         sdmmc_bus4: sdmmc-bus4 {
2046                                 rockchip,pins =
2047                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2048                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2049                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2050                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2051                         };
2052
2053                         sdmmc_clk: sdmmc-clk {
2054                                 rockchip,pins =
2055                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2056                         };
2057
2058                         sdmmc_cmd: sdmmc-cmd {
2059                                 rockchip,pins =
2060                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2061                         };
2062
2063                         sdmmc_cd: sdmcc-cd {
2064                                 rockchip,pins =
2065                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2066                         };
2067
2068                         sdmmc_wp: sdmmc-wp {
2069                                 rockchip,pins =
2070                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2071                         };
2072                 };
2073
2074                 spdif {
2075                         spdif_bus: spdif-bus {
2076                                 rockchip,pins =
2077                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2078                         };
2079
2080                         spdif_bus_1: spdif-bus-1 {
2081                                 rockchip,pins =
2082                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2083                         };
2084                 };
2085
2086                 spi0 {
2087                         spi0_clk: spi0-clk {
2088                                 rockchip,pins =
2089                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2090                         };
2091                         spi0_cs0: spi0-cs0 {
2092                                 rockchip,pins =
2093                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2094                         };
2095                         spi0_cs1: spi0-cs1 {
2096                                 rockchip,pins =
2097                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2098                         };
2099                         spi0_tx: spi0-tx {
2100                                 rockchip,pins =
2101                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2102                         };
2103                         spi0_rx: spi0-rx {
2104                                 rockchip,pins =
2105                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2106                         };
2107                 };
2108
2109                 spi1 {
2110                         spi1_clk: spi1-clk {
2111                                 rockchip,pins =
2112                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2113                         };
2114                         spi1_cs0: spi1-cs0 {
2115                                 rockchip,pins =
2116                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2117                         };
2118                         spi1_rx: spi1-rx {
2119                                 rockchip,pins =
2120                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2121                         };
2122                         spi1_tx: spi1-tx {
2123                                 rockchip,pins =
2124                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2125                         };
2126                 };
2127
2128                 spi2 {
2129                         spi2_clk: spi2-clk {
2130                                 rockchip,pins =
2131                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2132                         };
2133                         spi2_cs0: spi2-cs0 {
2134                                 rockchip,pins =
2135                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2136                         };
2137                         spi2_rx: spi2-rx {
2138                                 rockchip,pins =
2139                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2140                         };
2141                         spi2_tx: spi2-tx {
2142                                 rockchip,pins =
2143                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2144                         };
2145                 };
2146
2147                 spi3 {
2148                         spi3_clk: spi3-clk {
2149                                 rockchip,pins =
2150                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2151                         };
2152                         spi3_cs0: spi3-cs0 {
2153                                 rockchip,pins =
2154                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2155                         };
2156                         spi3_rx: spi3-rx {
2157                                 rockchip,pins =
2158                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2159                         };
2160                         spi3_tx: spi3-tx {
2161                                 rockchip,pins =
2162                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2163                         };
2164                 };
2165
2166                 spi4 {
2167                         spi4_clk: spi4-clk {
2168                                 rockchip,pins =
2169                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2170                         };
2171                         spi4_cs0: spi4-cs0 {
2172                                 rockchip,pins =
2173                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2174                         };
2175                         spi4_rx: spi4-rx {
2176                                 rockchip,pins =
2177                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2178                         };
2179                         spi4_tx: spi4-tx {
2180                                 rockchip,pins =
2181                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2182                         };
2183                 };
2184
2185                 spi5 {
2186                         spi5_clk: spi5-clk {
2187                                 rockchip,pins =
2188                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2189                         };
2190                         spi5_cs0: spi5-cs0 {
2191                                 rockchip,pins =
2192                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2193                         };
2194                         spi5_rx: spi5-rx {
2195                                 rockchip,pins =
2196                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2197                         };
2198                         spi5_tx: spi5-tx {
2199                                 rockchip,pins =
2200                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2201                         };
2202                 };
2203
2204                 tsadc {
2205                         otp_gpio: otp-gpio {
2206                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2207                         };
2208
2209                         otp_out: otp-out {
2210                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2211                         };
2212                 };
2213
2214                 uart0 {
2215                         uart0_xfer: uart0-xfer {
2216                                 rockchip,pins =
2217                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2218                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2219                         };
2220
2221                         uart0_cts: uart0-cts {
2222                                 rockchip,pins =
2223                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2224                         };
2225
2226                         uart0_rts: uart0-rts {
2227                                 rockchip,pins =
2228                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2229                         };
2230                 };
2231
2232                 uart1 {
2233                         uart1_xfer: uart1-xfer {
2234                                 rockchip,pins =
2235                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2236                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2237                         };
2238                 };
2239
2240                 uart2a {
2241                         uart2a_xfer: uart2a-xfer {
2242                                 rockchip,pins =
2243                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2244                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2245                         };
2246                 };
2247
2248                 uart2b {
2249                         uart2b_xfer: uart2b-xfer {
2250                                 rockchip,pins =
2251                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2252                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2253                         };
2254                 };
2255
2256                 uart2c {
2257                         uart2c_xfer: uart2c-xfer {
2258                                 rockchip,pins =
2259                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2260                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2261                         };
2262                 };
2263
2264                 uart3 {
2265                         uart3_xfer: uart3-xfer {
2266                                 rockchip,pins =
2267                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2268                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2269                         };
2270
2271                         uart3_cts: uart3-cts {
2272                                 rockchip,pins =
2273                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2274                         };
2275
2276                         uart3_rts: uart3-rts {
2277                                 rockchip,pins =
2278                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2279                         };
2280                 };
2281
2282                 uart4 {
2283                         uart4_xfer: uart4-xfer {
2284                                 rockchip,pins =
2285                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2286                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2287                         };
2288                 };
2289
2290                 uarthdcp {
2291                         uarthdcp_xfer: uarthdcp-xfer {
2292                                 rockchip,pins =
2293                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2294                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2295                         };
2296                 };
2297
2298                 pwm0 {
2299                         pwm0_pin: pwm0-pin {
2300                                 rockchip,pins =
2301                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2302                         };
2303
2304                         vop0_pwm_pin: vop0-pwm-pin {
2305                                 rockchip,pins =
2306                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2307                         };
2308                 };
2309
2310                 pwm1 {
2311                         pwm1_pin: pwm1-pin {
2312                                 rockchip,pins =
2313                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2314                         };
2315
2316                         vop1_pwm_pin: vop1-pwm-pin {
2317                                 rockchip,pins =
2318                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2319                         };
2320                 };
2321
2322                 pwm2 {
2323                         pwm2_pin: pwm2-pin {
2324                                 rockchip,pins =
2325                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2326                         };
2327                 };
2328
2329                 pwm3a {
2330                         pwm3a_pin: pwm3a-pin {
2331                                 rockchip,pins =
2332                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 pwm3b {
2337                         pwm3b_pin: pwm3b-pin {
2338                                 rockchip,pins =
2339                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2340                         };
2341                 };
2342
2343                 edp {
2344                         edp_hpd: edp-hpd {
2345                                 rockchip,pins =
2346                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2347                         };
2348                 };
2349
2350                 hdmi {
2351                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2352                                 rockchip,pins =
2353                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2354                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2355                         };
2356
2357                         hdmi_cec: hdmi-cec {
2358                                 rockchip,pins =
2359                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2360                         };
2361                 };
2362
2363                 pcie {
2364                         pcie_clkreqn: pci-clkreqn {
2365                                 rockchip,pins =
2366                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2367                         };
2368
2369                         pcie_clkreqnb: pci-clkreqnb {
2370                                 rockchip,pins =
2371                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2372                         };
2373                 };
2374         };
2375 };