2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/clock/rk3399-cru.h>
43 #include <dt-bindings/gpio/gpio.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pinctrl/rockchip.h>
47 #include <dt-bindings/thermal/thermal.h>
50 compatible = "rockchip,rk3399";
51 interrupt-parent = <&gic>;
103 compatible = "arm,cortex-a53", "arm,armv8";
106 #cooling-cells = <2>; /* min followed by max */
111 compatible = "arm,cortex-a53", "arm,armv8";
117 compatible = "arm,cortex-a53", "arm,armv8";
123 compatible = "arm,cortex-a53", "arm,armv8";
129 compatible = "arm,cortex-a72", "arm,armv8";
132 #cooling-cells = <2>; /* min followed by max */
137 compatible = "arm,cortex-a72", "arm,armv8";
143 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
151 compatible = "fixed-clock";
153 clock-frequency = <24000000>;
154 clock-output-names = "xin24m";
157 gic: interrupt-controller@fee00000 {
158 compatible = "arm,gic-v3";
159 #interrupt-cells = <3>;
160 #address-cells = <2>;
163 interrupt-controller;
165 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
166 <0x0 0xfef00000 0 0xc0000>, /* GICR */
167 <0x0 0xfff00000 0 0x10000>, /* GICC */
168 <0x0 0xfff10000 0 0x10000>, /* GICH */
169 <0x0 0xfff20000 0 0x10000>; /* GICV */
170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
171 its: interrupt-controller@fee20000 {
172 compatible = "arm,gic-v3-its";
174 reg = <0x0 0xfee20000 0x0 0x20000>;
179 compatible = "arm,amba-bus";
180 #address-cells = <2>;
184 dmac_bus: dma-controller@ff6d0000 {
185 compatible = "arm,pl330", "arm,primecell";
186 reg = <0x0 0xff6d0000 0x0 0x4000>;
187 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cru ACLK_DMAC0_PERILP>;
191 clock-names = "apb_pclk";
194 dmac_peri: dma-controller@ff6e0000 {
195 compatible = "arm,pl330", "arm,primecell";
196 reg = <0x0 0xff6e0000 0x0 0x4000>;
197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru ACLK_DMAC1_PERILP>;
201 clock-names = "apb_pclk";
205 saradc: saradc@ff100000 {
206 compatible = "rockchip,rk3399-saradc";
207 reg = <0x0 0xff100000 0x0 0x100>;
208 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
209 #io-channel-cells = <1>;
210 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
211 clock-names = "saradc", "apb_pclk";
216 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
217 reg = <0x0 0xff3c0000 0x0 0x1000>;
218 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
219 clock-names = "i2c", "i2c_sclk";
220 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&i2c0_xfer>;
223 #address-cells = <1>;
229 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
230 reg = <0x0 0xff110000 0x0 0x1000>;
231 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
232 clock-names = "i2c", "i2c_sclk";
233 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c1_xfer>;
236 #address-cells = <1>;
242 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
243 reg = <0x0 0xff120000 0x0 0x1000>;
244 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
245 clock-names = "i2c", "i2c_sclk";
246 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&i2c2_xfer>;
249 #address-cells = <1>;
255 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
256 reg = <0x0 0xff130000 0x0 0x1000>;
257 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
258 clock-names = "i2c", "i2c_sclk";
259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&i2c3_xfer>;
262 #address-cells = <1>;
268 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
269 reg = <0x0 0xff140000 0x0 0x1000>;
270 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
271 clock-names = "i2c", "i2c_sclk";
272 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&i2c5_xfer>;
275 #address-cells = <1>;
281 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
282 reg = <0x0 0xff150000 0x0 0x1000>;
283 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
284 clock-names = "i2c", "i2c_sclk";
285 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&i2c6_xfer>;
288 #address-cells = <1>;
294 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
295 reg = <0x0 0xff160000 0x0 0x1000>;
296 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
297 clock-names = "i2c", "i2c_sclk";
298 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c7_xfer>;
301 #address-cells = <1>;
306 uart0: serial@ff180000 {
307 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
308 reg = <0x0 0xff180000 0x0 0x100>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
317 uart1: serial@ff190000 {
318 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
319 reg = <0x0 0xff190000 0x0 0x100>;
320 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
321 clock-names = "baudclk", "apb_pclk";
322 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
328 uart2: serial@ff1a0000 {
329 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
330 reg = <0x0 0xff1a0000 0x0 0x100>;
331 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
332 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
339 uart3: serial@ff1b0000 {
340 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
341 reg = <0x0 0xff1b0000 0x0 0x100>;
342 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
343 clock-names = "baudclk", "apb_pclk";
344 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
351 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
352 reg = <0x0 0xff110000 0x0 0x1000>;
353 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
354 clock-names = "spiclk", "apb_pclk";
355 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
358 #address-cells = <1>;
364 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
365 reg = <0x0 0xff120000 0x0 0x1000>;
366 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
367 clock-names = "spiclk", "apb_pclk";
368 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
371 #address-cells = <1>;
377 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
378 reg = <0x0 0xff130000 0x0 0x1000>;
379 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
380 clock-names = "spiclk", "apb_pclk";
381 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
384 #address-cells = <1>;
390 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
391 reg = <0x0 0xff120000 0x0 0x1000>;
392 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
393 clock-names = "spiclk", "apb_pclk";
394 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
397 #address-cells = <1>;
403 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
404 reg = <0x0 0xff130000 0x0 0x1000>;
405 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
406 clock-names = "spiclk", "apb_pclk";
407 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
410 #address-cells = <1>;
416 #include "rk3368-thermal.dtsi"
419 tsadc: tsadc@ff260000 {
420 compatible = "rockchip,rk3399-tsadc";
421 reg = <0x0 0xff260000 0x0 0x100>;
422 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
424 clock-names = "tsadc", "apb_pclk";
425 resets = <&cru SRST_TSADC>;
426 reset-names = "tsadc-apb";
427 pinctrl-names = "init", "default", "sleep";
428 pinctrl-0 = <&otp_gpio>;
429 pinctrl-1 = <&otp_out>;
430 pinctrl-2 = <&otp_gpio>;
431 #thermal-sensor-cells = <1>;
432 rockchip,hw-tshut-temp = <95000>;
436 pmugrf: syscon@ff320000 {
437 compatible = "rockchip,rk3399-pmugrf", "syscon";
438 reg = <0x0 0xff320000 0x0 0x1000>;
442 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
443 reg = <0x0 0xff110000 0x0 0x1000>;
444 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
445 clock-names = "spiclk", "apb_pclk";
446 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
449 #address-cells = <1>;
454 uart4: serial@ff370000 {
455 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
456 reg = <0x0 0xff370000 0x0 0x100>;
457 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
458 clock-names = "baudclk", "apb_pclk";
459 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
466 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
467 reg = <0x0 0xff3d0000 0x0 0x1000>;
468 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
469 clock-names = "i2c", "i2c_sclk";
470 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c4_xfer>;
473 #address-cells = <1>;
479 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
480 reg = <0x0 0xff3e0000 0x0 0x1000>;
481 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
482 clock-names = "i2c", "i2c_sclk";
483 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&i2c8_xfer>;
486 #address-cells = <1>;
492 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
493 reg = <0x0 0xff420000 0x0 0x10>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pwm0_pin>;
497 clocks = <&cru PCLK_RKPWM_PMU>;
503 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
504 reg = <0x0 0xff420010 0x0 0x10>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&pwm1_pin>;
508 clocks = <&cru PCLK_RKPWM_PMU>;
514 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
515 reg = <0x0 0xff420020 0x0 0x10>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pwm2_pin>;
519 clocks = <&cru PCLK_RKPWM_PMU>;
525 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
526 reg = <0x0 0xff420030 0x0 0x10>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pwm3a_pin>;
530 clocks = <&cru PCLK_RKPWM_PMU>;
535 pmucru: pmu-clock-controller@ff750000 {
536 compatible = "rockchip,rk3399-pmucru";
537 reg = <0x0 0xff750000 0x0 0x1000>;
538 rockchip,grf = <&pmugrf>;
543 cru: clock-controller@ff760000 {
544 compatible = "rockchip,rk3399-cru";
545 reg = <0x0 0xff760000 0x0 0x1000>;
546 rockchip,grf = <&grf>;
551 grf: syscon@ff770000 {
552 compatible = "rockchip,rk3399-grf", "syscon";
553 reg = <0x0 0xff770000 0x0 0x10000>;
556 spdif: spdif@ff870000 {
557 compatible = "rockchip,rk3399-spdif";
558 reg = <0x0 0xff870000 0x0 0x1000>;
559 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
560 dmas = <&dmac_bus 7>;
562 clock-names = "hclk", "mclk";
563 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&spdif_bus>;
570 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
571 reg = <0x0 0xff880000 0x0 0x1000>;
572 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
573 #address-cells = <1>;
575 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
576 dma-names = "tx", "rx";
577 clock-names = "i2s_hclk", "i2s_clk";
578 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2s0_8ch_bus>;
585 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
586 reg = <0x0 0xff890000 0x0 0x1000>;
587 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>;
590 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
591 dma-names = "tx", "rx";
592 clock-names = "i2s_hclk", "i2s_clk";
593 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2s1_2ch_bus>;
600 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
601 reg = <0x0 0xff8a0000 0x0 0x1000>;
602 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
603 #address-cells = <1>;
605 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
606 dma-names = "tx", "rx";
607 clock-names = "i2s_hclk", "i2s_clk";
608 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
613 compatible = "rockchip,rk3399-pinctrl";
614 rockchip,grf = <&grf>;
615 rockchip,pmu = <&pmugrf>;
616 #address-cells = <0x2>;
620 gpio0: gpio0@ff720000 {
621 compatible = "rockchip,gpio-bank";
622 reg = <0x0 0xff720000 0x0 0x100>;
624 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-controller;
630 #interrupt-cells = <0x2>;
633 gpio1: gpio1@ff730000 {
634 compatible = "rockchip,gpio-bank";
635 reg = <0x0 0xff730000 0x0 0x100>;
637 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
642 interrupt-controller;
643 #interrupt-cells = <0x2>;
646 gpio2: gpio2@ff780000 {
647 compatible = "rockchip,gpio-bank";
648 reg = <0x0 0xff780000 0x0 0x100>;
650 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
655 interrupt-controller;
656 #interrupt-cells = <0x2>;
659 gpio3: gpio3@ff788000 {
660 compatible = "rockchip,gpio-bank";
661 reg = <0x0 0xff788000 0x0 0x100>;
663 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-controller;
669 #interrupt-cells = <0x2>;
672 gpio4: gpio4@ff790000 {
673 compatible = "rockchip,gpio-bank";
674 reg = <0x0 0xff790000 0x0 0x100>;
676 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
681 interrupt-controller;
682 #interrupt-cells = <0x2>;
685 pcfg_pull_up: pcfg-pull-up {
689 pcfg_pull_down: pcfg-pull-down {
693 pcfg_pull_none: pcfg-pull-none {
697 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
699 drive-strength = <12>;
702 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
704 drive-strength = <8>;
707 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
709 drive-strength = <4>;
712 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
714 drive-strength = <2>;
717 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
719 drive-strength = <12>;
725 <0 5 RK_FUNC_1 &pcfg_pull_up>;
730 rgmii_pins: rgmii-pins {
732 <3 11 RK_FUNC_1 &pcfg_pull_none>,
733 <3 13 RK_FUNC_1 &pcfg_pull_none>,
734 <3 8 RK_FUNC_1 &pcfg_pull_none>,
735 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
736 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
737 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
738 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
739 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
740 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
741 <3 6 RK_FUNC_1 &pcfg_pull_none>,
742 <3 7 RK_FUNC_1 &pcfg_pull_none>,
743 <3 2 RK_FUNC_1 &pcfg_pull_none>,
744 <3 3 RK_FUNC_1 &pcfg_pull_none>,
745 <3 14 RK_FUNC_1 &pcfg_pull_none>,
746 <3 9 RK_FUNC_1 &pcfg_pull_none>;
749 rmii_pins: rmii-pins {
751 <3 11 RK_FUNC_1 &pcfg_pull_none>,
752 <3 13 RK_FUNC_1 &pcfg_pull_none>,
753 <3 8 RK_FUNC_1 &pcfg_pull_none>,
754 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
755 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
756 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
757 <3 6 RK_FUNC_1 &pcfg_pull_none>,
758 <3 7 RK_FUNC_1 &pcfg_pull_none>,
759 <3 9 RK_FUNC_1 &pcfg_pull_none>,
760 <3 10 RK_FUNC_1 &pcfg_pull_none>;
765 i2c0_xfer: i2c0-xfer {
767 <1 15 RK_FUNC_2 &pcfg_pull_none>,
768 <1 16 RK_FUNC_2 &pcfg_pull_none>;
773 i2c1_xfer: i2c1-xfer {
775 <4 2 RK_FUNC_1 &pcfg_pull_none>,
776 <4 1 RK_FUNC_1 &pcfg_pull_none>;
781 i2c2_xfer: i2c2-xfer {
783 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
784 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
789 i2c3_xfer: i2c3-xfer {
791 <4 17 RK_FUNC_1 &pcfg_pull_none>,
792 <4 16 RK_FUNC_1 &pcfg_pull_none>;
797 i2c4_xfer: i2c4-xfer {
799 <1 12 RK_FUNC_1 &pcfg_pull_none>,
800 <1 11 RK_FUNC_1 &pcfg_pull_none>;
805 i2c5_xfer: i2c5-xfer {
807 <3 11 RK_FUNC_2 &pcfg_pull_none>,
808 <3 10 RK_FUNC_2 &pcfg_pull_none>;
813 i2c6_xfer: i2c6-xfer {
815 <2 10 RK_FUNC_2 &pcfg_pull_none>,
816 <2 9 RK_FUNC_2 &pcfg_pull_none>;
821 i2c7_xfer: i2c7-xfer {
823 <2 8 RK_FUNC_2 &pcfg_pull_none>,
824 <2 7 RK_FUNC_2 &pcfg_pull_none>;
829 i2c8_xfer: i2c8-xfer {
831 <1 21 RK_FUNC_1 &pcfg_pull_none>,
832 <1 20 RK_FUNC_1 &pcfg_pull_none>;
837 i2s0_8ch_bus: i2s0-8ch-bus {
839 <3 24 RK_FUNC_1 &pcfg_pull_none>,
840 <3 25 RK_FUNC_1 &pcfg_pull_none>,
841 <3 26 RK_FUNC_1 &pcfg_pull_none>,
842 <3 27 RK_FUNC_1 &pcfg_pull_none>,
843 <3 28 RK_FUNC_1 &pcfg_pull_none>,
844 <3 29 RK_FUNC_1 &pcfg_pull_none>,
845 <3 30 RK_FUNC_1 &pcfg_pull_none>,
846 <3 31 RK_FUNC_1 &pcfg_pull_none>,
847 <4 0 RK_FUNC_1 &pcfg_pull_none>;
852 i2s1_2ch_bus: i2s1-2ch-bus {
854 <4 3 RK_FUNC_1 &pcfg_pull_none>,
855 <4 4 RK_FUNC_1 &pcfg_pull_none>,
856 <4 5 RK_FUNC_1 &pcfg_pull_none>,
857 <4 6 RK_FUNC_1 &pcfg_pull_none>,
858 <4 7 RK_FUNC_1 &pcfg_pull_none>;
863 sdio0_bus1: sdio0-bus1 {
865 <2 20 RK_FUNC_1 &pcfg_pull_up>;
868 sdio0_bus4: sdio0-bus4 {
870 <2 20 RK_FUNC_1 &pcfg_pull_up>,
871 <2 21 RK_FUNC_1 &pcfg_pull_up>,
872 <2 22 RK_FUNC_1 &pcfg_pull_up>,
873 <2 23 RK_FUNC_1 &pcfg_pull_up>;
876 sdio0_cmd: sdio0-cmd {
878 <2 24 RK_FUNC_1 &pcfg_pull_up>;
881 sdio0_clk: sdio0-clk {
883 <2 25 RK_FUNC_1 &pcfg_pull_none>;
888 <2 26 RK_FUNC_1 &pcfg_pull_up>;
891 sdio0_pwr: sdio0-pwr {
893 <2 27 RK_FUNC_1 &pcfg_pull_up>;
896 sdio0_bkpwr: sdio0-bkpwr {
898 <2 28 RK_FUNC_1 &pcfg_pull_up>;
903 <0 3 RK_FUNC_1 &pcfg_pull_up>;
906 sdio0_int: sdio0-int {
908 <0 4 RK_FUNC_1 &pcfg_pull_up>;
913 sdmmc_bus1: sdmmc-bus1 {
915 <4 8 RK_FUNC_1 &pcfg_pull_up>;
918 sdmmc_bus4: sdmmc-bus4 {
920 <4 8 RK_FUNC_1 &pcfg_pull_up>,
921 <4 9 RK_FUNC_1 &pcfg_pull_up>,
922 <4 10 RK_FUNC_1 &pcfg_pull_up>,
923 <4 11 RK_FUNC_1 &pcfg_pull_up>;
926 sdmmc_clk: sdmmc-clk {
928 <4 12 RK_FUNC_1 &pcfg_pull_none>;
931 sdmmc_cmd: sdmmc-cmd {
933 <4 13 RK_FUNC_1 &pcfg_pull_up>;
938 <0 7 RK_FUNC_1 &pcfg_pull_up>;
943 <0 8 RK_FUNC_1 &pcfg_pull_up>;
948 spdif_bus: spdif-bus {
950 <4 21 RK_FUNC_1 &pcfg_pull_none>;
957 <3 6 RK_FUNC_2 &pcfg_pull_up>;
961 <3 7 RK_FUNC_2 &pcfg_pull_up>;
965 <3 8 RK_FUNC_2 &pcfg_pull_up>;
969 <3 5 RK_FUNC_2 &pcfg_pull_up>;
973 <3 4 RK_FUNC_2 &pcfg_pull_up>;
980 <1 9 RK_FUNC_2 &pcfg_pull_up>;
984 <1 10 RK_FUNC_2 &pcfg_pull_up>;
988 <1 7 RK_FUNC_2 &pcfg_pull_up>;
992 <1 8 RK_FUNC_2 &pcfg_pull_up>;
999 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1001 spi2_cs0: spi2-cs0 {
1003 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1007 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1011 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1016 spi3_clk: spi3-clk {
1018 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1020 spi3_cs0: spi3-cs0 {
1022 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1026 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1030 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1035 spi4_clk: spi4-clk {
1037 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1039 spi4_cs0: spi4-cs0 {
1041 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1045 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1049 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1054 spi5_clk: spi5-clk {
1056 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1058 spi5_cs0: spi5-cs0 {
1060 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1064 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1068 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1073 otp_gpio: otp-gpio {
1074 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1078 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1083 uart0_xfer: uart0-xfer {
1085 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1086 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1089 uart0_cts: uart0-cts {
1091 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1094 uart0_rts: uart0-rts {
1096 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1101 uart1_xfer: uart1-xfer {
1103 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1104 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1109 uart2a_xfer: uart2a-xfer {
1111 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1112 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1117 uart2b_xfer: uart2b-xfer {
1119 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1120 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1125 uart2c_xfer: uart2c-xfer {
1127 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1128 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1133 uart3_xfer: uart3-xfer {
1135 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1136 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1139 uart3_cts: uart3-cts {
1141 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1144 uart3_rts: uart3-rts {
1146 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1151 uart4_xfer: uart4-xfer {
1153 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1154 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1159 uarthdcp_xfer: uarthdcp-xfer {
1161 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1162 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1167 pwm0_pin: pwm0-pin {
1169 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1172 vop0_pwm_pin: vop0-pwm-pin {
1174 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1179 pwm1_pin: pwm1-pin {
1181 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1184 vop1_pwm_pin: vop1-pwm-pin {
1186 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1191 pwm2_pin: pwm2-pin {
1193 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1198 pwm3a_pin: pwm3a-pin {
1200 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1205 pwm3b_pin: pwm3b-pin {
1207 <1 14 RK_FUNC_1 &pcfg_pull_none>;