arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71         };
  72
  73         psci {
  74                 compatible = "arm,psci-1.0";
  75                 method = "smc";
  76         };
  77
  78         cpus {
  79                 #address-cells = <2>;
  80                 #size-cells = <0>;
  81
  82                 cpu-map {
  83                         cluster0 {
  84                                 core0 {
  85                                         cpu = <&cpu_l0>;
  86                                 };
  87                                 core1 {
  88                                         cpu = <&cpu_l1>;
  89                                 };
  90                                 core2 {
  91                                         cpu = <&cpu_l2>;
  92                                 };
  93                                 core3 {
  94                                         cpu = <&cpu_l3>;
  95                                 };
  96                         };
  97
  98                         cluster1 {
  99                                 core0 {
 100                                         cpu = <&cpu_b0>;
 101                                 };
 102                                 core1 {
 103                                         cpu = <&cpu_b1>;
 104                                 };
 105                         };
 106                 };
 107
 108                 cpu_l0: cpu@0 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53", "arm,armv8";
 111                         reg = <0x0 0x0>;
 112                         enable-method = "psci";
 113                         #cooling-cells = <2>; /* min followed by max */
 114                         clocks = <&cru ARMCLKL>;
 115                         operating-points-v2 = <&cluster0_opp>;
 116                 };
 117
 118                 cpu_l1: cpu@1 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a53", "arm,armv8";
 121                         reg = <0x0 0x1>;
 122                         enable-method = "psci";
 123                         clocks = <&cru ARMCLKL>;
 124                         operating-points-v2 = <&cluster0_opp>;
 125                 };
 126
 127                 cpu_l2: cpu@2 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x2>;
 131                         enable-method = "psci";
 132                         clocks = <&cru ARMCLKL>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                 };
 135
 136                 cpu_l3: cpu@3 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x3>;
 140                         enable-method = "psci";
 141                         clocks = <&cru ARMCLKL>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                 };
 144
 145                 cpu_b0: cpu@100 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a72", "arm,armv8";
 148                         reg = <0x0 0x100>;
 149                         enable-method = "psci";
 150                         #cooling-cells = <2>; /* min followed by max */
 151                         clocks = <&cru ARMCLKB>;
 152                         operating-points-v2 = <&cluster1_opp>;
 153                 };
 154
 155                 cpu_b1: cpu@101 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a72", "arm,armv8";
 158                         reg = <0x0 0x101>;
 159                         enable-method = "psci";
 160                         clocks = <&cru ARMCLKB>;
 161                         operating-points-v2 = <&cluster1_opp>;
 162                 };
 163         };
 164
 165         cluster0_opp: opp_table0 {
 166                 compatible = "operating-points-v2";
 167                 opp-shared;
 168
 169                 opp00 {
 170                         opp-hz = /bits/ 64 <408000000>;
 171                         opp-microvolt = <1000000>;
 172                         clock-latency-ns = <40000>;
 173                 };
 174                 opp01 {
 175                         opp-hz = /bits/ 64 <600000000>;
 176                         opp-microvolt = <1000000>;
 177                 };
 178                 opp02 {
 179                         opp-hz = /bits/ 64 <816000000>;
 180                         opp-microvolt = <1000000>;
 181                 };
 182                 opp03 {
 183                         opp-hz = /bits/ 64 <1008000000>;
 184                         opp-microvolt = <1000000>;
 185                 };
 186         };
 187
 188         cluster1_opp: opp_table1 {
 189                 compatible = "operating-points-v2";
 190                 opp-shared;
 191
 192                 opp00 {
 193                         opp-hz = /bits/ 64 <408000000>;
 194                         opp-microvolt = <1000000>;
 195                         clock-latency-ns = <40000>;
 196                 };
 197                 opp01 {
 198                         opp-hz = /bits/ 64 <600000000>;
 199                         opp-microvolt = <1000000>;
 200                 };
 201                 opp02 {
 202                         opp-hz = /bits/ 64 <816000000>;
 203                         opp-microvolt = <1000000>;
 204                 };
 205                 opp03 {
 206                         opp-hz = /bits/ 64 <1008000000>;
 207                         opp-microvolt = <1000000>;
 208                 };
 209                 opp04 {
 210                         opp-hz = /bits/ 64 <1200000000>;
 211                         opp-microvolt = <1000000>;
 212                 };
 213         };
 214
 215         timer {
 216                 compatible = "arm,armv8-timer";
 217                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 218                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 221         };
 222
 223         pmu_a53 {
 224                 compatible = "arm,cortex-a53-pmu";
 225                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 226                 interrupt-affinity = <&cpu_l0>,
 227                                      <&cpu_l1>,
 228                                      <&cpu_l2>,
 229                                      <&cpu_l3>;
 230         };
 231
 232         pmu_a72 {
 233                 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 235                 interrupt-affinity = <&cpu_b0>,
 236                                      <&cpu_b1>;
 237         };
 238
 239         xin24m: xin24m {
 240                 compatible = "fixed-clock";
 241                 #clock-cells = <0>;
 242                 clock-frequency = <24000000>;
 243                 clock-output-names = "xin24m";
 244         };
 245
 246         amba {
 247                 compatible = "arm,amba-bus";
 248                 #address-cells = <2>;
 249                 #size-cells = <2>;
 250                 ranges;
 251
 252                 dmac_bus: dma-controller@ff6d0000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 255                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258                         clocks = <&cru ACLK_DMAC0_PERILP>;
 259                         clock-names = "apb_pclk";
 260                 };
 261
 262                 dmac_peri: dma-controller@ff6e0000 {
 263                         compatible = "arm,pl330", "arm,primecell";
 264                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 265                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 266                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 267                         #dma-cells = <1>;
 268                         clocks = <&cru ACLK_DMAC1_PERILP>;
 269                         clock-names = "apb_pclk";
 270                 };
 271         };
 272
 273         emmc_phy: phy {
 274                 compatible = "rockchip,rk3399-emmc-phy";
 275                 reg-offset = <0xf780>;
 276                 #phy-cells = <0>;
 277                 rockchip,grf = <&grf>;
 278                 status = "disabled";
 279         };
 280
 281         sdio0: dwmmc@fe310000 {
 282                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 283                 reg = <0x0 0xfe310000 0x0 0x4000>;
 284                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 285                 clock-freq-min-max = <400000 150000000>;
 286                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 287                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 288                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 289                 fifo-depth = <0x100>;
 290                 status = "disabled";
 291         };
 292
 293         sdmmc: dwmmc@fe320000 {
 294                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 295                 reg = <0x0 0xfe320000 0x0 0x4000>;
 296                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 297                 clock-freq-min-max = <400000 150000000>;
 298                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 299                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 300                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 301                 fifo-depth = <0x100>;
 302                 status = "disabled";
 303         };
 304
 305         sdhci: sdhci@fe330000 {
 306                 compatible = "arasan,sdhci-5.1";
 307                 reg = <0x0 0xfe330000 0x0 0x10000>;
 308                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 310                 clock-names = "clk_xin", "clk_ahb";
 311                 phys = <&emmc_phy>;
 312                 phy-names = "phy_arasan";
 313                 status = "disabled";
 314         };
 315
 316         usb_host0_echi: usb@fe380000 {
 317                 compatible = "generic-ehci";
 318                 reg = <0x0 0xfe380000 0x0 0x20000>;
 319                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&cru HCLK_HOST0>;
 321                 clock-names = "hclk_host0";
 322                 status = "disabled";
 323         };
 324
 325         usb_host0_ohci: usb@fe3a0000 {
 326                 compatible = "generic-ohci";
 327                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 328                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru HCLK_HOST0>;
 330                 clock-names = "hclk_host0";
 331                 status = "disabled";
 332         };
 333
 334         usb_host1_echi: usb@fe3c0000 {
 335                 compatible = "generic-ehci";
 336                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 337                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&cru HCLK_HOST1>;
 339                 clock-names = "hclk_host1";
 340                 status = "disabled";
 341         };
 342
 343         usb_host1_ohci: usb@fe3e0000 {
 344                 compatible = "generic-ohci";
 345                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 346                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&cru HCLK_HOST1>;
 348                 clock-names = "hclk_host1";
 349                 status = "disabled";
 350         };
 351
 352         gic: interrupt-controller@fee00000 {
 353                 compatible = "arm,gic-v3";
 354                 #interrupt-cells = <3>;
 355                 #address-cells = <2>;
 356                 #size-cells = <2>;
 357                 ranges;
 358                 interrupt-controller;
 359
 360                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 361                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 362                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 363                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 364                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 365                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 366                 its: interrupt-controller@fee20000 {
 367                         compatible = "arm,gic-v3-its";
 368                         msi-controller;
 369                         reg = <0x0 0xfee20000 0x0 0x20000>;
 370                 };
 371         };
 372
 373         saradc: saradc@ff100000 {
 374                 compatible = "rockchip,rk3399-saradc";
 375                 reg = <0x0 0xff100000 0x0 0x100>;
 376                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 377                 #io-channel-cells = <1>;
 378                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 379                 clock-names = "saradc", "apb_pclk";
 380                 status = "disabled";
 381         };
 382
 383         i2c0: i2c@ff3c0000 {
 384                 compatible = "rockchip,rk3399-i2c";
 385                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 386                 clocks =  <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
 387                 clock-names = "i2c", "pclk";
 388                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c0_xfer>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 status = "disabled";
 394         };
 395
 396         i2c1: i2c@ff110000 {
 397                 compatible = "rockchip,rk3399-i2c";
 398                 reg = <0x0 0xff110000 0x0 0x1000>;
 399                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 400                 clock-names = "i2c", "pclk";
 401                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&i2c1_xfer>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 status = "disabled";
 407         };
 408
 409         i2c2: i2c@ff120000 {
 410                 compatible = "rockchip,rk3399-i2c";
 411                 reg = <0x0 0xff120000 0x0 0x1000>;
 412                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 413                 clock-names = "i2c", "pclk";
 414                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&i2c2_xfer>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 status = "disabled";
 420         };
 421
 422         i2c3: i2c@ff130000 {
 423                 compatible = "rockchip,rk3399-i2c";
 424                 reg = <0x0 0xff130000 0x0 0x1000>;
 425                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 426                 clock-names = "i2c", "pclk";
 427                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2c3_xfer>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 status = "disabled";
 433         };
 434
 435         i2c5: i2c@ff140000 {
 436                 compatible = "rockchip,rk3399-i2c";
 437                 reg = <0x0 0xff140000 0x0 0x1000>;
 438                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 439                 clock-names = "i2c", "pclk";
 440                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&i2c5_xfer>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 status = "disabled";
 446         };
 447
 448         i2c6: i2c@ff150000 {
 449                 compatible = "rockchip,rk3399-i2c";
 450                 reg = <0x0 0xff150000 0x0 0x1000>;
 451                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 452                 clock-names = "i2c", "pclk";
 453                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&i2c6_xfer>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 status = "disabled";
 459         };
 460
 461         i2c7: i2c@ff160000 {
 462                 compatible = "rockchip,rk3399-i2c";
 463                 reg = <0x0 0xff160000 0x0 0x1000>;
 464                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 465                 clock-names = "i2c", "pclk";
 466                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&i2c7_xfer>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 status = "disabled";
 472         };
 473
 474         uart0: serial@ff180000 {
 475                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 476                 reg = <0x0 0xff180000 0x0 0x100>;
 477                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 478                 clock-names = "baudclk", "apb_pclk";
 479                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 480                 reg-shift = <2>;
 481                 reg-io-width = <4>;
 482                 status = "disabled";
 483         };
 484
 485         uart1: serial@ff190000 {
 486                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 487                 reg = <0x0 0xff190000 0x0 0x100>;
 488                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 489                 clock-names = "baudclk", "apb_pclk";
 490                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 491                 reg-shift = <2>;
 492                 reg-io-width = <4>;
 493                 status = "disabled";
 494         };
 495
 496         uart2: serial@ff1a0000 {
 497                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 498                 reg = <0x0 0xff1a0000 0x0 0x100>;
 499                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 502                 reg-shift = <2>;
 503                 reg-io-width = <4>;
 504                 status = "disabled";
 505         };
 506
 507         uart3: serial@ff1b0000 {
 508                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 509                 reg = <0x0 0xff1b0000 0x0 0x100>;
 510                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 511                 clock-names = "baudclk", "apb_pclk";
 512                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 513                 reg-shift = <2>;
 514                 reg-io-width = <4>;
 515                 status = "disabled";
 516         };
 517
 518         spi0: spi@ff1c0000 {
 519                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 520                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 521                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 522                 clock-names = "spiclk", "apb_pclk";
 523                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         spi1: spi@ff1d0000 {
 532                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 533                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 535                 clock-names = "spiclk", "apb_pclk";
 536                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         spi2: spi@ff1e0000 {
 545                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 546                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 548                 clock-names = "spiclk", "apb_pclk";
 549                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         spi4: spi@ff1f0000 {
 558                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 559                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 561                 clock-names = "spiclk", "apb_pclk";
 562                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         spi5: spi@ff200000 {
 571                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 572                 reg = <0x0 0xff200000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 574                 clock-names = "spiclk", "apb_pclk";
 575                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         thermal-zones {
 584                 #include "rk3368-thermal.dtsi"
 585         };
 586
 587         tsadc: tsadc@ff260000 {
 588                 compatible = "rockchip,rk3399-tsadc";
 589                 reg = <0x0 0xff260000 0x0 0x100>;
 590                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 591                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 592                 clock-names = "tsadc", "apb_pclk";
 593                 resets = <&cru SRST_TSADC>;
 594                 reset-names = "tsadc-apb";
 595                 pinctrl-names = "init", "default", "sleep";
 596                 pinctrl-0 = <&otp_gpio>;
 597                 pinctrl-1 = <&otp_out>;
 598                 pinctrl-2 = <&otp_gpio>;
 599                 #thermal-sensor-cells = <1>;
 600                 rockchip,hw-tshut-temp = <95000>;
 601                 status = "disabled";
 602         };
 603
 604         pmu: power-management@ff31000 {
 605                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 606                 reg = <0x0 0xff310000 0x0 0x1000>;
 607
 608                 power: power-controller {
 609                         status = "disabled";
 610                         compatible = "rockchip,rk3399-power-controller";
 611                         #power-domain-cells = <1>;
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614
 615                         pd_center {
 616                                 reg = <RK3399_PD_CENTER>;
 617                                 #address-cells = <1>;
 618                                 #size-cells = <0>;
 619
 620                                 pd_vdu {
 621                                         reg = <RK3399_PD_VDU>;
 622                                 };
 623                                 pd_vcodec {
 624                                         reg = <RK3399_PD_VCODEC>;
 625                                 };
 626                                 pd_iep {
 627                                         reg = <RK3399_PD_IEP>;
 628                                 };
 629                                 pd_rga {
 630                                         reg = <RK3399_PD_RGA>;
 631                                 };
 632                         };
 633                         pd_vio {
 634                                 reg = <RK3399_PD_VIO>;
 635                                 #address-cells = <1>;
 636                                 #size-cells = <0>;
 637
 638                                 pd_isp0 {
 639                                         reg = <RK3399_PD_ISP0>;
 640                                 };
 641                                 pd_isp1 {
 642                                         reg = <RK3399_PD_ISP1>;
 643                                 };
 644                                 pd_hdcp {
 645                                         reg = <RK3399_PD_HDCP>;
 646                                 };
 647                                 pd_vo {
 648                                         reg = <RK3399_PD_VO>;
 649                                         #address-cells = <1>;
 650                                         #size-cells = <0>;
 651
 652                                         pd_vopb {
 653                                                 reg = <RK3399_PD_VOPB>;
 654                                         };
 655                                         pd_vopl {
 656                                                 reg = <RK3399_PD_VOPL>;
 657                                         };
 658                                 };
 659                         };
 660                         pd_gpu {
 661                                 reg = <RK3399_PD_GPU>;
 662                         };
 663                 };
 664         };
 665
 666         pmugrf: syscon@ff320000 {
 667                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 668                 reg = <0x0 0xff320000 0x0 0x1000>;
 669         };
 670
 671         spi3: spi@ff350000 {
 672                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 673                 reg = <0x0 0xff350000 0x0 0x1000>;
 674                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 675                 clock-names = "spiclk", "apb_pclk";
 676                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 status = "disabled";
 682         };
 683
 684         uart4: serial@ff370000 {
 685                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 686                 reg = <0x0 0xff370000 0x0 0x100>;
 687                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 688                 clock-names = "baudclk", "apb_pclk";
 689                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 690                 reg-shift = <2>;
 691                 reg-io-width = <4>;
 692                 status = "disabled";
 693         };
 694
 695         i2c4: i2c@ff3d0000 {
 696                 compatible = "rockchip,rk3399-i2c";
 697                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 698                 clocks = <&cru SCLK_I2C4_PMU>, <&cru PCLK_I2C4_PMU>;
 699                 clock-names = "i2c", "pclk";
 700                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&i2c4_xfer>;
 703                 #address-cells = <1>;
 704                 #size-cells = <0>;
 705                 status = "disabled";
 706         };
 707
 708         i2c8: i2c@ff3e0000 {
 709                 compatible = "rockchip,rk3399-i2c";
 710                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 711                 clocks = <&cru SCLK_I2C8_PMU>, <&cru PCLK_I2C8_PMU>;
 712                 clock-names = "i2c", "pclk";
 713                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 714                 pinctrl-names = "default";
 715                 pinctrl-0 = <&i2c8_xfer>;
 716                 #address-cells = <1>;
 717                 #size-cells = <0>;
 718                 status = "disabled";
 719         };
 720
 721         pwm0: pwm@ff420000 {
 722                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 723                 reg = <0x0 0xff420000 0x0 0x10>;
 724                 #pwm-cells = <3>;
 725                 pinctrl-names = "default";
 726                 pinctrl-0 = <&pwm0_pin>;
 727                 clocks = <&cru PCLK_RKPWM_PMU>;
 728                 clock-names = "pwm";
 729                 status = "disabled";
 730         };
 731
 732         pwm1: pwm@ff420010 {
 733                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 734                 reg = <0x0 0xff420010 0x0 0x10>;
 735                 #pwm-cells = <3>;
 736                 pinctrl-names = "default";
 737                 pinctrl-0 = <&pwm1_pin>;
 738                 clocks = <&cru PCLK_RKPWM_PMU>;
 739                 clock-names = "pwm";
 740                 status = "disabled";
 741         };
 742
 743         pwm2: pwm@ff420020 {
 744                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 745                 reg = <0x0 0xff420020 0x0 0x10>;
 746                 #pwm-cells = <3>;
 747                 pinctrl-names = "default";
 748                 pinctrl-0 = <&pwm2_pin>;
 749                 clocks = <&cru PCLK_RKPWM_PMU>;
 750                 clock-names = "pwm";
 751                 status = "disabled";
 752         };
 753
 754         pwm3: pwm@ff420030 {
 755                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 756                 reg = <0x0 0xff420030 0x0 0x10>;
 757                 #pwm-cells = <3>;
 758                 pinctrl-names = "default";
 759                 pinctrl-0 = <&pwm3a_pin>;
 760                 clocks = <&cru PCLK_RKPWM_PMU>;
 761                 clock-names = "pwm";
 762                 status = "disabled";
 763         };
 764
 765         pmucru: pmu-clock-controller@ff750000 {
 766                 compatible = "rockchip,rk3399-pmucru";
 767                 reg = <0x0 0xff750000 0x0 0x1000>;
 768                 rockchip,grf = <&pmugrf>;
 769                 #clock-cells = <1>;
 770                 #reset-cells = <1>;
 771         };
 772
 773         cru: clock-controller@ff760000 {
 774                 compatible = "rockchip,rk3399-cru";
 775                 reg = <0x0 0xff760000 0x0 0x1000>;
 776                 rockchip,grf = <&grf>;
 777                 #clock-cells = <1>;
 778                 #reset-cells = <1>;
 779         };
 780
 781         grf: syscon@ff770000 {
 782                 compatible = "rockchip,rk3399-grf", "syscon";
 783                 reg = <0x0 0xff770000 0x0 0x10000>;
 784         };
 785
 786         wdt0: watchdog@ff840000 {
 787                 compatible = "snps,dw-wdt";
 788                 reg = <0x0 0xff840000 0x0 0x100>;
 789                 clocks = <&cru PCLK_WDT>;
 790                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 791                 status = "disabled";
 792         };
 793
 794         spdif: spdif@ff870000 {
 795                 compatible = "rockchip,rk3399-spdif";
 796                 reg = <0x0 0xff870000 0x0 0x1000>;
 797                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 798                 dmas = <&dmac_bus 7>;
 799                 dma-names = "tx";
 800                 clock-names = "hclk", "mclk";
 801                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 802                 pinctrl-names = "default";
 803                 pinctrl-0 = <&spdif_bus>;
 804                 status = "disabled";
 805         };
 806
 807         i2s0: i2s@ff880000 {
 808                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 809                 reg = <0x0 0xff880000 0x0 0x1000>;
 810                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 811                 #address-cells = <1>;
 812                 #size-cells = <0>;
 813                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 814                 dma-names = "tx", "rx";
 815                 clock-names = "i2s_hclk", "i2s_clk";
 816                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 817                 pinctrl-names = "default";
 818                 pinctrl-0 = <&i2s0_8ch_bus>;
 819                 status = "disabled";
 820         };
 821
 822         i2s1: i2s@ff890000 {
 823                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 824                 reg = <0x0 0xff890000 0x0 0x1000>;
 825                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 826                 #address-cells = <1>;
 827                 #size-cells = <0>;
 828                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 829                 dma-names = "tx", "rx";
 830                 clock-names = "i2s_hclk", "i2s_clk";
 831                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 832                 pinctrl-names = "default";
 833                 pinctrl-0 = <&i2s1_2ch_bus>;
 834                 status = "disabled";
 835         };
 836
 837         i2s2: i2s@ff8a0000 {
 838                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 839                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 840                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 841                 #address-cells = <1>;
 842                 #size-cells = <0>;
 843                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 844                 dma-names = "tx", "rx";
 845                 clock-names = "i2s_hclk", "i2s_clk";
 846                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 847                 status = "disabled";
 848         };
 849
 850         pinctrl: pinctrl {
 851                 compatible = "rockchip,rk3399-pinctrl";
 852                 rockchip,grf = <&grf>;
 853                 rockchip,pmu = <&pmugrf>;
 854                 #address-cells = <0x2>;
 855                 #size-cells = <0x2>;
 856                 ranges;
 857
 858                 gpio0: gpio0@ff720000 {
 859                         compatible = "rockchip,gpio-bank";
 860                         reg = <0x0 0xff720000 0x0 0x100>;
 861                         clocks = <&cru PCLK_GPIO0_PMU>;
 862                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 863
 864                         gpio-controller;
 865                         #gpio-cells = <0x2>;
 866
 867                         interrupt-controller;
 868                         #interrupt-cells = <0x2>;
 869                 };
 870
 871                 gpio1: gpio1@ff730000 {
 872                         compatible = "rockchip,gpio-bank";
 873                         reg = <0x0 0xff730000 0x0 0x100>;
 874                         clocks = <&cru PCLK_GPIO1_PMU>;
 875                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 876
 877                         gpio-controller;
 878                         #gpio-cells = <0x2>;
 879
 880                         interrupt-controller;
 881                         #interrupt-cells = <0x2>;
 882                 };
 883
 884                 gpio2: gpio2@ff780000 {
 885                         compatible = "rockchip,gpio-bank";
 886                         reg = <0x0 0xff780000 0x0 0x100>;
 887                         clocks = <&cru PCLK_GPIO2>;
 888                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 889
 890                         gpio-controller;
 891                         #gpio-cells = <0x2>;
 892
 893                         interrupt-controller;
 894                         #interrupt-cells = <0x2>;
 895                 };
 896
 897                 gpio3: gpio3@ff788000 {
 898                         compatible = "rockchip,gpio-bank";
 899                         reg = <0x0 0xff788000 0x0 0x100>;
 900                         clocks = <&cru PCLK_GPIO3>;
 901                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 902
 903                         gpio-controller;
 904                         #gpio-cells = <0x2>;
 905
 906                         interrupt-controller;
 907                         #interrupt-cells = <0x2>;
 908                 };
 909
 910                 gpio4: gpio4@ff790000 {
 911                         compatible = "rockchip,gpio-bank";
 912                         reg = <0x0 0xff790000 0x0 0x100>;
 913                         clocks = <&cru PCLK_GPIO4>;
 914                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 915
 916                         gpio-controller;
 917                         #gpio-cells = <0x2>;
 918
 919                         interrupt-controller;
 920                         #interrupt-cells = <0x2>;
 921                 };
 922
 923                 pcfg_pull_up: pcfg-pull-up {
 924                         bias-pull-up;
 925                 };
 926
 927                 pcfg_pull_down: pcfg-pull-down {
 928                         bias-pull-down;
 929                 };
 930
 931                 pcfg_pull_none: pcfg-pull-none {
 932                         bias-disable;
 933                 };
 934
 935                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 936                         bias-disable;
 937                         drive-strength = <12>;
 938                 };
 939
 940                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 941                         bias-pull-up;
 942                         drive-strength = <8>;
 943                 };
 944
 945                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 946                         bias-pull-down;
 947                         drive-strength = <4>;
 948                 };
 949
 950                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 951                         bias-pull-up;
 952                         drive-strength = <2>;
 953                 };
 954
 955                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 956                         bias-pull-down;
 957                         drive-strength = <12>;
 958                 };
 959
 960                 emmc {
 961                         emmc_pwr: emmc-pwr {
 962                                 rockchip,pins =
 963                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 964                         };
 965                 };
 966
 967                 gmac {
 968                         rgmii_pins: rgmii-pins {
 969                                 rockchip,pins =
 970                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 971                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 972                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 973                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 974                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 975                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 976                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 977                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 978                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 979                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 980                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 981                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 982                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 983                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 984                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 985                         };
 986
 987                         rmii_pins: rmii-pins {
 988                                 rockchip,pins =
 989                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 990                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 991                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 992                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 993                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 994                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 995                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 996                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 997                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 998                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 999                         };
1000                 };
1001
1002                 i2c0 {
1003                         i2c0_xfer: i2c0-xfer {
1004                                 rockchip,pins =
1005                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1006                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1007                         };
1008                 };
1009
1010                 i2c1 {
1011                         i2c1_xfer: i2c1-xfer {
1012                                 rockchip,pins =
1013                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1014                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1015                         };
1016                 };
1017
1018                 i2c2 {
1019                         i2c2_xfer: i2c2-xfer {
1020                                 rockchip,pins =
1021                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1022                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1023                         };
1024                 };
1025
1026                 i2c3 {
1027                         i2c3_xfer: i2c3-xfer {
1028                                 rockchip,pins =
1029                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1030                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1031                         };
1032                 };
1033
1034                 i2c4 {
1035                         i2c4_xfer: i2c4-xfer {
1036                                 rockchip,pins =
1037                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1038                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1039                         };
1040                 };
1041
1042                 i2c5 {
1043                         i2c5_xfer: i2c5-xfer {
1044                                 rockchip,pins =
1045                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1046                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1047                         };
1048                 };
1049
1050                 i2c6 {
1051                         i2c6_xfer: i2c6-xfer {
1052                                 rockchip,pins =
1053                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1054                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1055                         };
1056                 };
1057
1058                 i2c7 {
1059                         i2c7_xfer: i2c7-xfer {
1060                                 rockchip,pins =
1061                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1062                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 i2c8 {
1067                         i2c8_xfer: i2c8-xfer {
1068                                 rockchip,pins =
1069                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1070                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072                 };
1073
1074                 i2s0 {
1075                         i2s0_8ch_bus: i2s0-8ch-bus {
1076                                 rockchip,pins =
1077                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1078                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1079                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1080                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1081                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1082                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1083                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1084                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1085                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 i2s1 {
1090                         i2s1_2ch_bus: i2s1-2ch-bus {
1091                                 rockchip,pins =
1092                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1093                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1094                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1095                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1096                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 sdio0 {
1101                         sdio0_bus1: sdio0-bus1 {
1102                                 rockchip,pins =
1103                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1104                         };
1105
1106                         sdio0_bus4: sdio0-bus4 {
1107                                 rockchip,pins =
1108                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1109                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1110                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1111                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1112                         };
1113
1114                         sdio0_cmd: sdio0-cmd {
1115                                 rockchip,pins =
1116                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1117                         };
1118
1119                         sdio0_clk: sdio0-clk {
1120                                 rockchip,pins =
1121                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1122                         };
1123
1124                         sdio0_cd: sdio0-cd {
1125                                 rockchip,pins =
1126                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1127                         };
1128
1129                         sdio0_pwr: sdio0-pwr {
1130                                 rockchip,pins =
1131                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1132                         };
1133
1134                         sdio0_bkpwr: sdio0-bkpwr {
1135                                 rockchip,pins =
1136                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1137                         };
1138
1139                         sdio0_wp: sdio0-wp {
1140                                 rockchip,pins =
1141                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1142                         };
1143
1144                         sdio0_int: sdio0-int {
1145                                 rockchip,pins =
1146                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1147                         };
1148                 };
1149
1150                 sdmmc {
1151                         sdmmc_bus1: sdmmc-bus1 {
1152                                 rockchip,pins =
1153                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1154                         };
1155
1156                         sdmmc_bus4: sdmmc-bus4 {
1157                                 rockchip,pins =
1158                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1159                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1160                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1161                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1162                         };
1163
1164                         sdmmc_clk: sdmmc-clk {
1165                                 rockchip,pins =
1166                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1167                         };
1168
1169                         sdmmc_cmd: sdmmc-cmd {
1170                                 rockchip,pins =
1171                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1172                         };
1173
1174                         sdmmc_cd: sdmcc-cd {
1175                                 rockchip,pins =
1176                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         sdmmc_wp: sdmmc-wp {
1180                                 rockchip,pins =
1181                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1182                         };
1183                 };
1184
1185                 spdif {
1186                         spdif_bus: spdif-bus {
1187                                 rockchip,pins =
1188                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 spi0 {
1193                         spi0_clk: spi0-clk {
1194                                 rockchip,pins =
1195                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1196                         };
1197                         spi0_cs0: spi0-cs0 {
1198                                 rockchip,pins =
1199                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1200                         };
1201                         spi0_cs1: spi0-cs1 {
1202                                 rockchip,pins =
1203                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1204                         };
1205                         spi0_tx: spi0-tx {
1206                                 rockchip,pins =
1207                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1208                         };
1209                         spi0_rx: spi0-rx {
1210                                 rockchip,pins =
1211                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1212                         };
1213                 };
1214
1215                 spi1 {
1216                         spi1_clk: spi1-clk {
1217                                 rockchip,pins =
1218                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1219                         };
1220                         spi1_cs0: spi1-cs0 {
1221                                 rockchip,pins =
1222                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1223                         };
1224                         spi1_rx: spi1-rx {
1225                                 rockchip,pins =
1226                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1227                         };
1228                         spi1_tx: spi1-tx {
1229                                 rockchip,pins =
1230                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1231                         };
1232                 };
1233
1234                 spi2 {
1235                         spi2_clk: spi2-clk {
1236                                 rockchip,pins =
1237                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1238                         };
1239                         spi2_cs0: spi2-cs0 {
1240                                 rockchip,pins =
1241                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1242                         };
1243                         spi2_rx: spi2-rx {
1244                                 rockchip,pins =
1245                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1246                         };
1247                         spi2_tx: spi2-tx {
1248                                 rockchip,pins =
1249                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1250                         };
1251                 };
1252
1253                 spi3 {
1254                         spi3_clk: spi3-clk {
1255                                 rockchip,pins =
1256                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1257                         };
1258                         spi3_cs0: spi3-cs0 {
1259                                 rockchip,pins =
1260                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1261                         };
1262                         spi3_rx: spi3-rx {
1263                                 rockchip,pins =
1264                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1265                         };
1266                         spi3_tx: spi3-tx {
1267                                 rockchip,pins =
1268                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1269                         };
1270                 };
1271
1272                 spi4 {
1273                         spi4_clk: spi4-clk {
1274                                 rockchip,pins =
1275                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1276                         };
1277                         spi4_cs0: spi4-cs0 {
1278                                 rockchip,pins =
1279                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1280                         };
1281                         spi4_rx: spi4-rx {
1282                                 rockchip,pins =
1283                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1284                         };
1285                         spi4_tx: spi4-tx {
1286                                 rockchip,pins =
1287                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1288                         };
1289                 };
1290
1291                 spi5 {
1292                         spi5_clk: spi5-clk {
1293                                 rockchip,pins =
1294                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1295                         };
1296                         spi5_cs0: spi5-cs0 {
1297                                 rockchip,pins =
1298                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1299                         };
1300                         spi5_rx: spi5-rx {
1301                                 rockchip,pins =
1302                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1303                         };
1304                         spi5_tx: spi5-tx {
1305                                 rockchip,pins =
1306                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1307                         };
1308                 };
1309
1310                 tsadc {
1311                         otp_gpio: otp-gpio {
1312                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1313                         };
1314
1315                         otp_out: otp-out {
1316                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1317                         };
1318                 };
1319
1320                 uart0 {
1321                         uart0_xfer: uart0-xfer {
1322                                 rockchip,pins =
1323                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1324                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1325                         };
1326
1327                         uart0_cts: uart0-cts {
1328                                 rockchip,pins =
1329                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331
1332                         uart0_rts: uart0-rts {
1333                                 rockchip,pins =
1334                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 uart1 {
1339                         uart1_xfer: uart1-xfer {
1340                                 rockchip,pins =
1341                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1342                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 uart2a {
1347                         uart2a_xfer: uart2a-xfer {
1348                                 rockchip,pins =
1349                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1350                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1351                         };
1352                 };
1353
1354                 uart2b {
1355                         uart2b_xfer: uart2b-xfer {
1356                                 rockchip,pins =
1357                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1358                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1359                         };
1360                 };
1361
1362                 uart2c {
1363                         uart2c_xfer: uart2c-xfer {
1364                                 rockchip,pins =
1365                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1366                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1367                         };
1368                 };
1369
1370                 uart3 {
1371                         uart3_xfer: uart3-xfer {
1372                                 rockchip,pins =
1373                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1374                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1375                         };
1376
1377                         uart3_cts: uart3-cts {
1378                                 rockchip,pins =
1379                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1380                         };
1381
1382                         uart3_rts: uart3-rts {
1383                                 rockchip,pins =
1384                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1385                         };
1386                 };
1387
1388                 uart4 {
1389                         uart4_xfer: uart4-xfer {
1390                                 rockchip,pins =
1391                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1392                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394                 };
1395
1396                 uarthdcp {
1397                         uarthdcp_xfer: uarthdcp-xfer {
1398                                 rockchip,pins =
1399                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1400                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1401                         };
1402                 };
1403
1404                 pwm0 {
1405                         pwm0_pin: pwm0-pin {
1406                                 rockchip,pins =
1407                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1408                         };
1409
1410                         vop0_pwm_pin: vop0-pwm-pin {
1411                                 rockchip,pins =
1412                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1413                         };
1414                 };
1415
1416                 pwm1 {
1417                         pwm1_pin: pwm1-pin {
1418                                 rockchip,pins =
1419                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421
1422                         vop1_pwm_pin: vop1-pwm-pin {
1423                                 rockchip,pins =
1424                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1425                         };
1426                 };
1427
1428                 pwm2 {
1429                         pwm2_pin: pwm2-pin {
1430                                 rockchip,pins =
1431                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1432                         };
1433                 };
1434
1435                 pwm3a {
1436                         pwm3a_pin: pwm3a-pin {
1437                                 rockchip,pins =
1438                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 pwm3b {
1443                         pwm3b_pin: pwm3b-pin {
1444                                 rockchip,pins =
1445                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1446                         };
1447                 };
1448
1449                 pmic {
1450                         pmic_int_l: pmic-int-l {
1451                                 rockchip,pins =
1452                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1453                         };
1454                 };
1455         };
1456 };