arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 power-domains = <&power RK3399_PD_GMAC>;
 326                 status = "disabled";
 327         };
 328
 329         emmc_phy: phy {
 330                 compatible = "rockchip,rk3399-emmc-phy";
 331                 reg-offset = <0xf780>;
 332                 #phy-cells = <0>;
 333                 rockchip,grf = <&grf>;
 334                 ctrl-base = <0xfe330000>;
 335                 status = "disabled";
 336         };
 337
 338         sdio0: dwmmc@fe310000 {
 339                 compatible = "rockchip,rk3399-dw-mshc",
 340                              "rockchip,rk3288-dw-mshc";
 341                 reg = <0x0 0xfe310000 0x0 0x4000>;
 342                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 343                 clock-freq-min-max = <400000 150000000>;
 344                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 345                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 346                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 347                 fifo-depth = <0x100>;
 348                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 349                 status = "disabled";
 350         };
 351
 352         sdmmc: dwmmc@fe320000 {
 353                 compatible = "rockchip,rk3399-dw-mshc",
 354                              "rockchip,rk3288-dw-mshc";
 355                 reg = <0x0 0xfe320000 0x0 0x4000>;
 356                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 357                 clock-freq-min-max = <400000 150000000>;
 358                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 359                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 360                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 361                 fifo-depth = <0x100>;
 362                 power-domains = <&power RK3399_PD_SD>;
 363                 status = "disabled";
 364         };
 365
 366         sdhci: sdhci@fe330000 {
 367                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 368                 reg = <0x0 0xfe330000 0x0 0x10000>;
 369                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 370                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 371                 clock-names = "clk_xin", "clk_ahb";
 372                 assigned-clocks = <&cru SCLK_EMMC>;
 373                 assigned-clock-parents = <&cru PLL_CPLL>;
 374                 assigned-clock-rates = <200000000>;
 375                 phys = <&emmc_phy>;
 376                 phy-names = "phy_arasan";
 377                 power-domains = <&power RK3399_PD_EMMC>;
 378                 status = "disabled";
 379         };
 380
 381         usb_host0_ehci: usb@fe380000 {
 382                 compatible = "generic-ehci";
 383                 reg = <0x0 0xfe380000 0x0 0x20000>;
 384                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 386                          <&cru SCLK_USBPHY0_480M_SRC>;
 387                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 388                 phys = <&u2phy0_host>;
 389                 phy-names = "usb";
 390                 power-domains = <&power RK3399_PD_PERIHP>;
 391                 status = "disabled";
 392         };
 393
 394         usb_host0_ohci: usb@fe3a0000 {
 395                 compatible = "generic-ohci";
 396                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 397                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 399                          <&cru SCLK_USBPHY0_480M_SRC>;
 400                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 401                 phys = <&u2phy0_host>;
 402                 phy-names = "usb";
 403                 power-domains = <&power RK3399_PD_PERIHP>;
 404                 status = "disabled";
 405         };
 406
 407         usb_host1_ehci: usb@fe3c0000 {
 408                 compatible = "generic-ehci";
 409                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 410                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 411                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 412                          <&cru SCLK_USBPHY1_480M_SRC>;
 413                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 414                 phys = <&u2phy1_host>;
 415                 phy-names = "usb";
 416                 power-domains = <&power RK3399_PD_PERIHP>;
 417                 status = "disabled";
 418         };
 419
 420         usb_host1_ohci: usb@fe3e0000 {
 421                 compatible = "generic-ohci";
 422                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 423                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 424                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 425                          <&cru SCLK_USBPHY1_480M_SRC>;
 426                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 427                 phys = <&u2phy1_host>;
 428                 phy-names = "usb";
 429                 power-domains = <&power RK3399_PD_PERIHP>;
 430                 status = "disabled";
 431         };
 432
 433         usbdrd3_0: usb@fe800000 {
 434                 compatible = "rockchip,rk3399-dwc3";
 435                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 436                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 437                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 438                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 439                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 440                               "aclk_usb3", "aclk_usb3_grf";
 441                 power-domains = <&power RK3399_PD_USB3>;
 442                 #address-cells = <2>;
 443                 #size-cells = <2>;
 444                 ranges;
 445                 status = "disabled";
 446                 usbdrd_dwc3_0: dwc3@fe800000 {
 447                         compatible = "snps,dwc3";
 448                         reg = <0x0 0xfe800000 0x0 0x100000>;
 449                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 450                         dr_mode = "otg";
 451                         phys = <&u2phy0_otg>;
 452                         phy-names = "usb2-phy";
 453                         phy_type = "utmi_wide";
 454                         snps,dis_enblslpm_quirk;
 455                         snps,dis-u2-freeclk-exists-quirk;
 456                         snps,dis-del-phy-power-chg-quirk;
 457                         snps,xhci-slow-suspend-quirk;
 458                         status = "disabled";
 459                 };
 460         };
 461
 462         usbdrd3_1: usb@fe900000 {
 463                 compatible = "rockchip,rk3399-dwc3";
 464                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 465                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 466                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 467                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 468                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 469                               "aclk_usb3", "aclk_usb3_grf";
 470                 power-domains = <&power RK3399_PD_USB3>;
 471                 #address-cells = <2>;
 472                 #size-cells = <2>;
 473                 ranges;
 474                 status = "disabled";
 475                 usbdrd_dwc3_1: dwc3@fe900000 {
 476                         compatible = "snps,dwc3";
 477                         reg = <0x0 0xfe900000 0x0 0x100000>;
 478                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 479                         dr_mode = "otg";
 480                         phys = <&u2phy1_otg>;
 481                         phy-names = "usb2-phy";
 482                         phy_type = "utmi_wide";
 483                         snps,dis_enblslpm_quirk;
 484                         snps,dis-u2-freeclk-exists-quirk;
 485                         snps,dis-del-phy-power-chg-quirk;
 486                         snps,xhci-slow-suspend-quirk;
 487                         status = "disabled";
 488                 };
 489         };
 490
 491         gic: interrupt-controller@fee00000 {
 492                 compatible = "arm,gic-v3";
 493                 #interrupt-cells = <4>;
 494                 #address-cells = <2>;
 495                 #size-cells = <2>;
 496                 ranges;
 497                 interrupt-controller;
 498
 499                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 500                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 501                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 502                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 503                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 504                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 505                 its: interrupt-controller@fee20000 {
 506                         compatible = "arm,gic-v3-its";
 507                         msi-controller;
 508                         reg = <0x0 0xfee20000 0x0 0x20000>;
 509                 };
 510
 511                 ppi-partitions {
 512                         part0: interrupt-partition-0 {
 513                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 514                         };
 515
 516                         part1: interrupt-partition-1 {
 517                                 affinity = <&cpu_b0 &cpu_b1>;
 518                         };
 519                 };
 520         };
 521
 522         saradc: saradc@ff100000 {
 523                 compatible = "rockchip,rk3399-saradc";
 524                 reg = <0x0 0xff100000 0x0 0x100>;
 525                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 526                 #io-channel-cells = <1>;
 527                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 528                 clock-names = "saradc", "apb_pclk";
 529                 status = "disabled";
 530         };
 531
 532         i2c0: i2c@ff3c0000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 535                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c0_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c1: i2c@ff110000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff110000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c1_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         i2c2: i2c@ff120000 {
 559                 compatible = "rockchip,rk3399-i2c";
 560                 reg = <0x0 0xff120000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 562                 clock-names = "i2c", "pclk";
 563                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c2_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c3: i2c@ff130000 {
 572                 compatible = "rockchip,rk3399-i2c";
 573                 reg = <0x0 0xff130000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 575                 clock-names = "i2c", "pclk";
 576                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c3_xfer>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         i2c5: i2c@ff140000 {
 585                 compatible = "rockchip,rk3399-i2c";
 586                 reg = <0x0 0xff140000 0x0 0x1000>;
 587                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 588                 clock-names = "i2c", "pclk";
 589                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c5_xfer>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 status = "disabled";
 595         };
 596
 597         i2c6: i2c@ff150000 {
 598                 compatible = "rockchip,rk3399-i2c";
 599                 reg = <0x0 0xff150000 0x0 0x1000>;
 600                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 601                 clock-names = "i2c", "pclk";
 602                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&i2c6_xfer>;
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 status = "disabled";
 608         };
 609
 610         i2c7: i2c@ff160000 {
 611                 compatible = "rockchip,rk3399-i2c";
 612                 reg = <0x0 0xff160000 0x0 0x1000>;
 613                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 614                 clock-names = "i2c", "pclk";
 615                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&i2c7_xfer>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 status = "disabled";
 621         };
 622
 623         uart0: serial@ff180000 {
 624                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 625                 reg = <0x0 0xff180000 0x0 0x100>;
 626                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 627                 clock-names = "baudclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 629                 reg-shift = <2>;
 630                 reg-io-width = <4>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 633                 status = "disabled";
 634         };
 635
 636         uart1: serial@ff190000 {
 637                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 638                 reg = <0x0 0xff190000 0x0 0x100>;
 639                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 640                 clock-names = "baudclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 642                 reg-shift = <2>;
 643                 reg-io-width = <4>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&uart1_xfer>;
 646                 status = "disabled";
 647         };
 648
 649         uart2: serial@ff1a0000 {
 650                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 651                 reg = <0x0 0xff1a0000 0x0 0x100>;
 652                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 653                 clock-names = "baudclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 reg-shift = <2>;
 656                 reg-io-width = <4>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&uart2c_xfer>;
 659                 status = "disabled";
 660         };
 661
 662         uart3: serial@ff1b0000 {
 663                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 664                 reg = <0x0 0xff1b0000 0x0 0x100>;
 665                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 666                 clock-names = "baudclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 reg-shift = <2>;
 669                 reg-io-width = <4>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 672                 status = "disabled";
 673         };
 674
 675         spi0: spi@ff1c0000 {
 676                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 677                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 678                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 679                 clock-names = "spiclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "disabled";
 686         };
 687
 688         spi1: spi@ff1d0000 {
 689                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 690                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 691                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 692                 clock-names = "spiclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         spi2: spi@ff1e0000 {
 702                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 703                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 704                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 705                 clock-names = "spiclk", "apb_pclk";
 706                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 709                 #address-cells = <1>;
 710                 #size-cells = <0>;
 711                 status = "disabled";
 712         };
 713
 714         spi4: spi@ff1f0000 {
 715                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 716                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 717                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 718                 clock-names = "spiclk", "apb_pclk";
 719                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 722                 #address-cells = <1>;
 723                 #size-cells = <0>;
 724                 status = "disabled";
 725         };
 726
 727         spi5: spi@ff200000 {
 728                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 729                 reg = <0x0 0xff200000 0x0 0x1000>;
 730                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 731                 clock-names = "spiclk", "apb_pclk";
 732                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 735                 #address-cells = <1>;
 736                 #size-cells = <0>;
 737                 status = "disabled";
 738         };
 739
 740         thermal-zones {
 741                 soc_thermal: soc-thermal {
 742                         polling-delay-passive = <20>; /* milliseconds */
 743                         polling-delay = <1000>; /* milliseconds */
 744                         sustainable-power = <1000>; /* milliwatts */
 745
 746                         thermal-sensors = <&tsadc 0>;
 747
 748                         trips {
 749                                 threshold: trip-point@0 {
 750                                         temperature = <70000>; /* millicelsius */
 751                                         hysteresis = <2000>; /* millicelsius */
 752                                         type = "passive";
 753                                 };
 754                                 target: trip-point@1 {
 755                                         temperature = <85000>; /* millicelsius */
 756                                         hysteresis = <2000>; /* millicelsius */
 757                                         type = "passive";
 758                                 };
 759                                 soc_crit: soc-crit {
 760                                         temperature = <95000>; /* millicelsius */
 761                                         hysteresis = <2000>; /* millicelsius */
 762                                         type = "critical";
 763                                 };
 764                         };
 765
 766                         cooling-maps {
 767                                 map0 {
 768                                         trip = <&target>;
 769                                         cooling-device =
 770                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 771                                         contribution = <4096>;
 772                                 };
 773                                 map1 {
 774                                         trip = <&target>;
 775                                         cooling-device =
 776                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 777                                         contribution = <1024>;
 778                                 };
 779                                 map2 {
 780                                         trip = <&target>;
 781                                         cooling-device =
 782                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 783                                         contribution = <4096>;
 784                                 };
 785                         };
 786                 };
 787
 788                 gpu_thermal: gpu-thermal {
 789                         polling-delay-passive = <100>; /* milliseconds */
 790                         polling-delay = <1000>; /* milliseconds */
 791
 792                         thermal-sensors = <&tsadc 1>;
 793                 };
 794         };
 795
 796         tsadc: tsadc@ff260000 {
 797                 compatible = "rockchip,rk3399-tsadc";
 798                 reg = <0x0 0xff260000 0x0 0x100>;
 799                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 800                 rockchip,grf = <&grf>;
 801                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 802                 clock-names = "tsadc", "apb_pclk";
 803                 assigned-clocks = <&cru SCLK_TSADC>;
 804                 assigned-clock-rates = <750000>;
 805                 resets = <&cru SRST_TSADC>;
 806                 reset-names = "tsadc-apb";
 807                 pinctrl-names = "init", "default", "sleep";
 808                 pinctrl-0 = <&otp_gpio>;
 809                 pinctrl-1 = <&otp_out>;
 810                 pinctrl-2 = <&otp_gpio>;
 811                 #thermal-sensor-cells = <1>;
 812                 rockchip,hw-tshut-temp = <95000>;
 813                 status = "disabled";
 814         };
 815
 816         qos_emmc: qos@ffa58000 {
 817                 compatible = "syscon";
 818                 reg = <0x0 0xffa58000 0x0 0x20>;
 819         };
 820
 821         qos_gmac: qos@ffa5c000 {
 822                 compatible = "syscon";
 823                 reg = <0x0 0xffa5c000 0x0 0x20>;
 824         };
 825
 826         qos_pcie: qos@ffa60080 {
 827                 compatible = "syscon";
 828                 reg = <0x0 0xffa60080 0x0 0x20>;
 829         };
 830
 831         qos_usb_host0: qos@ffa60100 {
 832                 compatible = "syscon";
 833                 reg = <0x0 0xffa60100 0x0 0x20>;
 834         };
 835
 836         qos_usb_host1: qos@ffa60180 {
 837                 compatible = "syscon";
 838                 reg = <0x0 0xffa60180 0x0 0x20>;
 839         };
 840
 841         qos_usb_otg0: qos@ffa70000 {
 842                 compatible = "syscon";
 843                 reg = <0x0 0xffa70000 0x0 0x20>;
 844         };
 845
 846         qos_usb_otg1: qos@ffa70080 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffa70080 0x0 0x20>;
 849         };
 850
 851         qos_sd: qos@ffa74000 {
 852                 compatible = "syscon";
 853                 reg = <0x0 0xffa74000 0x0 0x20>;
 854         };
 855
 856         qos_sdioaudio: qos@ffa76000 {
 857                 compatible = "syscon";
 858                 reg = <0x0 0xffa76000 0x0 0x20>;
 859         };
 860
 861         qos_hdcp: qos@ffa90000 {
 862                 compatible = "syscon";
 863                 reg = <0x0 0xffa90000 0x0 0x20>;
 864         };
 865
 866         qos_iep: qos@ffa98000 {
 867                 compatible = "syscon";
 868                 reg = <0x0 0xffa98000 0x0 0x20>;
 869         };
 870
 871         qos_isp0_m0: qos@ffaa0000 {
 872                 compatible = "syscon";
 873                 reg = <0x0 0xffaa0000 0x0 0x20>;
 874         };
 875
 876         qos_isp0_m1: qos@ffaa0080 {
 877                 compatible = "syscon";
 878                 reg = <0x0 0xffaa0080 0x0 0x20>;
 879         };
 880
 881         qos_isp1_m0: qos@ffaa8000 {
 882                 compatible = "syscon";
 883                 reg = <0x0 0xffaa8000 0x0 0x20>;
 884         };
 885
 886         qos_isp1_m1: qos@ffaa8080 {
 887                 compatible = "syscon";
 888                 reg = <0x0 0xffaa8080 0x0 0x20>;
 889         };
 890
 891         qos_rga_r: qos@ffab0000 {
 892                 compatible = "syscon";
 893                 reg = <0x0 0xffab0000 0x0 0x20>;
 894         };
 895
 896         qos_rga_w: qos@ffab0080 {
 897                 compatible = "syscon";
 898                 reg = <0x0 0xffab0080 0x0 0x20>;
 899         };
 900
 901         qos_video_m0: qos@ffab8000 {
 902                 compatible = "syscon";
 903                 reg = <0x0 0xffab8000 0x0 0x20>;
 904         };
 905
 906         qos_video_m1_r: qos@ffac0000 {
 907                 compatible = "syscon";
 908                 reg = <0x0 0xffac0000 0x0 0x20>;
 909         };
 910
 911         qos_video_m1_w: qos@ffac0080 {
 912                 compatible = "syscon";
 913                 reg = <0x0 0xffac0080 0x0 0x20>;
 914         };
 915
 916         qos_vop_big_r: qos@ffac8000 {
 917                 compatible = "syscon";
 918                 reg = <0x0 0xffac8000 0x0 0x20>;
 919         };
 920
 921         qos_vop_big_w: qos@ffac8080 {
 922                 compatible = "syscon";
 923                 reg = <0x0 0xffac8080 0x0 0x20>;
 924         };
 925
 926         qos_vop_little: qos@ffad0000 {
 927                 compatible = "syscon";
 928                 reg = <0x0 0xffad0000 0x0 0x20>;
 929         };
 930
 931         qos_perihp: qos@ffad8080 {
 932                 compatible = "syscon";
 933                 reg = <0x0 0xffad8080 0x0 0x20>;
 934         };
 935
 936         qos_gpu: qos@ffae0000 {
 937                 compatible = "syscon";
 938                 reg = <0x0 0xffae0000 0x0 0x20>;
 939         };
 940
 941         pmu: power-management@ff310000 {
 942                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 943                 reg = <0x0 0xff310000 0x0 0x1000>;
 944
 945                 /*
 946                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 947                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 948                  * Some of the power domains are grouped together for every
 949                  * voltage domain.
 950                  * The detail contents as below.
 951                  */
 952                 power: power-controller {
 953                         compatible = "rockchip,rk3399-power-controller";
 954                         #power-domain-cells = <1>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957
 958                         /* These power domains are grouped by VD_CENTER */
 959                         pd_iep@RK3399_PD_IEP {
 960                                 reg = <RK3399_PD_IEP>;
 961                                 clocks = <&cru ACLK_IEP>,
 962                                          <&cru HCLK_IEP>;
 963                                 pm_qos = <&qos_iep>;
 964                         };
 965                         pd_rga@RK3399_PD_RGA {
 966                                 reg = <RK3399_PD_RGA>;
 967                                 clocks = <&cru ACLK_RGA>,
 968                                          <&cru HCLK_RGA>;
 969                                 pm_qos = <&qos_rga_r>,
 970                                          <&qos_rga_w>;
 971                         };
 972                         pd_vcodec@RK3399_PD_VCODEC {
 973                                 reg = <RK3399_PD_VCODEC>;
 974                                 clocks = <&cru ACLK_VCODEC>,
 975                                          <&cru HCLK_VCODEC>;
 976                                 pm_qos = <&qos_video_m0>;
 977                         };
 978                         pd_vdu@RK3399_PD_VDU {
 979                                 reg = <RK3399_PD_VDU>;
 980                                 clocks = <&cru ACLK_VDU>,
 981                                          <&cru HCLK_VDU>;
 982                                 pm_qos = <&qos_video_m1_r>,
 983                                          <&qos_video_m1_w>;
 984                         };
 985
 986                         /* These power domains are grouped by VD_GPU */
 987                         pd_gpu@RK3399_PD_GPU {
 988                                 reg = <RK3399_PD_GPU>;
 989                                 clocks = <&cru ACLK_GPU>;
 990                                 pm_qos = <&qos_gpu>;
 991                         };
 992
 993                         /* These power domains are grouped by VD_LOGIC */
 994                         pd_emmc@RK3399_PD_EMMC {
 995                                 reg = <RK3399_PD_EMMC>;
 996                                 clocks = <&cru ACLK_EMMC>;
 997                                 pm_qos = <&qos_emmc>;
 998                         };
 999                         pd_gmac@RK3399_PD_GMAC {
1000                                 reg = <RK3399_PD_GMAC>;
1001                                 clocks = <&cru ACLK_GMAC>;
1002                                 pm_qos = <&qos_gmac>;
1003                         };
1004                         pd_perihp@RK3399_PD_PERIHP {
1005                                 reg = <RK3399_PD_PERIHP>;
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008                                 clocks = <&cru ACLK_PERIHP>;
1009                                 pm_qos = <&qos_perihp>,
1010                                          <&qos_pcie>,
1011                                          <&qos_usb_host0>,
1012                                          <&qos_usb_host1>;
1013
1014                                 pd_sd@RK3399_PD_SD {
1015                                         reg = <RK3399_PD_SD>;
1016                                         clocks = <&cru HCLK_SDMMC>,
1017                                                  <&cru SCLK_SDMMC>;
1018                                         pm_qos = <&qos_sd>;
1019                                 };
1020                         };
1021                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1022                                 reg = <RK3399_PD_SDIOAUDIO>;
1023                                 clocks = <&cru HCLK_SDIO>;
1024                                 pm_qos = <&qos_sdioaudio>;
1025                         };
1026                         pd_usb3@RK3399_PD_USB3 {
1027                                 reg = <RK3399_PD_USB3>;
1028                                 clocks = <&cru ACLK_USB3>;
1029                                 pm_qos = <&qos_usb_otg0>,
1030                                          <&qos_usb_otg1>;
1031                         };
1032                         pd_vio@RK3399_PD_VIO {
1033                                 reg = <RK3399_PD_VIO>;
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036
1037                                 pd_hdcp@RK3399_PD_HDCP {
1038                                         reg = <RK3399_PD_HDCP>;
1039                                         clocks = <&cru ACLK_HDCP>,
1040                                                  <&cru HCLK_HDCP>,
1041                                                  <&cru PCLK_HDCP>;
1042                                         pm_qos = <&qos_hdcp>;
1043                                 };
1044                                 pd_isp0@RK3399_PD_ISP0 {
1045                                         reg = <RK3399_PD_ISP0>;
1046                                         clocks = <&cru ACLK_ISP0>,
1047                                                  <&cru HCLK_ISP0>;
1048                                         pm_qos = <&qos_isp0_m0>,
1049                                                  <&qos_isp0_m1>;
1050                                 };
1051                                 pd_isp1@RK3399_PD_ISP1 {
1052                                         reg = <RK3399_PD_ISP1>;
1053                                         clocks = <&cru ACLK_ISP1>,
1054                                                  <&cru HCLK_ISP1>;
1055                                         pm_qos = <&qos_isp1_m0>,
1056                                                  <&qos_isp1_m1>;
1057                                 };
1058                                 pd_vo@RK3399_PD_VO {
1059                                         reg = <RK3399_PD_VO>;
1060                                         #address-cells = <1>;
1061                                         #size-cells = <0>;
1062
1063                                         pd_vopb@RK3399_PD_VOPB {
1064                                                 reg = <RK3399_PD_VOPB>;
1065                                                 clocks = <&cru ACLK_VOP0>,
1066                                                          <&cru HCLK_VOP0>;
1067                                                 pm_qos = <&qos_vop_big_r>,
1068                                                          <&qos_vop_big_w>;
1069                                         };
1070                                         pd_vopl@RK3399_PD_VOPL {
1071                                                 reg = <RK3399_PD_VOPL>;
1072                                                 clocks = <&cru ACLK_VOP1>,
1073                                                          <&cru HCLK_VOP1>;
1074                                                 pm_qos = <&qos_vop_little>;
1075                                         };
1076                                 };
1077                         };
1078                 };
1079         };
1080
1081         pmugrf: syscon@ff320000 {
1082                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1083                 reg = <0x0 0xff320000 0x0 0x1000>;
1084
1085                 reboot-mode {
1086                         compatible = "syscon-reboot-mode";
1087                         offset = <0x300>;
1088                         mode-bootloader = <BOOT_LOADER>;
1089                         mode-charge = <BOOT_CHARGING>;
1090                         mode-fastboot = <BOOT_FASTBOOT>;
1091                         mode-loader = <BOOT_LOADER>;
1092                         mode-normal = <BOOT_NORMAL>;
1093                         mode-recovery = <BOOT_RECOVERY>;
1094                 };
1095         };
1096
1097         spi3: spi@ff350000 {
1098                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1099                 reg = <0x0 0xff350000 0x0 0x1000>;
1100                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1101                 clock-names = "spiclk", "apb_pclk";
1102                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1103                 pinctrl-names = "default";
1104                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1105                 #address-cells = <1>;
1106                 #size-cells = <0>;
1107                 status = "disabled";
1108         };
1109
1110         uart4: serial@ff370000 {
1111                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1112                 reg = <0x0 0xff370000 0x0 0x100>;
1113                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1114                 clock-names = "baudclk", "apb_pclk";
1115                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1116                 reg-shift = <2>;
1117                 reg-io-width = <4>;
1118                 pinctrl-names = "default";
1119                 pinctrl-0 = <&uart4_xfer>;
1120                 status = "disabled";
1121         };
1122
1123         i2c4: i2c@ff3d0000 {
1124                 compatible = "rockchip,rk3399-i2c";
1125                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1126                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1127                 clock-names = "i2c", "pclk";
1128                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1129                 pinctrl-names = "default";
1130                 pinctrl-0 = <&i2c4_xfer>;
1131                 #address-cells = <1>;
1132                 #size-cells = <0>;
1133                 status = "disabled";
1134         };
1135
1136         i2c8: i2c@ff3e0000 {
1137                 compatible = "rockchip,rk3399-i2c";
1138                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1139                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1140                 clock-names = "i2c", "pclk";
1141                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1142                 pinctrl-names = "default";
1143                 pinctrl-0 = <&i2c8_xfer>;
1144                 #address-cells = <1>;
1145                 #size-cells = <0>;
1146                 status = "disabled";
1147         };
1148
1149         pcie0: pcie@f8000000 {
1150                 compatible = "rockchip,rk3399-pcie";
1151                 #address-cells = <3>;
1152                 #size-cells = <2>;
1153                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1154                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1155                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1156                               "hclk_pcie", "clk_pciephy_ref";
1157                 bus-range = <0x0 0x1>;
1158                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1159                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1160                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1161                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1162                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1163                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1164                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1165                       < 0x0 0xfd000000 0x0 0x1000000 >;
1166                 reg-name = "axi-base", "apb-base";
1167                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1168                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1169                          <&cru SRST_PCIE_PIPE>;
1170                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1171                               "mgmt-sticky-rst", "pipe-rst";
1172                 rockchip,grf = <&grf>;
1173                 pcie-conf = <0xe220>;
1174                 pcie-status = <0xe2a4>;
1175                 pcie-laneoff = <0xe214>;
1176                 power-domains = <&power RK3399_PD_PERIHP>;
1177                 msi-parent = <&its>;
1178                 #interrupt-cells = <1>;
1179                 interrupt-map-mask = <0 0 0 7>;
1180                 interrupt-map = <0 0 0 1 &pcie0 1>,
1181                                 <0 0 0 2 &pcie0 2>,
1182                                 <0 0 0 3 &pcie0 3>,
1183                                 <0 0 0 4 &pcie0 4>;
1184                 status = "disabled";
1185                 pcie_intc: interrupt-controller {
1186                         interrupt-controller;
1187                         #address-cells = <0>;
1188                         #interrupt-cells = <1>;
1189                 };
1190         };
1191
1192         pwm0: pwm@ff420000 {
1193                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1194                 reg = <0x0 0xff420000 0x0 0x10>;
1195                 #pwm-cells = <3>;
1196                 pinctrl-names = "default";
1197                 pinctrl-0 = <&pwm0_pin>;
1198                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1199                 clock-names = "pwm";
1200                 status = "disabled";
1201         };
1202
1203         pwm1: pwm@ff420010 {
1204                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1205                 reg = <0x0 0xff420010 0x0 0x10>;
1206                 #pwm-cells = <3>;
1207                 pinctrl-names = "default";
1208                 pinctrl-0 = <&pwm1_pin>;
1209                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1210                 clock-names = "pwm";
1211                 status = "disabled";
1212         };
1213
1214         pwm2: pwm@ff420020 {
1215                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1216                 reg = <0x0 0xff420020 0x0 0x10>;
1217                 #pwm-cells = <3>;
1218                 pinctrl-names = "default";
1219                 pinctrl-0 = <&pwm2_pin>;
1220                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1221                 clock-names = "pwm";
1222                 status = "disabled";
1223         };
1224
1225         pwm3: pwm@ff420030 {
1226                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1227                 reg = <0x0 0xff420030 0x0 0x10>;
1228                 #pwm-cells = <3>;
1229                 pinctrl-names = "default";
1230                 pinctrl-0 = <&pwm3a_pin>;
1231                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1232                 clock-names = "pwm";
1233                 status = "disabled";
1234         };
1235
1236         rga: rga@ff680000 {
1237                 compatible = "rockchip,rk3399-rga";
1238                 reg = <0x0 0xff680000 0x0 0x10000>;
1239                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1240                 interrupt-names = "rga";
1241                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1242                 clock-names = "aclk", "hclk", "sclk";
1243                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1244                 reset-names = "core", "axi", "ahb";
1245                 power-domains = <&power RK3399_PD_RGA>;
1246                 status = "disabled";
1247         };
1248
1249         pmucru: pmu-clock-controller@ff750000 {
1250                 compatible = "rockchip,rk3399-pmucru";
1251                 reg = <0x0 0xff750000 0x0 0x1000>;
1252                 #clock-cells = <1>;
1253                 #reset-cells = <1>;
1254                 assigned-clocks = <&pmucru PLL_PPLL>;
1255                 assigned-clock-rates = <676000000>;
1256         };
1257
1258         cru: clock-controller@ff760000 {
1259                 compatible = "rockchip,rk3399-cru";
1260                 reg = <0x0 0xff760000 0x0 0x1000>;
1261                 #clock-cells = <1>;
1262                 #reset-cells = <1>;
1263                 assigned-clocks =
1264                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1265                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1266                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1267                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1268                         <&cru PLL_NPLL>,
1269                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1270                         <&cru PCLK_PERIHP>,
1271                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1272                         <&cru PCLK_PERILP0>,
1273                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1274                 assigned-clock-rates =
1275                          <400000000>,  <200000000>,
1276                          <400000000>,  <200000000>,
1277                          <816000000>, <816000000>,
1278                          <594000000>,  <800000000>,
1279                         <1000000000>,
1280                          <150000000>,   <75000000>,
1281                           <37500000>,
1282                          <100000000>,  <100000000>,
1283                           <50000000>,
1284                          <100000000>,   <50000000>;
1285         };
1286
1287         grf: syscon@ff770000 {
1288                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1289                 reg = <0x0 0xff770000 0x0 0x10000>;
1290                 #address-cells = <1>;
1291                 #size-cells = <1>;
1292
1293                 u2phy0: usb2-phy@e450 {
1294                         compatible = "rockchip,rk3399-usb2phy";
1295                         reg = <0xe450 0x10>;
1296                         clocks = <&cru SCLK_USB2PHY0_REF>;
1297                         clock-names = "phyclk";
1298                         #clock-cells = <0>;
1299                         clock-output-names = "clk_usbphy0_480m";
1300                         status = "disabled";
1301
1302                         u2phy0_otg: otg-port {
1303                                 #phy-cells = <0>;
1304                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1305                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1306                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1307                                 interrupt-names = "otg-bvalid", "otg-id",
1308                                                   "linestate";
1309                                 status = "disabled";
1310                         };
1311
1312                         u2phy0_host: host-port {
1313                                 #phy-cells = <0>;
1314                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1315                                 interrupt-names = "linestate";
1316                                 status = "disabled";
1317                         };
1318                 };
1319
1320                 u2phy1: usb2-phy@e460 {
1321                         compatible = "rockchip,rk3399-usb2phy";
1322                         reg = <0xe460 0x10>;
1323                         clocks = <&cru SCLK_USB2PHY1_REF>;
1324                         clock-names = "phyclk";
1325                         #clock-cells = <0>;
1326                         clock-output-names = "clk_usbphy1_480m";
1327                         status = "disabled";
1328
1329                         u2phy1_otg: otg-port {
1330                                 #phy-cells = <0>;
1331                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1332                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1333                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1334                                 interrupt-names = "otg-bvalid", "otg-id",
1335                                                   "linestate";
1336                                 status = "disabled";
1337                         };
1338
1339                         u2phy1_host: host-port {
1340                                 #phy-cells = <0>;
1341                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1342                                 interrupt-names = "linestate";
1343                                 status = "disabled";
1344                         };
1345                 };
1346         };
1347
1348         tcphy0: phy@ff7c0000 {
1349                 compatible = "rockchip,rk3399-typec-phy";
1350                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1351                 rockchip,grf = <&grf>;
1352                 #phy-cells = <1>;
1353                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1354                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1355                 clock-names = "tcpdcore", "tcpdphy-ref";
1356                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1357                 assigned-clock-rates = <50000000>;
1358                 resets = <&cru SRST_UPHY0>,
1359                          <&cru SRST_UPHY0_PIPE_L00>,
1360                          <&cru SRST_P_UPHY0_TCPHY>;
1361                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1362                 rockchip,typec-conn-dir = <0xe580 0 16>;
1363                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1364                 rockchip,external-psm = <0xe588 14 30>;
1365                 rockchip,pipe-status = <0xe5c0 0 0>;
1366                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1367                 status = "disabled";
1368         };
1369
1370         tcphy1: phy@ff800000 {
1371                 compatible = "rockchip,rk3399-typec-phy";
1372                 reg = <0x0 0xff800000 0x0 0x40000>;
1373                 rockchip,grf = <&grf>;
1374                 #phy-cells = <1>;
1375                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1376                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1377                 clock-names = "tcpdcore", "tcpdphy-ref";
1378                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1379                 assigned-clock-rates = <50000000>;
1380                 resets = <&cru SRST_UPHY1>,
1381                          <&cru SRST_UPHY1_PIPE_L00>,
1382                          <&cru SRST_P_UPHY1_TCPHY>;
1383                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1384                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1385                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1386                 rockchip,external-psm = <0xe594 14 30>;
1387                 rockchip,pipe-status = <0xe5c0 16 16>;
1388                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1389                 status = "disabled";
1390         };
1391
1392         watchdog@ff840000 {
1393                 compatible = "snps,dw-wdt";
1394                 reg = <0x0 0xff840000 0x0 0x100>;
1395                 clocks = <&cru PCLK_WDT>;
1396                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1397         };
1398
1399         rktimer: rktimer@ff850000 {
1400                 compatible = "rockchip,rk3399-timer";
1401                 reg = <0x0 0xff850000 0x0 0x1000>;
1402                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1403                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1404                 clock-names = "pclk", "timer";
1405         };
1406
1407         spdif: spdif@ff870000 {
1408                 compatible = "rockchip,rk3399-spdif";
1409                 reg = <0x0 0xff870000 0x0 0x1000>;
1410                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1411                 dmas = <&dmac_bus 7>;
1412                 dma-names = "tx";
1413                 clock-names = "mclk", "hclk";
1414                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1415                 pinctrl-names = "default";
1416                 pinctrl-0 = <&spdif_bus>;
1417                 status = "disabled";
1418         };
1419
1420         i2s0: i2s@ff880000 {
1421                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1422                 reg = <0x0 0xff880000 0x0 0x1000>;
1423                 rockchip,grf = <&grf>;
1424                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1425                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1426                 dma-names = "tx", "rx";
1427                 clock-names = "i2s_clk", "i2s_hclk";
1428                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1429                 pinctrl-names = "default";
1430                 pinctrl-0 = <&i2s0_8ch_bus>;
1431                 status = "disabled";
1432         };
1433
1434         i2s1: i2s@ff890000 {
1435                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1436                 reg = <0x0 0xff890000 0x0 0x1000>;
1437                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1438                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1439                 dma-names = "tx", "rx";
1440                 clock-names = "i2s_clk", "i2s_hclk";
1441                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1442                 pinctrl-names = "default";
1443                 pinctrl-0 = <&i2s1_2ch_bus>;
1444                 status = "disabled";
1445         };
1446
1447         i2s2: i2s@ff8a0000 {
1448                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1449                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1450                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1451                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1452                 dma-names = "tx", "rx";
1453                 clock-names = "i2s_clk", "i2s_hclk";
1454                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1455                 status = "disabled";
1456         };
1457
1458         gpu: gpu@ff9a0000 {
1459                 compatible = "arm,malit860",
1460                              "arm,malit86x",
1461                              "arm,malit8xx",
1462                              "arm,mali-midgard";
1463
1464                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1465
1466                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1467                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1468                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1469                 interrupt-names = "GPU", "JOB", "MMU";
1470
1471                 clocks = <&cru ACLK_GPU>;
1472                 clock-names = "clk_mali";
1473                 #cooling-cells = <2>; /* min followed by max */
1474                 operating-points-v2 = <&gpu_opp_table>;
1475                 power-domains = <&power RK3399_PD_GPU>;
1476                 power-off-delay-ms = <200>;
1477                 status = "disabled";
1478
1479                 gpu_power_model: power_model {
1480                         compatible = "arm,mali-simple-power-model";
1481                         voltage = <900>;
1482                         frequency = <500>;
1483                         static-power = <300>;
1484                         dynamic-power = <396>;
1485                         ts = <32000 4700 (-80) 2>;
1486                         thermal-zone = "gpu-thermal";
1487                 };
1488         };
1489
1490         gpu_opp_table: gpu_opp_table {
1491                 compatible = "operating-points-v2";
1492                 opp-shared;
1493
1494                 opp@200000000 {
1495                         opp-hz = /bits/ 64 <200000000>;
1496                         opp-microvolt = <900000>;
1497                 };
1498                 opp@300000000 {
1499                         opp-hz = /bits/ 64 <300000000>;
1500                         opp-microvolt = <900000>;
1501                 };
1502                 opp@400000000 {
1503                         opp-hz = /bits/ 64 <400000000>;
1504                         opp-microvolt = <900000>;
1505                 };
1506
1507         };
1508
1509         vopl: vop@ff8f0000 {
1510                 compatible = "rockchip,rk3399-vop-lit";
1511                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1512                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1513                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1514                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1515                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1516                 reset-names = "axi", "ahb", "dclk";
1517                 power-domains = <&power RK3399_PD_VOPL>;
1518                 iommus = <&vopl_mmu>;
1519                 status = "disabled";
1520
1521                 vopl_out: port {
1522                         #address-cells = <1>;
1523                         #size-cells = <0>;
1524
1525                         vopl_out_mipi: endpoint@0 {
1526                                 reg = <0>;
1527                                 remote-endpoint = <&mipi_in_vopl>;
1528                         };
1529
1530                         vopl_out_edp: endpoint@1 {
1531                                 reg = <1>;
1532                                 remote-endpoint = <&edp_in_vopl>;
1533                         };
1534
1535                         vopl_out_hdmi: endpoint@2 {
1536                                 reg = <2>;
1537                                 remote-endpoint = <&hdmi_in_vopl>;
1538                         };
1539                 };
1540         };
1541
1542         vop1_pwm: voppwm@ff8f01a0 {
1543                 compatible = "rockchip,vop-pwm";
1544                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1545                 #pwm-cells = <3>;
1546                 pinctrl-names = "default";
1547                 pinctrl-0 = <&vop1_pwm_pin>;
1548                 clocks = <&cru SCLK_VOP1_PWM>;
1549                 clock-names = "pwm";
1550                 status = "disabled";
1551         };
1552
1553         vopl_mmu: iommu@ff8f3f00 {
1554                 compatible = "rockchip,iommu";
1555                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1556                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1557                 interrupt-names = "vopl_mmu";
1558                 #iommu-cells = <0>;
1559                 status = "disabled";
1560         };
1561
1562         vopb: vop@ff900000 {
1563                 compatible = "rockchip,rk3399-vop-big";
1564                 reg = <0x0 0xff900000 0x0 0x3efc>;
1565                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1566                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1567                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1568                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1569                 reset-names = "axi", "ahb", "dclk";
1570                 power-domains = <&power RK3399_PD_VOPB>;
1571                 iommus = <&vopb_mmu>;
1572                 status = "disabled";
1573
1574                 vopb_out: port {
1575                         #address-cells = <1>;
1576                         #size-cells = <0>;
1577
1578                         vopb_out_edp: endpoint@0 {
1579                                 reg = <0>;
1580                                 remote-endpoint = <&edp_in_vopb>;
1581                         };
1582
1583                         vopb_out_mipi: endpoint@1 {
1584                                 reg = <1>;
1585                                 remote-endpoint = <&mipi_in_vopb>;
1586                         };
1587
1588                         vopb_out_hdmi: endpoint@2 {
1589                                 reg = <2>;
1590                                 remote-endpoint = <&hdmi_in_vopb>;
1591                         };
1592                 };
1593         };
1594
1595         vop0_pwm: voppwm@ff9001a0 {
1596                 compatible = "rockchip,vop-pwm";
1597                 reg = <0x0 0xff9001a0 0x0 0x10>;
1598                 #pwm-cells = <3>;
1599                 pinctrl-names = "default";
1600                 pinctrl-0 = <&vop0_pwm_pin>;
1601                 clocks = <&cru SCLK_VOP0_PWM>;
1602                 clock-names = "pwm";
1603                 status = "disabled";
1604         };
1605
1606         vopb_mmu: iommu@ff903f00 {
1607                 compatible = "rockchip,iommu";
1608                 reg = <0x0 0xff903f00 0x0 0x100>;
1609                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1610                 interrupt-names = "vopb_mmu";
1611                 #iommu-cells = <0>;
1612                 status = "disabled";
1613         };
1614
1615         hdmi: hdmi@ff940000 {
1616                 compatible = "rockchip,rk3399-dw-hdmi";
1617                 reg = <0x0 0xff940000 0x0 0x20000>;
1618                 reg-io-width = <4>;
1619                 rockchip,grf = <&grf>;
1620                 power-domains = <&power RK3399_PD_HDCP>;
1621                 pinctrl-names = "default";
1622                 pinctrl-0 = <&hdmi_i2c_xfer>;
1623                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1624                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1625                 clock-names = "iahb", "isfr", "vpll", "grf";
1626                 status = "disabled";
1627
1628                 ports {
1629                         hdmi_in: port {
1630                                 #address-cells = <1>;
1631                                 #size-cells = <0>;
1632                                 hdmi_in_vopb: endpoint@0 {
1633                                         reg = <0>;
1634                                         remote-endpoint = <&vopb_out_hdmi>;
1635                                 };
1636                                 hdmi_in_vopl: endpoint@1 {
1637                                         reg = <1>;
1638                                         remote-endpoint = <&vopl_out_hdmi>;
1639                                 };
1640                         };
1641                 };
1642         };
1643
1644         mipi_dsi: mipi@ff960000 {
1645                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1646                 reg = <0x0 0xff960000 0x0 0x8000>;
1647                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1648                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1649                          <&cru SCLK_DPHY_TX0_CFG>;
1650                 clock-names = "ref", "pclk", "phy_cfg";
1651                 power-domains = <&power RK3399_PD_VIO>;
1652                 rockchip,grf = <&grf>;
1653                 #address-cells = <1>;
1654                 #size-cells = <0>;
1655                 status = "disabled";
1656
1657                 ports {
1658                         #address-cells = <1>;
1659                         #size-cells = <0>;
1660                         reg = <1>;
1661
1662                         mipi_in: port {
1663                                 #address-cells = <1>;
1664                                 #size-cells = <0>;
1665
1666                                 mipi_in_vopb: endpoint@0 {
1667                                         reg = <0>;
1668                                         remote-endpoint = <&vopb_out_mipi>;
1669                                 };
1670                                 mipi_in_vopl: endpoint@1 {
1671                                         reg = <1>;
1672                                         remote-endpoint = <&vopl_out_mipi>;
1673                                 };
1674                         };
1675                 };
1676         };
1677
1678         edp: edp@ff970000 {
1679                 compatible = "rockchip,rk3399-edp";
1680                 reg = <0x0 0xff970000 0x0 0x8000>;
1681                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1682                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1683                 clock-names = "dp", "pclk";
1684                 resets = <&cru SRST_P_EDP_CTRL>;
1685                 reset-names = "dp";
1686                 rockchip,grf = <&grf>;
1687                 status = "disabled";
1688                 pinctrl-names = "default";
1689                 pinctrl-0 = <&edp_hpd>;
1690
1691                 ports {
1692                         #address-cells = <1>;
1693                         #size-cells = <0>;
1694
1695                         edp_in: port@0 {
1696                                 reg = <0>;
1697                                 #address-cells = <1>;
1698                                 #size-cells = <0>;
1699
1700                                 edp_in_vopb: endpoint@0 {
1701                                         reg = <0>;
1702                                         remote-endpoint = <&vopb_out_edp>;
1703                                 };
1704
1705                                 edp_in_vopl: endpoint@1 {
1706                                         reg = <1>;
1707                                         remote-endpoint = <&vopl_out_edp>;
1708                                 };
1709                         };
1710                 };
1711         };
1712
1713         display_subsystem: display-subsystem {
1714                 compatible = "rockchip,display-subsystem";
1715                 ports = <&vopl_out>, <&vopb_out>;
1716                 status = "disabled";
1717         };
1718
1719         pinctrl: pinctrl {
1720                 compatible = "rockchip,rk3399-pinctrl";
1721                 rockchip,grf = <&grf>;
1722                 rockchip,pmu = <&pmugrf>;
1723                 #address-cells = <0x2>;
1724                 #size-cells = <0x2>;
1725                 ranges;
1726
1727                 gpio0: gpio0@ff720000 {
1728                         compatible = "rockchip,gpio-bank";
1729                         reg = <0x0 0xff720000 0x0 0x100>;
1730                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1731                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1732
1733                         gpio-controller;
1734                         #gpio-cells = <0x2>;
1735
1736                         interrupt-controller;
1737                         #interrupt-cells = <0x2>;
1738                 };
1739
1740                 gpio1: gpio1@ff730000 {
1741                         compatible = "rockchip,gpio-bank";
1742                         reg = <0x0 0xff730000 0x0 0x100>;
1743                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1744                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1745
1746                         gpio-controller;
1747                         #gpio-cells = <0x2>;
1748
1749                         interrupt-controller;
1750                         #interrupt-cells = <0x2>;
1751                 };
1752
1753                 gpio2: gpio2@ff780000 {
1754                         compatible = "rockchip,gpio-bank";
1755                         reg = <0x0 0xff780000 0x0 0x100>;
1756                         clocks = <&cru PCLK_GPIO2>;
1757                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1758
1759                         gpio-controller;
1760                         #gpio-cells = <0x2>;
1761
1762                         interrupt-controller;
1763                         #interrupt-cells = <0x2>;
1764                 };
1765
1766                 gpio3: gpio3@ff788000 {
1767                         compatible = "rockchip,gpio-bank";
1768                         reg = <0x0 0xff788000 0x0 0x100>;
1769                         clocks = <&cru PCLK_GPIO3>;
1770                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1771
1772                         gpio-controller;
1773                         #gpio-cells = <0x2>;
1774
1775                         interrupt-controller;
1776                         #interrupt-cells = <0x2>;
1777                 };
1778
1779                 gpio4: gpio4@ff790000 {
1780                         compatible = "rockchip,gpio-bank";
1781                         reg = <0x0 0xff790000 0x0 0x100>;
1782                         clocks = <&cru PCLK_GPIO4>;
1783                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1784
1785                         gpio-controller;
1786                         #gpio-cells = <0x2>;
1787
1788                         interrupt-controller;
1789                         #interrupt-cells = <0x2>;
1790                 };
1791
1792                 pcfg_pull_up: pcfg-pull-up {
1793                         bias-pull-up;
1794                 };
1795
1796                 pcfg_pull_down: pcfg-pull-down {
1797                         bias-pull-down;
1798                 };
1799
1800                 pcfg_pull_none: pcfg-pull-none {
1801                         bias-disable;
1802                 };
1803
1804                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1805                         bias-pull-up;
1806                         drive-strength = <20>;
1807                 };
1808
1809                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1810                         bias-disable;
1811                         drive-strength = <20>;
1812                 };
1813
1814                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1815                         bias-disable;
1816                         drive-strength = <18>;
1817                 };
1818
1819                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1820                         bias-disable;
1821                         drive-strength = <12>;
1822                 };
1823
1824                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1825                         bias-pull-up;
1826                         drive-strength = <8>;
1827                 };
1828
1829                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1830                         bias-pull-down;
1831                         drive-strength = <4>;
1832                 };
1833
1834                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1835                         bias-pull-up;
1836                         drive-strength = <2>;
1837                 };
1838
1839                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1840                         bias-pull-down;
1841                         drive-strength = <12>;
1842                 };
1843
1844                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1845                         bias-disable;
1846                         drive-strength = <13>;
1847                 };
1848
1849                 emmc {
1850                         emmc_pwr: emmc-pwr {
1851                                 rockchip,pins =
1852                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1853                         };
1854                 };
1855
1856                 gmac {
1857                         rgmii_pins: rgmii-pins {
1858                                 rockchip,pins =
1859                                         /* mac_txclk */
1860                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1861                                         /* mac_rxclk */
1862                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1863                                         /* mac_mdio */
1864                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1865                                         /* mac_txen */
1866                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1867                                         /* mac_clk */
1868                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1869                                         /* mac_rxdv */
1870                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1871                                         /* mac_mdc */
1872                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1873                                         /* mac_rxd1 */
1874                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1875                                         /* mac_rxd0 */
1876                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1877                                         /* mac_txd1 */
1878                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1879                                         /* mac_txd0 */
1880                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1881                                         /* mac_rxd3 */
1882                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1883                                         /* mac_rxd2 */
1884                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1885                                         /* mac_txd3 */
1886                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1887                                         /* mac_txd2 */
1888                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1889                         };
1890
1891                         rmii_pins: rmii-pins {
1892                                 rockchip,pins =
1893                                         /* mac_mdio */
1894                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1895                                         /* mac_txen */
1896                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1897                                         /* mac_clk */
1898                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1899                                         /* mac_rxer */
1900                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1901                                         /* mac_rxdv */
1902                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1903                                         /* mac_mdc */
1904                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1905                                         /* mac_rxd1 */
1906                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1907                                         /* mac_rxd0 */
1908                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1909                                         /* mac_txd1 */
1910                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1911                                         /* mac_txd0 */
1912                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1913                         };
1914                 };
1915
1916                 i2c0 {
1917                         i2c0_xfer: i2c0-xfer {
1918                                 rockchip,pins =
1919                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1920                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1921                         };
1922                 };
1923
1924                 i2c1 {
1925                         i2c1_xfer: i2c1-xfer {
1926                                 rockchip,pins =
1927                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1928                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 i2c2 {
1933                         i2c2_xfer: i2c2-xfer {
1934                                 rockchip,pins =
1935                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1936                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1937                         };
1938                 };
1939
1940                 i2c3 {
1941                         i2c3_xfer: i2c3-xfer {
1942                                 rockchip,pins =
1943                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1944                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1945                         };
1946
1947                         i2c3_gpio: i2c3_gpio {
1948                                 rockchip,pins =
1949                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1950                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1951                         };
1952
1953                 };
1954
1955                 i2c4 {
1956                         i2c4_xfer: i2c4-xfer {
1957                                 rockchip,pins =
1958                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1959                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1960                         };
1961                 };
1962
1963                 i2c5 {
1964                         i2c5_xfer: i2c5-xfer {
1965                                 rockchip,pins =
1966                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1967                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1968                         };
1969                 };
1970
1971                 i2c6 {
1972                         i2c6_xfer: i2c6-xfer {
1973                                 rockchip,pins =
1974                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1975                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1976                         };
1977                 };
1978
1979                 i2c7 {
1980                         i2c7_xfer: i2c7-xfer {
1981                                 rockchip,pins =
1982                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1983                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1984                         };
1985                 };
1986
1987                 i2c8 {
1988                         i2c8_xfer: i2c8-xfer {
1989                                 rockchip,pins =
1990                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1991                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1992                         };
1993                 };
1994
1995                 i2s0 {
1996                         i2s0_8ch_bus: i2s0-8ch-bus {
1997                                 rockchip,pins =
1998                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1999                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2000                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2001                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2002                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2003                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2004                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2005                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2006                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2007                         };
2008                 };
2009
2010                 i2s1 {
2011                         i2s1_2ch_bus: i2s1-2ch-bus {
2012                                 rockchip,pins =
2013                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2014                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2015                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2016                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2017                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 sdio0 {
2022                         sdio0_bus1: sdio0-bus1 {
2023                                 rockchip,pins =
2024                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2025                         };
2026
2027                         sdio0_bus4: sdio0-bus4 {
2028                                 rockchip,pins =
2029                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2030                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2031                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2032                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2033                         };
2034
2035                         sdio0_cmd: sdio0-cmd {
2036                                 rockchip,pins =
2037                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2038                         };
2039
2040                         sdio0_clk: sdio0-clk {
2041                                 rockchip,pins =
2042                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2043                         };
2044
2045                         sdio0_cd: sdio0-cd {
2046                                 rockchip,pins =
2047                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2048                         };
2049
2050                         sdio0_pwr: sdio0-pwr {
2051                                 rockchip,pins =
2052                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2053                         };
2054
2055                         sdio0_bkpwr: sdio0-bkpwr {
2056                                 rockchip,pins =
2057                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2058                         };
2059
2060                         sdio0_wp: sdio0-wp {
2061                                 rockchip,pins =
2062                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2063                         };
2064
2065                         sdio0_int: sdio0-int {
2066                                 rockchip,pins =
2067                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2068                         };
2069                 };
2070
2071                 sdmmc {
2072                         sdmmc_bus1: sdmmc-bus1 {
2073                                 rockchip,pins =
2074                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2075                         };
2076
2077                         sdmmc_bus4: sdmmc-bus4 {
2078                                 rockchip,pins =
2079                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2080                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2081                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2082                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2083                         };
2084
2085                         sdmmc_clk: sdmmc-clk {
2086                                 rockchip,pins =
2087                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2088                         };
2089
2090                         sdmmc_cmd: sdmmc-cmd {
2091                                 rockchip,pins =
2092                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2093                         };
2094
2095                         sdmmc_cd: sdmcc-cd {
2096                                 rockchip,pins =
2097                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2098                         };
2099
2100                         sdmmc_wp: sdmmc-wp {
2101                                 rockchip,pins =
2102                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2103                         };
2104                 };
2105
2106                 spdif {
2107                         spdif_bus: spdif-bus {
2108                                 rockchip,pins =
2109                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2110                         };
2111
2112                         spdif_bus_1: spdif-bus-1 {
2113                                 rockchip,pins =
2114                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2115                         };
2116                 };
2117
2118                 spi0 {
2119                         spi0_clk: spi0-clk {
2120                                 rockchip,pins =
2121                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2122                         };
2123                         spi0_cs0: spi0-cs0 {
2124                                 rockchip,pins =
2125                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2126                         };
2127                         spi0_cs1: spi0-cs1 {
2128                                 rockchip,pins =
2129                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2130                         };
2131                         spi0_tx: spi0-tx {
2132                                 rockchip,pins =
2133                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2134                         };
2135                         spi0_rx: spi0-rx {
2136                                 rockchip,pins =
2137                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2138                         };
2139                 };
2140
2141                 spi1 {
2142                         spi1_clk: spi1-clk {
2143                                 rockchip,pins =
2144                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2145                         };
2146                         spi1_cs0: spi1-cs0 {
2147                                 rockchip,pins =
2148                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2149                         };
2150                         spi1_rx: spi1-rx {
2151                                 rockchip,pins =
2152                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2153                         };
2154                         spi1_tx: spi1-tx {
2155                                 rockchip,pins =
2156                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2157                         };
2158                 };
2159
2160                 spi2 {
2161                         spi2_clk: spi2-clk {
2162                                 rockchip,pins =
2163                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2164                         };
2165                         spi2_cs0: spi2-cs0 {
2166                                 rockchip,pins =
2167                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2168                         };
2169                         spi2_rx: spi2-rx {
2170                                 rockchip,pins =
2171                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2172                         };
2173                         spi2_tx: spi2-tx {
2174                                 rockchip,pins =
2175                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2176                         };
2177                 };
2178
2179                 spi3 {
2180                         spi3_clk: spi3-clk {
2181                                 rockchip,pins =
2182                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2183                         };
2184                         spi3_cs0: spi3-cs0 {
2185                                 rockchip,pins =
2186                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2187                         };
2188                         spi3_rx: spi3-rx {
2189                                 rockchip,pins =
2190                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2191                         };
2192                         spi3_tx: spi3-tx {
2193                                 rockchip,pins =
2194                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196                 };
2197
2198                 spi4 {
2199                         spi4_clk: spi4-clk {
2200                                 rockchip,pins =
2201                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2202                         };
2203                         spi4_cs0: spi4-cs0 {
2204                                 rockchip,pins =
2205                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2206                         };
2207                         spi4_rx: spi4-rx {
2208                                 rockchip,pins =
2209                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2210                         };
2211                         spi4_tx: spi4-tx {
2212                                 rockchip,pins =
2213                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2214                         };
2215                 };
2216
2217                 spi5 {
2218                         spi5_clk: spi5-clk {
2219                                 rockchip,pins =
2220                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2221                         };
2222                         spi5_cs0: spi5-cs0 {
2223                                 rockchip,pins =
2224                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2225                         };
2226                         spi5_rx: spi5-rx {
2227                                 rockchip,pins =
2228                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2229                         };
2230                         spi5_tx: spi5-tx {
2231                                 rockchip,pins =
2232                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2233                         };
2234                 };
2235
2236                 tsadc {
2237                         otp_gpio: otp-gpio {
2238                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2239                         };
2240
2241                         otp_out: otp-out {
2242                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2243                         };
2244                 };
2245
2246                 uart0 {
2247                         uart0_xfer: uart0-xfer {
2248                                 rockchip,pins =
2249                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2250                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2251                         };
2252
2253                         uart0_cts: uart0-cts {
2254                                 rockchip,pins =
2255                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2256                         };
2257
2258                         uart0_rts: uart0-rts {
2259                                 rockchip,pins =
2260                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2261                         };
2262                 };
2263
2264                 uart1 {
2265                         uart1_xfer: uart1-xfer {
2266                                 rockchip,pins =
2267                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2268                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2269                         };
2270                 };
2271
2272                 uart2a {
2273                         uart2a_xfer: uart2a-xfer {
2274                                 rockchip,pins =
2275                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2276                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2277                         };
2278                 };
2279
2280                 uart2b {
2281                         uart2b_xfer: uart2b-xfer {
2282                                 rockchip,pins =
2283                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2284                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2285                         };
2286                 };
2287
2288                 uart2c {
2289                         uart2c_xfer: uart2c-xfer {
2290                                 rockchip,pins =
2291                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2292                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2293                         };
2294                 };
2295
2296                 uart3 {
2297                         uart3_xfer: uart3-xfer {
2298                                 rockchip,pins =
2299                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2300                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2301                         };
2302
2303                         uart3_cts: uart3-cts {
2304                                 rockchip,pins =
2305                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2306                         };
2307
2308                         uart3_rts: uart3-rts {
2309                                 rockchip,pins =
2310                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2311                         };
2312                 };
2313
2314                 uart4 {
2315                         uart4_xfer: uart4-xfer {
2316                                 rockchip,pins =
2317                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2318                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2319                         };
2320                 };
2321
2322                 uarthdcp {
2323                         uarthdcp_xfer: uarthdcp-xfer {
2324                                 rockchip,pins =
2325                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2326                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2327                         };
2328                 };
2329
2330                 pwm0 {
2331                         pwm0_pin: pwm0-pin {
2332                                 rockchip,pins =
2333                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2334                         };
2335
2336                         vop0_pwm_pin: vop0-pwm-pin {
2337                                 rockchip,pins =
2338                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2339                         };
2340                 };
2341
2342                 pwm1 {
2343                         pwm1_pin: pwm1-pin {
2344                                 rockchip,pins =
2345                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2346                         };
2347
2348                         vop1_pwm_pin: vop1-pwm-pin {
2349                                 rockchip,pins =
2350                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2351                         };
2352                 };
2353
2354                 pwm2 {
2355                         pwm2_pin: pwm2-pin {
2356                                 rockchip,pins =
2357                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2358                         };
2359                 };
2360
2361                 pwm3a {
2362                         pwm3a_pin: pwm3a-pin {
2363                                 rockchip,pins =
2364                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2365                         };
2366                 };
2367
2368                 pwm3b {
2369                         pwm3b_pin: pwm3b-pin {
2370                                 rockchip,pins =
2371                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2372                         };
2373                 };
2374
2375                 edp {
2376                         edp_hpd: edp-hpd {
2377                                 rockchip,pins =
2378                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2379                         };
2380                 };
2381
2382                 hdmi {
2383                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2384                                 rockchip,pins =
2385                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2386                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2387                         };
2388
2389                         hdmi_cec: hdmi-cec {
2390                                 rockchip,pins =
2391                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2392                         };
2393                 };
2394
2395                 pcie {
2396                         pcie_clkreqn: pci-clkreqn {
2397                                 rockchip,pins =
2398                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2399                         };
2400
2401                         pcie_clkreqnb: pci-clkreqnb {
2402                                 rockchip,pins =
2403                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2404                         };
2405                 };
2406         };
2407 };