2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
74 compatible = "arm,psci-1.0";
110 compatible = "arm,cortex-a53", "arm,armv8";
112 enable-method = "psci";
113 #cooling-cells = <2>; /* min followed by max */
114 clocks = <&cru ARMCLKL>;
115 operating-points-v2 = <&cluster0_opp>;
120 compatible = "arm,cortex-a53", "arm,armv8";
122 enable-method = "psci";
123 clocks = <&cru ARMCLKL>;
124 operating-points-v2 = <&cluster0_opp>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 enable-method = "psci";
132 clocks = <&cru ARMCLKL>;
133 operating-points-v2 = <&cluster0_opp>;
138 compatible = "arm,cortex-a53", "arm,armv8";
140 enable-method = "psci";
141 clocks = <&cru ARMCLKL>;
142 operating-points-v2 = <&cluster0_opp>;
147 compatible = "arm,cortex-a72", "arm,armv8";
149 enable-method = "psci";
150 #cooling-cells = <2>; /* min followed by max */
151 clocks = <&cru ARMCLKB>;
152 operating-points-v2 = <&cluster1_opp>;
157 compatible = "arm,cortex-a72", "arm,armv8";
159 enable-method = "psci";
160 clocks = <&cru ARMCLKB>;
161 operating-points-v2 = <&cluster1_opp>;
165 cluster0_opp: opp_table0 {
166 compatible = "operating-points-v2";
170 opp-hz = /bits/ 64 <408000000>;
171 opp-microvolt = <1000000>;
172 clock-latency-ns = <40000>;
175 opp-hz = /bits/ 64 <600000000>;
176 opp-microvolt = <1000000>;
179 opp-hz = /bits/ 64 <816000000>;
180 opp-microvolt = <1000000>;
183 opp-hz = /bits/ 64 <1008000000>;
184 opp-microvolt = <1000000>;
188 cluster1_opp: opp_table1 {
189 compatible = "operating-points-v2";
193 opp-hz = /bits/ 64 <408000000>;
194 opp-microvolt = <1000000>;
195 clock-latency-ns = <40000>;
198 opp-hz = /bits/ 64 <600000000>;
199 opp-microvolt = <1000000>;
202 opp-hz = /bits/ 64 <816000000>;
203 opp-microvolt = <1000000>;
206 opp-hz = /bits/ 64 <1008000000>;
207 opp-microvolt = <1000000>;
210 opp-hz = /bits/ 64 <1200000000>;
211 opp-microvolt = <1000000>;
216 compatible = "arm,armv8-timer";
217 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
218 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
224 compatible = "arm,cortex-a53-pmu";
225 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
226 interrupt-affinity = <&cpu_l0>,
233 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
235 interrupt-affinity = <&cpu_b0>,
240 compatible = "fixed-clock";
242 clock-frequency = <24000000>;
243 clock-output-names = "xin24m";
247 compatible = "arm,amba-bus";
248 #address-cells = <2>;
252 dmac_bus: dma-controller@ff6d0000 {
253 compatible = "arm,pl330", "arm,primecell";
254 reg = <0x0 0xff6d0000 0x0 0x4000>;
255 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru ACLK_DMAC0_PERILP>;
259 clock-names = "apb_pclk";
262 dmac_peri: dma-controller@ff6e0000 {
263 compatible = "arm,pl330", "arm,primecell";
264 reg = <0x0 0xff6e0000 0x0 0x4000>;
265 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cru ACLK_DMAC1_PERILP>;
269 clock-names = "apb_pclk";
274 compatible = "rockchip,rk3399-emmc-phy";
275 reg-offset = <0xf780>;
277 rockchip,grf = <&grf>;
281 sdio0: dwmmc@fe310000 {
282 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
283 reg = <0x0 0xfe310000 0x0 0x4000>;
284 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
285 clock-freq-min-max = <400000 150000000>;
286 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
287 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
288 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
289 fifo-depth = <0x100>;
293 sdmmc: dwmmc@fe320000 {
294 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
295 reg = <0x0 0xfe320000 0x0 0x4000>;
296 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
297 clock-freq-min-max = <400000 150000000>;
298 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
299 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
300 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
301 fifo-depth = <0x100>;
305 sdhci: sdhci@fe330000 {
306 compatible = "arasan,sdhci-5.1";
307 reg = <0x0 0xfe330000 0x0 0x10000>;
308 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
312 phy-names = "phy_arasan";
316 usb_host0_echi: usb@fe380000 {
317 compatible = "generic-ehci";
318 reg = <0x0 0xfe380000 0x0 0x20000>;
319 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_HOST0>;
321 clock-names = "hclk_host0";
325 usb_host0_ohci: usb@fe3a0000 {
326 compatible = "generic-ohci";
327 reg = <0x0 0xfe3a0000 0x0 0x20000>;
328 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cru HCLK_HOST0>;
330 clock-names = "hclk_host0";
334 usb_host1_echi: usb@fe3c0000 {
335 compatible = "generic-ehci";
336 reg = <0x0 0xfe3c0000 0x0 0x20000>;
337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru HCLK_HOST1>;
339 clock-names = "hclk_host1";
343 usb_host1_ohci: usb@fe3e0000 {
344 compatible = "generic-ohci";
345 reg = <0x0 0xfe3e0000 0x0 0x20000>;
346 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&cru HCLK_HOST1>;
348 clock-names = "hclk_host1";
352 gic: interrupt-controller@fee00000 {
353 compatible = "arm,gic-v3";
354 #interrupt-cells = <3>;
355 #address-cells = <2>;
358 interrupt-controller;
360 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
361 <0x0 0xfef00000 0 0xc0000>, /* GICR */
362 <0x0 0xfff00000 0 0x10000>, /* GICC */
363 <0x0 0xfff10000 0 0x10000>, /* GICH */
364 <0x0 0xfff20000 0 0x10000>; /* GICV */
365 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
366 its: interrupt-controller@fee20000 {
367 compatible = "arm,gic-v3-its";
369 reg = <0x0 0xfee20000 0x0 0x20000>;
373 saradc: saradc@ff100000 {
374 compatible = "rockchip,rk3399-saradc";
375 reg = <0x0 0xff100000 0x0 0x100>;
376 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
377 #io-channel-cells = <1>;
378 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
379 clock-names = "saradc", "apb_pclk";
384 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
385 reg = <0x0 0xff3c0000 0x0 0x1000>;
386 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
387 clock-names = "i2c", "i2c_sclk";
388 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c0_xfer>;
391 #address-cells = <1>;
397 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
398 reg = <0x0 0xff110000 0x0 0x1000>;
399 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
400 clock-names = "i2c", "i2c_sclk";
401 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2c1_xfer>;
404 #address-cells = <1>;
410 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
411 reg = <0x0 0xff120000 0x0 0x1000>;
412 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
413 clock-names = "i2c", "i2c_sclk";
414 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c2_xfer>;
417 #address-cells = <1>;
423 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
424 reg = <0x0 0xff130000 0x0 0x1000>;
425 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
426 clock-names = "i2c", "i2c_sclk";
427 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c3_xfer>;
430 #address-cells = <1>;
436 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
437 reg = <0x0 0xff140000 0x0 0x1000>;
438 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
439 clock-names = "i2c", "i2c_sclk";
440 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&i2c5_xfer>;
443 #address-cells = <1>;
449 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
450 reg = <0x0 0xff150000 0x0 0x1000>;
451 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
452 clock-names = "i2c", "i2c_sclk";
453 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c6_xfer>;
456 #address-cells = <1>;
462 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
463 reg = <0x0 0xff160000 0x0 0x1000>;
464 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
465 clock-names = "i2c", "i2c_sclk";
466 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&i2c7_xfer>;
469 #address-cells = <1>;
474 uart0: serial@ff180000 {
475 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
476 reg = <0x0 0xff180000 0x0 0x100>;
477 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
478 clock-names = "baudclk", "apb_pclk";
479 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
485 uart1: serial@ff190000 {
486 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
487 reg = <0x0 0xff190000 0x0 0x100>;
488 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
489 clock-names = "baudclk", "apb_pclk";
490 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
496 uart2: serial@ff1a0000 {
497 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
498 reg = <0x0 0xff1a0000 0x0 0x100>;
499 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
500 clock-names = "baudclk", "apb_pclk";
501 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
507 uart3: serial@ff1b0000 {
508 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
509 reg = <0x0 0xff1b0000 0x0 0x100>;
510 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
511 clock-names = "baudclk", "apb_pclk";
512 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
519 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
520 reg = <0x0 0xff1c0000 0x0 0x1000>;
521 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
522 clock-names = "spiclk", "apb_pclk";
523 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
526 #address-cells = <1>;
532 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
533 reg = <0x0 0xff1d0000 0x0 0x1000>;
534 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
535 clock-names = "spiclk", "apb_pclk";
536 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
539 #address-cells = <1>;
545 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
546 reg = <0x0 0xff1e0000 0x0 0x1000>;
547 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
548 clock-names = "spiclk", "apb_pclk";
549 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
552 #address-cells = <1>;
558 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
559 reg = <0x0 0xff1f0000 0x0 0x1000>;
560 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
561 clock-names = "spiclk", "apb_pclk";
562 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
565 #address-cells = <1>;
571 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
572 reg = <0x0 0xff200000 0x0 0x1000>;
573 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
574 clock-names = "spiclk", "apb_pclk";
575 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
578 #address-cells = <1>;
584 #include "rk3368-thermal.dtsi"
587 tsadc: tsadc@ff260000 {
588 compatible = "rockchip,rk3399-tsadc";
589 reg = <0x0 0xff260000 0x0 0x100>;
590 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
592 clock-names = "tsadc", "apb_pclk";
593 resets = <&cru SRST_TSADC>;
594 reset-names = "tsadc-apb";
595 pinctrl-names = "init", "default", "sleep";
596 pinctrl-0 = <&otp_gpio>;
597 pinctrl-1 = <&otp_out>;
598 pinctrl-2 = <&otp_gpio>;
599 #thermal-sensor-cells = <1>;
600 rockchip,hw-tshut-temp = <95000>;
604 pmu: power-management@ff31000 {
605 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
606 reg = <0x0 0xff310000 0x0 0x1000>;
608 power: power-controller {
610 compatible = "rockchip,rk3399-power-controller";
611 #power-domain-cells = <1>;
612 #address-cells = <1>;
616 reg = <RK3399_PD_CENTER>;
617 #address-cells = <1>;
621 reg = <RK3399_PD_VDU>;
624 reg = <RK3399_PD_VCODEC>;
627 reg = <RK3399_PD_IEP>;
630 reg = <RK3399_PD_RGA>;
634 reg = <RK3399_PD_VIO>;
635 #address-cells = <1>;
639 reg = <RK3399_PD_ISP0>;
642 reg = <RK3399_PD_ISP1>;
645 reg = <RK3399_PD_HDCP>;
648 reg = <RK3399_PD_VO>;
649 #address-cells = <1>;
653 reg = <RK3399_PD_VOPB>;
656 reg = <RK3399_PD_VOPL>;
661 reg = <RK3399_PD_GPU>;
666 pmugrf: syscon@ff320000 {
667 compatible = "rockchip,rk3399-pmugrf", "syscon";
668 reg = <0x0 0xff320000 0x0 0x1000>;
672 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
673 reg = <0x0 0xff350000 0x0 0x1000>;
674 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
675 clock-names = "spiclk", "apb_pclk";
676 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
679 #address-cells = <1>;
684 uart4: serial@ff370000 {
685 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
686 reg = <0x0 0xff370000 0x0 0x100>;
687 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
688 clock-names = "baudclk", "apb_pclk";
689 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
696 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
697 reg = <0x0 0xff3d0000 0x0 0x1000>;
698 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
699 clock-names = "i2c", "i2c_sclk";
700 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&i2c4_xfer>;
703 #address-cells = <1>;
709 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
710 reg = <0x0 0xff3e0000 0x0 0x1000>;
711 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
712 clock-names = "i2c", "i2c_sclk";
713 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c8_xfer>;
716 #address-cells = <1>;
722 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
723 reg = <0x0 0xff420000 0x0 0x10>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&pwm0_pin>;
727 clocks = <&cru PCLK_RKPWM_PMU>;
733 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
734 reg = <0x0 0xff420010 0x0 0x10>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&pwm1_pin>;
738 clocks = <&cru PCLK_RKPWM_PMU>;
744 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
745 reg = <0x0 0xff420020 0x0 0x10>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pwm2_pin>;
749 clocks = <&cru PCLK_RKPWM_PMU>;
755 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
756 reg = <0x0 0xff420030 0x0 0x10>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&pwm3a_pin>;
760 clocks = <&cru PCLK_RKPWM_PMU>;
765 pmucru: pmu-clock-controller@ff750000 {
766 compatible = "rockchip,rk3399-pmucru";
767 reg = <0x0 0xff750000 0x0 0x1000>;
768 rockchip,grf = <&pmugrf>;
773 cru: clock-controller@ff760000 {
774 compatible = "rockchip,rk3399-cru";
775 reg = <0x0 0xff760000 0x0 0x1000>;
776 rockchip,grf = <&grf>;
781 grf: syscon@ff770000 {
782 compatible = "rockchip,rk3399-grf", "syscon";
783 reg = <0x0 0xff770000 0x0 0x10000>;
786 wdt0: watchdog@ff840000 {
787 compatible = "snps,dw-wdt";
788 reg = <0x0 0xff840000 0x0 0x100>;
789 clocks = <&cru PCLK_WDT>;
790 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
794 spdif: spdif@ff870000 {
795 compatible = "rockchip,rk3399-spdif";
796 reg = <0x0 0xff870000 0x0 0x1000>;
797 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
798 dmas = <&dmac_bus 7>;
800 clock-names = "hclk", "mclk";
801 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&spdif_bus>;
808 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
809 reg = <0x0 0xff880000 0x0 0x1000>;
810 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
811 #address-cells = <1>;
813 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
814 dma-names = "tx", "rx";
815 clock-names = "i2s_hclk", "i2s_clk";
816 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&i2s0_8ch_bus>;
823 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
824 reg = <0x0 0xff890000 0x0 0x1000>;
825 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
826 #address-cells = <1>;
828 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
829 dma-names = "tx", "rx";
830 clock-names = "i2s_hclk", "i2s_clk";
831 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
832 pinctrl-names = "default";
833 pinctrl-0 = <&i2s1_2ch_bus>;
838 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
839 reg = <0x0 0xff8a0000 0x0 0x1000>;
840 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
841 #address-cells = <1>;
843 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
844 dma-names = "tx", "rx";
845 clock-names = "i2s_hclk", "i2s_clk";
846 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
851 compatible = "rockchip,rk3399-pinctrl";
852 rockchip,grf = <&grf>;
853 rockchip,pmu = <&pmugrf>;
854 #address-cells = <0x2>;
858 gpio0: gpio0@ff720000 {
859 compatible = "rockchip,gpio-bank";
860 reg = <0x0 0xff720000 0x0 0x100>;
861 clocks = <&cru PCLK_GPIO0_PMU>;
862 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
867 interrupt-controller;
868 #interrupt-cells = <0x2>;
871 gpio1: gpio1@ff730000 {
872 compatible = "rockchip,gpio-bank";
873 reg = <0x0 0xff730000 0x0 0x100>;
874 clocks = <&cru PCLK_GPIO1_PMU>;
875 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
880 interrupt-controller;
881 #interrupt-cells = <0x2>;
884 gpio2: gpio2@ff780000 {
885 compatible = "rockchip,gpio-bank";
886 reg = <0x0 0xff780000 0x0 0x100>;
887 clocks = <&cru PCLK_GPIO2>;
888 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-controller;
894 #interrupt-cells = <0x2>;
897 gpio3: gpio3@ff788000 {
898 compatible = "rockchip,gpio-bank";
899 reg = <0x0 0xff788000 0x0 0x100>;
900 clocks = <&cru PCLK_GPIO3>;
901 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
906 interrupt-controller;
907 #interrupt-cells = <0x2>;
910 gpio4: gpio4@ff790000 {
911 compatible = "rockchip,gpio-bank";
912 reg = <0x0 0xff790000 0x0 0x100>;
913 clocks = <&cru PCLK_GPIO4>;
914 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
919 interrupt-controller;
920 #interrupt-cells = <0x2>;
923 pcfg_pull_up: pcfg-pull-up {
927 pcfg_pull_down: pcfg-pull-down {
931 pcfg_pull_none: pcfg-pull-none {
935 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
937 drive-strength = <12>;
940 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
942 drive-strength = <8>;
945 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
947 drive-strength = <4>;
950 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
952 drive-strength = <2>;
955 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
957 drive-strength = <12>;
963 <0 5 RK_FUNC_1 &pcfg_pull_up>;
968 rgmii_pins: rgmii-pins {
970 <3 11 RK_FUNC_1 &pcfg_pull_none>,
971 <3 13 RK_FUNC_1 &pcfg_pull_none>,
972 <3 8 RK_FUNC_1 &pcfg_pull_none>,
973 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
974 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
975 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
976 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
977 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
978 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
979 <3 6 RK_FUNC_1 &pcfg_pull_none>,
980 <3 7 RK_FUNC_1 &pcfg_pull_none>,
981 <3 2 RK_FUNC_1 &pcfg_pull_none>,
982 <3 3 RK_FUNC_1 &pcfg_pull_none>,
983 <3 14 RK_FUNC_1 &pcfg_pull_none>,
984 <3 9 RK_FUNC_1 &pcfg_pull_none>;
987 rmii_pins: rmii-pins {
989 <3 11 RK_FUNC_1 &pcfg_pull_none>,
990 <3 13 RK_FUNC_1 &pcfg_pull_none>,
991 <3 8 RK_FUNC_1 &pcfg_pull_none>,
992 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
993 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
994 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
995 <3 6 RK_FUNC_1 &pcfg_pull_none>,
996 <3 7 RK_FUNC_1 &pcfg_pull_none>,
997 <3 9 RK_FUNC_1 &pcfg_pull_none>,
998 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1003 i2c0_xfer: i2c0-xfer {
1005 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1006 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1011 i2c1_xfer: i2c1-xfer {
1013 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1014 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1019 i2c2_xfer: i2c2-xfer {
1021 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1022 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1027 i2c3_xfer: i2c3-xfer {
1029 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1030 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1035 i2c4_xfer: i2c4-xfer {
1037 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1038 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1043 i2c5_xfer: i2c5-xfer {
1045 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1046 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1051 i2c6_xfer: i2c6-xfer {
1053 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1054 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1059 i2c7_xfer: i2c7-xfer {
1061 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1062 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1067 i2c8_xfer: i2c8-xfer {
1069 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1070 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1075 i2s0_8ch_bus: i2s0-8ch-bus {
1077 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1078 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1079 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1080 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1081 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1082 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1083 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1084 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1085 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1090 i2s1_2ch_bus: i2s1-2ch-bus {
1092 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1093 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1094 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1095 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1096 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1101 sdio0_bus1: sdio0-bus1 {
1103 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1106 sdio0_bus4: sdio0-bus4 {
1108 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1109 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1110 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1111 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1114 sdio0_cmd: sdio0-cmd {
1116 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1119 sdio0_clk: sdio0-clk {
1121 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1124 sdio0_cd: sdio0-cd {
1126 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1129 sdio0_pwr: sdio0-pwr {
1131 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1134 sdio0_bkpwr: sdio0-bkpwr {
1136 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1139 sdio0_wp: sdio0-wp {
1141 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1144 sdio0_int: sdio0-int {
1146 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1151 sdmmc_bus1: sdmmc-bus1 {
1153 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1156 sdmmc_bus4: sdmmc-bus4 {
1158 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1159 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1160 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1161 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1164 sdmmc_clk: sdmmc-clk {
1166 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1169 sdmmc_cmd: sdmmc-cmd {
1171 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1174 sdmmc_cd: sdmcc-cd {
1176 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1179 sdmmc_wp: sdmmc-wp {
1181 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1186 spdif_bus: spdif-bus {
1188 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1193 spi0_clk: spi0-clk {
1195 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1197 spi0_cs0: spi0-cs0 {
1199 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1201 spi0_cs1: spi0-cs1 {
1203 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1207 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1211 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1216 spi1_clk: spi1-clk {
1218 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1220 spi1_cs0: spi1-cs0 {
1222 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1226 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1230 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1235 spi2_clk: spi2-clk {
1237 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1239 spi2_cs0: spi2-cs0 {
1241 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1245 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1249 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1254 spi3_clk: spi3-clk {
1256 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1258 spi3_cs0: spi3-cs0 {
1260 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1264 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1268 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1273 spi4_clk: spi4-clk {
1275 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1277 spi4_cs0: spi4-cs0 {
1279 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1283 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1287 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1292 spi5_clk: spi5-clk {
1294 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1296 spi5_cs0: spi5-cs0 {
1298 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1302 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1306 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1311 otp_gpio: otp-gpio {
1312 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1316 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1321 uart0_xfer: uart0-xfer {
1323 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1324 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1327 uart0_cts: uart0-cts {
1329 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1332 uart0_rts: uart0-rts {
1334 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1339 uart1_xfer: uart1-xfer {
1341 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1342 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1347 uart2a_xfer: uart2a-xfer {
1349 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1350 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1355 uart2b_xfer: uart2b-xfer {
1357 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1358 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1363 uart2c_xfer: uart2c-xfer {
1365 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1366 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1371 uart3_xfer: uart3-xfer {
1373 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1374 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1377 uart3_cts: uart3-cts {
1379 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1382 uart3_rts: uart3-rts {
1384 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1389 uart4_xfer: uart4-xfer {
1391 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1392 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1397 uarthdcp_xfer: uarthdcp-xfer {
1399 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1400 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1405 pwm0_pin: pwm0-pin {
1407 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1410 vop0_pwm_pin: vop0-pwm-pin {
1412 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1417 pwm1_pin: pwm1-pin {
1419 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1422 vop1_pwm_pin: vop1-pwm-pin {
1424 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1429 pwm2_pin: pwm2-pin {
1431 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1436 pwm3a_pin: pwm3a-pin {
1438 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1443 pwm3b_pin: pwm3b-pin {
1445 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1450 pmic_int_l: pmic-int-l {
1452 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;