arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&cpu_sleep>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&cpu_sleep>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&cpu_sleep>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&cpu_sleep>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185                         cpu_sleep: cpu-sleep-0 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <350>;
 190                                 exit-latency-us = <600>;
 191                                 min-residency-us = <1150>;
 192                         };
 193                 };
 194
 195                 /include/ "rk3399-sched-energy.dtsi"
 196
 197         };
 198
 199         cluster0_opp: opp_table0 {
 200                 compatible = "operating-points-v2";
 201                 opp-shared;
 202
 203                 opp@408000000 {
 204                         opp-hz = /bits/ 64 <408000000>;
 205                         opp-microvolt = <800000>;
 206                         clock-latency-ns = <40000>;
 207                 };
 208                 opp@600000000 {
 209                         opp-hz = /bits/ 64 <600000000>;
 210                         opp-microvolt = <800000>;
 211                 };
 212                 opp@816000000 {
 213                         opp-hz = /bits/ 64 <816000000>;
 214                         opp-microvolt = <800000>;
 215                 };
 216                 opp@1008000000 {
 217                         opp-hz = /bits/ 64 <1008000000>;
 218                         opp-microvolt = <875000>;
 219                 };
 220                 opp@1200000000 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <925000>;
 223                 };
 224                 opp@1416000000 {
 225                         opp-hz = /bits/ 64 <1416000000>;
 226                         opp-microvolt = <1025000>;
 227                 };
 228         };
 229
 230         cluster1_opp: opp_table1 {
 231                 compatible = "operating-points-v2";
 232                 opp-shared;
 233
 234                 opp@408000000 {
 235                         opp-hz = /bits/ 64 <408000000>;
 236                         opp-microvolt = <800000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@600000000 {
 240                         opp-hz = /bits/ 64 <600000000>;
 241                         opp-microvolt = <800000>;
 242                 };
 243                 opp@816000000 {
 244                         opp-hz = /bits/ 64 <816000000>;
 245                         opp-microvolt = <800000>;
 246                 };
 247                 opp@1008000000 {
 248                         opp-hz = /bits/ 64 <1008000000>;
 249                         opp-microvolt = <850000>;
 250                 };
 251                 opp@1200000000 {
 252                         opp-hz = /bits/ 64 <1200000000>;
 253                         opp-microvolt = <925000>;
 254                 };
 255         };
 256
 257         timer {
 258                 compatible = "arm,armv8-timer";
 259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 263         };
 264
 265         pmu_a53 {
 266                 compatible = "arm,cortex-a53-pmu";
 267                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 268         };
 269
 270         pmu_a72 {
 271                 compatible = "arm,cortex-a72-pmu";
 272                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 273         };
 274
 275         xin24m: xin24m {
 276                 compatible = "fixed-clock";
 277                 #clock-cells = <0>;
 278                 clock-frequency = <24000000>;
 279                 clock-output-names = "xin24m";
 280         };
 281
 282         amba {
 283                 compatible = "arm,amba-bus";
 284                 #address-cells = <2>;
 285                 #size-cells = <2>;
 286                 ranges;
 287
 288                 dmac_bus: dma-controller@ff6d0000 {
 289                         compatible = "arm,pl330", "arm,primecell";
 290                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 291                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 292                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 293                         #dma-cells = <1>;
 294                         clocks = <&cru ACLK_DMAC0_PERILP>;
 295                         clock-names = "apb_pclk";
 296                         peripherals-req-type-burst;
 297                 };
 298
 299                 dmac_peri: dma-controller@ff6e0000 {
 300                         compatible = "arm,pl330", "arm,primecell";
 301                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 302                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 303                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 304                         #dma-cells = <1>;
 305                         clocks = <&cru ACLK_DMAC1_PERILP>;
 306                         clock-names = "apb_pclk";
 307                         peripherals-req-type-burst;
 308                 };
 309         };
 310
 311         gmac: eth@fe300000 {
 312                 compatible = "rockchip,rk3399-gmac";
 313                 reg = <0x0 0xfe300000 0x0 0x10000>;
 314                 rockchip,grf = <&grf>;
 315                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 316                 interrupt-names = "macirq";
 317                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 318                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 319                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 320                          <&cru PCLK_GMAC>;
 321                 clock-names = "stmmaceth", "mac_clk_rx",
 322                               "mac_clk_tx", "clk_mac_ref",
 323                               "clk_mac_refout", "aclk_mac",
 324                               "pclk_mac";
 325                 resets = <&cru SRST_A_GMAC>;
 326                 reset-names = "stmmaceth";
 327                 power-domains = <&power RK3399_PD_GMAC>;
 328                 status = "disabled";
 329         };
 330
 331         emmc_phy: phy {
 332                 compatible = "rockchip,rk3399-emmc-phy";
 333                 reg-offset = <0xf780>;
 334                 #phy-cells = <0>;
 335                 rockchip,grf = <&grf>;
 336                 ctrl-base = <0xfe330000>;
 337                 status = "disabled";
 338         };
 339
 340         sdio0: dwmmc@fe310000 {
 341                 compatible = "rockchip,rk3399-dw-mshc",
 342                              "rockchip,rk3288-dw-mshc";
 343                 reg = <0x0 0xfe310000 0x0 0x4000>;
 344                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clock-freq-min-max = <400000 150000000>;
 346                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 347                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 348                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 349                 fifo-depth = <0x100>;
 350                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 351                 status = "disabled";
 352         };
 353
 354         sdmmc: dwmmc@fe320000 {
 355                 compatible = "rockchip,rk3399-dw-mshc",
 356                              "rockchip,rk3288-dw-mshc";
 357                 reg = <0x0 0xfe320000 0x0 0x4000>;
 358                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 359                 clock-freq-min-max = <400000 150000000>;
 360                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 361                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 362                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 363                 fifo-depth = <0x100>;
 364                 power-domains = <&power RK3399_PD_SD>;
 365                 status = "disabled";
 366         };
 367
 368         sdhci: sdhci@fe330000 {
 369                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 370                 reg = <0x0 0xfe330000 0x0 0x10000>;
 371                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 373                 clock-names = "clk_xin", "clk_ahb";
 374                 assigned-clocks = <&cru SCLK_EMMC>;
 375                 assigned-clock-parents = <&cru PLL_CPLL>;
 376                 assigned-clock-rates = <200000000>;
 377                 phys = <&emmc_phy>;
 378                 phy-names = "phy_arasan";
 379                 power-domains = <&power RK3399_PD_EMMC>;
 380                 status = "disabled";
 381         };
 382
 383         usb_host0_ehci: usb@fe380000 {
 384                 compatible = "generic-ehci";
 385                 reg = <0x0 0xfe380000 0x0 0x20000>;
 386                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 387                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 388                          <&cru SCLK_USBPHY0_480M_SRC>;
 389                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 390                 phys = <&u2phy0_host>;
 391                 phy-names = "usb";
 392                 power-domains = <&power RK3399_PD_PERIHP>;
 393                 status = "disabled";
 394         };
 395
 396         usb_host0_ohci: usb@fe3a0000 {
 397                 compatible = "generic-ohci";
 398                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 399                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 400                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 401                          <&cru SCLK_USBPHY0_480M_SRC>;
 402                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 403                 phys = <&u2phy0_host>;
 404                 phy-names = "usb";
 405                 power-domains = <&power RK3399_PD_PERIHP>;
 406                 status = "disabled";
 407         };
 408
 409         usb_host1_ehci: usb@fe3c0000 {
 410                 compatible = "generic-ehci";
 411                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 412                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 413                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 414                          <&cru SCLK_USBPHY1_480M_SRC>;
 415                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 416                 phys = <&u2phy1_host>;
 417                 phy-names = "usb";
 418                 power-domains = <&power RK3399_PD_PERIHP>;
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 427                          <&cru SCLK_USBPHY1_480M_SRC>;
 428                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 429                 phys = <&u2phy1_host>;
 430                 phy-names = "usb";
 431                 power-domains = <&power RK3399_PD_PERIHP>;
 432                 status = "disabled";
 433         };
 434
 435         usbdrd3_0: usb@fe800000 {
 436                 compatible = "rockchip,rk3399-dwc3";
 437                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 438                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 439                 clock-names = "ref_clk", "suspend_clk",
 440                               "bus_clk", "grf_clk";
 441                 power-domains = <&power RK3399_PD_USB3>;
 442                 resets = <&cru SRST_A_USB3_OTG0>;
 443                 reset-names = "usb3-otg";
 444                 #address-cells = <2>;
 445                 #size-cells = <2>;
 446                 ranges;
 447                 status = "disabled";
 448                 usbdrd_dwc3_0: dwc3@fe800000 {
 449                         compatible = "snps,dwc3";
 450                         reg = <0x0 0xfe800000 0x0 0x100000>;
 451                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 452                         dr_mode = "otg";
 453                         phys = <&u2phy0_otg>, <&tcphy0 1>;
 454                         phy-names = "usb2-phy", "usb3-phy";
 455                         phy_type = "utmi_wide";
 456                         snps,dis_enblslpm_quirk;
 457                         snps,dis-u2-freeclk-exists-quirk;
 458                         snps,dis-del-phy-power-chg-quirk;
 459                         snps,xhci-slow-suspend-quirk;
 460                         status = "disabled";
 461                 };
 462         };
 463
 464         usbdrd3_1: usb@fe900000 {
 465                 compatible = "rockchip,rk3399-dwc3";
 466                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 467                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 468                 clock-names = "ref_clk", "suspend_clk",
 469                               "bus_clk", "grf_clk";
 470                 power-domains = <&power RK3399_PD_USB3>;
 471                 resets = <&cru SRST_A_USB3_OTG1>;
 472                 reset-names = "usb3-otg";
 473                 #address-cells = <2>;
 474                 #size-cells = <2>;
 475                 ranges;
 476                 status = "disabled";
 477                 usbdrd_dwc3_1: dwc3@fe900000 {
 478                         compatible = "snps,dwc3";
 479                         reg = <0x0 0xfe900000 0x0 0x100000>;
 480                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 481                         dr_mode = "host";
 482                         phys = <&u2phy1_otg>, <&tcphy1 1>;
 483                         phy-names = "usb2-phy", "usb3-phy";
 484                         phy_type = "utmi_wide";
 485                         snps,dis_enblslpm_quirk;
 486                         snps,dis-u2-freeclk-exists-quirk;
 487                         snps,dis-del-phy-power-chg-quirk;
 488                         snps,xhci-slow-suspend-quirk;
 489                         status = "disabled";
 490                 };
 491         };
 492
 493         gic: interrupt-controller@fee00000 {
 494                 compatible = "arm,gic-v3";
 495                 #interrupt-cells = <4>;
 496                 #address-cells = <2>;
 497                 #size-cells = <2>;
 498                 ranges;
 499                 interrupt-controller;
 500
 501                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 502                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 503                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 504                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 505                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 506                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 507                 its: interrupt-controller@fee20000 {
 508                         compatible = "arm,gic-v3-its";
 509                         msi-controller;
 510                         reg = <0x0 0xfee20000 0x0 0x20000>;
 511                 };
 512
 513                 ppi-partitions {
 514                         part0: interrupt-partition-0 {
 515                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 516                         };
 517
 518                         part1: interrupt-partition-1 {
 519                                 affinity = <&cpu_b0 &cpu_b1>;
 520                         };
 521                 };
 522         };
 523
 524         saradc: saradc@ff100000 {
 525                 compatible = "rockchip,rk3399-saradc";
 526                 reg = <0x0 0xff100000 0x0 0x100>;
 527                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 #io-channel-cells = <1>;
 529                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 530                 clock-names = "saradc", "apb_pclk";
 531                 status = "disabled";
 532         };
 533
 534         i2c0: i2c@ff3c0000 {
 535                 compatible = "rockchip,rk3399-i2c";
 536                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 537                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 538                 clock-names = "i2c", "pclk";
 539                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c0_xfer>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         i2c1: i2c@ff110000 {
 548                 compatible = "rockchip,rk3399-i2c";
 549                 reg = <0x0 0xff110000 0x0 0x1000>;
 550                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 551                 clock-names = "i2c", "pclk";
 552                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2c1_xfer>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 status = "disabled";
 558         };
 559
 560         i2c2: i2c@ff120000 {
 561                 compatible = "rockchip,rk3399-i2c";
 562                 reg = <0x0 0xff120000 0x0 0x1000>;
 563                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 564                 clock-names = "i2c", "pclk";
 565                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c2_xfer>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         i2c3: i2c@ff130000 {
 574                 compatible = "rockchip,rk3399-i2c";
 575                 reg = <0x0 0xff130000 0x0 0x1000>;
 576                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 577                 clock-names = "i2c", "pclk";
 578                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c3_xfer>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         i2c5: i2c@ff140000 {
 587                 compatible = "rockchip,rk3399-i2c";
 588                 reg = <0x0 0xff140000 0x0 0x1000>;
 589                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 590                 clock-names = "i2c", "pclk";
 591                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&i2c5_xfer>;
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         i2c6: i2c@ff150000 {
 600                 compatible = "rockchip,rk3399-i2c";
 601                 reg = <0x0 0xff150000 0x0 0x1000>;
 602                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 603                 clock-names = "i2c", "pclk";
 604                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2c6_xfer>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         i2c7: i2c@ff160000 {
 613                 compatible = "rockchip,rk3399-i2c";
 614                 reg = <0x0 0xff160000 0x0 0x1000>;
 615                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 616                 clock-names = "i2c", "pclk";
 617                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&i2c7_xfer>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 status = "disabled";
 623         };
 624
 625         uart0: serial@ff180000 {
 626                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 627                 reg = <0x0 0xff180000 0x0 0x100>;
 628                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 635                 status = "disabled";
 636         };
 637
 638         uart1: serial@ff190000 {
 639                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 640                 reg = <0x0 0xff190000 0x0 0x100>;
 641                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 642                 clock-names = "baudclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 644                 reg-shift = <2>;
 645                 reg-io-width = <4>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&uart1_xfer>;
 648                 status = "disabled";
 649         };
 650
 651         uart2: serial@ff1a0000 {
 652                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 653                 reg = <0x0 0xff1a0000 0x0 0x100>;
 654                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 655                 clock-names = "baudclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 657                 reg-shift = <2>;
 658                 reg-io-width = <4>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&uart2c_xfer>;
 661                 status = "disabled";
 662         };
 663
 664         uart3: serial@ff1b0000 {
 665                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 666                 reg = <0x0 0xff1b0000 0x0 0x100>;
 667                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 668                 clock-names = "baudclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 670                 reg-shift = <2>;
 671                 reg-io-width = <4>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 674                 status = "disabled";
 675         };
 676
 677         spi0: spi@ff1c0000 {
 678                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 679                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 680                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 681                 clock-names = "spiclk", "apb_pclk";
 682                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 status = "disabled";
 688         };
 689
 690         spi1: spi@ff1d0000 {
 691                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 692                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 693                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 694                 clock-names = "spiclk", "apb_pclk";
 695                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 status = "disabled";
 701         };
 702
 703         spi2: spi@ff1e0000 {
 704                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 705                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 706                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 707                 clock-names = "spiclk", "apb_pclk";
 708                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 status = "disabled";
 714         };
 715
 716         spi4: spi@ff1f0000 {
 717                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 718                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 719                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 720                 clock-names = "spiclk", "apb_pclk";
 721                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 724                 #address-cells = <1>;
 725                 #size-cells = <0>;
 726                 status = "disabled";
 727         };
 728
 729         spi5: spi@ff200000 {
 730                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 731                 reg = <0x0 0xff200000 0x0 0x1000>;
 732                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 733                 clock-names = "spiclk", "apb_pclk";
 734                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 737                 #address-cells = <1>;
 738                 #size-cells = <0>;
 739                 status = "disabled";
 740         };
 741
 742         thermal-zones {
 743                 soc_thermal: soc-thermal {
 744                         polling-delay-passive = <20>; /* milliseconds */
 745                         polling-delay = <1000>; /* milliseconds */
 746                         sustainable-power = <1000>; /* milliwatts */
 747
 748                         thermal-sensors = <&tsadc 0>;
 749
 750                         trips {
 751                                 threshold: trip-point@0 {
 752                                         temperature = <70000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 target: trip-point@1 {
 757                                         temperature = <85000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "passive";
 760                                 };
 761                                 soc_crit: soc-crit {
 762                                         temperature = <95000>; /* millicelsius */
 763                                         hysteresis = <2000>; /* millicelsius */
 764                                         type = "critical";
 765                                 };
 766                         };
 767
 768                         cooling-maps {
 769                                 map0 {
 770                                         trip = <&target>;
 771                                         cooling-device =
 772                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 773                                         contribution = <4096>;
 774                                 };
 775                                 map1 {
 776                                         trip = <&target>;
 777                                         cooling-device =
 778                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 779                                         contribution = <1024>;
 780                                 };
 781                                 map2 {
 782                                         trip = <&target>;
 783                                         cooling-device =
 784                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 785                                         contribution = <4096>;
 786                                 };
 787                         };
 788                 };
 789
 790                 gpu_thermal: gpu-thermal {
 791                         polling-delay-passive = <100>; /* milliseconds */
 792                         polling-delay = <1000>; /* milliseconds */
 793
 794                         thermal-sensors = <&tsadc 1>;
 795                 };
 796         };
 797
 798         tsadc: tsadc@ff260000 {
 799                 compatible = "rockchip,rk3399-tsadc";
 800                 reg = <0x0 0xff260000 0x0 0x100>;
 801                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 802                 rockchip,grf = <&grf>;
 803                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 804                 clock-names = "tsadc", "apb_pclk";
 805                 assigned-clocks = <&cru SCLK_TSADC>;
 806                 assigned-clock-rates = <750000>;
 807                 resets = <&cru SRST_TSADC>;
 808                 reset-names = "tsadc-apb";
 809                 pinctrl-names = "init", "default", "sleep";
 810                 pinctrl-0 = <&otp_gpio>;
 811                 pinctrl-1 = <&otp_out>;
 812                 pinctrl-2 = <&otp_gpio>;
 813                 #thermal-sensor-cells = <1>;
 814                 rockchip,hw-tshut-temp = <95000>;
 815                 status = "disabled";
 816         };
 817
 818         qos_emmc: qos@ffa58000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa58000 0x0 0x20>;
 821         };
 822
 823         qos_gmac: qos@ffa5c000 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa5c000 0x0 0x20>;
 826         };
 827
 828         qos_pcie: qos@ffa60080 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa60080 0x0 0x20>;
 831         };
 832
 833         qos_usb_host0: qos@ffa60100 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa60100 0x0 0x20>;
 836         };
 837
 838         qos_usb_host1: qos@ffa60180 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa60180 0x0 0x20>;
 841         };
 842
 843         qos_usb_otg0: qos@ffa70000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa70000 0x0 0x20>;
 846         };
 847
 848         qos_usb_otg1: qos@ffa70080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa70080 0x0 0x20>;
 851         };
 852
 853         qos_sd: qos@ffa74000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa74000 0x0 0x20>;
 856         };
 857
 858         qos_sdioaudio: qos@ffa76000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa76000 0x0 0x20>;
 861         };
 862
 863         qos_hdcp: qos@ffa90000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa90000 0x0 0x20>;
 866         };
 867
 868         qos_iep: qos@ffa98000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa98000 0x0 0x20>;
 871         };
 872
 873         qos_isp0_m0: qos@ffaa0000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffaa0000 0x0 0x20>;
 876         };
 877
 878         qos_isp0_m1: qos@ffaa0080 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffaa0080 0x0 0x20>;
 881         };
 882
 883         qos_isp1_m0: qos@ffaa8000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffaa8000 0x0 0x20>;
 886         };
 887
 888         qos_isp1_m1: qos@ffaa8080 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffaa8080 0x0 0x20>;
 891         };
 892
 893         qos_rga_r: qos@ffab0000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffab0000 0x0 0x20>;
 896         };
 897
 898         qos_rga_w: qos@ffab0080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffab0080 0x0 0x20>;
 901         };
 902
 903         qos_video_m0: qos@ffab8000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffab8000 0x0 0x20>;
 906         };
 907
 908         qos_video_m1_r: qos@ffac0000 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffac0000 0x0 0x20>;
 911         };
 912
 913         qos_video_m1_w: qos@ffac0080 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffac0080 0x0 0x20>;
 916         };
 917
 918         qos_vop_big_r: qos@ffac8000 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffac8000 0x0 0x20>;
 921         };
 922
 923         qos_vop_big_w: qos@ffac8080 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffac8080 0x0 0x20>;
 926         };
 927
 928         qos_vop_little: qos@ffad0000 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad0000 0x0 0x20>;
 931         };
 932
 933         qos_perihp: qos@ffad8080 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffad8080 0x0 0x20>;
 936         };
 937
 938         qos_gpu: qos@ffae0000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffae0000 0x0 0x20>;
 941         };
 942
 943         pmu: power-management@ff310000 {
 944                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 945                 reg = <0x0 0xff310000 0x0 0x1000>;
 946
 947                 /*
 948                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 949                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 950                  * Some of the power domains are grouped together for every
 951                  * voltage domain.
 952                  * The detail contents as below.
 953                  */
 954                 power: power-controller {
 955                         compatible = "rockchip,rk3399-power-controller";
 956                         #power-domain-cells = <1>;
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959
 960                         /* These power domains are grouped by VD_CENTER */
 961                         pd_iep@RK3399_PD_IEP {
 962                                 reg = <RK3399_PD_IEP>;
 963                                 clocks = <&cru ACLK_IEP>,
 964                                          <&cru HCLK_IEP>;
 965                                 pm_qos = <&qos_iep>;
 966                         };
 967                         pd_rga@RK3399_PD_RGA {
 968                                 reg = <RK3399_PD_RGA>;
 969                                 clocks = <&cru ACLK_RGA>,
 970                                          <&cru HCLK_RGA>;
 971                                 pm_qos = <&qos_rga_r>,
 972                                          <&qos_rga_w>;
 973                         };
 974                         pd_vcodec@RK3399_PD_VCODEC {
 975                                 reg = <RK3399_PD_VCODEC>;
 976                                 clocks = <&cru ACLK_VCODEC>,
 977                                          <&cru HCLK_VCODEC>;
 978                                 pm_qos = <&qos_video_m0>;
 979                         };
 980                         pd_vdu@RK3399_PD_VDU {
 981                                 reg = <RK3399_PD_VDU>;
 982                                 clocks = <&cru ACLK_VDU>,
 983                                          <&cru HCLK_VDU>;
 984                                 pm_qos = <&qos_video_m1_r>,
 985                                          <&qos_video_m1_w>;
 986                         };
 987
 988                         /* These power domains are grouped by VD_GPU */
 989                         pd_gpu@RK3399_PD_GPU {
 990                                 reg = <RK3399_PD_GPU>;
 991                                 clocks = <&cru ACLK_GPU>;
 992                                 pm_qos = <&qos_gpu>;
 993                         };
 994
 995                         /* These power domains are grouped by VD_LOGIC */
 996                         pd_emmc@RK3399_PD_EMMC {
 997                                 reg = <RK3399_PD_EMMC>;
 998                                 clocks = <&cru ACLK_EMMC>;
 999                                 pm_qos = <&qos_emmc>;
1000                         };
1001                         pd_gmac@RK3399_PD_GMAC {
1002                                 reg = <RK3399_PD_GMAC>;
1003                                 clocks = <&cru ACLK_GMAC>;
1004                                 pm_qos = <&qos_gmac>;
1005                         };
1006                         pd_perihp@RK3399_PD_PERIHP {
1007                                 reg = <RK3399_PD_PERIHP>;
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 clocks = <&cru ACLK_PERIHP>;
1011                                 pm_qos = <&qos_perihp>,
1012                                          <&qos_pcie>,
1013                                          <&qos_usb_host0>,
1014                                          <&qos_usb_host1>;
1015
1016                                 pd_sd@RK3399_PD_SD {
1017                                         reg = <RK3399_PD_SD>;
1018                                         clocks = <&cru HCLK_SDMMC>,
1019                                                  <&cru SCLK_SDMMC>;
1020                                         pm_qos = <&qos_sd>;
1021                                 };
1022                         };
1023                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1024                                 reg = <RK3399_PD_SDIOAUDIO>;
1025                                 clocks = <&cru HCLK_SDIO>;
1026                                 pm_qos = <&qos_sdioaudio>;
1027                         };
1028                         pd_usb3@RK3399_PD_USB3 {
1029                                 reg = <RK3399_PD_USB3>;
1030                                 clocks = <&cru ACLK_USB3>;
1031                                 pm_qos = <&qos_usb_otg0>,
1032                                          <&qos_usb_otg1>;
1033                         };
1034                         pd_vio@RK3399_PD_VIO {
1035                                 reg = <RK3399_PD_VIO>;
1036                                 #address-cells = <1>;
1037                                 #size-cells = <0>;
1038
1039                                 pd_hdcp@RK3399_PD_HDCP {
1040                                         reg = <RK3399_PD_HDCP>;
1041                                         clocks = <&cru ACLK_HDCP>,
1042                                                  <&cru HCLK_HDCP>,
1043                                                  <&cru PCLK_HDCP>;
1044                                         pm_qos = <&qos_hdcp>;
1045                                 };
1046                                 pd_isp0@RK3399_PD_ISP0 {
1047                                         reg = <RK3399_PD_ISP0>;
1048                                         clocks = <&cru ACLK_ISP0>,
1049                                                  <&cru HCLK_ISP0>;
1050                                         pm_qos = <&qos_isp0_m0>,
1051                                                  <&qos_isp0_m1>;
1052                                 };
1053                                 pd_isp1@RK3399_PD_ISP1 {
1054                                         reg = <RK3399_PD_ISP1>;
1055                                         clocks = <&cru ACLK_ISP1>,
1056                                                  <&cru HCLK_ISP1>;
1057                                         pm_qos = <&qos_isp1_m0>,
1058                                                  <&qos_isp1_m1>;
1059                                 };
1060                                 pd_vo@RK3399_PD_VO {
1061                                         reg = <RK3399_PD_VO>;
1062                                         #address-cells = <1>;
1063                                         #size-cells = <0>;
1064
1065                                         pd_vopb@RK3399_PD_VOPB {
1066                                                 reg = <RK3399_PD_VOPB>;
1067                                                 clocks = <&cru ACLK_VOP0>,
1068                                                          <&cru HCLK_VOP0>;
1069                                                 pm_qos = <&qos_vop_big_r>,
1070                                                          <&qos_vop_big_w>;
1071                                         };
1072                                         pd_vopl@RK3399_PD_VOPL {
1073                                                 reg = <RK3399_PD_VOPL>;
1074                                                 clocks = <&cru ACLK_VOP1>,
1075                                                          <&cru HCLK_VOP1>;
1076                                                 pm_qos = <&qos_vop_little>;
1077                                         };
1078                                 };
1079                         };
1080                 };
1081         };
1082
1083         pmugrf: syscon@ff320000 {
1084                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1085                 reg = <0x0 0xff320000 0x0 0x1000>;
1086
1087                 reboot-mode {
1088                         compatible = "syscon-reboot-mode";
1089                         offset = <0x300>;
1090                         mode-bootloader = <BOOT_LOADER>;
1091                         mode-charge = <BOOT_CHARGING>;
1092                         mode-fastboot = <BOOT_FASTBOOT>;
1093                         mode-loader = <BOOT_LOADER>;
1094                         mode-normal = <BOOT_NORMAL>;
1095                         mode-recovery = <BOOT_RECOVERY>;
1096                         mode-ums = <BOOT_UMS>;
1097                 };
1098         };
1099
1100         spi3: spi@ff350000 {
1101                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1102                 reg = <0x0 0xff350000 0x0 0x1000>;
1103                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1104                 clock-names = "spiclk", "apb_pclk";
1105                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1106                 pinctrl-names = "default";
1107                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1108                 #address-cells = <1>;
1109                 #size-cells = <0>;
1110                 status = "disabled";
1111         };
1112
1113         uart4: serial@ff370000 {
1114                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1115                 reg = <0x0 0xff370000 0x0 0x100>;
1116                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1117                 clock-names = "baudclk", "apb_pclk";
1118                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1119                 reg-shift = <2>;
1120                 reg-io-width = <4>;
1121                 pinctrl-names = "default";
1122                 pinctrl-0 = <&uart4_xfer>;
1123                 status = "disabled";
1124         };
1125
1126         i2c4: i2c@ff3d0000 {
1127                 compatible = "rockchip,rk3399-i2c";
1128                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1129                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1130                 clock-names = "i2c", "pclk";
1131                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1132                 pinctrl-names = "default";
1133                 pinctrl-0 = <&i2c4_xfer>;
1134                 #address-cells = <1>;
1135                 #size-cells = <0>;
1136                 status = "disabled";
1137         };
1138
1139         i2c8: i2c@ff3e0000 {
1140                 compatible = "rockchip,rk3399-i2c";
1141                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1142                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1143                 clock-names = "i2c", "pclk";
1144                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1145                 pinctrl-names = "default";
1146                 pinctrl-0 = <&i2c8_xfer>;
1147                 #address-cells = <1>;
1148                 #size-cells = <0>;
1149                 status = "disabled";
1150         };
1151
1152         pcie_phy: phy@e220 {
1153                 compatible = "rockchip,rk3399-pcie-phy";
1154                 #phy-cells = <0>;
1155                 rockchip,grf = <&grf>;
1156                 clocks = <&cru SCLK_PCIEPHY_REF>;
1157                 clock-names = "refclk";
1158                 resets = <&cru SRST_PCIEPHY>;
1159                 reset-names = "phy";
1160                 status = "disabled";
1161         };
1162
1163         pcie0: pcie@f8000000 {
1164                 compatible = "rockchip,rk3399-pcie";
1165                 #address-cells = <3>;
1166                 #size-cells = <2>;
1167                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1168                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1169                 clock-names = "aclk", "aclk-perf",
1170                               "hclk", "pm";
1171                 bus-range = <0x0 0x1>;
1172                 msi-map = <0x0 &its 0x0 0x1000>;
1173                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1174                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1175                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1176                 interrupt-names = "sys", "legacy", "client";
1177                 #interrupt-cells = <1>;
1178                 interrupt-map-mask = <0 0 0 7>;
1179                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1180                                 <0 0 0 2 &pcie0_intc 1>,
1181                                 <0 0 0 3 &pcie0_intc 2>,
1182                                 <0 0 0 4 &pcie0_intc 3>;
1183                 phys = <&pcie_phy>;
1184                 phy-names = "pcie-phy";
1185                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1186                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1187                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1188                       <0x0 0xfd000000 0x0 0x1000000>;
1189                 reg-names = "axi-base", "apb-base";
1190                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1191                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1192                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1193                 status = "disabled";
1194                 pcie0_intc: interrupt-controller {
1195                         interrupt-controller;
1196                         #address-cells = <0>;
1197                         #interrupt-cells = <1>;
1198                 };
1199         };
1200
1201         pwm0: pwm@ff420000 {
1202                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1203                 reg = <0x0 0xff420000 0x0 0x10>;
1204                 #pwm-cells = <3>;
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&pwm0_pin>;
1207                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1208                 clock-names = "pwm";
1209                 status = "disabled";
1210         };
1211
1212         pwm1: pwm@ff420010 {
1213                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1214                 reg = <0x0 0xff420010 0x0 0x10>;
1215                 #pwm-cells = <3>;
1216                 pinctrl-names = "default";
1217                 pinctrl-0 = <&pwm1_pin>;
1218                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1219                 clock-names = "pwm";
1220                 status = "disabled";
1221         };
1222
1223         pwm2: pwm@ff420020 {
1224                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1225                 reg = <0x0 0xff420020 0x0 0x10>;
1226                 #pwm-cells = <3>;
1227                 pinctrl-names = "default";
1228                 pinctrl-0 = <&pwm2_pin>;
1229                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1230                 clock-names = "pwm";
1231                 status = "disabled";
1232         };
1233
1234         pwm3: pwm@ff420030 {
1235                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1236                 reg = <0x0 0xff420030 0x0 0x10>;
1237                 #pwm-cells = <3>;
1238                 pinctrl-names = "default";
1239                 pinctrl-0 = <&pwm3a_pin>;
1240                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1241                 clock-names = "pwm";
1242                 status = "disabled";
1243         };
1244
1245         dfi: dfi@ff630000 {
1246                 reg = <0x00 0xff630000 0x00 0x4000>;
1247                 compatible = "rockchip,rk3399-dfi";
1248                 rockchip,pmu = <&pmugrf>;
1249                 clocks = <&cru PCLK_DDR_MON>;
1250                 clock-names = "pclk_ddr_mon";
1251                 status = "disabled";
1252         };
1253
1254         dmc: dmc {
1255                 compatible = "rockchip,rk3399-dmc";
1256                 devfreq-events = <&dfi>;
1257                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1258                 clocks = <&cru SCLK_DDRCLK>;
1259                 clock-names = "dmc_clk";
1260                 ddr_timing = <&ddr_timing>;
1261                 operating-points-v2 = <&dmc_opp_table>;
1262                 status = "disabled";
1263         };
1264
1265         dmc_opp_table: dmc_opp_table {
1266                 compatible = "operating-points-v2";
1267
1268                 opp00 {
1269                         opp-hz = /bits/ 64 <666000000>;
1270                         opp-microvolt = <900000>;
1271                 };
1272         };
1273
1274         rga: rga@ff680000 {
1275                 compatible = "rockchip,rk3399-rga";
1276                 reg = <0x0 0xff680000 0x0 0x10000>;
1277                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1278                 interrupt-names = "rga";
1279                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1280                 clock-names = "aclk", "hclk", "sclk";
1281                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1282                 reset-names = "core", "axi", "ahb";
1283                 power-domains = <&power RK3399_PD_RGA>;
1284                 status = "disabled";
1285         };
1286
1287         efuse0: efuse@ff690000 {
1288                 compatible = "rockchip,rk3399-efuse";
1289                 reg = <0x0 0xff690000 0x0 0x80>;
1290                 #address-cells = <1>;
1291                 #size-cells = <1>;
1292                 clocks = <&cru PCLK_EFUSE1024NS>;
1293                 clock-names = "pclk_efuse";
1294
1295                 /* Data cells */
1296                 cpul_leakage: cpul-leakage {
1297                         reg = <0x1a 0x1>;
1298                 };
1299                 cpub_leakage: cpub-leakage {
1300                         reg = <0x17 0x1>;
1301                 };
1302                 gpu_leakage: gpu-leakage {
1303                         reg = <0x18 0x1>;
1304                 };
1305                 center_leakage: center-leakage {
1306                         reg = <0x19 0x1>;
1307                 };
1308                 logic_leakage: logic-leakage {
1309                         reg = <0x1b 0x1>;
1310                 };
1311                 wafer_info: wafer-info {
1312                         reg = <0x1c 0x1>;
1313                 };
1314         };
1315
1316         pmucru: pmu-clock-controller@ff750000 {
1317                 compatible = "rockchip,rk3399-pmucru";
1318                 reg = <0x0 0xff750000 0x0 0x1000>;
1319                 #clock-cells = <1>;
1320                 #reset-cells = <1>;
1321                 assigned-clocks = <&pmucru PLL_PPLL>;
1322                 assigned-clock-rates = <676000000>;
1323         };
1324
1325         cru: clock-controller@ff760000 {
1326                 compatible = "rockchip,rk3399-cru";
1327                 reg = <0x0 0xff760000 0x0 0x1000>;
1328                 #clock-cells = <1>;
1329                 #reset-cells = <1>;
1330                 assigned-clocks =
1331                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1332                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1333                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1334                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1335                         <&cru PLL_NPLL>,
1336                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1337                         <&cru PCLK_PERIHP>,
1338                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1339                         <&cru PCLK_PERILP0>,
1340                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1341                 assigned-clock-rates =
1342                          <400000000>,  <200000000>,
1343                          <400000000>,  <200000000>,
1344                          <816000000>, <816000000>,
1345                          <594000000>,  <800000000>,
1346                         <1000000000>,
1347                          <150000000>,   <75000000>,
1348                           <37500000>,
1349                          <100000000>,  <100000000>,
1350                           <50000000>,
1351                          <100000000>,   <50000000>;
1352         };
1353
1354         grf: syscon@ff770000 {
1355                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1356                 reg = <0x0 0xff770000 0x0 0x10000>;
1357                 #address-cells = <1>;
1358                 #size-cells = <1>;
1359
1360                 u2phy0: usb2-phy@e450 {
1361                         compatible = "rockchip,rk3399-usb2phy";
1362                         reg = <0xe450 0x10>;
1363                         clocks = <&cru SCLK_USB2PHY0_REF>;
1364                         clock-names = "phyclk";
1365                         #clock-cells = <0>;
1366                         clock-output-names = "clk_usbphy0_480m";
1367                         status = "disabled";
1368
1369                         u2phy0_otg: otg-port {
1370                                 #phy-cells = <0>;
1371                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1372                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1373                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1374                                 interrupt-names = "otg-bvalid", "otg-id",
1375                                                   "linestate";
1376                                 status = "disabled";
1377                         };
1378
1379                         u2phy0_host: host-port {
1380                                 #phy-cells = <0>;
1381                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1382                                 interrupt-names = "linestate";
1383                                 status = "disabled";
1384                         };
1385                 };
1386
1387                 u2phy1: usb2-phy@e460 {
1388                         compatible = "rockchip,rk3399-usb2phy";
1389                         reg = <0xe460 0x10>;
1390                         clocks = <&cru SCLK_USB2PHY1_REF>;
1391                         clock-names = "phyclk";
1392                         #clock-cells = <0>;
1393                         clock-output-names = "clk_usbphy1_480m";
1394                         status = "disabled";
1395
1396                         u2phy1_otg: otg-port {
1397                                 #phy-cells = <0>;
1398                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1399                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1400                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1401                                 interrupt-names = "otg-bvalid", "otg-id",
1402                                                   "linestate";
1403                                 status = "disabled";
1404                         };
1405
1406                         u2phy1_host: host-port {
1407                                 #phy-cells = <0>;
1408                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1409                                 interrupt-names = "linestate";
1410                                 status = "disabled";
1411                         };
1412                 };
1413         };
1414
1415         tcphy0: phy@ff7c0000 {
1416                 compatible = "rockchip,rk3399-typec-phy";
1417                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1418                 rockchip,grf = <&grf>;
1419                 #phy-cells = <1>;
1420                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1421                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1422                 clock-names = "tcpdcore", "tcpdphy-ref";
1423                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1424                 assigned-clock-rates = <50000000>;
1425                 resets = <&cru SRST_UPHY0>,
1426                          <&cru SRST_UPHY0_PIPE_L00>,
1427                          <&cru SRST_P_UPHY0_TCPHY>;
1428                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1429                 rockchip,typec-conn-dir = <0xe580 0 16>;
1430                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1431                 rockchip,external-psm = <0xe588 14 30>;
1432                 rockchip,pipe-status = <0xe5c0 0 0>;
1433                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1434                 status = "disabled";
1435         };
1436
1437         tcphy1: phy@ff800000 {
1438                 compatible = "rockchip,rk3399-typec-phy";
1439                 reg = <0x0 0xff800000 0x0 0x40000>;
1440                 rockchip,grf = <&grf>;
1441                 #phy-cells = <1>;
1442                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1443                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1444                 clock-names = "tcpdcore", "tcpdphy-ref";
1445                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1446                 assigned-clock-rates = <50000000>;
1447                 resets = <&cru SRST_UPHY1>,
1448                          <&cru SRST_UPHY1_PIPE_L00>,
1449                          <&cru SRST_P_UPHY1_TCPHY>;
1450                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1451                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1452                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1453                 rockchip,external-psm = <0xe594 14 30>;
1454                 rockchip,pipe-status = <0xe5c0 16 16>;
1455                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1456                 status = "disabled";
1457         };
1458
1459         watchdog@ff848000 {
1460                 compatible = "snps,dw-wdt";
1461                 reg = <0x0 0xff848000 0x0 0x100>;
1462                 clocks = <&cru PCLK_WDT>;
1463                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1464         };
1465
1466         rktimer: rktimer@ff850000 {
1467                 compatible = "rockchip,rk3399-timer";
1468                 reg = <0x0 0xff850000 0x0 0x1000>;
1469                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1470                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1471                 clock-names = "pclk", "timer";
1472         };
1473
1474         spdif: spdif@ff870000 {
1475                 compatible = "rockchip,rk3399-spdif";
1476                 reg = <0x0 0xff870000 0x0 0x1000>;
1477                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1478                 dmas = <&dmac_bus 7>;
1479                 dma-names = "tx";
1480                 clock-names = "mclk", "hclk";
1481                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1482                 pinctrl-names = "default";
1483                 pinctrl-0 = <&spdif_bus>;
1484                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1485                 status = "disabled";
1486         };
1487
1488         i2s0: i2s@ff880000 {
1489                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1490                 reg = <0x0 0xff880000 0x0 0x1000>;
1491                 rockchip,grf = <&grf>;
1492                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1493                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1494                 dma-names = "tx", "rx";
1495                 clock-names = "i2s_clk", "i2s_hclk";
1496                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1497                 pinctrl-names = "default";
1498                 pinctrl-0 = <&i2s0_8ch_bus>;
1499                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1500                 status = "disabled";
1501         };
1502
1503         i2s1: i2s@ff890000 {
1504                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1505                 reg = <0x0 0xff890000 0x0 0x1000>;
1506                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1507                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1508                 dma-names = "tx", "rx";
1509                 clock-names = "i2s_clk", "i2s_hclk";
1510                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1511                 pinctrl-names = "default";
1512                 pinctrl-0 = <&i2s1_2ch_bus>;
1513                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1514                 status = "disabled";
1515         };
1516
1517         i2s2: i2s@ff8a0000 {
1518                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1519                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1520                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1521                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1522                 dma-names = "tx", "rx";
1523                 clock-names = "i2s_clk", "i2s_hclk";
1524                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1525                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1526                 status = "disabled";
1527         };
1528
1529         gpu: gpu@ff9a0000 {
1530                 compatible = "arm,malit860",
1531                              "arm,malit86x",
1532                              "arm,malit8xx",
1533                              "arm,mali-midgard";
1534
1535                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1536
1537                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1538                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1539                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1540                 interrupt-names = "GPU", "JOB", "MMU";
1541
1542                 clocks = <&cru ACLK_GPU>;
1543                 clock-names = "clk_mali";
1544                 #cooling-cells = <2>; /* min followed by max */
1545                 operating-points-v2 = <&gpu_opp_table>;
1546                 power-domains = <&power RK3399_PD_GPU>;
1547                 power-off-delay-ms = <200>;
1548                 status = "disabled";
1549
1550                 gpu_power_model: power_model {
1551                         compatible = "arm,mali-simple-power-model";
1552                         voltage = <900>;
1553                         frequency = <500>;
1554                         static-power = <300>;
1555                         dynamic-power = <396>;
1556                         ts = <32000 4700 (-80) 2>;
1557                         thermal-zone = "gpu-thermal";
1558                 };
1559         };
1560
1561         gpu_opp_table: gpu_opp_table {
1562                 compatible = "operating-points-v2";
1563                 opp-shared;
1564
1565                 opp@200000000 {
1566                         opp-hz = /bits/ 64 <200000000>;
1567                         opp-microvolt = <900000>;
1568                 };
1569                 opp@300000000 {
1570                         opp-hz = /bits/ 64 <300000000>;
1571                         opp-microvolt = <900000>;
1572                 };
1573                 opp@400000000 {
1574                         opp-hz = /bits/ 64 <400000000>;
1575                         opp-microvolt = <900000>;
1576                 };
1577
1578         };
1579
1580         vopl: vop@ff8f0000 {
1581                 compatible = "rockchip,rk3399-vop-lit";
1582                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1583                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1584                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1585                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1586                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1587                 reset-names = "axi", "ahb", "dclk";
1588                 power-domains = <&power RK3399_PD_VOPL>;
1589                 iommus = <&vopl_mmu>;
1590                 status = "disabled";
1591
1592                 vopl_out: port {
1593                         #address-cells = <1>;
1594                         #size-cells = <0>;
1595
1596                         vopl_out_mipi: endpoint@0 {
1597                                 reg = <0>;
1598                                 remote-endpoint = <&mipi_in_vopl>;
1599                         };
1600
1601                         vopl_out_edp: endpoint@1 {
1602                                 reg = <1>;
1603                                 remote-endpoint = <&edp_in_vopl>;
1604                         };
1605
1606                         vopl_out_hdmi: endpoint@2 {
1607                                 reg = <2>;
1608                                 remote-endpoint = <&hdmi_in_vopl>;
1609                         };
1610                 };
1611         };
1612
1613         vop1_pwm: voppwm@ff8f01a0 {
1614                 compatible = "rockchip,vop-pwm";
1615                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1616                 #pwm-cells = <3>;
1617                 pinctrl-names = "default";
1618                 pinctrl-0 = <&vop1_pwm_pin>;
1619                 clocks = <&cru SCLK_VOP1_PWM>;
1620                 clock-names = "pwm";
1621                 status = "disabled";
1622         };
1623
1624         vopl_mmu: iommu@ff8f3f00 {
1625                 compatible = "rockchip,iommu";
1626                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1627                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1628                 interrupt-names = "vopl_mmu";
1629                 #iommu-cells = <0>;
1630                 status = "disabled";
1631         };
1632
1633         vopb: vop@ff900000 {
1634                 compatible = "rockchip,rk3399-vop-big";
1635                 reg = <0x0 0xff900000 0x0 0x3efc>;
1636                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1637                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1638                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1639                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1640                 reset-names = "axi", "ahb", "dclk";
1641                 power-domains = <&power RK3399_PD_VOPB>;
1642                 iommus = <&vopb_mmu>;
1643                 status = "disabled";
1644
1645                 vopb_out: port {
1646                         #address-cells = <1>;
1647                         #size-cells = <0>;
1648
1649                         vopb_out_edp: endpoint@0 {
1650                                 reg = <0>;
1651                                 remote-endpoint = <&edp_in_vopb>;
1652                         };
1653
1654                         vopb_out_mipi: endpoint@1 {
1655                                 reg = <1>;
1656                                 remote-endpoint = <&mipi_in_vopb>;
1657                         };
1658
1659                         vopb_out_hdmi: endpoint@2 {
1660                                 reg = <2>;
1661                                 remote-endpoint = <&hdmi_in_vopb>;
1662                         };
1663                 };
1664         };
1665
1666         vop0_pwm: voppwm@ff9001a0 {
1667                 compatible = "rockchip,vop-pwm";
1668                 reg = <0x0 0xff9001a0 0x0 0x10>;
1669                 #pwm-cells = <3>;
1670                 pinctrl-names = "default";
1671                 pinctrl-0 = <&vop0_pwm_pin>;
1672                 clocks = <&cru SCLK_VOP0_PWM>;
1673                 clock-names = "pwm";
1674                 status = "disabled";
1675         };
1676
1677         vopb_mmu: iommu@ff903f00 {
1678                 compatible = "rockchip,iommu";
1679                 reg = <0x0 0xff903f00 0x0 0x100>;
1680                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1681                 interrupt-names = "vopb_mmu";
1682                 #iommu-cells = <0>;
1683                 status = "disabled";
1684         };
1685
1686         hdmi: hdmi@ff940000 {
1687                 compatible = "rockchip,rk3399-dw-hdmi";
1688                 reg = <0x0 0xff940000 0x0 0x20000>;
1689                 reg-io-width = <4>;
1690                 rockchip,grf = <&grf>;
1691                 power-domains = <&power RK3399_PD_HDCP>;
1692                 pinctrl-names = "default";
1693                 pinctrl-0 = <&hdmi_i2c_xfer>;
1694                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1695                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1696                 clock-names = "iahb", "isfr", "vpll", "grf";
1697                 status = "disabled";
1698
1699                 ports {
1700                         hdmi_in: port {
1701                                 #address-cells = <1>;
1702                                 #size-cells = <0>;
1703                                 hdmi_in_vopb: endpoint@0 {
1704                                         reg = <0>;
1705                                         remote-endpoint = <&vopb_out_hdmi>;
1706                                 };
1707                                 hdmi_in_vopl: endpoint@1 {
1708                                         reg = <1>;
1709                                         remote-endpoint = <&vopl_out_hdmi>;
1710                                 };
1711                         };
1712                 };
1713         };
1714
1715         mipi_dsi: mipi@ff960000 {
1716                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1717                 reg = <0x0 0xff960000 0x0 0x8000>;
1718                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1719                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1720                          <&cru SCLK_DPHY_TX0_CFG>;
1721                 clock-names = "ref", "pclk", "phy_cfg";
1722                 power-domains = <&power RK3399_PD_VIO>;
1723                 rockchip,grf = <&grf>;
1724                 #address-cells = <1>;
1725                 #size-cells = <0>;
1726                 status = "disabled";
1727
1728                 ports {
1729                         #address-cells = <1>;
1730                         #size-cells = <0>;
1731                         reg = <1>;
1732
1733                         mipi_in: port {
1734                                 #address-cells = <1>;
1735                                 #size-cells = <0>;
1736
1737                                 mipi_in_vopb: endpoint@0 {
1738                                         reg = <0>;
1739                                         remote-endpoint = <&vopb_out_mipi>;
1740                                 };
1741                                 mipi_in_vopl: endpoint@1 {
1742                                         reg = <1>;
1743                                         remote-endpoint = <&vopl_out_mipi>;
1744                                 };
1745                         };
1746                 };
1747         };
1748
1749         edp: edp@ff970000 {
1750                 compatible = "rockchip,rk3399-edp";
1751                 reg = <0x0 0xff970000 0x0 0x8000>;
1752                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1753                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1754                 clock-names = "dp", "pclk";
1755                 resets = <&cru SRST_P_EDP_CTRL>;
1756                 reset-names = "dp";
1757                 rockchip,grf = <&grf>;
1758                 status = "disabled";
1759                 pinctrl-names = "default";
1760                 pinctrl-0 = <&edp_hpd>;
1761
1762                 ports {
1763                         #address-cells = <1>;
1764                         #size-cells = <0>;
1765
1766                         edp_in: port@0 {
1767                                 reg = <0>;
1768                                 #address-cells = <1>;
1769                                 #size-cells = <0>;
1770
1771                                 edp_in_vopb: endpoint@0 {
1772                                         reg = <0>;
1773                                         remote-endpoint = <&vopb_out_edp>;
1774                                 };
1775
1776                                 edp_in_vopl: endpoint@1 {
1777                                         reg = <1>;
1778                                         remote-endpoint = <&vopl_out_edp>;
1779                                 };
1780                         };
1781                 };
1782         };
1783
1784         display_subsystem: display-subsystem {
1785                 compatible = "rockchip,display-subsystem";
1786                 ports = <&vopl_out>, <&vopb_out>;
1787                 status = "disabled";
1788         };
1789
1790         pinctrl: pinctrl {
1791                 compatible = "rockchip,rk3399-pinctrl";
1792                 rockchip,grf = <&grf>;
1793                 rockchip,pmu = <&pmugrf>;
1794                 #address-cells = <0x2>;
1795                 #size-cells = <0x2>;
1796                 ranges;
1797
1798                 gpio0: gpio0@ff720000 {
1799                         compatible = "rockchip,gpio-bank";
1800                         reg = <0x0 0xff720000 0x0 0x100>;
1801                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1802                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1803
1804                         gpio-controller;
1805                         #gpio-cells = <0x2>;
1806
1807                         interrupt-controller;
1808                         #interrupt-cells = <0x2>;
1809                 };
1810
1811                 gpio1: gpio1@ff730000 {
1812                         compatible = "rockchip,gpio-bank";
1813                         reg = <0x0 0xff730000 0x0 0x100>;
1814                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1815                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1816
1817                         gpio-controller;
1818                         #gpio-cells = <0x2>;
1819
1820                         interrupt-controller;
1821                         #interrupt-cells = <0x2>;
1822                 };
1823
1824                 gpio2: gpio2@ff780000 {
1825                         compatible = "rockchip,gpio-bank";
1826                         reg = <0x0 0xff780000 0x0 0x100>;
1827                         clocks = <&cru PCLK_GPIO2>;
1828                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1829
1830                         gpio-controller;
1831                         #gpio-cells = <0x2>;
1832
1833                         interrupt-controller;
1834                         #interrupt-cells = <0x2>;
1835                 };
1836
1837                 gpio3: gpio3@ff788000 {
1838                         compatible = "rockchip,gpio-bank";
1839                         reg = <0x0 0xff788000 0x0 0x100>;
1840                         clocks = <&cru PCLK_GPIO3>;
1841                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1842
1843                         gpio-controller;
1844                         #gpio-cells = <0x2>;
1845
1846                         interrupt-controller;
1847                         #interrupt-cells = <0x2>;
1848                 };
1849
1850                 gpio4: gpio4@ff790000 {
1851                         compatible = "rockchip,gpio-bank";
1852                         reg = <0x0 0xff790000 0x0 0x100>;
1853                         clocks = <&cru PCLK_GPIO4>;
1854                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1855
1856                         gpio-controller;
1857                         #gpio-cells = <0x2>;
1858
1859                         interrupt-controller;
1860                         #interrupt-cells = <0x2>;
1861                 };
1862
1863                 pcfg_pull_up: pcfg-pull-up {
1864                         bias-pull-up;
1865                 };
1866
1867                 pcfg_pull_down: pcfg-pull-down {
1868                         bias-pull-down;
1869                 };
1870
1871                 pcfg_pull_none: pcfg-pull-none {
1872                         bias-disable;
1873                 };
1874
1875                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1876                         bias-pull-up;
1877                         drive-strength = <20>;
1878                 };
1879
1880                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1881                         bias-disable;
1882                         drive-strength = <20>;
1883                 };
1884
1885                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1886                         bias-disable;
1887                         drive-strength = <18>;
1888                 };
1889
1890                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1891                         bias-disable;
1892                         drive-strength = <12>;
1893                 };
1894
1895                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1896                         bias-pull-up;
1897                         drive-strength = <8>;
1898                 };
1899
1900                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1901                         bias-pull-down;
1902                         drive-strength = <4>;
1903                 };
1904
1905                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1906                         bias-pull-up;
1907                         drive-strength = <2>;
1908                 };
1909
1910                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1911                         bias-pull-down;
1912                         drive-strength = <12>;
1913                 };
1914
1915                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1916                         bias-disable;
1917                         drive-strength = <13>;
1918                 };
1919
1920                 pcfg_output_high: pcfg-output-high {
1921                         output-high;
1922                 };
1923
1924                 pcfg_output_low: pcfg-output-low {
1925                         output-low;
1926                 };
1927
1928                 pcfg_input: pcfg-input {
1929                         input-enable;
1930                 };
1931
1932                 emmc {
1933                         emmc_pwr: emmc-pwr {
1934                                 rockchip,pins =
1935                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1936                         };
1937                 };
1938
1939                 gmac {
1940                         rgmii_pins: rgmii-pins {
1941                                 rockchip,pins =
1942                                         /* mac_txclk */
1943                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1944                                         /* mac_rxclk */
1945                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1946                                         /* mac_mdio */
1947                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1948                                         /* mac_txen */
1949                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1950                                         /* mac_clk */
1951                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1952                                         /* mac_rxdv */
1953                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1954                                         /* mac_mdc */
1955                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1956                                         /* mac_rxd1 */
1957                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1958                                         /* mac_rxd0 */
1959                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1960                                         /* mac_txd1 */
1961                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1962                                         /* mac_txd0 */
1963                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1964                                         /* mac_rxd3 */
1965                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1966                                         /* mac_rxd2 */
1967                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1968                                         /* mac_txd3 */
1969                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1970                                         /* mac_txd2 */
1971                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1972                         };
1973
1974                         rmii_pins: rmii-pins {
1975                                 rockchip,pins =
1976                                         /* mac_mdio */
1977                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1978                                         /* mac_txen */
1979                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1980                                         /* mac_clk */
1981                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1982                                         /* mac_rxer */
1983                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1984                                         /* mac_rxdv */
1985                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1986                                         /* mac_mdc */
1987                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1988                                         /* mac_rxd1 */
1989                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1990                                         /* mac_rxd0 */
1991                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1992                                         /* mac_txd1 */
1993                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1994                                         /* mac_txd0 */
1995                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1996                         };
1997                 };
1998
1999                 i2c0 {
2000                         i2c0_xfer: i2c0-xfer {
2001                                 rockchip,pins =
2002                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2003                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2004                         };
2005                 };
2006
2007                 i2c1 {
2008                         i2c1_xfer: i2c1-xfer {
2009                                 rockchip,pins =
2010                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2011                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2012                         };
2013                 };
2014
2015                 i2c2 {
2016                         i2c2_xfer: i2c2-xfer {
2017                                 rockchip,pins =
2018                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2019                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2020                         };
2021                 };
2022
2023                 i2c3 {
2024                         i2c3_xfer: i2c3-xfer {
2025                                 rockchip,pins =
2026                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2027                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2028                         };
2029
2030                         i2c3_gpio: i2c3_gpio {
2031                                 rockchip,pins =
2032                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2033                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2034                         };
2035
2036                 };
2037
2038                 i2c4 {
2039                         i2c4_xfer: i2c4-xfer {
2040                                 rockchip,pins =
2041                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2042                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2043                         };
2044                 };
2045
2046                 i2c5 {
2047                         i2c5_xfer: i2c5-xfer {
2048                                 rockchip,pins =
2049                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2050                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2051                         };
2052                 };
2053
2054                 i2c6 {
2055                         i2c6_xfer: i2c6-xfer {
2056                                 rockchip,pins =
2057                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2058                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2059                         };
2060                 };
2061
2062                 i2c7 {
2063                         i2c7_xfer: i2c7-xfer {
2064                                 rockchip,pins =
2065                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2066                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2067                         };
2068                 };
2069
2070                 i2c8 {
2071                         i2c8_xfer: i2c8-xfer {
2072                                 rockchip,pins =
2073                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2074                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2075                         };
2076                 };
2077
2078                 i2s0 {
2079                         i2s0_8ch_bus: i2s0-8ch-bus {
2080                                 rockchip,pins =
2081                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2082                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2083                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2084                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2085                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2086                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2087                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2088                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2089                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2090                         };
2091                 };
2092
2093                 i2s1 {
2094                         i2s1_2ch_bus: i2s1-2ch-bus {
2095                                 rockchip,pins =
2096                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2097                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2098                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2099                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2100                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2101                         };
2102                 };
2103
2104                 sdio0 {
2105                         sdio0_bus1: sdio0-bus1 {
2106                                 rockchip,pins =
2107                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2108                         };
2109
2110                         sdio0_bus4: sdio0-bus4 {
2111                                 rockchip,pins =
2112                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2113                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2114                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2115                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2116                         };
2117
2118                         sdio0_cmd: sdio0-cmd {
2119                                 rockchip,pins =
2120                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2121                         };
2122
2123                         sdio0_clk: sdio0-clk {
2124                                 rockchip,pins =
2125                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2126                         };
2127
2128                         sdio0_cd: sdio0-cd {
2129                                 rockchip,pins =
2130                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2131                         };
2132
2133                         sdio0_pwr: sdio0-pwr {
2134                                 rockchip,pins =
2135                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2136                         };
2137
2138                         sdio0_bkpwr: sdio0-bkpwr {
2139                                 rockchip,pins =
2140                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2141                         };
2142
2143                         sdio0_wp: sdio0-wp {
2144                                 rockchip,pins =
2145                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2146                         };
2147
2148                         sdio0_int: sdio0-int {
2149                                 rockchip,pins =
2150                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2151                         };
2152                 };
2153
2154                 sdmmc {
2155                         sdmmc_bus1: sdmmc-bus1 {
2156                                 rockchip,pins =
2157                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2158                         };
2159
2160                         sdmmc_bus4: sdmmc-bus4 {
2161                                 rockchip,pins =
2162                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2163                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2164                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2165                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2166                         };
2167
2168                         sdmmc_clk: sdmmc-clk {
2169                                 rockchip,pins =
2170                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2171                         };
2172
2173                         sdmmc_cmd: sdmmc-cmd {
2174                                 rockchip,pins =
2175                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2176                         };
2177
2178                         sdmmc_cd: sdmcc-cd {
2179                                 rockchip,pins =
2180                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2181                         };
2182
2183                         sdmmc_wp: sdmmc-wp {
2184                                 rockchip,pins =
2185                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2186                         };
2187                 };
2188
2189                 spdif {
2190                         spdif_bus: spdif-bus {
2191                                 rockchip,pins =
2192                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2193                         };
2194
2195                         spdif_bus_1: spdif-bus-1 {
2196                                 rockchip,pins =
2197                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2198                         };
2199                 };
2200
2201                 spi0 {
2202                         spi0_clk: spi0-clk {
2203                                 rockchip,pins =
2204                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2205                         };
2206                         spi0_cs0: spi0-cs0 {
2207                                 rockchip,pins =
2208                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2209                         };
2210                         spi0_cs1: spi0-cs1 {
2211                                 rockchip,pins =
2212                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2213                         };
2214                         spi0_tx: spi0-tx {
2215                                 rockchip,pins =
2216                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2217                         };
2218                         spi0_rx: spi0-rx {
2219                                 rockchip,pins =
2220                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2221                         };
2222                 };
2223
2224                 spi1 {
2225                         spi1_clk: spi1-clk {
2226                                 rockchip,pins =
2227                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2228                         };
2229                         spi1_cs0: spi1-cs0 {
2230                                 rockchip,pins =
2231                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2232                         };
2233                         spi1_rx: spi1-rx {
2234                                 rockchip,pins =
2235                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2236                         };
2237                         spi1_tx: spi1-tx {
2238                                 rockchip,pins =
2239                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2240                         };
2241                 };
2242
2243                 spi2 {
2244                         spi2_clk: spi2-clk {
2245                                 rockchip,pins =
2246                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2247                         };
2248                         spi2_cs0: spi2-cs0 {
2249                                 rockchip,pins =
2250                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2251                         };
2252                         spi2_rx: spi2-rx {
2253                                 rockchip,pins =
2254                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2255                         };
2256                         spi2_tx: spi2-tx {
2257                                 rockchip,pins =
2258                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2259                         };
2260                 };
2261
2262                 spi3 {
2263                         spi3_clk: spi3-clk {
2264                                 rockchip,pins =
2265                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2266                         };
2267                         spi3_cs0: spi3-cs0 {
2268                                 rockchip,pins =
2269                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2270                         };
2271                         spi3_rx: spi3-rx {
2272                                 rockchip,pins =
2273                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2274                         };
2275                         spi3_tx: spi3-tx {
2276                                 rockchip,pins =
2277                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2278                         };
2279                 };
2280
2281                 spi4 {
2282                         spi4_clk: spi4-clk {
2283                                 rockchip,pins =
2284                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2285                         };
2286                         spi4_cs0: spi4-cs0 {
2287                                 rockchip,pins =
2288                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2289                         };
2290                         spi4_rx: spi4-rx {
2291                                 rockchip,pins =
2292                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2293                         };
2294                         spi4_tx: spi4-tx {
2295                                 rockchip,pins =
2296                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2297                         };
2298                 };
2299
2300                 spi5 {
2301                         spi5_clk: spi5-clk {
2302                                 rockchip,pins =
2303                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2304                         };
2305                         spi5_cs0: spi5-cs0 {
2306                                 rockchip,pins =
2307                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2308                         };
2309                         spi5_rx: spi5-rx {
2310                                 rockchip,pins =
2311                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2312                         };
2313                         spi5_tx: spi5-tx {
2314                                 rockchip,pins =
2315                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2316                         };
2317                 };
2318
2319                 tsadc {
2320                         otp_gpio: otp-gpio {
2321                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2322                         };
2323
2324                         otp_out: otp-out {
2325                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2326                         };
2327                 };
2328
2329                 uart0 {
2330                         uart0_xfer: uart0-xfer {
2331                                 rockchip,pins =
2332                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2333                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2334                         };
2335
2336                         uart0_cts: uart0-cts {
2337                                 rockchip,pins =
2338                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2339                         };
2340
2341                         uart0_rts: uart0-rts {
2342                                 rockchip,pins =
2343                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2344                         };
2345                 };
2346
2347                 uart1 {
2348                         uart1_xfer: uart1-xfer {
2349                                 rockchip,pins =
2350                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2351                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2352                         };
2353                 };
2354
2355                 uart2a {
2356                         uart2a_xfer: uart2a-xfer {
2357                                 rockchip,pins =
2358                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2359                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2360                         };
2361                 };
2362
2363                 uart2b {
2364                         uart2b_xfer: uart2b-xfer {
2365                                 rockchip,pins =
2366                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2367                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2368                         };
2369                 };
2370
2371                 uart2c {
2372                         uart2c_xfer: uart2c-xfer {
2373                                 rockchip,pins =
2374                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2375                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2376                         };
2377                 };
2378
2379                 uart3 {
2380                         uart3_xfer: uart3-xfer {
2381                                 rockchip,pins =
2382                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2383                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2384                         };
2385
2386                         uart3_cts: uart3-cts {
2387                                 rockchip,pins =
2388                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2389                         };
2390
2391                         uart3_rts: uart3-rts {
2392                                 rockchip,pins =
2393                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2394                         };
2395                 };
2396
2397                 uart4 {
2398                         uart4_xfer: uart4-xfer {
2399                                 rockchip,pins =
2400                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2401                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2402                         };
2403                 };
2404
2405                 uarthdcp {
2406                         uarthdcp_xfer: uarthdcp-xfer {
2407                                 rockchip,pins =
2408                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2409                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2410                         };
2411                 };
2412
2413                 pwm0 {
2414                         pwm0_pin: pwm0-pin {
2415                                 rockchip,pins =
2416                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2417                         };
2418
2419                         vop0_pwm_pin: vop0-pwm-pin {
2420                                 rockchip,pins =
2421                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2422                         };
2423                 };
2424
2425                 pwm1 {
2426                         pwm1_pin: pwm1-pin {
2427                                 rockchip,pins =
2428                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2429                         };
2430
2431                         vop1_pwm_pin: vop1-pwm-pin {
2432                                 rockchip,pins =
2433                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2434                         };
2435                 };
2436
2437                 pwm2 {
2438                         pwm2_pin: pwm2-pin {
2439                                 rockchip,pins =
2440                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2441                         };
2442                 };
2443
2444                 pwm3a {
2445                         pwm3a_pin: pwm3a-pin {
2446                                 rockchip,pins =
2447                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2448                         };
2449                 };
2450
2451                 pwm3b {
2452                         pwm3b_pin: pwm3b-pin {
2453                                 rockchip,pins =
2454                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2455                         };
2456                 };
2457
2458                 edp {
2459                         edp_hpd: edp-hpd {
2460                                 rockchip,pins =
2461                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2462                         };
2463                 };
2464
2465                 hdmi {
2466                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2467                                 rockchip,pins =
2468                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2469                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2470                         };
2471
2472                         hdmi_cec: hdmi-cec {
2473                                 rockchip,pins =
2474                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2475                         };
2476                 };
2477
2478                 pcie {
2479                         pcie_clkreqn: pci-clkreqn {
2480                                 rockchip,pins =
2481                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2482                         };
2483
2484                         pcie_clkreqnb: pci-clkreqnb {
2485                                 rockchip,pins =
2486                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2487                         };
2488                 };
2489         };
2490 };