2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
264 compatible = "arm,cortex-a53-pmu";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
269 compatible = "arm,cortex-a72-pmu";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
274 compatible = "fixed-clock";
276 clock-frequency = <24000000>;
277 clock-output-names = "xin24m";
281 compatible = "arm,amba-bus";
282 #address-cells = <2>;
286 dmac_bus: dma-controller@ff6d0000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x0 0xff6d0000 0x0 0x4000>;
289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
292 clocks = <&cru ACLK_DMAC0_PERILP>;
293 clock-names = "apb_pclk";
294 peripherals-req-type-burst;
297 dmac_peri: dma-controller@ff6e0000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff6e0000 0x0 0x4000>;
300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
301 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
303 clocks = <&cru ACLK_DMAC1_PERILP>;
304 clock-names = "apb_pclk";
305 peripherals-req-type-burst;
310 compatible = "rockchip,rk3399-gmac";
311 reg = <0x0 0xfe300000 0x0 0x10000>;
312 rockchip,grf = <&grf>;
313 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
314 interrupt-names = "macirq";
315 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
316 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
317 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
319 clock-names = "stmmaceth", "mac_clk_rx",
320 "mac_clk_tx", "clk_mac_ref",
321 "clk_mac_refout", "aclk_mac",
323 resets = <&cru SRST_A_GMAC>;
324 reset-names = "stmmaceth";
329 compatible = "rockchip,rk3399-emmc-phy";
330 reg-offset = <0xf780>;
332 rockchip,grf = <&grf>;
333 ctrl-base = <0xfe330000>;
337 sdio0: dwmmc@fe310000 {
338 compatible = "rockchip,rk3399-dw-mshc",
339 "rockchip,rk3288-dw-mshc";
340 reg = <0x0 0xfe310000 0x0 0x4000>;
341 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
344 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
345 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
346 fifo-depth = <0x100>;
347 power-domains = <&power RK3399_PD_SDIOAUDIO>;
351 sdmmc: dwmmc@fe320000 {
352 compatible = "rockchip,rk3399-dw-mshc",
353 "rockchip,rk3288-dw-mshc";
354 reg = <0x0 0xfe320000 0x0 0x4000>;
355 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
356 clock-freq-min-max = <400000 150000000>;
357 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
358 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
359 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
360 fifo-depth = <0x100>;
361 power-domains = <&power RK3399_PD_SD>;
365 sdhci: sdhci@fe330000 {
366 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
367 reg = <0x0 0xfe330000 0x0 0x10000>;
368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
369 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
370 clock-names = "clk_xin", "clk_ahb";
371 assigned-clocks = <&cru SCLK_EMMC>;
372 assigned-clock-parents = <&cru PLL_CPLL>;
373 assigned-clock-rates = <200000000>;
375 phy-names = "phy_arasan";
376 power-domains = <&power RK3399_PD_EMMC>;
380 usb_host0_ehci: usb@fe380000 {
381 compatible = "generic-ehci";
382 reg = <0x0 0xfe380000 0x0 0x20000>;
383 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
384 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
385 <&cru SCLK_USBPHY0_480M_SRC>;
386 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
387 phys = <&u2phy0_host>;
392 usb_host0_ohci: usb@fe3a0000 {
393 compatible = "generic-ohci";
394 reg = <0x0 0xfe3a0000 0x0 0x20000>;
395 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
396 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
397 <&cru SCLK_USBPHY0_480M_SRC>;
398 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
399 phys = <&u2phy0_host>;
404 usb_host1_ehci: usb@fe3c0000 {
405 compatible = "generic-ehci";
406 reg = <0x0 0xfe3c0000 0x0 0x20000>;
407 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
408 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
409 <&cru SCLK_USBPHY1_480M_SRC>;
410 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
411 phys = <&u2phy1_host>;
416 usb_host1_ohci: usb@fe3e0000 {
417 compatible = "generic-ohci";
418 reg = <0x0 0xfe3e0000 0x0 0x20000>;
419 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
420 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
421 <&cru SCLK_USBPHY1_480M_SRC>;
422 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
423 phys = <&u2phy1_host>;
428 usbdrd3_0: usb@fe800000 {
429 compatible = "rockchip,dwc3";
430 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
431 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
432 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
433 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
434 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
435 "aclk_usb3", "aclk_usb3_grf";
436 #address-cells = <2>;
440 usbdrd_dwc3_0: dwc3@fe800000 {
441 compatible = "snps,dwc3";
442 reg = <0x0 0xfe800000 0x0 0x100000>;
443 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
445 phys = <&u2phy0_otg>;
446 phy-names = "usb2-phy";
447 snps,dis_enblslpm_quirk;
448 snps,phyif_utmi_16_bits;
449 snps,dis_u2_freeclk_exists_quirk;
450 snps,dis_del_phy_power_chg_quirk;
451 snps,xhci_slow_suspend_quirk;
456 usbdrd3_1: usb@fe900000 {
457 compatible = "rockchip,dwc3";
458 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
459 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
460 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
461 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
462 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
463 "aclk_usb3", "aclk_usb3_grf";
464 #address-cells = <2>;
468 usbdrd_dwc3_1: dwc3@fe900000 {
469 compatible = "snps,dwc3";
470 reg = <0x0 0xfe900000 0x0 0x100000>;
471 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
473 phys = <&u2phy1_otg>;
474 phy-names = "usb2-phy";
475 snps,dis_enblslpm_quirk;
476 snps,phyif_utmi_16_bits;
477 snps,dis_u2_freeclk_exists_quirk;
478 snps,dis_del_phy_power_chg_quirk;
479 snps,xhci_slow_suspend_quirk;
484 gic: interrupt-controller@fee00000 {
485 compatible = "arm,gic-v3";
486 #interrupt-cells = <4>;
487 #address-cells = <2>;
490 interrupt-controller;
492 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
493 <0x0 0xfef00000 0 0xc0000>, /* GICR */
494 <0x0 0xfff00000 0 0x10000>, /* GICC */
495 <0x0 0xfff10000 0 0x10000>, /* GICH */
496 <0x0 0xfff20000 0 0x10000>; /* GICV */
497 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
498 its: interrupt-controller@fee20000 {
499 compatible = "arm,gic-v3-its";
501 reg = <0x0 0xfee20000 0x0 0x20000>;
505 part0: interrupt-partition-0 {
506 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
509 part1: interrupt-partition-1 {
510 affinity = <&cpu_b0 &cpu_b1>;
515 saradc: saradc@ff100000 {
516 compatible = "rockchip,rk3399-saradc";
517 reg = <0x0 0xff100000 0x0 0x100>;
518 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
519 #io-channel-cells = <1>;
520 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
521 clock-names = "saradc", "apb_pclk";
526 compatible = "rockchip,rk3399-i2c";
527 reg = <0x0 0xff3c0000 0x0 0x1000>;
528 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
529 clock-names = "i2c", "pclk";
530 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c0_xfer>;
533 #address-cells = <1>;
539 compatible = "rockchip,rk3399-i2c";
540 reg = <0x0 0xff110000 0x0 0x1000>;
541 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
542 clock-names = "i2c", "pclk";
543 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c1_xfer>;
546 #address-cells = <1>;
552 compatible = "rockchip,rk3399-i2c";
553 reg = <0x0 0xff120000 0x0 0x1000>;
554 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
555 clock-names = "i2c", "pclk";
556 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c2_xfer>;
559 #address-cells = <1>;
565 compatible = "rockchip,rk3399-i2c";
566 reg = <0x0 0xff130000 0x0 0x1000>;
567 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
568 clock-names = "i2c", "pclk";
569 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c3_xfer>;
572 #address-cells = <1>;
578 compatible = "rockchip,rk3399-i2c";
579 reg = <0x0 0xff140000 0x0 0x1000>;
580 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
581 clock-names = "i2c", "pclk";
582 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c5_xfer>;
585 #address-cells = <1>;
591 compatible = "rockchip,rk3399-i2c";
592 reg = <0x0 0xff150000 0x0 0x1000>;
593 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
594 clock-names = "i2c", "pclk";
595 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c6_xfer>;
598 #address-cells = <1>;
604 compatible = "rockchip,rk3399-i2c";
605 reg = <0x0 0xff160000 0x0 0x1000>;
606 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
607 clock-names = "i2c", "pclk";
608 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c7_xfer>;
611 #address-cells = <1>;
616 uart0: serial@ff180000 {
617 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
618 reg = <0x0 0xff180000 0x0 0x100>;
619 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
620 clock-names = "baudclk", "apb_pclk";
621 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
629 uart1: serial@ff190000 {
630 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
631 reg = <0x0 0xff190000 0x0 0x100>;
632 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
633 clock-names = "baudclk", "apb_pclk";
634 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&uart1_xfer>;
642 uart2: serial@ff1a0000 {
643 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
644 reg = <0x0 0xff1a0000 0x0 0x100>;
645 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
646 clock-names = "baudclk", "apb_pclk";
647 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&uart2c_xfer>;
655 uart3: serial@ff1b0000 {
656 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
657 reg = <0x0 0xff1b0000 0x0 0x100>;
658 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
659 clock-names = "baudclk", "apb_pclk";
660 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
669 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
670 reg = <0x0 0xff1c0000 0x0 0x1000>;
671 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
672 clock-names = "spiclk", "apb_pclk";
673 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
676 #address-cells = <1>;
682 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
683 reg = <0x0 0xff1d0000 0x0 0x1000>;
684 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
685 clock-names = "spiclk", "apb_pclk";
686 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
689 #address-cells = <1>;
695 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
696 reg = <0x0 0xff1e0000 0x0 0x1000>;
697 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
698 clock-names = "spiclk", "apb_pclk";
699 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
702 #address-cells = <1>;
708 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
709 reg = <0x0 0xff1f0000 0x0 0x1000>;
710 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
711 clock-names = "spiclk", "apb_pclk";
712 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
715 #address-cells = <1>;
721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
722 reg = <0x0 0xff200000 0x0 0x1000>;
723 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
724 clock-names = "spiclk", "apb_pclk";
725 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
728 #address-cells = <1>;
734 soc_thermal: soc-thermal {
735 polling-delay-passive = <20>; /* milliseconds */
736 polling-delay = <1000>; /* milliseconds */
737 sustainable-power = <1000>; /* milliwatts */
739 thermal-sensors = <&tsadc 0>;
742 threshold: trip-point@0 {
743 temperature = <70000>; /* millicelsius */
744 hysteresis = <2000>; /* millicelsius */
747 target: trip-point@1 {
748 temperature = <85000>; /* millicelsius */
749 hysteresis = <2000>; /* millicelsius */
753 temperature = <95000>; /* millicelsius */
754 hysteresis = <2000>; /* millicelsius */
763 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
764 contribution = <4096>;
769 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
770 contribution = <1024>;
775 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
776 contribution = <4096>;
781 gpu_thermal: gpu-thermal {
782 polling-delay-passive = <100>; /* milliseconds */
783 polling-delay = <1000>; /* milliseconds */
785 thermal-sensors = <&tsadc 1>;
789 tsadc: tsadc@ff260000 {
790 compatible = "rockchip,rk3399-tsadc";
791 reg = <0x0 0xff260000 0x0 0x100>;
792 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
793 rockchip,grf = <&grf>;
794 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
795 clock-names = "tsadc", "apb_pclk";
796 assigned-clocks = <&cru SCLK_TSADC>;
797 assigned-clock-rates = <750000>;
798 resets = <&cru SRST_TSADC>;
799 reset-names = "tsadc-apb";
800 pinctrl-names = "init", "default", "sleep";
801 pinctrl-0 = <&otp_gpio>;
802 pinctrl-1 = <&otp_out>;
803 pinctrl-2 = <&otp_gpio>;
804 #thermal-sensor-cells = <1>;
805 rockchip,hw-tshut-temp = <95000>;
809 qos_emmc: qos@ffa58000 {
810 compatible = "syscon";
811 reg = <0x0 0xffa58000 0x0 0x20>;
814 qos_gmac: qos@ffa5c000 {
815 compatible = "syscon";
816 reg = <0x0 0xffa5c000 0x0 0x20>;
819 qos_pcie: qos@ffa60080 {
820 compatible = "syscon";
821 reg = <0x0 0xffa60080 0x0 0x20>;
824 qos_usb_host0: qos@ffa60100 {
825 compatible = "syscon";
826 reg = <0x0 0xffa60100 0x0 0x20>;
829 qos_usb_host1: qos@ffa60180 {
830 compatible = "syscon";
831 reg = <0x0 0xffa60180 0x0 0x20>;
834 qos_usb_otg0: qos@ffa70000 {
835 compatible = "syscon";
836 reg = <0x0 0xffa70000 0x0 0x20>;
839 qos_usb_otg1: qos@ffa70080 {
840 compatible = "syscon";
841 reg = <0x0 0xffa70080 0x0 0x20>;
844 qos_sd: qos@ffa74000 {
845 compatible = "syscon";
846 reg = <0x0 0xffa74000 0x0 0x20>;
849 qos_sdioaudio: qos@ffa76000 {
850 compatible = "syscon";
851 reg = <0x0 0xffa76000 0x0 0x20>;
854 qos_hdcp: qos@ffa90000 {
855 compatible = "syscon";
856 reg = <0x0 0xffa90000 0x0 0x20>;
859 qos_iep: qos@ffa98000 {
860 compatible = "syscon";
861 reg = <0x0 0xffa98000 0x0 0x20>;
864 qos_isp0_m0: qos@ffaa0000 {
865 compatible = "syscon";
866 reg = <0x0 0xffaa0000 0x0 0x20>;
869 qos_isp0_m1: qos@ffaa0080 {
870 compatible = "syscon";
871 reg = <0x0 0xffaa0080 0x0 0x20>;
874 qos_isp1_m0: qos@ffaa8000 {
875 compatible = "syscon";
876 reg = <0x0 0xffaa8000 0x0 0x20>;
879 qos_isp1_m1: qos@ffaa8080 {
880 compatible = "syscon";
881 reg = <0x0 0xffaa8080 0x0 0x20>;
884 qos_rga_r: qos@ffab0000 {
885 compatible = "syscon";
886 reg = <0x0 0xffab0000 0x0 0x20>;
889 qos_rga_w: qos@ffab0080 {
890 compatible = "syscon";
891 reg = <0x0 0xffab0080 0x0 0x20>;
894 qos_video_m0: qos@ffab8000 {
895 compatible = "syscon";
896 reg = <0x0 0xffab8000 0x0 0x20>;
899 qos_video_m1_r: qos@ffac0000 {
900 compatible = "syscon";
901 reg = <0x0 0xffac0000 0x0 0x20>;
904 qos_video_m1_w: qos@ffac0080 {
905 compatible = "syscon";
906 reg = <0x0 0xffac0080 0x0 0x20>;
909 qos_vop_big_r: qos@ffac8000 {
910 compatible = "syscon";
911 reg = <0x0 0xffac8000 0x0 0x20>;
914 qos_vop_big_w: qos@ffac8080 {
915 compatible = "syscon";
916 reg = <0x0 0xffac8080 0x0 0x20>;
919 qos_vop_little: qos@ffad0000 {
920 compatible = "syscon";
921 reg = <0x0 0xffad0000 0x0 0x20>;
924 qos_perihp: qos@ffad8080 {
925 compatible = "syscon";
926 reg = <0x0 0xffad8080 0x0 0x20>;
929 qos_gpu: qos@ffae0000 {
930 compatible = "syscon";
931 reg = <0x0 0xffae0000 0x0 0x20>;
934 pmu: power-management@ff310000 {
935 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
936 reg = <0x0 0xff310000 0x0 0x1000>;
939 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
940 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
941 * Some of the power domains are grouped together for every
943 * The detail contents as below.
945 power: power-controller {
946 compatible = "rockchip,rk3399-power-controller";
947 #power-domain-cells = <1>;
948 #address-cells = <1>;
951 /* These power domains are grouped by VD_CENTER */
952 pd_iep@RK3399_PD_IEP {
953 reg = <RK3399_PD_IEP>;
954 clocks = <&cru ACLK_IEP>,
958 pd_rga@RK3399_PD_RGA {
959 reg = <RK3399_PD_RGA>;
960 clocks = <&cru ACLK_RGA>,
962 pm_qos = <&qos_rga_r>,
965 pd_vcodec@RK3399_PD_VCODEC {
966 reg = <RK3399_PD_VCODEC>;
967 clocks = <&cru ACLK_VCODEC>,
969 pm_qos = <&qos_video_m0>;
971 pd_vdu@RK3399_PD_VDU {
972 reg = <RK3399_PD_VDU>;
973 clocks = <&cru ACLK_VDU>,
975 pm_qos = <&qos_video_m1_r>,
979 /* These power domains are grouped by VD_GPU */
980 pd_gpu@RK3399_PD_GPU {
981 reg = <RK3399_PD_GPU>;
982 clocks = <&cru ACLK_GPU>;
986 /* These power domains are grouped by VD_LOGIC */
987 pd_emmc@RK3399_PD_EMMC {
988 reg = <RK3399_PD_EMMC>;
989 clocks = <&cru ACLK_EMMC>;
990 pm_qos = <&qos_emmc>;
992 pd_gmac@RK3399_PD_GMAC {
993 reg = <RK3399_PD_GMAC>;
994 clocks = <&cru ACLK_GMAC>;
995 pm_qos = <&qos_gmac>;
997 pd_perihp@RK3399_PD_PERIHP {
998 reg = <RK3399_PD_PERIHP>;
999 clocks = <&cru ACLK_PERIHP>;
1000 pm_qos = <&qos_perihp>,
1005 pd_sd@RK3399_PD_SD {
1006 reg = <RK3399_PD_SD>;
1007 clocks = <&cru HCLK_SDMMC>;
1010 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1011 reg = <RK3399_PD_SDIOAUDIO>;
1012 clocks = <&cru HCLK_SDIO>;
1013 pm_qos = <&qos_sdioaudio>;
1015 pd_usb3@RK3399_PD_USB3 {
1016 reg = <RK3399_PD_USB3>;
1017 clocks = <&cru ACLK_USB3>;
1018 pm_qos = <&qos_usb_otg0>,
1021 pd_vio@RK3399_PD_VIO {
1022 reg = <RK3399_PD_VIO>;
1023 #address-cells = <1>;
1026 pd_hdcp@RK3399_PD_HDCP {
1027 reg = <RK3399_PD_HDCP>;
1028 clocks = <&cru ACLK_HDCP>,
1031 pm_qos = <&qos_hdcp>;
1033 pd_isp0@RK3399_PD_ISP0 {
1034 reg = <RK3399_PD_ISP0>;
1035 clocks = <&cru ACLK_ISP0>,
1037 pm_qos = <&qos_isp0_m0>,
1040 pd_isp1@RK3399_PD_ISP1 {
1041 reg = <RK3399_PD_ISP1>;
1042 clocks = <&cru ACLK_ISP1>,
1044 pm_qos = <&qos_isp1_m0>,
1047 pd_vo@RK3399_PD_VO {
1048 reg = <RK3399_PD_VO>;
1049 #address-cells = <1>;
1052 pd_vopb@RK3399_PD_VOPB {
1053 reg = <RK3399_PD_VOPB>;
1054 clocks = <&cru ACLK_VOP0>,
1056 pm_qos = <&qos_vop_big_r>,
1059 pd_vopl@RK3399_PD_VOPL {
1060 reg = <RK3399_PD_VOPL>;
1061 clocks = <&cru ACLK_VOP1>,
1063 pm_qos = <&qos_vop_little>;
1070 pmugrf: syscon@ff320000 {
1071 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1072 reg = <0x0 0xff320000 0x0 0x1000>;
1075 compatible = "syscon-reboot-mode";
1077 mode-bootloader = <BOOT_LOADER>;
1078 mode-charge = <BOOT_CHARGING>;
1079 mode-fastboot = <BOOT_FASTBOOT>;
1080 mode-loader = <BOOT_LOADER>;
1081 mode-normal = <BOOT_NORMAL>;
1082 mode-recovery = <BOOT_RECOVERY>;
1086 spi3: spi@ff350000 {
1087 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1088 reg = <0x0 0xff350000 0x0 0x1000>;
1089 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1090 clock-names = "spiclk", "apb_pclk";
1091 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1094 #address-cells = <1>;
1096 status = "disabled";
1099 uart4: serial@ff370000 {
1100 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1101 reg = <0x0 0xff370000 0x0 0x100>;
1102 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1103 clock-names = "baudclk", "apb_pclk";
1104 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&uart4_xfer>;
1109 status = "disabled";
1112 i2c4: i2c@ff3d0000 {
1113 compatible = "rockchip,rk3399-i2c";
1114 reg = <0x0 0xff3d0000 0x0 0x1000>;
1115 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1116 clock-names = "i2c", "pclk";
1117 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&i2c4_xfer>;
1120 #address-cells = <1>;
1122 status = "disabled";
1125 i2c8: i2c@ff3e0000 {
1126 compatible = "rockchip,rk3399-i2c";
1127 reg = <0x0 0xff3e0000 0x0 0x1000>;
1128 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1129 clock-names = "i2c", "pclk";
1130 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&i2c8_xfer>;
1133 #address-cells = <1>;
1135 status = "disabled";
1138 pcie0: pcie@f8000000 {
1139 compatible = "rockchip,rk3399-pcie";
1140 #address-cells = <3>;
1142 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1143 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1144 clock-names = "aclk_pcie", "aclk_perf_pcie",
1145 "hclk_pcie", "clk_pciephy_ref";
1146 bus-range = <0x0 0x1>;
1147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1148 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1149 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1150 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1151 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1152 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1153 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1154 < 0x0 0xfd000000 0x0 0x1000000 >;
1155 reg-name = "axi-base", "apb-base";
1156 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1157 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1158 <&cru SRST_PCIE_PIPE>;
1159 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1160 "mgmt-sticky-rst", "pipe-rst";
1161 rockchip,grf = <&grf>;
1162 pcie-conf = <0xe220>;
1163 pcie-status = <0xe2a4>;
1164 pcie-laneoff = <0xe214>;
1165 power-domains = <&power RK3399_PD_PERIHP>;
1166 msi-parent = <&its>;
1167 #interrupt-cells = <1>;
1168 interrupt-map-mask = <0 0 0 7>;
1169 interrupt-map = <0 0 0 1 &pcie0 1>,
1173 status = "disabled";
1174 pcie_intc: interrupt-controller {
1175 interrupt-controller;
1176 #address-cells = <0>;
1177 #interrupt-cells = <1>;
1181 pwm0: pwm@ff420000 {
1182 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1183 reg = <0x0 0xff420000 0x0 0x10>;
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&pwm0_pin>;
1187 clocks = <&pmucru PCLK_RKPWM_PMU>;
1188 clock-names = "pwm";
1189 status = "disabled";
1192 pwm1: pwm@ff420010 {
1193 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1194 reg = <0x0 0xff420010 0x0 0x10>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&pwm1_pin>;
1198 clocks = <&pmucru PCLK_RKPWM_PMU>;
1199 clock-names = "pwm";
1200 status = "disabled";
1203 pwm2: pwm@ff420020 {
1204 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1205 reg = <0x0 0xff420020 0x0 0x10>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&pwm2_pin>;
1209 clocks = <&pmucru PCLK_RKPWM_PMU>;
1210 clock-names = "pwm";
1211 status = "disabled";
1214 pwm3: pwm@ff420030 {
1215 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1216 reg = <0x0 0xff420030 0x0 0x10>;
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&pwm3a_pin>;
1220 clocks = <&pmucru PCLK_RKPWM_PMU>;
1221 clock-names = "pwm";
1222 status = "disabled";
1226 compatible = "rockchip,rk3399-rga";
1227 reg = <0x0 0xff680000 0x0 0x10000>;
1228 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1229 interrupt-names = "rga";
1230 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1231 clock-names = "aclk", "hclk", "sclk";
1232 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1233 reset-names = "core", "axi", "ahb";
1234 power-domains = <&power RK3399_PD_RGA>;
1235 status = "disabled";
1238 pmucru: pmu-clock-controller@ff750000 {
1239 compatible = "rockchip,rk3399-pmucru";
1240 reg = <0x0 0xff750000 0x0 0x1000>;
1243 assigned-clocks = <&pmucru PLL_PPLL>;
1244 assigned-clock-rates = <676000000>;
1247 cru: clock-controller@ff760000 {
1248 compatible = "rockchip,rk3399-cru";
1249 reg = <0x0 0xff760000 0x0 0x1000>;
1253 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1254 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1255 <&cru ARMCLKL>, <&cru ARMCLKB>,
1256 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1258 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1260 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1261 <&cru PCLK_PERILP0>,
1262 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1263 assigned-clock-rates =
1264 <400000000>, <200000000>,
1265 <400000000>, <200000000>,
1266 <816000000>, <816000000>,
1267 <594000000>, <800000000>,
1269 <150000000>, <75000000>,
1271 <100000000>, <100000000>,
1273 <100000000>, <50000000>;
1276 grf: syscon@ff770000 {
1277 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1278 reg = <0x0 0xff770000 0x0 0x10000>;
1279 #address-cells = <1>;
1282 u2phy0: usb2-phy@e450 {
1283 compatible = "rockchip,rk3399-usb2phy";
1284 reg = <0xe450 0x10>;
1285 clocks = <&cru SCLK_USB2PHY0_REF>;
1286 clock-names = "phyclk";
1288 clock-output-names = "clk_usbphy0_480m";
1289 status = "disabled";
1291 u2phy0_otg: otg-port {
1293 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1294 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1295 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1296 interrupt-names = "otg-bvalid", "otg-id",
1298 status = "disabled";
1301 u2phy0_host: host-port {
1303 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1304 interrupt-names = "linestate";
1305 status = "disabled";
1309 u2phy1: usb2-phy@e460 {
1310 compatible = "rockchip,rk3399-usb2phy";
1311 reg = <0xe460 0x10>;
1312 clocks = <&cru SCLK_USB2PHY1_REF>;
1313 clock-names = "phyclk";
1315 clock-output-names = "clk_usbphy1_480m";
1316 status = "disabled";
1318 u2phy1_otg: otg-port {
1320 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1323 interrupt-names = "otg-bvalid", "otg-id",
1325 status = "disabled";
1328 u2phy1_host: host-port {
1330 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1331 interrupt-names = "linestate";
1332 status = "disabled";
1337 tcphy0: phy@ff7c0000 {
1338 compatible = "rockchip,rk3399-typec-phy";
1339 reg = <0x0 0xff7c0000 0x0 0x40000>;
1340 rockchip,grf = <&grf>;
1342 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1343 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1344 clock-names = "tcpdcore", "tcpdphy-ref";
1345 resets = <&cru SRST_UPHY0>,
1346 <&cru SRST_UPHY0_PIPE_L00>,
1347 <&cru SRST_P_UPHY0_TCPHY>;
1348 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1349 rockchip,typec-conn-dir = <0xe580 0 16>;
1350 rockchip,usb3tousb2-en = <0xe580 3 19>;
1351 rockchip,external-psm = <0xe588 14 30>;
1352 rockchip,pipe-status = <0xe5c0 0 0>;
1353 rockchip,uphy-dp-sel = <0x6268 19 19>;
1354 status = "disabled";
1357 tcphy1: phy@ff800000 {
1358 compatible = "rockchip,rk3399-typec-phy";
1359 reg = <0x0 0xff800000 0x0 0x40000>;
1360 rockchip,grf = <&grf>;
1362 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1363 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1364 clock-names = "tcpdcore", "tcpdphy-ref";
1365 resets = <&cru SRST_UPHY1>,
1366 <&cru SRST_UPHY1_PIPE_L00>,
1367 <&cru SRST_P_UPHY1_TCPHY>;
1368 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1369 rockchip,typec-conn-dir = <0xe58c 0 16>;
1370 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1371 rockchip,external-psm = <0xe594 14 30>;
1372 rockchip,pipe-status = <0xe5c0 16 16>;
1373 rockchip,uphy-dp-sel = <0x6268 3 19>;
1374 status = "disabled";
1378 compatible = "snps,dw-wdt";
1379 reg = <0x0 0xff840000 0x0 0x100>;
1380 clocks = <&cru PCLK_WDT>;
1381 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1384 rktimer: rktimer@ff850000 {
1385 compatible = "rockchip,rk3399-timer";
1386 reg = <0x0 0xff850000 0x0 0x1000>;
1387 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1388 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1389 clock-names = "pclk", "timer";
1392 spdif: spdif@ff870000 {
1393 compatible = "rockchip,rk3399-spdif";
1394 reg = <0x0 0xff870000 0x0 0x1000>;
1395 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1396 dmas = <&dmac_bus 7>;
1398 clock-names = "mclk", "hclk";
1399 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&spdif_bus>;
1402 status = "disabled";
1405 i2s0: i2s@ff880000 {
1406 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1407 reg = <0x0 0xff880000 0x0 0x1000>;
1408 rockchip,grf = <&grf>;
1409 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1410 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1411 dma-names = "tx", "rx";
1412 clock-names = "i2s_clk", "i2s_hclk";
1413 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&i2s0_8ch_bus>;
1416 status = "disabled";
1419 i2s1: i2s@ff890000 {
1420 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1421 reg = <0x0 0xff890000 0x0 0x1000>;
1422 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1423 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1424 dma-names = "tx", "rx";
1425 clock-names = "i2s_clk", "i2s_hclk";
1426 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1427 pinctrl-names = "default";
1428 pinctrl-0 = <&i2s1_2ch_bus>;
1429 status = "disabled";
1432 i2s2: i2s@ff8a0000 {
1433 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1434 reg = <0x0 0xff8a0000 0x0 0x1000>;
1435 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1436 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1437 dma-names = "tx", "rx";
1438 clock-names = "i2s_clk", "i2s_hclk";
1439 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1440 status = "disabled";
1444 compatible = "arm,malit860",
1449 reg = <0x0 0xff9a0000 0x0 0x10000>;
1451 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1452 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1453 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1454 interrupt-names = "GPU", "JOB", "MMU";
1456 clocks = <&cru ACLK_GPU>;
1457 clock-names = "clk_mali";
1458 #cooling-cells = <2>; /* min followed by max */
1459 operating-points-v2 = <&gpu_opp_table>;
1460 power-domains = <&power RK3399_PD_GPU>;
1461 power-off-delay-ms = <200>;
1462 status = "disabled";
1464 gpu_power_model: power_model {
1465 compatible = "arm,mali-simple-power-model";
1468 static-power = <300>;
1469 dynamic-power = <396>;
1470 ts = <32000 4700 (-80) 2>;
1471 thermal-zone = "gpu-thermal";
1475 gpu_opp_table: gpu_opp_table {
1476 compatible = "operating-points-v2";
1480 opp-hz = /bits/ 64 <200000000>;
1481 opp-microvolt = <900000>;
1484 opp-hz = /bits/ 64 <300000000>;
1485 opp-microvolt = <900000>;
1488 opp-hz = /bits/ 64 <400000000>;
1489 opp-microvolt = <900000>;
1494 vopl: vop@ff8f0000 {
1495 compatible = "rockchip,rk3399-vop-lit";
1496 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1497 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1498 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1499 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1500 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1501 reset-names = "axi", "ahb", "dclk";
1502 power-domains = <&power RK3399_PD_VOPL>;
1503 iommus = <&vopl_mmu>;
1504 status = "disabled";
1507 #address-cells = <1>;
1510 vopl_out_mipi: endpoint@0 {
1512 remote-endpoint = <&mipi_in_vopl>;
1515 vopl_out_edp: endpoint@1 {
1517 remote-endpoint = <&edp_in_vopl>;
1520 vopl_out_hdmi: endpoint@2 {
1522 remote-endpoint = <&hdmi_in_vopl>;
1527 vopl_mmu: iommu@ff8f3f00 {
1528 compatible = "rockchip,iommu";
1529 reg = <0x0 0xff8f3f00 0x0 0x100>;
1530 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1531 interrupt-names = "vopl_mmu";
1533 status = "disabled";
1536 vopb: vop@ff900000 {
1537 compatible = "rockchip,rk3399-vop-big";
1538 reg = <0x0 0xff900000 0x0 0x3efc>;
1539 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1540 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1541 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1542 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1543 reset-names = "axi", "ahb", "dclk";
1544 power-domains = <&power RK3399_PD_VOPB>;
1545 iommus = <&vopb_mmu>;
1546 status = "disabled";
1549 #address-cells = <1>;
1552 vopb_out_edp: endpoint@0 {
1554 remote-endpoint = <&edp_in_vopb>;
1557 vopb_out_mipi: endpoint@1 {
1559 remote-endpoint = <&mipi_in_vopb>;
1562 vopb_out_hdmi: endpoint@2 {
1564 remote-endpoint = <&hdmi_in_vopb>;
1569 vopb_mmu: iommu@ff903f00 {
1570 compatible = "rockchip,iommu";
1571 reg = <0x0 0xff903f00 0x0 0x100>;
1572 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1573 interrupt-names = "vopb_mmu";
1575 status = "disabled";
1578 hdmi: hdmi@ff940000 {
1579 compatible = "rockchip,rk3399-dw-hdmi";
1580 reg = <0x0 0xff940000 0x0 0x20000>;
1582 rockchip,grf = <&grf>;
1583 power-domains = <&power RK3399_PD_HDCP>;
1584 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1585 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1586 clock-names = "iahb", "isfr", "vpll", "grf";
1587 status = "disabled";
1591 #address-cells = <1>;
1593 hdmi_in_vopb: endpoint@0 {
1595 remote-endpoint = <&vopb_out_hdmi>;
1597 hdmi_in_vopl: endpoint@1 {
1599 remote-endpoint = <&vopl_out_hdmi>;
1605 mipi_dsi: mipi@ff960000 {
1606 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1607 reg = <0x0 0xff960000 0x0 0x8000>;
1608 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1609 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1610 <&cru SCLK_DPHY_TX0_CFG>;
1611 clock-names = "ref", "pclk", "phy_cfg";
1612 power-domains = <&power RK3399_PD_VIO>;
1613 rockchip,grf = <&grf>;
1614 #address-cells = <1>;
1616 status = "disabled";
1619 #address-cells = <1>;
1624 #address-cells = <1>;
1627 mipi_in_vopb: endpoint@0 {
1629 remote-endpoint = <&vopb_out_mipi>;
1631 mipi_in_vopl: endpoint@1 {
1633 remote-endpoint = <&vopl_out_mipi>;
1640 compatible = "rockchip,rk3399-edp";
1641 reg = <0x0 0xff970000 0x0 0x8000>;
1642 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1643 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1644 clock-names = "dp", "pclk";
1645 resets = <&cru SRST_P_EDP_CTRL>;
1647 rockchip,grf = <&grf>;
1648 status = "disabled";
1649 pinctrl-names = "default";
1650 pinctrl-0 = <&edp_hpd>;
1653 #address-cells = <1>;
1658 #address-cells = <1>;
1661 edp_in_vopb: endpoint@0 {
1663 remote-endpoint = <&vopb_out_edp>;
1666 edp_in_vopl: endpoint@1 {
1668 remote-endpoint = <&vopl_out_edp>;
1674 display_subsystem: display-subsystem {
1675 compatible = "rockchip,display-subsystem";
1676 ports = <&vopl_out>, <&vopb_out>;
1677 status = "disabled";
1681 compatible = "rockchip,rk3399-pinctrl";
1682 rockchip,grf = <&grf>;
1683 rockchip,pmu = <&pmugrf>;
1684 #address-cells = <0x2>;
1685 #size-cells = <0x2>;
1688 gpio0: gpio0@ff720000 {
1689 compatible = "rockchip,gpio-bank";
1690 reg = <0x0 0xff720000 0x0 0x100>;
1691 clocks = <&pmucru PCLK_GPIO0_PMU>;
1692 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1695 #gpio-cells = <0x2>;
1697 interrupt-controller;
1698 #interrupt-cells = <0x2>;
1701 gpio1: gpio1@ff730000 {
1702 compatible = "rockchip,gpio-bank";
1703 reg = <0x0 0xff730000 0x0 0x100>;
1704 clocks = <&pmucru PCLK_GPIO1_PMU>;
1705 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1708 #gpio-cells = <0x2>;
1710 interrupt-controller;
1711 #interrupt-cells = <0x2>;
1714 gpio2: gpio2@ff780000 {
1715 compatible = "rockchip,gpio-bank";
1716 reg = <0x0 0xff780000 0x0 0x100>;
1717 clocks = <&cru PCLK_GPIO2>;
1718 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1721 #gpio-cells = <0x2>;
1723 interrupt-controller;
1724 #interrupt-cells = <0x2>;
1727 gpio3: gpio3@ff788000 {
1728 compatible = "rockchip,gpio-bank";
1729 reg = <0x0 0xff788000 0x0 0x100>;
1730 clocks = <&cru PCLK_GPIO3>;
1731 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1734 #gpio-cells = <0x2>;
1736 interrupt-controller;
1737 #interrupt-cells = <0x2>;
1740 gpio4: gpio4@ff790000 {
1741 compatible = "rockchip,gpio-bank";
1742 reg = <0x0 0xff790000 0x0 0x100>;
1743 clocks = <&cru PCLK_GPIO4>;
1744 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1747 #gpio-cells = <0x2>;
1749 interrupt-controller;
1750 #interrupt-cells = <0x2>;
1753 pcfg_pull_up: pcfg-pull-up {
1757 pcfg_pull_down: pcfg-pull-down {
1761 pcfg_pull_none: pcfg-pull-none {
1765 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1767 drive-strength = <20>;
1770 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1772 drive-strength = <20>;
1775 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1777 drive-strength = <18>;
1780 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1782 drive-strength = <12>;
1785 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1787 drive-strength = <8>;
1790 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1792 drive-strength = <4>;
1795 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1797 drive-strength = <2>;
1800 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1802 drive-strength = <12>;
1805 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1807 drive-strength = <13>;
1811 emmc_pwr: emmc-pwr {
1813 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1818 rgmii_pins: rgmii-pins {
1821 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1823 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1825 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1827 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1829 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1831 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1833 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1835 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1837 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1839 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1841 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1843 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1845 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1847 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1849 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1852 rmii_pins: rmii-pins {
1855 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1857 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1859 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1861 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1863 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1865 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1867 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1869 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1871 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1873 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1878 i2c0_xfer: i2c0-xfer {
1880 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1881 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1886 i2c1_xfer: i2c1-xfer {
1888 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1889 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1894 i2c2_xfer: i2c2-xfer {
1896 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1897 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1902 i2c3_xfer: i2c3-xfer {
1904 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1905 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1908 i2c3_gpio: i2c3_gpio {
1910 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1911 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1917 i2c4_xfer: i2c4-xfer {
1919 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1920 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1925 i2c5_xfer: i2c5-xfer {
1927 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1928 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1933 i2c6_xfer: i2c6-xfer {
1935 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1936 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1941 i2c7_xfer: i2c7-xfer {
1943 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1944 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1949 i2c8_xfer: i2c8-xfer {
1951 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1952 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1957 i2s0_8ch_bus: i2s0-8ch-bus {
1959 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1960 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1961 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1962 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1963 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1964 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1965 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1966 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1967 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1972 i2s1_2ch_bus: i2s1-2ch-bus {
1974 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1975 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1976 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1977 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1978 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1983 sdio0_bus1: sdio0-bus1 {
1985 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1988 sdio0_bus4: sdio0-bus4 {
1990 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1991 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1992 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1993 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1996 sdio0_cmd: sdio0-cmd {
1998 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2001 sdio0_clk: sdio0-clk {
2003 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2006 sdio0_cd: sdio0-cd {
2008 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2011 sdio0_pwr: sdio0-pwr {
2013 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2016 sdio0_bkpwr: sdio0-bkpwr {
2018 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2021 sdio0_wp: sdio0-wp {
2023 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2026 sdio0_int: sdio0-int {
2028 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2033 sdmmc_bus1: sdmmc-bus1 {
2035 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2038 sdmmc_bus4: sdmmc-bus4 {
2040 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2041 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2042 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2043 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2046 sdmmc_clk: sdmmc-clk {
2048 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2051 sdmmc_cmd: sdmmc-cmd {
2053 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2056 sdmmc_cd: sdmcc-cd {
2058 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2061 sdmmc_wp: sdmmc-wp {
2063 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2068 spdif_bus: spdif-bus {
2070 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2073 spdif_bus_1: spdif-bus-1 {
2075 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2080 spi0_clk: spi0-clk {
2082 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2084 spi0_cs0: spi0-cs0 {
2086 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2088 spi0_cs1: spi0-cs1 {
2090 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2094 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2098 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2103 spi1_clk: spi1-clk {
2105 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2107 spi1_cs0: spi1-cs0 {
2109 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2113 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2117 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2122 spi2_clk: spi2-clk {
2124 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2126 spi2_cs0: spi2-cs0 {
2128 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2132 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2136 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2141 spi3_clk: spi3-clk {
2143 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2145 spi3_cs0: spi3-cs0 {
2147 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2151 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2155 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2160 spi4_clk: spi4-clk {
2162 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2164 spi4_cs0: spi4-cs0 {
2166 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2170 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2174 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2179 spi5_clk: spi5-clk {
2181 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2183 spi5_cs0: spi5-cs0 {
2185 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2189 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2193 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2198 otp_gpio: otp-gpio {
2199 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2203 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2208 uart0_xfer: uart0-xfer {
2210 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2211 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2214 uart0_cts: uart0-cts {
2216 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2219 uart0_rts: uart0-rts {
2221 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2226 uart1_xfer: uart1-xfer {
2228 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2229 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2234 uart2a_xfer: uart2a-xfer {
2236 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2237 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2242 uart2b_xfer: uart2b-xfer {
2244 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2245 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2250 uart2c_xfer: uart2c-xfer {
2252 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2253 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2258 uart3_xfer: uart3-xfer {
2260 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2261 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2264 uart3_cts: uart3-cts {
2266 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2269 uart3_rts: uart3-rts {
2271 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2276 uart4_xfer: uart4-xfer {
2278 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2279 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2284 uarthdcp_xfer: uarthdcp-xfer {
2286 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2287 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2292 pwm0_pin: pwm0-pin {
2294 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2297 vop0_pwm_pin: vop0-pwm-pin {
2299 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2304 pwm1_pin: pwm1-pin {
2306 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2309 vop1_pwm_pin: vop1-pwm-pin {
2311 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2316 pwm2_pin: pwm2-pin {
2318 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2323 pwm3a_pin: pwm3a-pin {
2325 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2330 pwm3b_pin: pwm3b-pin {
2332 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2339 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2344 hdmi_i2c_xfer: hdmi-i2c-xfer {
2346 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2347 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2350 hdmi_cec: hdmi-cec {
2352 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2357 pcie_clkreqn: pci-clkreqn {
2359 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2362 pcie_clkreqnb: pci-clkreqnb {
2364 <4 24 RK_FUNC_1 &pcfg_pull_none>;