arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         xin24m: xin24m {
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <24000000>;
 228                 clock-output-names = "xin24m";
 229         };
 230
 231         amba {
 232                 compatible = "arm,amba-bus";
 233                 #address-cells = <2>;
 234                 #size-cells = <2>;
 235                 ranges;
 236
 237                 dmac_bus: dma-controller@ff6d0000 {
 238                         compatible = "arm,pl330", "arm,primecell";
 239                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 240                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 242                         #dma-cells = <1>;
 243                         clocks = <&cru ACLK_DMAC0_PERILP>;
 244                         clock-names = "apb_pclk";
 245                 };
 246
 247                 dmac_peri: dma-controller@ff6e0000 {
 248                         compatible = "arm,pl330", "arm,primecell";
 249                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 250                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 252                         #dma-cells = <1>;
 253                         clocks = <&cru ACLK_DMAC1_PERILP>;
 254                         clock-names = "apb_pclk";
 255                 };
 256         };
 257
 258         gmac: eth@fe300000 {
 259                 compatible = "rockchip,rk3399-gmac";
 260                 reg = <0x0 0xfe300000 0x0 0x10000>;
 261                 rockchip,grf = <&grf>;
 262                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 263                 interrupt-names = "macirq";
 264                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 265                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 266                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 267                          <&cru PCLK_GMAC>;
 268                 clock-names = "stmmaceth", "mac_clk_rx",
 269                               "mac_clk_tx", "clk_mac_ref",
 270                               "clk_mac_refout", "aclk_mac",
 271                               "pclk_mac";
 272                 resets = <&cru SRST_A_GMAC>;
 273                 reset-names = "stmmaceth";
 274                 status = "disabled";
 275         };
 276
 277         emmc_phy: phy {
 278                 compatible = "rockchip,rk3399-emmc-phy";
 279                 reg-offset = <0xf780>;
 280                 #phy-cells = <0>;
 281                 rockchip,grf = <&grf>;
 282                 status = "disabled";
 283         };
 284
 285         sdio0: dwmmc@fe310000 {
 286                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 287                 reg = <0x0 0xfe310000 0x0 0x4000>;
 288                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 289                 clock-freq-min-max = <400000 150000000>;
 290                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 291                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 292                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 293                 fifo-depth = <0x100>;
 294                 status = "disabled";
 295         };
 296
 297         sdmmc: dwmmc@fe320000 {
 298                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 299                 reg = <0x0 0xfe320000 0x0 0x4000>;
 300                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 301                 clock-freq-min-max = <400000 150000000>;
 302                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 303                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 304                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 305                 fifo-depth = <0x100>;
 306                 status = "disabled";
 307         };
 308
 309         sdhci: sdhci@fe330000 {
 310                 compatible = "arasan,sdhci-5.1";
 311                 reg = <0x0 0xfe330000 0x0 0x10000>;
 312                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 314                 clock-names = "clk_xin", "clk_ahb";
 315                 phys = <&emmc_phy>;
 316                 phy-names = "phy_arasan";
 317                 status = "disabled";
 318         };
 319
 320         usb2phy {
 321                 compatible = "rockchip,rk3399-usb-phy";
 322                 rockchip,grf = <&grf>;
 323                 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326
 327                 usb2phy0: usb2-phy0 {
 328                         #phy-cells = <0>;
 329                         #clock-cells = <0>;
 330                         reg = <0xe458>;
 331                 };
 332
 333                 usb2phy1: usb2-phy1 {
 334                         #phy-cells = <0>;
 335                         #clock-cells = <0>;
 336                         reg = <0xe468>;
 337                 };
 338         };
 339
 340         usb_host0_echi: usb@fe380000 {
 341                 compatible = "generic-ehci";
 342                 reg = <0x0 0xfe380000 0x0 0x20000>;
 343                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 345                 clock-names = "hclk_host0", "hclk_host0_arb";
 346                 phys = <&usb2phy0>;
 347                 phy-names = "usb2_phy0";
 348                 status = "disabled";
 349         };
 350
 351         usb_host0_ohci: usb@fe3a0000 {
 352                 compatible = "generic-ohci";
 353                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 354                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 356                 clock-names = "hclk_host0", "hclk_host0_arb";
 357                 status = "disabled";
 358         };
 359
 360         usb_host1_echi: usb@fe3c0000 {
 361                 compatible = "generic-ehci";
 362                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 363                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 365                 clock-names = "hclk_host1", "hclk_host1_arb";
 366                 phys = <&usb2phy1>;
 367                 phy-names = "usb2_phy1";
 368                 status = "disabled";
 369         };
 370
 371         usb_host1_ohci: usb@fe3e0000 {
 372                 compatible = "generic-ohci";
 373                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 374                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 376                 clock-names = "hclk_host1", "hclk_host1_arb";
 377                 status = "disabled";
 378         };
 379
 380         usbdrd3_0: usb@fe800000 {
 381                 compatible = "rockchip,dwc3";
 382                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 383                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 384                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 385                          <&cru ACLK_USB3_GRF>;
 386                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 387                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 388                               "aclk_usb3", "aclk_usb3_noc",
 389                               "aclk_usb3_grf";
 390                 #address-cells = <2>;
 391                 #size-cells = <2>;
 392                 ranges;
 393                 status = "disabled";
 394                 usbdrd_dwc3_0: dwc3 {
 395                         compatible = "snps,dwc3";
 396                         reg = <0x0 0xfe800000 0x0 0x100000>;
 397                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 398                         dr_mode = "otg";
 399                         tx-fifo-resize;
 400                         snps,dis_enblslpm_quirk;
 401                         snps,phyif_utmi_16_bits;
 402                         snps,dis_u2_freeclk_exists_quirk;
 403                         snps,dis_del_phy_power_chg_quirk;
 404                         status = "disabled";
 405                 };
 406         };
 407
 408         usbdrd3_1: usb@fe900000 {
 409                 compatible = "rockchip,dwc3";
 410                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 411                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 412                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 413                          <&cru ACLK_USB3_GRF>;
 414                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 415                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 416                               "aclk_usb3", "aclk_usb3_noc",
 417                               "aclk_usb3_grf";
 418                 #address-cells = <2>;
 419                 #size-cells = <2>;
 420                 ranges;
 421                 status = "disabled";
 422                 usbdrd_dwc3_1: dwc3 {
 423                         compatible = "snps,dwc3";
 424                         reg = <0x0 0xfe900000 0x0 0x100000>;
 425                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 426                         dr_mode = "otg";
 427                         tx-fifo-resize;
 428                         snps,dis_enblslpm_quirk;
 429                         snps,phyif_utmi_16_bits;
 430                         snps,dis_u2_freeclk_exists_quirk;
 431                         snps,dis_del_phy_power_chg_quirk;
 432                         status = "disabled";
 433                 };
 434         };
 435
 436         gic: interrupt-controller@fee00000 {
 437                 compatible = "arm,gic-v3";
 438                 #interrupt-cells = <3>;
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 interrupt-controller;
 443
 444                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 445                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 446                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 447                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 448                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 449                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 450                 its: interrupt-controller@fee20000 {
 451                         compatible = "arm,gic-v3-its";
 452                         msi-controller;
 453                         reg = <0x0 0xfee20000 0x0 0x20000>;
 454                 };
 455         };
 456
 457         saradc: saradc@ff100000 {
 458                 compatible = "rockchip,rk3399-saradc";
 459                 reg = <0x0 0xff100000 0x0 0x100>;
 460                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 461                 #io-channel-cells = <1>;
 462                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 463                 clock-names = "saradc", "apb_pclk";
 464                 status = "disabled";
 465         };
 466
 467         i2c0: i2c@ff3c0000 {
 468                 compatible = "rockchip,rk3399-i2c";
 469                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 470                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 471                 clock-names = "i2c", "pclk";
 472                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&i2c0_xfer>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c1: i2c@ff110000 {
 481                 compatible = "rockchip,rk3399-i2c";
 482                 reg = <0x0 0xff110000 0x0 0x1000>;
 483                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 484                 clock-names = "i2c", "pclk";
 485                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c1_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff120000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff120000 0x0 0x1000>;
 496                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c2_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff130000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff130000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 510                 clock-names = "i2c", "pclk";
 511                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c3_xfer>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         i2c5: i2c@ff140000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff140000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 523                 clock-names = "i2c", "pclk";
 524                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c5_xfer>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         i2c6: i2c@ff150000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff150000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c6_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c7: i2c@ff160000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff160000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c7_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         uart0: serial@ff180000 {
 559                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 560                 reg = <0x0 0xff180000 0x0 0x100>;
 561                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 562                 clock-names = "baudclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 564                 reg-shift = <2>;
 565                 reg-io-width = <4>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 568                 status = "disabled";
 569         };
 570
 571         uart1: serial@ff190000 {
 572                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 573                 reg = <0x0 0xff190000 0x0 0x100>;
 574                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 575                 clock-names = "baudclk", "apb_pclk";
 576                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 577                 reg-shift = <2>;
 578                 reg-io-width = <4>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&uart1_xfer>;
 581                 status = "disabled";
 582         };
 583
 584         uart2: serial@ff1a0000 {
 585                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff1a0000 0x0 0x100>;
 587                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 588                 clock-names = "baudclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 590                 reg-shift = <2>;
 591                 reg-io-width = <4>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&uart2c_xfer>;
 594                 status = "disabled";
 595         };
 596
 597         uart3: serial@ff1b0000 {
 598                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff1b0000 0x0 0x100>;
 600                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 601                 clock-names = "baudclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 607                 status = "disabled";
 608         };
 609
 610         spi0: spi@ff1c0000 {
 611                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 612                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 613                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 614                 clock-names = "spiclk", "apb_pclk";
 615                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 status = "disabled";
 621         };
 622
 623         spi1: spi@ff1d0000 {
 624                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 625                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 626                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 627                 clock-names = "spiclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 status = "disabled";
 634         };
 635
 636         spi2: spi@ff1e0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi4: spi@ff1f0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi5: spi@ff200000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff200000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         thermal-zones {
 676                 #include "rk3368-thermal.dtsi"
 677         };
 678
 679         tsadc: tsadc@ff260000 {
 680                 compatible = "rockchip,rk3399-tsadc";
 681                 reg = <0x0 0xff260000 0x0 0x100>;
 682                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 683                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 684                 clock-names = "tsadc", "apb_pclk";
 685                 resets = <&cru SRST_TSADC>;
 686                 reset-names = "tsadc-apb";
 687                 pinctrl-names = "init", "default", "sleep";
 688                 pinctrl-0 = <&otp_gpio>;
 689                 pinctrl-1 = <&otp_out>;
 690                 pinctrl-2 = <&otp_gpio>;
 691                 #thermal-sensor-cells = <1>;
 692                 rockchip,hw-tshut-temp = <95000>;
 693                 status = "disabled";
 694         };
 695
 696         pmu: power-management@ff31000 {
 697                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 698                 reg = <0x0 0xff310000 0x0 0x1000>;
 699
 700                 power: power-controller {
 701                         status = "disabled";
 702                         compatible = "rockchip,rk3399-power-controller";
 703                         #power-domain-cells = <1>;
 704                         #address-cells = <1>;
 705                         #size-cells = <0>;
 706
 707                         pd_center {
 708                                 reg = <RK3399_PD_CENTER>;
 709                                 #address-cells = <1>;
 710                                 #size-cells = <0>;
 711
 712                                 pd_vdu {
 713                                         reg = <RK3399_PD_VDU>;
 714                                 };
 715                                 pd_vcodec {
 716                                         reg = <RK3399_PD_VCODEC>;
 717                                 };
 718                                 pd_iep {
 719                                         reg = <RK3399_PD_IEP>;
 720                                 };
 721                                 pd_rga {
 722                                         reg = <RK3399_PD_RGA>;
 723                                 };
 724                         };
 725                         pd_vio {
 726                                 reg = <RK3399_PD_VIO>;
 727                                 #address-cells = <1>;
 728                                 #size-cells = <0>;
 729
 730                                 pd_isp0 {
 731                                         reg = <RK3399_PD_ISP0>;
 732                                 };
 733                                 pd_isp1 {
 734                                         reg = <RK3399_PD_ISP1>;
 735                                 };
 736                                 pd_hdcp {
 737                                         reg = <RK3399_PD_HDCP>;
 738                                 };
 739                                 pd_vo {
 740                                         reg = <RK3399_PD_VO>;
 741                                         #address-cells = <1>;
 742                                         #size-cells = <0>;
 743
 744                                         pd_vopb {
 745                                                 reg = <RK3399_PD_VOPB>;
 746                                         };
 747                                         pd_vopl {
 748                                                 reg = <RK3399_PD_VOPL>;
 749                                         };
 750                                 };
 751                         };
 752                         pd_gpu {
 753                                 reg = <RK3399_PD_GPU>;
 754                         };
 755                 };
 756         };
 757
 758         pmugrf: syscon@ff320000 {
 759                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 760                 reg = <0x0 0xff320000 0x0 0x1000>;
 761         };
 762
 763         spi3: spi@ff350000 {
 764                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 765                 reg = <0x0 0xff350000 0x0 0x1000>;
 766                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 767                 clock-names = "spiclk", "apb_pclk";
 768                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 769                 pinctrl-names = "default";
 770                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 771                 #address-cells = <1>;
 772                 #size-cells = <0>;
 773                 status = "disabled";
 774         };
 775
 776         uart4: serial@ff370000 {
 777                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 778                 reg = <0x0 0xff370000 0x0 0x100>;
 779                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 780                 clock-names = "baudclk", "apb_pclk";
 781                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 782                 reg-shift = <2>;
 783                 reg-io-width = <4>;
 784                 pinctrl-names = "default";
 785                 pinctrl-0 = <&uart4_xfer>;
 786                 status = "disabled";
 787         };
 788
 789         i2c4: i2c@ff3d0000 {
 790                 compatible = "rockchip,rk3399-i2c";
 791                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 792                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 793                 clock-names = "i2c", "pclk";
 794                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 795                 pinctrl-names = "default";
 796                 pinctrl-0 = <&i2c4_xfer>;
 797                 #address-cells = <1>;
 798                 #size-cells = <0>;
 799                 status = "disabled";
 800         };
 801
 802         i2c8: i2c@ff3e0000 {
 803                 compatible = "rockchip,rk3399-i2c";
 804                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 805                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 806                 clock-names = "i2c", "pclk";
 807                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 808                 pinctrl-names = "default";
 809                 pinctrl-0 = <&i2c8_xfer>;
 810                 #address-cells = <1>;
 811                 #size-cells = <0>;
 812                 status = "disabled";
 813         };
 814
 815         pwm0: pwm@ff420000 {
 816                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 817                 reg = <0x0 0xff420000 0x0 0x10>;
 818                 #pwm-cells = <3>;
 819                 pinctrl-names = "default";
 820                 pinctrl-0 = <&pwm0_pin>;
 821                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 822                 clock-names = "pwm";
 823                 status = "disabled";
 824         };
 825
 826         pwm1: pwm@ff420010 {
 827                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 828                 reg = <0x0 0xff420010 0x0 0x10>;
 829                 #pwm-cells = <3>;
 830                 pinctrl-names = "default";
 831                 pinctrl-0 = <&pwm1_pin>;
 832                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 833                 clock-names = "pwm";
 834                 status = "disabled";
 835         };
 836
 837         pwm2: pwm@ff420020 {
 838                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 839                 reg = <0x0 0xff420020 0x0 0x10>;
 840                 #pwm-cells = <3>;
 841                 pinctrl-names = "default";
 842                 pinctrl-0 = <&pwm2_pin>;
 843                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 844                 clock-names = "pwm";
 845                 status = "disabled";
 846         };
 847
 848         pwm3: pwm@ff420030 {
 849                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 850                 reg = <0x0 0xff420030 0x0 0x10>;
 851                 #pwm-cells = <3>;
 852                 pinctrl-names = "default";
 853                 pinctrl-0 = <&pwm3a_pin>;
 854                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 855                 clock-names = "pwm";
 856                 status = "disabled";
 857         };
 858
 859         pmucru: pmu-clock-controller@ff750000 {
 860                 compatible = "rockchip,rk3399-pmucru";
 861                 reg = <0x0 0xff750000 0x0 0x1000>;
 862                 rockchip,grf = <&pmugrf>;
 863                 #clock-cells = <1>;
 864                 #reset-cells = <1>;
 865                 assigned-clocks = <&pmucru PLL_PPLL>;
 866                 assigned-clock-rates = <676000000>;
 867         };
 868
 869         cru: clock-controller@ff760000 {
 870                 compatible = "rockchip,rk3399-cru";
 871                 reg = <0x0 0xff760000 0x0 0x1000>;
 872                 rockchip,grf = <&grf>;
 873                 #clock-cells = <1>;
 874                 #reset-cells = <1>;
 875                 assigned-clocks =
 876                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 877                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 878                         <&cru PLL_NPLL>,
 879                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 880                         <&cru PCLK_PERIHP>,
 881                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 882                         <&cru PCLK_PERILP0>,
 883                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 884                 assigned-clock-rates =
 885                          <816000000>, <1008000000>,
 886                          <594000000>,  <800000000>,
 887                         <1000000000>,
 888                          <150000000>,   <75000000>,
 889                           <37500000>,
 890                          <100000000>,  <100000000>,
 891                           <50000000>,
 892                          <100000000>,   <50000000>;
 893         };
 894
 895         grf: syscon@ff770000 {
 896                 compatible = "rockchip,rk3399-grf", "syscon";
 897                 reg = <0x0 0xff770000 0x0 0x10000>;
 898         };
 899
 900         wdt0: watchdog@ff840000 {
 901                 compatible = "snps,dw-wdt";
 902                 reg = <0x0 0xff840000 0x0 0x100>;
 903                 clocks = <&cru PCLK_WDT>;
 904                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 905                 status = "disabled";
 906         };
 907
 908         spdif: spdif@ff870000 {
 909                 compatible = "rockchip,rk3399-spdif";
 910                 reg = <0x0 0xff870000 0x0 0x1000>;
 911                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 912                 dmas = <&dmac_bus 7>;
 913                 dma-names = "tx";
 914                 clock-names = "hclk", "mclk";
 915                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 916                 pinctrl-names = "default";
 917                 pinctrl-0 = <&spdif_bus>;
 918                 status = "disabled";
 919         };
 920
 921         i2s0: i2s@ff880000 {
 922                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 923                 reg = <0x0 0xff880000 0x0 0x1000>;
 924                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 925                 #address-cells = <1>;
 926                 #size-cells = <0>;
 927                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 928                 dma-names = "tx", "rx";
 929                 clock-names = "i2s_hclk", "i2s_clk";
 930                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 931                 pinctrl-names = "default";
 932                 pinctrl-0 = <&i2s0_8ch_bus>;
 933                 status = "disabled";
 934         };
 935
 936         i2s1: i2s@ff890000 {
 937                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 938                 reg = <0x0 0xff890000 0x0 0x1000>;
 939                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 940                 #address-cells = <1>;
 941                 #size-cells = <0>;
 942                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 943                 dma-names = "tx", "rx";
 944                 clock-names = "i2s_hclk", "i2s_clk";
 945                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 946                 pinctrl-names = "default";
 947                 pinctrl-0 = <&i2s1_2ch_bus>;
 948                 status = "disabled";
 949         };
 950
 951         i2s2: i2s@ff8a0000 {
 952                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 953                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 954                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 955                 #address-cells = <1>;
 956                 #size-cells = <0>;
 957                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 958                 dma-names = "tx", "rx";
 959                 clock-names = "i2s_hclk", "i2s_clk";
 960                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 961                 status = "disabled";
 962         };
 963
 964         pinctrl: pinctrl {
 965                 compatible = "rockchip,rk3399-pinctrl";
 966                 rockchip,grf = <&grf>;
 967                 rockchip,pmu = <&pmugrf>;
 968                 #address-cells = <0x2>;
 969                 #size-cells = <0x2>;
 970                 ranges;
 971
 972                 gpio0: gpio0@ff720000 {
 973                         compatible = "rockchip,gpio-bank";
 974                         reg = <0x0 0xff720000 0x0 0x100>;
 975                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 976                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 977
 978                         gpio-controller;
 979                         #gpio-cells = <0x2>;
 980
 981                         interrupt-controller;
 982                         #interrupt-cells = <0x2>;
 983                 };
 984
 985                 gpio1: gpio1@ff730000 {
 986                         compatible = "rockchip,gpio-bank";
 987                         reg = <0x0 0xff730000 0x0 0x100>;
 988                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 989                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 990
 991                         gpio-controller;
 992                         #gpio-cells = <0x2>;
 993
 994                         interrupt-controller;
 995                         #interrupt-cells = <0x2>;
 996                 };
 997
 998                 gpio2: gpio2@ff780000 {
 999                         compatible = "rockchip,gpio-bank";
1000                         reg = <0x0 0xff780000 0x0 0x100>;
1001                         clocks = <&cru PCLK_GPIO2>;
1002                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1003
1004                         gpio-controller;
1005                         #gpio-cells = <0x2>;
1006
1007                         interrupt-controller;
1008                         #interrupt-cells = <0x2>;
1009                 };
1010
1011                 gpio3: gpio3@ff788000 {
1012                         compatible = "rockchip,gpio-bank";
1013                         reg = <0x0 0xff788000 0x0 0x100>;
1014                         clocks = <&cru PCLK_GPIO3>;
1015                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1016
1017                         gpio-controller;
1018                         #gpio-cells = <0x2>;
1019
1020                         interrupt-controller;
1021                         #interrupt-cells = <0x2>;
1022                 };
1023
1024                 gpio4: gpio4@ff790000 {
1025                         compatible = "rockchip,gpio-bank";
1026                         reg = <0x0 0xff790000 0x0 0x100>;
1027                         clocks = <&cru PCLK_GPIO4>;
1028                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1029
1030                         gpio-controller;
1031                         #gpio-cells = <0x2>;
1032
1033                         interrupt-controller;
1034                         #interrupt-cells = <0x2>;
1035                 };
1036
1037                 pcfg_pull_up: pcfg-pull-up {
1038                         bias-pull-up;
1039                 };
1040
1041                 pcfg_pull_down: pcfg-pull-down {
1042                         bias-pull-down;
1043                 };
1044
1045                 pcfg_pull_none: pcfg-pull-none {
1046                         bias-disable;
1047                 };
1048
1049                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1050                         bias-disable;
1051                         drive-strength = <12>;
1052                 };
1053
1054                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1055                         bias-pull-up;
1056                         drive-strength = <8>;
1057                 };
1058
1059                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1060                         bias-pull-down;
1061                         drive-strength = <4>;
1062                 };
1063
1064                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1065                         bias-pull-up;
1066                         drive-strength = <2>;
1067                 };
1068
1069                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1070                         bias-pull-down;
1071                         drive-strength = <12>;
1072                 };
1073
1074                 emmc {
1075                         emmc_pwr: emmc-pwr {
1076                                 rockchip,pins =
1077                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1078                         };
1079                 };
1080
1081                 gmac {
1082                         rgmii_pins: rgmii-pins {
1083                                 rockchip,pins =
1084                                         /* mac_txclk */
1085                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1086                                         /* mac_rxclk */
1087                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1088                                         /* mac_mdio */
1089                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1090                                         /* mac_txen */
1091                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1092                                         /* mac_clk */
1093                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1094                                         /* mac_rxdv */
1095                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1096                                         /* mac_mdc */
1097                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1098                                         /* mac_rxd1 */
1099                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1100                                         /* mac_rxd0 */
1101                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1102                                         /* mac_txd1 */
1103                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1104                                         /* mac_txd0 */
1105                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1106                                         /* mac_rxd3 */
1107                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1108                                         /* mac_rxd2 */
1109                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1110                                         /* mac_txd3 */
1111                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1112                                         /* mac_txd2 */
1113                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1114                         };
1115
1116                         rmii_pins: rmii-pins {
1117                                 rockchip,pins =
1118                                         /* mac_mdio */
1119                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1120                                         /* mac_txen */
1121                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1122                                         /* mac_clk */
1123                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1124                                         /* mac_rxer */
1125                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1126                                         /* mac_rxdv */
1127                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1128                                         /* mac_mdc */
1129                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1130                                         /* mac_rxd1 */
1131                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1132                                         /* mac_rxd0 */
1133                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1134                                         /* mac_txd1 */
1135                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1136                                         /* mac_txd0 */
1137                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1138                         };
1139                 };
1140
1141                 i2c0 {
1142                         i2c0_xfer: i2c0-xfer {
1143                                 rockchip,pins =
1144                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1145                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1146                         };
1147                 };
1148
1149                 i2c1 {
1150                         i2c1_xfer: i2c1-xfer {
1151                                 rockchip,pins =
1152                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1153                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1154                         };
1155                 };
1156
1157                 i2c2 {
1158                         i2c2_xfer: i2c2-xfer {
1159                                 rockchip,pins =
1160                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1161                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1162                         };
1163                 };
1164
1165                 i2c3 {
1166                         i2c3_xfer: i2c3-xfer {
1167                                 rockchip,pins =
1168                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1169                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2c4 {
1174                         i2c4_xfer: i2c4-xfer {
1175                                 rockchip,pins =
1176                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1177                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 i2c5 {
1182                         i2c5_xfer: i2c5-xfer {
1183                                 rockchip,pins =
1184                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1185                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 i2c6 {
1190                         i2c6_xfer: i2c6-xfer {
1191                                 rockchip,pins =
1192                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1193                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1194                         };
1195                 };
1196
1197                 i2c7 {
1198                         i2c7_xfer: i2c7-xfer {
1199                                 rockchip,pins =
1200                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1201                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 i2c8 {
1206                         i2c8_xfer: i2c8-xfer {
1207                                 rockchip,pins =
1208                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1209                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 i2s0 {
1214                         i2s0_8ch_bus: i2s0-8ch-bus {
1215                                 rockchip,pins =
1216                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1217                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1218                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1219                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1220                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1221                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1222                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1223                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1224                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 i2s1 {
1229                         i2s1_2ch_bus: i2s1-2ch-bus {
1230                                 rockchip,pins =
1231                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1232                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1233                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1234                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1235                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1236                         };
1237                 };
1238
1239                 sdio0 {
1240                         sdio0_bus1: sdio0-bus1 {
1241                                 rockchip,pins =
1242                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1243                         };
1244
1245                         sdio0_bus4: sdio0-bus4 {
1246                                 rockchip,pins =
1247                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1248                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1249                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1250                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1251                         };
1252
1253                         sdio0_cmd: sdio0-cmd {
1254                                 rockchip,pins =
1255                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1256                         };
1257
1258                         sdio0_clk: sdio0-clk {
1259                                 rockchip,pins =
1260                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1261                         };
1262
1263                         sdio0_cd: sdio0-cd {
1264                                 rockchip,pins =
1265                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1266                         };
1267
1268                         sdio0_pwr: sdio0-pwr {
1269                                 rockchip,pins =
1270                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1271                         };
1272
1273                         sdio0_bkpwr: sdio0-bkpwr {
1274                                 rockchip,pins =
1275                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio0_wp: sdio0-wp {
1279                                 rockchip,pins =
1280                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1281                         };
1282
1283                         sdio0_int: sdio0-int {
1284                                 rockchip,pins =
1285                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287                 };
1288
1289                 sdmmc {
1290                         sdmmc_bus1: sdmmc-bus1 {
1291                                 rockchip,pins =
1292                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1293                         };
1294
1295                         sdmmc_bus4: sdmmc-bus4 {
1296                                 rockchip,pins =
1297                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1298                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1299                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1300                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1301                         };
1302
1303                         sdmmc_clk: sdmmc-clk {
1304                                 rockchip,pins =
1305                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307
1308                         sdmmc_cmd: sdmmc-cmd {
1309                                 rockchip,pins =
1310                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1311                         };
1312
1313                         sdmmc_cd: sdmcc-cd {
1314                                 rockchip,pins =
1315                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1316                         };
1317
1318                         sdmmc_wp: sdmmc-wp {
1319                                 rockchip,pins =
1320                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1321                         };
1322                 };
1323
1324                 spdif {
1325                         spdif_bus: spdif-bus {
1326                                 rockchip,pins =
1327                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1328                         };
1329                 };
1330
1331                 spi0 {
1332                         spi0_clk: spi0-clk {
1333                                 rockchip,pins =
1334                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1335                         };
1336                         spi0_cs0: spi0-cs0 {
1337                                 rockchip,pins =
1338                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1339                         };
1340                         spi0_cs1: spi0-cs1 {
1341                                 rockchip,pins =
1342                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1343                         };
1344                         spi0_tx: spi0-tx {
1345                                 rockchip,pins =
1346                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1347                         };
1348                         spi0_rx: spi0-rx {
1349                                 rockchip,pins =
1350                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1351                         };
1352                 };
1353
1354                 spi1 {
1355                         spi1_clk: spi1-clk {
1356                                 rockchip,pins =
1357                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_cs0: spi1-cs0 {
1360                                 rockchip,pins =
1361                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1362                         };
1363                         spi1_rx: spi1-rx {
1364                                 rockchip,pins =
1365                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1366                         };
1367                         spi1_tx: spi1-tx {
1368                                 rockchip,pins =
1369                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1370                         };
1371                 };
1372
1373                 spi2 {
1374                         spi2_clk: spi2-clk {
1375                                 rockchip,pins =
1376                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378                         spi2_cs0: spi2-cs0 {
1379                                 rockchip,pins =
1380                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382                         spi2_rx: spi2-rx {
1383                                 rockchip,pins =
1384                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386                         spi2_tx: spi2-tx {
1387                                 rockchip,pins =
1388                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1389                         };
1390                 };
1391
1392                 spi3 {
1393                         spi3_clk: spi3-clk {
1394                                 rockchip,pins =
1395                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397                         spi3_cs0: spi3-cs0 {
1398                                 rockchip,pins =
1399                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1400                         };
1401                         spi3_rx: spi3-rx {
1402                                 rockchip,pins =
1403                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1404                         };
1405                         spi3_tx: spi3-tx {
1406                                 rockchip,pins =
1407                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1408                         };
1409                 };
1410
1411                 spi4 {
1412                         spi4_clk: spi4-clk {
1413                                 rockchip,pins =
1414                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1415                         };
1416                         spi4_cs0: spi4-cs0 {
1417                                 rockchip,pins =
1418                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1419                         };
1420                         spi4_rx: spi4-rx {
1421                                 rockchip,pins =
1422                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1423                         };
1424                         spi4_tx: spi4-tx {
1425                                 rockchip,pins =
1426                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1427                         };
1428                 };
1429
1430                 spi5 {
1431                         spi5_clk: spi5-clk {
1432                                 rockchip,pins =
1433                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1434                         };
1435                         spi5_cs0: spi5-cs0 {
1436                                 rockchip,pins =
1437                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1438                         };
1439                         spi5_rx: spi5-rx {
1440                                 rockchip,pins =
1441                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1442                         };
1443                         spi5_tx: spi5-tx {
1444                                 rockchip,pins =
1445                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1446                         };
1447                 };
1448
1449                 tsadc {
1450                         otp_gpio: otp-gpio {
1451                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1452                         };
1453
1454                         otp_out: otp-out {
1455                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 uart0 {
1460                         uart0_xfer: uart0-xfer {
1461                                 rockchip,pins =
1462                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1463                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465
1466                         uart0_cts: uart0-cts {
1467                                 rockchip,pins =
1468                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470
1471                         uart0_rts: uart0-rts {
1472                                 rockchip,pins =
1473                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1474                         };
1475                 };
1476
1477                 uart1 {
1478                         uart1_xfer: uart1-xfer {
1479                                 rockchip,pins =
1480                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1481                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 uart2a {
1486                         uart2a_xfer: uart2a-xfer {
1487                                 rockchip,pins =
1488                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1489                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 uart2b {
1494                         uart2b_xfer: uart2b-xfer {
1495                                 rockchip,pins =
1496                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1497                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 uart2c {
1502                         uart2c_xfer: uart2c-xfer {
1503                                 rockchip,pins =
1504                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1505                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 uart3 {
1510                         uart3_xfer: uart3-xfer {
1511                                 rockchip,pins =
1512                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1513                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1514                         };
1515
1516                         uart3_cts: uart3-cts {
1517                                 rockchip,pins =
1518                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1519                         };
1520
1521                         uart3_rts: uart3-rts {
1522                                 rockchip,pins =
1523                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 uart4 {
1528                         uart4_xfer: uart4-xfer {
1529                                 rockchip,pins =
1530                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1531                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 uarthdcp {
1536                         uarthdcp_xfer: uarthdcp-xfer {
1537                                 rockchip,pins =
1538                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1539                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1540                         };
1541                 };
1542
1543                 pwm0 {
1544                         pwm0_pin: pwm0-pin {
1545                                 rockchip,pins =
1546                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1547                         };
1548
1549                         vop0_pwm_pin: vop0-pwm-pin {
1550                                 rockchip,pins =
1551                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 pwm1 {
1556                         pwm1_pin: pwm1-pin {
1557                                 rockchip,pins =
1558                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1559                         };
1560
1561                         vop1_pwm_pin: vop1-pwm-pin {
1562                                 rockchip,pins =
1563                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1564                         };
1565                 };
1566
1567                 pwm2 {
1568                         pwm2_pin: pwm2-pin {
1569                                 rockchip,pins =
1570                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1571                         };
1572                 };
1573
1574                 pwm3a {
1575                         pwm3a_pin: pwm3a-pin {
1576                                 rockchip,pins =
1577                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1578                         };
1579                 };
1580
1581                 pwm3b {
1582                         pwm3b_pin: pwm3b-pin {
1583                                 rockchip,pins =
1584                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1585                         };
1586                 };
1587
1588                 pmic {
1589                         pmic_int_l: pmic-int-l {
1590                                 rockchip,pins =
1591                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1592                         };
1593                 };
1594         };
1595 };