arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 status = "disabled";
 326         };
 327
 328         emmc_phy: phy {
 329                 compatible = "rockchip,rk3399-emmc-phy";
 330                 reg-offset = <0xf780>;
 331                 #phy-cells = <0>;
 332                 rockchip,grf = <&grf>;
 333                 ctrl-base = <0xfe330000>;
 334                 status = "disabled";
 335         };
 336
 337         sdio0: dwmmc@fe310000 {
 338                 compatible = "rockchip,rk3399-dw-mshc",
 339                              "rockchip,rk3288-dw-mshc";
 340                 reg = <0x0 0xfe310000 0x0 0x4000>;
 341                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 344                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 346                 fifo-depth = <0x100>;
 347                 status = "disabled";
 348         };
 349
 350         sdmmc: dwmmc@fe320000 {
 351                 compatible = "rockchip,rk3399-dw-mshc",
 352                              "rockchip,rk3288-dw-mshc";
 353                 reg = <0x0 0xfe320000 0x0 0x4000>;
 354                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clock-freq-min-max = <400000 150000000>;
 356                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 357                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 358                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 359                 fifo-depth = <0x100>;
 360                 status = "disabled";
 361         };
 362
 363         sdhci: sdhci@fe330000 {
 364                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 365                 reg = <0x0 0xfe330000 0x0 0x10000>;
 366                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 367                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 368                 clock-names = "clk_xin", "clk_ahb";
 369                 assigned-clocks = <&cru SCLK_EMMC>;
 370                 assigned-clock-parents = <&cru PLL_CPLL>;
 371                 assigned-clock-rates = <200000000>;
 372                 phys = <&emmc_phy>;
 373                 phy-names = "phy_arasan";
 374                 status = "disabled";
 375         };
 376
 377         usb_host0_ehci: usb@fe380000 {
 378                 compatible = "generic-ehci";
 379                 reg = <0x0 0xfe380000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 382                          <&cru SCLK_USBPHY0_480M_SRC>;
 383                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 384                 phys = <&u2phy0_host>;
 385                 phy-names = "usb";
 386                 status = "disabled";
 387         };
 388
 389         usb_host0_ohci: usb@fe3a0000 {
 390                 compatible = "generic-ohci";
 391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 394                          <&cru SCLK_USBPHY0_480M_SRC>;
 395                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 396                 phys = <&u2phy0_host>;
 397                 phy-names = "usb";
 398                 status = "disabled";
 399         };
 400
 401         usb_host1_ehci: usb@fe3c0000 {
 402                 compatible = "generic-ehci";
 403                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 404                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 405                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 406                          <&cru SCLK_USBPHY1_480M_SRC>;
 407                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 408                 phys = <&u2phy1_host>;
 409                 phy-names = "usb";
 410                 status = "disabled";
 411         };
 412
 413         usb_host1_ohci: usb@fe3e0000 {
 414                 compatible = "generic-ohci";
 415                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 416                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 417                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 418                          <&cru SCLK_USBPHY1_480M_SRC>;
 419                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 420                 phys = <&u2phy1_host>;
 421                 phy-names = "usb";
 422                 status = "disabled";
 423         };
 424
 425         usbdrd3_0: usb@fe800000 {
 426                 compatible = "rockchip,dwc3";
 427                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 428                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 429                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 430                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 431                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 432                               "aclk_usb3", "aclk_usb3_grf";
 433                 #address-cells = <2>;
 434                 #size-cells = <2>;
 435                 ranges;
 436                 status = "disabled";
 437                 usbdrd_dwc3_0: dwc3@fe800000 {
 438                         compatible = "snps,dwc3";
 439                         reg = <0x0 0xfe800000 0x0 0x100000>;
 440                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 441                         dr_mode = "otg";
 442                         snps,dis_enblslpm_quirk;
 443                         snps,phyif_utmi_16_bits;
 444                         snps,dis_u2_freeclk_exists_quirk;
 445                         snps,dis_del_phy_power_chg_quirk;
 446                         snps,xhci_slow_suspend_quirk;
 447                         status = "disabled";
 448                 };
 449         };
 450
 451         usbdrd3_1: usb@fe900000 {
 452                 compatible = "rockchip,dwc3";
 453                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 454                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 455                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 456                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 457                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 458                               "aclk_usb3", "aclk_usb3_grf";
 459                 #address-cells = <2>;
 460                 #size-cells = <2>;
 461                 ranges;
 462                 status = "disabled";
 463                 usbdrd_dwc3_1: dwc3@fe900000 {
 464                         compatible = "snps,dwc3";
 465                         reg = <0x0 0xfe900000 0x0 0x100000>;
 466                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 467                         dr_mode = "otg";
 468                         snps,dis_enblslpm_quirk;
 469                         snps,phyif_utmi_16_bits;
 470                         snps,dis_u2_freeclk_exists_quirk;
 471                         snps,dis_del_phy_power_chg_quirk;
 472                         snps,xhci_slow_suspend_quirk;
 473                         status = "disabled";
 474                 };
 475         };
 476
 477         gic: interrupt-controller@fee00000 {
 478                 compatible = "arm,gic-v3";
 479                 #interrupt-cells = <4>;
 480                 #address-cells = <2>;
 481                 #size-cells = <2>;
 482                 ranges;
 483                 interrupt-controller;
 484
 485                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 486                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 487                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 488                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 489                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 490                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 491                 its: interrupt-controller@fee20000 {
 492                         compatible = "arm,gic-v3-its";
 493                         msi-controller;
 494                         reg = <0x0 0xfee20000 0x0 0x20000>;
 495                 };
 496
 497                 ppi-partitions {
 498                         part0: interrupt-partition-0 {
 499                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 500                         };
 501
 502                         part1: interrupt-partition-1 {
 503                                 affinity = <&cpu_b0 &cpu_b1>;
 504                         };
 505                 };
 506         };
 507
 508         saradc: saradc@ff100000 {
 509                 compatible = "rockchip,rk3399-saradc";
 510                 reg = <0x0 0xff100000 0x0 0x100>;
 511                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 #io-channel-cells = <1>;
 513                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 514                 clock-names = "saradc", "apb_pclk";
 515                 status = "disabled";
 516         };
 517
 518         i2c0: i2c@ff3c0000 {
 519                 compatible = "rockchip,rk3399-i2c";
 520                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 521                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 522                 clock-names = "i2c", "pclk";
 523                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c0_xfer>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         i2c1: i2c@ff110000 {
 532                 compatible = "rockchip,rk3399-i2c";
 533                 reg = <0x0 0xff110000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 535                 clock-names = "i2c", "pclk";
 536                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c1_xfer>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         i2c2: i2c@ff120000 {
 545                 compatible = "rockchip,rk3399-i2c";
 546                 reg = <0x0 0xff120000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c2_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c3: i2c@ff130000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff130000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 561                 clock-names = "i2c", "pclk";
 562                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c3_xfer>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c5: i2c@ff140000 {
 571                 compatible = "rockchip,rk3399-i2c";
 572                 reg = <0x0 0xff140000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c5_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c6: i2c@ff150000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff150000 0x0 0x1000>;
 586                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c6_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         i2c7: i2c@ff160000 {
 597                 compatible = "rockchip,rk3399-i2c";
 598                 reg = <0x0 0xff160000 0x0 0x1000>;
 599                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 600                 clock-names = "i2c", "pclk";
 601                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c7_xfer>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 status = "disabled";
 607         };
 608
 609         uart0: serial@ff180000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff180000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 619                 status = "disabled";
 620         };
 621
 622         uart1: serial@ff190000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff190000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart1_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart2: serial@ff1a0000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff1a0000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart2c_xfer>;
 645                 status = "disabled";
 646         };
 647
 648         uart3: serial@ff1b0000 {
 649                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 650                 reg = <0x0 0xff1b0000 0x0 0x100>;
 651                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 658                 status = "disabled";
 659         };
 660
 661         spi0: spi@ff1c0000 {
 662                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 663                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 664                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 665                 clock-names = "spiclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         spi1: spi@ff1d0000 {
 675                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 676                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 677                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 678                 clock-names = "spiclk", "apb_pclk";
 679                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         spi2: spi@ff1e0000 {
 688                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 689                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 690                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 691                 clock-names = "spiclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi4: spi@ff1f0000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         spi5: spi@ff200000 {
 714                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 715                 reg = <0x0 0xff200000 0x0 0x1000>;
 716                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 717                 clock-names = "spiclk", "apb_pclk";
 718                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 719                 pinctrl-names = "default";
 720                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 721                 #address-cells = <1>;
 722                 #size-cells = <0>;
 723                 status = "disabled";
 724         };
 725
 726         thermal-zones {
 727                 soc_thermal: soc-thermal {
 728                         polling-delay-passive = <20>; /* milliseconds */
 729                         polling-delay = <1000>; /* milliseconds */
 730                         sustainable-power = <1000>; /* milliwatts */
 731
 732                         thermal-sensors = <&tsadc 0>;
 733
 734                         trips {
 735                                 threshold: trip-point@0 {
 736                                         temperature = <70000>; /* millicelsius */
 737                                         hysteresis = <2000>; /* millicelsius */
 738                                         type = "passive";
 739                                 };
 740                                 target: trip-point@1 {
 741                                         temperature = <85000>; /* millicelsius */
 742                                         hysteresis = <2000>; /* millicelsius */
 743                                         type = "passive";
 744                                 };
 745                                 soc_crit: soc-crit {
 746                                         temperature = <95000>; /* millicelsius */
 747                                         hysteresis = <2000>; /* millicelsius */
 748                                         type = "critical";
 749                                 };
 750                         };
 751
 752                         cooling-maps {
 753                                 map0 {
 754                                         trip = <&target>;
 755                                         cooling-device =
 756                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 757                                         contribution = <4096>;
 758                                 };
 759                                 map1 {
 760                                         trip = <&target>;
 761                                         cooling-device =
 762                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 763                                         contribution = <1024>;
 764                                 };
 765                                 map2 {
 766                                         trip = <&target>;
 767                                         cooling-device =
 768                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 769                                         contribution = <4096>;
 770                                 };
 771                         };
 772                 };
 773
 774                 gpu_thermal: gpu-thermal {
 775                         polling-delay-passive = <100>; /* milliseconds */
 776                         polling-delay = <1000>; /* milliseconds */
 777
 778                         thermal-sensors = <&tsadc 1>;
 779                 };
 780         };
 781
 782         tsadc: tsadc@ff260000 {
 783                 compatible = "rockchip,rk3399-tsadc";
 784                 reg = <0x0 0xff260000 0x0 0x100>;
 785                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 786                 rockchip,grf = <&grf>;
 787                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 788                 clock-names = "tsadc", "apb_pclk";
 789                 assigned-clocks = <&cru SCLK_TSADC>;
 790                 assigned-clock-rates = <750000>;
 791                 resets = <&cru SRST_TSADC>;
 792                 reset-names = "tsadc-apb";
 793                 pinctrl-names = "init", "default", "sleep";
 794                 pinctrl-0 = <&otp_gpio>;
 795                 pinctrl-1 = <&otp_out>;
 796                 pinctrl-2 = <&otp_gpio>;
 797                 #thermal-sensor-cells = <1>;
 798                 rockchip,hw-tshut-temp = <95000>;
 799                 status = "disabled";
 800         };
 801
 802         qos_hdcp: qos@ffa90000 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffa90000 0x0 0x20>;
 805         };
 806
 807         qos_iep: qos@ffa98000 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffa98000 0x0 0x20>;
 810         };
 811
 812         qos_isp0_m0: qos@ffaa0000 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffaa0000 0x0 0x20>;
 815         };
 816
 817         qos_isp0_m1: qos@ffaa0080 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffaa0080 0x0 0x20>;
 820         };
 821
 822         qos_isp1_m0: qos@ffaa8000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffaa8000 0x0 0x20>;
 825         };
 826
 827         qos_isp1_m1: qos@ffaa8080 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffaa8080 0x0 0x20>;
 830         };
 831
 832         qos_rga_r: qos@ffab0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffab0000 0x0 0x20>;
 835         };
 836
 837         qos_rga_w: qos@ffab0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffab0080 0x0 0x20>;
 840         };
 841
 842         qos_video_m0: qos@ffab8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffab8000 0x0 0x20>;
 845         };
 846
 847         qos_video_m1_r: qos@ffac0000 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffac0000 0x0 0x20>;
 850         };
 851
 852         qos_video_m1_w: qos@ffac0080 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffac0080 0x0 0x20>;
 855         };
 856
 857         qos_vop_big_r: qos@ffac8000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffac8000 0x0 0x20>;
 860         };
 861
 862         qos_vop_big_w: qos@ffac8080 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffac8080 0x0 0x20>;
 865         };
 866
 867         qos_vop_little: qos@ffad0000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffad0000 0x0 0x20>;
 870         };
 871
 872         qos_gpu: qos@ffae0000 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffae0000 0x0 0x20>;
 875         };
 876
 877         pmu: power-management@ff310000 {
 878                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 879                 reg = <0x0 0xff310000 0x0 0x1000>;
 880
 881                 /*
 882                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 883                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 884                  * Some of the power domains are grouped together for every
 885                  * voltage domain.
 886                  * The detail contents as below.
 887                  */
 888                 power: power-controller {
 889                         compatible = "rockchip,rk3399-power-controller";
 890                         #power-domain-cells = <1>;
 891                         #address-cells = <1>;
 892                         #size-cells = <0>;
 893
 894                         /* These power domains are grouped by VD_CENTER */
 895                         pd_iep@RK3399_PD_IEP {
 896                                 reg = <RK3399_PD_IEP>;
 897                                 clocks = <&cru ACLK_IEP>,
 898                                          <&cru HCLK_IEP>;
 899                                 pm_qos = <&qos_iep>;
 900                         };
 901                         pd_rga@RK3399_PD_RGA {
 902                                 reg = <RK3399_PD_RGA>;
 903                                 clocks = <&cru ACLK_RGA>,
 904                                          <&cru HCLK_RGA>;
 905                                 pm_qos = <&qos_rga_r>,
 906                                          <&qos_rga_w>;
 907                         };
 908                         pd_vcodec@RK3399_PD_VCODEC {
 909                                 reg = <RK3399_PD_VCODEC>;
 910                                 clocks = <&cru ACLK_VCODEC>,
 911                                          <&cru HCLK_VCODEC>;
 912                                 pm_qos = <&qos_video_m0>;
 913                         };
 914                         pd_vdu@RK3399_PD_VDU {
 915                                 reg = <RK3399_PD_VDU>;
 916                                 clocks = <&cru ACLK_VDU>,
 917                                          <&cru HCLK_VDU>;
 918                                 pm_qos = <&qos_video_m1_r>,
 919                                          <&qos_video_m1_w>;
 920                         };
 921
 922                         /* These power domains are grouped by VD_GPU */
 923                         pd_gpu@RK3399_PD_GPU {
 924                                 reg = <RK3399_PD_GPU>;
 925                                 clocks = <&cru ACLK_GPU>;
 926                                 pm_qos = <&qos_gpu>;
 927                         };
 928
 929                         /* These power domains are grouped by VD_LOGIC */
 930                         pd_vio@RK3399_PD_VIO {
 931                                 reg = <RK3399_PD_VIO>;
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934
 935                                 pd_hdcp@RK3399_PD_HDCP {
 936                                         reg = <RK3399_PD_HDCP>;
 937                                         clocks = <&cru ACLK_HDCP>,
 938                                                  <&cru HCLK_HDCP>,
 939                                                  <&cru PCLK_HDCP>;
 940                                         pm_qos = <&qos_hdcp>;
 941                                 };
 942                                 pd_isp0@RK3399_PD_ISP0 {
 943                                         reg = <RK3399_PD_ISP0>;
 944                                         clocks = <&cru ACLK_ISP0>,
 945                                                  <&cru HCLK_ISP0>;
 946                                         pm_qos = <&qos_isp0_m0>,
 947                                                  <&qos_isp0_m1>;
 948                                 };
 949                                 pd_isp1@RK3399_PD_ISP1 {
 950                                         reg = <RK3399_PD_ISP1>;
 951                                         clocks = <&cru ACLK_ISP1>,
 952                                                  <&cru HCLK_ISP1>;
 953                                         pm_qos = <&qos_isp1_m0>,
 954                                                  <&qos_isp1_m1>;
 955                                 };
 956                                 pd_vo@RK3399_PD_VO {
 957                                         reg = <RK3399_PD_VO>;
 958                                         #address-cells = <1>;
 959                                         #size-cells = <0>;
 960
 961                                         pd_vopb@RK3399_PD_VOPB {
 962                                                 reg = <RK3399_PD_VOPB>;
 963                                                 clocks = <&cru ACLK_VOP0>,
 964                                                          <&cru HCLK_VOP0>;
 965                                                 pm_qos = <&qos_vop_big_r>,
 966                                                          <&qos_vop_big_w>;
 967                                         };
 968                                         pd_vopl@RK3399_PD_VOPL {
 969                                                 reg = <RK3399_PD_VOPL>;
 970                                                 clocks = <&cru ACLK_VOP1>,
 971                                                          <&cru HCLK_VOP1>;
 972                                                 pm_qos = <&qos_vop_little>;
 973                                         };
 974                                 };
 975                         };
 976                 };
 977         };
 978
 979         pmugrf: syscon@ff320000 {
 980                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 981                 reg = <0x0 0xff320000 0x0 0x1000>;
 982
 983                 reboot-mode {
 984                         compatible = "syscon-reboot-mode";
 985                         offset = <0x300>;
 986                         mode-bootloader = <BOOT_LOADER>;
 987                         mode-charge = <BOOT_CHARGING>;
 988                         mode-fastboot = <BOOT_FASTBOOT>;
 989                         mode-loader = <BOOT_LOADER>;
 990                         mode-normal = <BOOT_NORMAL>;
 991                         mode-recovery = <BOOT_RECOVERY>;
 992                 };
 993         };
 994
 995         spi3: spi@ff350000 {
 996                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 997                 reg = <0x0 0xff350000 0x0 0x1000>;
 998                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 999                 clock-names = "spiclk", "apb_pclk";
1000                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1001                 pinctrl-names = "default";
1002                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1003                 #address-cells = <1>;
1004                 #size-cells = <0>;
1005                 status = "disabled";
1006         };
1007
1008         uart4: serial@ff370000 {
1009                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1010                 reg = <0x0 0xff370000 0x0 0x100>;
1011                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1012                 clock-names = "baudclk", "apb_pclk";
1013                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1014                 reg-shift = <2>;
1015                 reg-io-width = <4>;
1016                 pinctrl-names = "default";
1017                 pinctrl-0 = <&uart4_xfer>;
1018                 status = "disabled";
1019         };
1020
1021         i2c4: i2c@ff3d0000 {
1022                 compatible = "rockchip,rk3399-i2c";
1023                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1024                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1025                 clock-names = "i2c", "pclk";
1026                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1027                 pinctrl-names = "default";
1028                 pinctrl-0 = <&i2c4_xfer>;
1029                 #address-cells = <1>;
1030                 #size-cells = <0>;
1031                 status = "disabled";
1032         };
1033
1034         i2c8: i2c@ff3e0000 {
1035                 compatible = "rockchip,rk3399-i2c";
1036                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1037                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1038                 clock-names = "i2c", "pclk";
1039                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1040                 pinctrl-names = "default";
1041                 pinctrl-0 = <&i2c8_xfer>;
1042                 #address-cells = <1>;
1043                 #size-cells = <0>;
1044                 status = "disabled";
1045         };
1046
1047         pcie0: pcie@f8000000 {
1048                 compatible = "rockchip,rk3399-pcie";
1049                 #address-cells = <3>;
1050                 #size-cells = <2>;
1051                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1052                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1053                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1054                               "hclk_pcie", "clk_pciephy_ref";
1055                 bus-range = <0x0 0x1>;
1056                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1057                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1058                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1059                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1060                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1061                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1062                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1063                       < 0x0 0xfd000000 0x0 0x1000000 >;
1064                 reg-name = "axi-base", "apb-base";
1065                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1066                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1067                          <&cru SRST_PCIE_PIPE>;
1068                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1069                               "mgmt-sticky-rst", "pipe-rst";
1070                 rockchip,grf = <&grf>;
1071                 pcie-conf = <0xe220>;
1072                 pcie-status = <0xe2a4>;
1073                 pcie-laneoff = <0xe214>;
1074                 msi-parent = <&its>;
1075                 #interrupt-cells = <1>;
1076                 interrupt-map-mask = <0 0 0 7>;
1077                 interrupt-map = <0 0 0 1 &pcie0 1>,
1078                                 <0 0 0 2 &pcie0 2>,
1079                                 <0 0 0 3 &pcie0 3>,
1080                                 <0 0 0 4 &pcie0 4>;
1081                 status = "disabled";
1082                 pcie_intc: interrupt-controller {
1083                         interrupt-controller;
1084                         #address-cells = <0>;
1085                         #interrupt-cells = <1>;
1086                 };
1087         };
1088
1089         pwm0: pwm@ff420000 {
1090                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1091                 reg = <0x0 0xff420000 0x0 0x10>;
1092                 #pwm-cells = <3>;
1093                 pinctrl-names = "default";
1094                 pinctrl-0 = <&pwm0_pin>;
1095                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1096                 clock-names = "pwm";
1097                 status = "disabled";
1098         };
1099
1100         pwm1: pwm@ff420010 {
1101                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1102                 reg = <0x0 0xff420010 0x0 0x10>;
1103                 #pwm-cells = <3>;
1104                 pinctrl-names = "default";
1105                 pinctrl-0 = <&pwm1_pin>;
1106                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1107                 clock-names = "pwm";
1108                 status = "disabled";
1109         };
1110
1111         pwm2: pwm@ff420020 {
1112                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1113                 reg = <0x0 0xff420020 0x0 0x10>;
1114                 #pwm-cells = <3>;
1115                 pinctrl-names = "default";
1116                 pinctrl-0 = <&pwm2_pin>;
1117                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1118                 clock-names = "pwm";
1119                 status = "disabled";
1120         };
1121
1122         pwm3: pwm@ff420030 {
1123                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1124                 reg = <0x0 0xff420030 0x0 0x10>;
1125                 #pwm-cells = <3>;
1126                 pinctrl-names = "default";
1127                 pinctrl-0 = <&pwm3a_pin>;
1128                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1129                 clock-names = "pwm";
1130                 status = "disabled";
1131         };
1132
1133         rga: rga@ff680000 {
1134                 compatible = "rockchip,rk3399-rga";
1135                 reg = <0x0 0xff680000 0x0 0x10000>;
1136                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1137                 interrupt-names = "rga";
1138                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1139                 clock-names = "aclk", "hclk", "sclk";
1140                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1141                 reset-names = "core", "axi", "ahb";
1142                 status = "disabled";
1143         };
1144
1145         pmucru: pmu-clock-controller@ff750000 {
1146                 compatible = "rockchip,rk3399-pmucru";
1147                 reg = <0x0 0xff750000 0x0 0x1000>;
1148                 #clock-cells = <1>;
1149                 #reset-cells = <1>;
1150                 assigned-clocks = <&pmucru PLL_PPLL>;
1151                 assigned-clock-rates = <676000000>;
1152         };
1153
1154         cru: clock-controller@ff760000 {
1155                 compatible = "rockchip,rk3399-cru";
1156                 reg = <0x0 0xff760000 0x0 0x1000>;
1157                 #clock-cells = <1>;
1158                 #reset-cells = <1>;
1159                 assigned-clocks =
1160                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1161                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1162                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1163                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1164                         <&cru PLL_NPLL>,
1165                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1166                         <&cru PCLK_PERIHP>,
1167                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1168                         <&cru PCLK_PERILP0>,
1169                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1170                 assigned-clock-rates =
1171                          <400000000>,  <200000000>,
1172                          <400000000>,  <200000000>,
1173                          <816000000>, <816000000>,
1174                          <594000000>,  <800000000>,
1175                         <1000000000>,
1176                          <150000000>,   <75000000>,
1177                           <37500000>,
1178                          <100000000>,  <100000000>,
1179                           <50000000>,
1180                          <100000000>,   <50000000>;
1181         };
1182
1183         grf: syscon@ff770000 {
1184                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1185                 reg = <0x0 0xff770000 0x0 0x10000>;
1186                 #address-cells = <1>;
1187                 #size-cells = <1>;
1188
1189                 u2phy0: usb2-phy@e450 {
1190                         compatible = "rockchip,rk3399-usb2phy";
1191                         reg = <0xe450 0x10>;
1192                         clocks = <&cru SCLK_USB2PHY0_REF>;
1193                         clock-names = "phyclk";
1194                         #clock-cells = <0>;
1195                         clock-output-names = "clk_usbphy0_480m";
1196                         status = "disabled";
1197
1198                         u2phy0_otg: otg-port {
1199                                 #phy-cells = <0>;
1200                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1201                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1202                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1203                                 interrupt-names = "otg-bvalid", "otg-id",
1204                                                   "linestate";
1205                                 status = "disabled";
1206                         };
1207
1208                         u2phy0_host: host-port {
1209                                 #phy-cells = <0>;
1210                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1211                                 interrupt-names = "linestate";
1212                                 status = "disabled";
1213                         };
1214                 };
1215
1216                 u2phy1: usb2-phy@e460 {
1217                         compatible = "rockchip,rk3399-usb2phy";
1218                         reg = <0xe460 0x10>;
1219                         clocks = <&cru SCLK_USB2PHY1_REF>;
1220                         clock-names = "phyclk";
1221                         #clock-cells = <0>;
1222                         clock-output-names = "clk_usbphy1_480m";
1223                         status = "disabled";
1224
1225                         u2phy1_otg: otg-port {
1226                                 #phy-cells = <0>;
1227                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1228                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1229                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1230                                 interrupt-names = "otg-bvalid", "otg-id",
1231                                                   "linestate";
1232                                 status = "disabled";
1233                         };
1234
1235                         u2phy1_host: host-port {
1236                                 #phy-cells = <0>;
1237                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1238                                 interrupt-names = "linestate";
1239                                 status = "disabled";
1240                         };
1241                 };
1242         };
1243
1244         tcphy0: phy@ff7c0000 {
1245                 compatible = "rockchip,rk3399-typec-phy";
1246                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1247                 rockchip,grf = <&grf>;
1248                 #phy-cells = <0>;
1249                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1250                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1251                 clock-names = "tcpdcore", "tcpdphy-ref";
1252                 resets = <&cru SRST_UPHY0>,
1253                          <&cru SRST_UPHY0_PIPE_L00>,
1254                          <&cru SRST_P_UPHY0_TCPHY>;
1255                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1256                 rockchip,typec-conn-dir = <0xe580 0 16>;
1257                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1258                 rockchip,external-psm = <0xe588 14 30>;
1259                 rockchip,pipe-status = <0xe5c0 0 0>;
1260                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1261                 status = "disabled";
1262         };
1263
1264         tcphy1: phy@ff800000 {
1265                 compatible = "rockchip,rk3399-typec-phy";
1266                 reg = <0x0 0xff800000 0x0 0x40000>;
1267                 rockchip,grf = <&grf>;
1268                 #phy-cells = <0>;
1269                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1270                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1271                 clock-names = "tcpdcore", "tcpdphy-ref";
1272                 resets = <&cru SRST_UPHY1>,
1273                          <&cru SRST_UPHY1_PIPE_L00>,
1274                          <&cru SRST_P_UPHY1_TCPHY>;
1275                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1276                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1277                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1278                 rockchip,external-psm = <0xe594 14 30>;
1279                 rockchip,pipe-status = <0xe5c0 16 16>;
1280                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1281                 status = "disabled";
1282         };
1283
1284         watchdog@ff840000 {
1285                 compatible = "snps,dw-wdt";
1286                 reg = <0x0 0xff840000 0x0 0x100>;
1287                 clocks = <&cru PCLK_WDT>;
1288                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1289         };
1290
1291         rktimer: rktimer@ff850000 {
1292                 compatible = "rockchip,rk3399-timer";
1293                 reg = <0x0 0xff850000 0x0 0x1000>;
1294                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1295                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1296                 clock-names = "pclk", "timer";
1297         };
1298
1299         spdif: spdif@ff870000 {
1300                 compatible = "rockchip,rk3399-spdif";
1301                 reg = <0x0 0xff870000 0x0 0x1000>;
1302                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1303                 dmas = <&dmac_bus 7>;
1304                 dma-names = "tx";
1305                 clock-names = "mclk", "hclk";
1306                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1307                 pinctrl-names = "default";
1308                 pinctrl-0 = <&spdif_bus>;
1309                 status = "disabled";
1310         };
1311
1312         i2s0: i2s@ff880000 {
1313                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1314                 reg = <0x0 0xff880000 0x0 0x1000>;
1315                 rockchip,grf = <&grf>;
1316                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1317                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1318                 dma-names = "tx", "rx";
1319                 clock-names = "i2s_clk", "i2s_hclk";
1320                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1321                 pinctrl-names = "default";
1322                 pinctrl-0 = <&i2s0_8ch_bus>;
1323                 status = "disabled";
1324         };
1325
1326         i2s1: i2s@ff890000 {
1327                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1328                 reg = <0x0 0xff890000 0x0 0x1000>;
1329                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1330                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1331                 dma-names = "tx", "rx";
1332                 clock-names = "i2s_clk", "i2s_hclk";
1333                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1334                 pinctrl-names = "default";
1335                 pinctrl-0 = <&i2s1_2ch_bus>;
1336                 status = "disabled";
1337         };
1338
1339         i2s2: i2s@ff8a0000 {
1340                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1341                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1342                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1343                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1344                 dma-names = "tx", "rx";
1345                 clock-names = "i2s_clk", "i2s_hclk";
1346                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1347                 status = "disabled";
1348         };
1349
1350         gpu: gpu@ff9a0000 {
1351                 compatible = "arm,malit860",
1352                              "arm,malit86x",
1353                              "arm,malit8xx",
1354                              "arm,mali-midgard";
1355
1356                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1357
1358                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1359                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1360                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1361                 interrupt-names = "GPU", "JOB", "MMU";
1362
1363                 clocks = <&cru ACLK_GPU>;
1364                 clock-names = "clk_mali";
1365                 #cooling-cells = <2>; /* min followed by max */
1366                 operating-points-v2 = <&gpu_opp_table>;
1367                 power-domains = <&power RK3399_PD_GPU>;
1368                 power-off-delay-ms = <200>;
1369                 status = "disabled";
1370
1371                 gpu_power_model: power_model {
1372                         compatible = "arm,mali-simple-power-model";
1373                         voltage = <900>;
1374                         frequency = <500>;
1375                         static-power = <300>;
1376                         dynamic-power = <396>;
1377                         ts = <32000 4700 (-80) 2>;
1378                         thermal-zone = "gpu-thermal";
1379                 };
1380         };
1381
1382         gpu_opp_table: gpu_opp_table {
1383                 compatible = "operating-points-v2";
1384                 opp-shared;
1385
1386                 opp@200000000 {
1387                         opp-hz = /bits/ 64 <200000000>;
1388                         opp-microvolt = <900000>;
1389                 };
1390                 opp@300000000 {
1391                         opp-hz = /bits/ 64 <300000000>;
1392                         opp-microvolt = <900000>;
1393                 };
1394                 opp@400000000 {
1395                         opp-hz = /bits/ 64 <400000000>;
1396                         opp-microvolt = <900000>;
1397                 };
1398
1399         };
1400
1401         vopl: vop@ff8f0000 {
1402                 compatible = "rockchip,rk3399-vop-lit";
1403                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1404                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1405                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1406                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1407                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1408                 reset-names = "axi", "ahb", "dclk";
1409                 power-domains = <&power RK3399_PD_VOPL>;
1410                 iommus = <&vopl_mmu>;
1411                 status = "disabled";
1412
1413                 vopl_out: port {
1414                         #address-cells = <1>;
1415                         #size-cells = <0>;
1416
1417                         vopl_out_mipi: endpoint@0 {
1418                                 reg = <0>;
1419                                 remote-endpoint = <&mipi_in_vopl>;
1420                         };
1421
1422                         vopl_out_edp: endpoint@1 {
1423                                 reg = <1>;
1424                                 remote-endpoint = <&edp_in_vopl>;
1425                         };
1426
1427                         vopl_out_hdmi: endpoint@2 {
1428                                 reg = <2>;
1429                                 remote-endpoint = <&hdmi_in_vopl>;
1430                         };
1431                 };
1432         };
1433
1434         vopl_mmu: iommu@ff8f3f00 {
1435                 compatible = "rockchip,iommu";
1436                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1437                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1438                 interrupt-names = "vopl_mmu";
1439                 #iommu-cells = <0>;
1440                 status = "disabled";
1441         };
1442
1443         vopb: vop@ff900000 {
1444                 compatible = "rockchip,rk3399-vop-big";
1445                 reg = <0x0 0xff900000 0x0 0x3efc>;
1446                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1447                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1448                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1449                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1450                 reset-names = "axi", "ahb", "dclk";
1451                 power-domains = <&power RK3399_PD_VOPB>;
1452                 iommus = <&vopb_mmu>;
1453                 status = "disabled";
1454
1455                 vopb_out: port {
1456                         #address-cells = <1>;
1457                         #size-cells = <0>;
1458
1459                         vopb_out_edp: endpoint@0 {
1460                                 reg = <0>;
1461                                 remote-endpoint = <&edp_in_vopb>;
1462                         };
1463
1464                         vopb_out_mipi: endpoint@1 {
1465                                 reg = <1>;
1466                                 remote-endpoint = <&mipi_in_vopb>;
1467                         };
1468
1469                         vopb_out_hdmi: endpoint@2 {
1470                                 reg = <2>;
1471                                 remote-endpoint = <&hdmi_in_vopb>;
1472                         };
1473                 };
1474         };
1475
1476         vopb_mmu: iommu@ff903f00 {
1477                 compatible = "rockchip,iommu";
1478                 reg = <0x0 0xff903f00 0x0 0x100>;
1479                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1480                 interrupt-names = "vopb_mmu";
1481                 #iommu-cells = <0>;
1482                 status = "disabled";
1483         };
1484
1485         hdmi: hdmi@ff940000 {
1486                 compatible = "rockchip,rk3399-dw-hdmi";
1487                 reg = <0x0 0xff940000 0x0 0x20000>;
1488                 reg-io-width = <4>;
1489                 rockchip,grf = <&grf>;
1490                 power-domains = <&power RK3399_PD_HDCP>;
1491                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1492                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1493                 clock-names = "iahb", "isfr", "vpll", "grf";
1494                 status = "disabled";
1495
1496                 ports {
1497                         hdmi_in: port {
1498                                 #address-cells = <1>;
1499                                 #size-cells = <0>;
1500                                 hdmi_in_vopb: endpoint@0 {
1501                                         reg = <0>;
1502                                         remote-endpoint = <&vopb_out_hdmi>;
1503                                 };
1504                                 hdmi_in_vopl: endpoint@1 {
1505                                         reg = <1>;
1506                                         remote-endpoint = <&vopl_out_hdmi>;
1507                                 };
1508                         };
1509                 };
1510         };
1511
1512         mipi_dsi: mipi@ff960000 {
1513                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1514                 reg = <0x0 0xff960000 0x0 0x8000>;
1515                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1516                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1517                          <&cru SCLK_DPHY_TX0_CFG>;
1518                 clock-names = "ref", "pclk", "phy_cfg";
1519                 power-domains = <&power RK3399_PD_VIO>;
1520                 rockchip,grf = <&grf>;
1521                 #address-cells = <1>;
1522                 #size-cells = <0>;
1523                 status = "disabled";
1524
1525                 ports {
1526                         #address-cells = <1>;
1527                         #size-cells = <0>;
1528                         reg = <1>;
1529
1530                         mipi_in: port {
1531                                 #address-cells = <1>;
1532                                 #size-cells = <0>;
1533
1534                                 mipi_in_vopb: endpoint@0 {
1535                                         reg = <0>;
1536                                         remote-endpoint = <&vopb_out_mipi>;
1537                                 };
1538                                 mipi_in_vopl: endpoint@1 {
1539                                         reg = <1>;
1540                                         remote-endpoint = <&vopl_out_mipi>;
1541                                 };
1542                         };
1543                 };
1544         };
1545
1546         edp: edp@ff970000 {
1547                 compatible = "rockchip,rk3399-edp";
1548                 reg = <0x0 0xff970000 0x0 0x8000>;
1549                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1550                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1551                 clock-names = "dp", "pclk";
1552                 resets = <&cru SRST_P_EDP_CTRL>;
1553                 reset-names = "dp";
1554                 rockchip,grf = <&grf>;
1555                 status = "disabled";
1556                 pinctrl-names = "default";
1557                 pinctrl-0 = <&edp_hpd>;
1558
1559                 ports {
1560                         #address-cells = <1>;
1561                         #size-cells = <0>;
1562
1563                         edp_in: port@0 {
1564                                 reg = <0>;
1565                                 #address-cells = <1>;
1566                                 #size-cells = <0>;
1567
1568                                 edp_in_vopb: endpoint@0 {
1569                                         reg = <0>;
1570                                         remote-endpoint = <&vopb_out_edp>;
1571                                 };
1572
1573                                 edp_in_vopl: endpoint@1 {
1574                                         reg = <1>;
1575                                         remote-endpoint = <&vopl_out_edp>;
1576                                 };
1577                         };
1578                 };
1579         };
1580
1581         display_subsystem: display-subsystem {
1582                 compatible = "rockchip,display-subsystem";
1583                 ports = <&vopl_out>, <&vopb_out>;
1584                 status = "disabled";
1585         };
1586
1587         pinctrl: pinctrl {
1588                 compatible = "rockchip,rk3399-pinctrl";
1589                 rockchip,grf = <&grf>;
1590                 rockchip,pmu = <&pmugrf>;
1591                 #address-cells = <0x2>;
1592                 #size-cells = <0x2>;
1593                 ranges;
1594
1595                 gpio0: gpio0@ff720000 {
1596                         compatible = "rockchip,gpio-bank";
1597                         reg = <0x0 0xff720000 0x0 0x100>;
1598                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1599                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1600
1601                         gpio-controller;
1602                         #gpio-cells = <0x2>;
1603
1604                         interrupt-controller;
1605                         #interrupt-cells = <0x2>;
1606                 };
1607
1608                 gpio1: gpio1@ff730000 {
1609                         compatible = "rockchip,gpio-bank";
1610                         reg = <0x0 0xff730000 0x0 0x100>;
1611                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1612                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1613
1614                         gpio-controller;
1615                         #gpio-cells = <0x2>;
1616
1617                         interrupt-controller;
1618                         #interrupt-cells = <0x2>;
1619                 };
1620
1621                 gpio2: gpio2@ff780000 {
1622                         compatible = "rockchip,gpio-bank";
1623                         reg = <0x0 0xff780000 0x0 0x100>;
1624                         clocks = <&cru PCLK_GPIO2>;
1625                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1626
1627                         gpio-controller;
1628                         #gpio-cells = <0x2>;
1629
1630                         interrupt-controller;
1631                         #interrupt-cells = <0x2>;
1632                 };
1633
1634                 gpio3: gpio3@ff788000 {
1635                         compatible = "rockchip,gpio-bank";
1636                         reg = <0x0 0xff788000 0x0 0x100>;
1637                         clocks = <&cru PCLK_GPIO3>;
1638                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1639
1640                         gpio-controller;
1641                         #gpio-cells = <0x2>;
1642
1643                         interrupt-controller;
1644                         #interrupt-cells = <0x2>;
1645                 };
1646
1647                 gpio4: gpio4@ff790000 {
1648                         compatible = "rockchip,gpio-bank";
1649                         reg = <0x0 0xff790000 0x0 0x100>;
1650                         clocks = <&cru PCLK_GPIO4>;
1651                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1652
1653                         gpio-controller;
1654                         #gpio-cells = <0x2>;
1655
1656                         interrupt-controller;
1657                         #interrupt-cells = <0x2>;
1658                 };
1659
1660                 pcfg_pull_up: pcfg-pull-up {
1661                         bias-pull-up;
1662                 };
1663
1664                 pcfg_pull_down: pcfg-pull-down {
1665                         bias-pull-down;
1666                 };
1667
1668                 pcfg_pull_none: pcfg-pull-none {
1669                         bias-disable;
1670                 };
1671
1672                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1673                         bias-pull-up;
1674                         drive-strength = <20>;
1675                 };
1676
1677                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1678                         bias-disable;
1679                         drive-strength = <20>;
1680                 };
1681
1682                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1683                         bias-disable;
1684                         drive-strength = <18>;
1685                 };
1686
1687                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1688                         bias-disable;
1689                         drive-strength = <12>;
1690                 };
1691
1692                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1693                         bias-pull-up;
1694                         drive-strength = <8>;
1695                 };
1696
1697                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1698                         bias-pull-down;
1699                         drive-strength = <4>;
1700                 };
1701
1702                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1703                         bias-pull-up;
1704                         drive-strength = <2>;
1705                 };
1706
1707                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1708                         bias-pull-down;
1709                         drive-strength = <12>;
1710                 };
1711
1712                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1713                         bias-disable;
1714                         drive-strength = <13>;
1715                 };
1716
1717                 emmc {
1718                         emmc_pwr: emmc-pwr {
1719                                 rockchip,pins =
1720                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722                 };
1723
1724                 gmac {
1725                         rgmii_pins: rgmii-pins {
1726                                 rockchip,pins =
1727                                         /* mac_txclk */
1728                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1729                                         /* mac_rxclk */
1730                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1731                                         /* mac_mdio */
1732                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1733                                         /* mac_txen */
1734                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1735                                         /* mac_clk */
1736                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1737                                         /* mac_rxdv */
1738                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1739                                         /* mac_mdc */
1740                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1741                                         /* mac_rxd1 */
1742                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1743                                         /* mac_rxd0 */
1744                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1745                                         /* mac_txd1 */
1746                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1747                                         /* mac_txd0 */
1748                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1749                                         /* mac_rxd3 */
1750                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1751                                         /* mac_rxd2 */
1752                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1753                                         /* mac_txd3 */
1754                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1755                                         /* mac_txd2 */
1756                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1757                         };
1758
1759                         rmii_pins: rmii-pins {
1760                                 rockchip,pins =
1761                                         /* mac_mdio */
1762                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1763                                         /* mac_txen */
1764                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1765                                         /* mac_clk */
1766                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1767                                         /* mac_rxer */
1768                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1769                                         /* mac_rxdv */
1770                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1771                                         /* mac_mdc */
1772                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1773                                         /* mac_rxd1 */
1774                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1775                                         /* mac_rxd0 */
1776                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1777                                         /* mac_txd1 */
1778                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1779                                         /* mac_txd0 */
1780                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1781                         };
1782                 };
1783
1784                 i2c0 {
1785                         i2c0_xfer: i2c0-xfer {
1786                                 rockchip,pins =
1787                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1788                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 i2c1 {
1793                         i2c1_xfer: i2c1-xfer {
1794                                 rockchip,pins =
1795                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1796                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1797                         };
1798                 };
1799
1800                 i2c2 {
1801                         i2c2_xfer: i2c2-xfer {
1802                                 rockchip,pins =
1803                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1804                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1805                         };
1806                 };
1807
1808                 i2c3 {
1809                         i2c3_xfer: i2c3-xfer {
1810                                 rockchip,pins =
1811                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1812                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1813                         };
1814
1815                         i2c3_gpio: i2c3_gpio {
1816                                 rockchip,pins =
1817                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1818                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1819                         };
1820
1821                 };
1822
1823                 i2c4 {
1824                         i2c4_xfer: i2c4-xfer {
1825                                 rockchip,pins =
1826                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1827                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829                 };
1830
1831                 i2c5 {
1832                         i2c5_xfer: i2c5-xfer {
1833                                 rockchip,pins =
1834                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1835                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1836                         };
1837                 };
1838
1839                 i2c6 {
1840                         i2c6_xfer: i2c6-xfer {
1841                                 rockchip,pins =
1842                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1843                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1844                         };
1845                 };
1846
1847                 i2c7 {
1848                         i2c7_xfer: i2c7-xfer {
1849                                 rockchip,pins =
1850                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1851                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1852                         };
1853                 };
1854
1855                 i2c8 {
1856                         i2c8_xfer: i2c8-xfer {
1857                                 rockchip,pins =
1858                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1859                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1860                         };
1861                 };
1862
1863                 i2s0 {
1864                         i2s0_8ch_bus: i2s0-8ch-bus {
1865                                 rockchip,pins =
1866                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1867                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1868                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1869                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1870                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1871                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1872                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1873                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1874                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1875                         };
1876                 };
1877
1878                 i2s1 {
1879                         i2s1_2ch_bus: i2s1-2ch-bus {
1880                                 rockchip,pins =
1881                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1882                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1883                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1884                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1885                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1886                         };
1887                 };
1888
1889                 sdio0 {
1890                         sdio0_bus1: sdio0-bus1 {
1891                                 rockchip,pins =
1892                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1893                         };
1894
1895                         sdio0_bus4: sdio0-bus4 {
1896                                 rockchip,pins =
1897                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1898                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1899                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1900                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1901                         };
1902
1903                         sdio0_cmd: sdio0-cmd {
1904                                 rockchip,pins =
1905                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1906                         };
1907
1908                         sdio0_clk: sdio0-clk {
1909                                 rockchip,pins =
1910                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1911                         };
1912
1913                         sdio0_cd: sdio0-cd {
1914                                 rockchip,pins =
1915                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1916                         };
1917
1918                         sdio0_pwr: sdio0-pwr {
1919                                 rockchip,pins =
1920                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1921                         };
1922
1923                         sdio0_bkpwr: sdio0-bkpwr {
1924                                 rockchip,pins =
1925                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1926                         };
1927
1928                         sdio0_wp: sdio0-wp {
1929                                 rockchip,pins =
1930                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932
1933                         sdio0_int: sdio0-int {
1934                                 rockchip,pins =
1935                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1936                         };
1937                 };
1938
1939                 sdmmc {
1940                         sdmmc_bus1: sdmmc-bus1 {
1941                                 rockchip,pins =
1942                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1943                         };
1944
1945                         sdmmc_bus4: sdmmc-bus4 {
1946                                 rockchip,pins =
1947                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1948                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1949                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1950                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1951                         };
1952
1953                         sdmmc_clk: sdmmc-clk {
1954                                 rockchip,pins =
1955                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1956                         };
1957
1958                         sdmmc_cmd: sdmmc-cmd {
1959                                 rockchip,pins =
1960                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1961                         };
1962
1963                         sdmmc_cd: sdmcc-cd {
1964                                 rockchip,pins =
1965                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967
1968                         sdmmc_wp: sdmmc-wp {
1969                                 rockchip,pins =
1970                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1971                         };
1972                 };
1973
1974                 spdif {
1975                         spdif_bus: spdif-bus {
1976                                 rockchip,pins =
1977                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1978                         };
1979
1980                         spdif_bus_1: spdif-bus-1 {
1981                                 rockchip,pins =
1982                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1983                         };
1984                 };
1985
1986                 spi0 {
1987                         spi0_clk: spi0-clk {
1988                                 rockchip,pins =
1989                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1990                         };
1991                         spi0_cs0: spi0-cs0 {
1992                                 rockchip,pins =
1993                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1994                         };
1995                         spi0_cs1: spi0-cs1 {
1996                                 rockchip,pins =
1997                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1998                         };
1999                         spi0_tx: spi0-tx {
2000                                 rockchip,pins =
2001                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2002                         };
2003                         spi0_rx: spi0-rx {
2004                                 rockchip,pins =
2005                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2006                         };
2007                 };
2008
2009                 spi1 {
2010                         spi1_clk: spi1-clk {
2011                                 rockchip,pins =
2012                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2013                         };
2014                         spi1_cs0: spi1-cs0 {
2015                                 rockchip,pins =
2016                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2017                         };
2018                         spi1_rx: spi1-rx {
2019                                 rockchip,pins =
2020                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2021                         };
2022                         spi1_tx: spi1-tx {
2023                                 rockchip,pins =
2024                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2025                         };
2026                 };
2027
2028                 spi2 {
2029                         spi2_clk: spi2-clk {
2030                                 rockchip,pins =
2031                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2032                         };
2033                         spi2_cs0: spi2-cs0 {
2034                                 rockchip,pins =
2035                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2036                         };
2037                         spi2_rx: spi2-rx {
2038                                 rockchip,pins =
2039                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2040                         };
2041                         spi2_tx: spi2-tx {
2042                                 rockchip,pins =
2043                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2044                         };
2045                 };
2046
2047                 spi3 {
2048                         spi3_clk: spi3-clk {
2049                                 rockchip,pins =
2050                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2051                         };
2052                         spi3_cs0: spi3-cs0 {
2053                                 rockchip,pins =
2054                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2055                         };
2056                         spi3_rx: spi3-rx {
2057                                 rockchip,pins =
2058                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2059                         };
2060                         spi3_tx: spi3-tx {
2061                                 rockchip,pins =
2062                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2063                         };
2064                 };
2065
2066                 spi4 {
2067                         spi4_clk: spi4-clk {
2068                                 rockchip,pins =
2069                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2070                         };
2071                         spi4_cs0: spi4-cs0 {
2072                                 rockchip,pins =
2073                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2074                         };
2075                         spi4_rx: spi4-rx {
2076                                 rockchip,pins =
2077                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2078                         };
2079                         spi4_tx: spi4-tx {
2080                                 rockchip,pins =
2081                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2082                         };
2083                 };
2084
2085                 spi5 {
2086                         spi5_clk: spi5-clk {
2087                                 rockchip,pins =
2088                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2089                         };
2090                         spi5_cs0: spi5-cs0 {
2091                                 rockchip,pins =
2092                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2093                         };
2094                         spi5_rx: spi5-rx {
2095                                 rockchip,pins =
2096                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2097                         };
2098                         spi5_tx: spi5-tx {
2099                                 rockchip,pins =
2100                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2101                         };
2102                 };
2103
2104                 tsadc {
2105                         otp_gpio: otp-gpio {
2106                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2107                         };
2108
2109                         otp_out: otp-out {
2110                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2111                         };
2112                 };
2113
2114                 uart0 {
2115                         uart0_xfer: uart0-xfer {
2116                                 rockchip,pins =
2117                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2118                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2119                         };
2120
2121                         uart0_cts: uart0-cts {
2122                                 rockchip,pins =
2123                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2124                         };
2125
2126                         uart0_rts: uart0-rts {
2127                                 rockchip,pins =
2128                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2129                         };
2130                 };
2131
2132                 uart1 {
2133                         uart1_xfer: uart1-xfer {
2134                                 rockchip,pins =
2135                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2136                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 uart2a {
2141                         uart2a_xfer: uart2a-xfer {
2142                                 rockchip,pins =
2143                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2144                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2145                         };
2146                 };
2147
2148                 uart2b {
2149                         uart2b_xfer: uart2b-xfer {
2150                                 rockchip,pins =
2151                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2152                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2153                         };
2154                 };
2155
2156                 uart2c {
2157                         uart2c_xfer: uart2c-xfer {
2158                                 rockchip,pins =
2159                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2160                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2161                         };
2162                 };
2163
2164                 uart3 {
2165                         uart3_xfer: uart3-xfer {
2166                                 rockchip,pins =
2167                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2168                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2169                         };
2170
2171                         uart3_cts: uart3-cts {
2172                                 rockchip,pins =
2173                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2174                         };
2175
2176                         uart3_rts: uart3-rts {
2177                                 rockchip,pins =
2178                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2179                         };
2180                 };
2181
2182                 uart4 {
2183                         uart4_xfer: uart4-xfer {
2184                                 rockchip,pins =
2185                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2186                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2187                         };
2188                 };
2189
2190                 uarthdcp {
2191                         uarthdcp_xfer: uarthdcp-xfer {
2192                                 rockchip,pins =
2193                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2194                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2195                         };
2196                 };
2197
2198                 pwm0 {
2199                         pwm0_pin: pwm0-pin {
2200                                 rockchip,pins =
2201                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2202                         };
2203
2204                         vop0_pwm_pin: vop0-pwm-pin {
2205                                 rockchip,pins =
2206                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2207                         };
2208                 };
2209
2210                 pwm1 {
2211                         pwm1_pin: pwm1-pin {
2212                                 rockchip,pins =
2213                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2214                         };
2215
2216                         vop1_pwm_pin: vop1-pwm-pin {
2217                                 rockchip,pins =
2218                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2219                         };
2220                 };
2221
2222                 pwm2 {
2223                         pwm2_pin: pwm2-pin {
2224                                 rockchip,pins =
2225                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2226                         };
2227                 };
2228
2229                 pwm3a {
2230                         pwm3a_pin: pwm3a-pin {
2231                                 rockchip,pins =
2232                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2233                         };
2234                 };
2235
2236                 pwm3b {
2237                         pwm3b_pin: pwm3b-pin {
2238                                 rockchip,pins =
2239                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2240                         };
2241                 };
2242
2243                 edp {
2244                         edp_hpd: edp-hpd {
2245                                 rockchip,pins =
2246                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2247                         };
2248                 };
2249
2250                 hdmi {
2251                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2252                                 rockchip,pins =
2253                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2254                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2255                         };
2256
2257                         hdmi_cec: hdmi-cec {
2258                                 rockchip,pins =
2259                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2260                         };
2261                 };
2262
2263                 pcie {
2264                         pcie_clkreqn: pci-clkreqn {
2265                                 rockchip,pins =
2266                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2267                         };
2268
2269                         pcie_clkreqnb: pci-clkreqnb {
2270                                 rockchip,pins =
2271                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2272                         };
2273                 };
2274         };
2275 };