arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                 };
 122
 123                 cpu_l1: cpu@1 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x1>;
 127                         enable-method = "psci";
 128                         clocks = <&cru ARMCLKL>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         operating-points-v2 = <&cluster0_opp>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         operating-points-v2 = <&cluster0_opp>;
 141                 };
 142
 143                 cpu_l3: cpu@3 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         reg = <0x0 0x3>;
 147                         enable-method = "psci";
 148                         clocks = <&cru ARMCLKL>;
 149                         cpu-idle-states = <&cpu_sleep>;
 150                         operating-points-v2 = <&cluster0_opp>;
 151                 };
 152
 153                 cpu_b0: cpu@100 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a72", "arm,armv8";
 156                         reg = <0x0 0x100>;
 157                         enable-method = "psci";
 158                         #cooling-cells = <2>; /* min followed by max */
 159                         dynamic-power-coefficient = <1068>;
 160                         clocks = <&cru ARMCLKB>;
 161                         cpu-idle-states = <&cpu_sleep>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164
 165                 cpu_b1: cpu@101 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a72", "arm,armv8";
 168                         reg = <0x0 0x101>;
 169                         enable-method = "psci";
 170                         clocks = <&cru ARMCLKB>;
 171                         cpu-idle-states = <&cpu_sleep>;
 172                         operating-points-v2 = <&cluster1_opp>;
 173                 };
 174
 175                 idle-states {
 176                         entry-method = "psci";
 177                         cpu_sleep: cpu-sleep-0 {
 178                                 compatible = "arm,idle-state";
 179                                 local-timer-stop;
 180                                 arm,psci-suspend-param = <0x0010000>;
 181                                 entry-latency-us = <350>;
 182                                 exit-latency-us = <600>;
 183                                 min-residency-us = <1150>;
 184                         };
 185                 };
 186         };
 187
 188         cluster0_opp: opp_table0 {
 189                 compatible = "operating-points-v2";
 190                 opp-shared;
 191
 192                 opp00 {
 193                         opp-hz = /bits/ 64 <408000000>;
 194                         opp-microvolt = <800000>;
 195                         clock-latency-ns = <40000>;
 196                 };
 197                 opp01 {
 198                         opp-hz = /bits/ 64 <600000000>;
 199                         opp-microvolt = <800000>;
 200                 };
 201                 opp02 {
 202                         opp-hz = /bits/ 64 <816000000>;
 203                         opp-microvolt = <800000>;
 204                 };
 205                 opp03 {
 206                         opp-hz = /bits/ 64 <1008000000>;
 207                         opp-microvolt = <875000>;
 208                 };
 209                 opp04 {
 210                         opp-hz = /bits/ 64 <1200000000>;
 211                         opp-microvolt = <925000>;
 212                 };
 213                 opp05 {
 214                         opp-hz = /bits/ 64 <1416000000>;
 215                         opp-microvolt = <1025000>;
 216                 };
 217         };
 218
 219         cluster1_opp: opp_table1 {
 220                 compatible = "operating-points-v2";
 221                 opp-shared;
 222
 223                 opp00 {
 224                         opp-hz = /bits/ 64 <408000000>;
 225                         opp-microvolt = <800000>;
 226                         clock-latency-ns = <40000>;
 227                 };
 228                 opp01 {
 229                         opp-hz = /bits/ 64 <600000000>;
 230                         opp-microvolt = <800000>;
 231                 };
 232                 opp02 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <800000>;
 235                 };
 236                 opp03 {
 237                         opp-hz = /bits/ 64 <1008000000>;
 238                         opp-microvolt = <850000>;
 239                 };
 240                 opp04 {
 241                         opp-hz = /bits/ 64 <1200000000>;
 242                         opp-microvolt = <925000>;
 243                 };
 244         };
 245
 246         timer {
 247                 compatible = "arm,armv8-timer";
 248                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 251                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 252         };
 253
 254         arm-pmu {
 255                 compatible = "arm,armv8-pmuv3";
 256                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 257         };
 258
 259         xin24m: xin24m {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <24000000>;
 263                 clock-output-names = "xin24m";
 264         };
 265
 266         amba {
 267                 compatible = "arm,amba-bus";
 268                 #address-cells = <2>;
 269                 #size-cells = <2>;
 270                 ranges;
 271
 272                 dmac_bus: dma-controller@ff6d0000 {
 273                         compatible = "arm,pl330", "arm,primecell";
 274                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 275                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 277                         #dma-cells = <1>;
 278                         clocks = <&cru ACLK_DMAC0_PERILP>;
 279                         clock-names = "apb_pclk";
 280                 };
 281
 282                 dmac_peri: dma-controller@ff6e0000 {
 283                         compatible = "arm,pl330", "arm,primecell";
 284                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 285                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 287                         #dma-cells = <1>;
 288                         clocks = <&cru ACLK_DMAC1_PERILP>;
 289                         clock-names = "apb_pclk";
 290                 };
 291         };
 292
 293         gmac: eth@fe300000 {
 294                 compatible = "rockchip,rk3399-gmac";
 295                 reg = <0x0 0xfe300000 0x0 0x10000>;
 296                 rockchip,grf = <&grf>;
 297                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 298                 interrupt-names = "macirq";
 299                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 300                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 301                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 302                          <&cru PCLK_GMAC>;
 303                 clock-names = "stmmaceth", "mac_clk_rx",
 304                               "mac_clk_tx", "clk_mac_ref",
 305                               "clk_mac_refout", "aclk_mac",
 306                               "pclk_mac";
 307                 resets = <&cru SRST_A_GMAC>;
 308                 reset-names = "stmmaceth";
 309                 status = "disabled";
 310         };
 311
 312         emmc_phy: phy {
 313                 compatible = "rockchip,rk3399-emmc-phy";
 314                 reg-offset = <0xf780>;
 315                 #phy-cells = <0>;
 316                 rockchip,grf = <&grf>;
 317                 ctrl-base = <0xfe330000>;
 318                 status = "disabled";
 319         };
 320
 321         sdio0: dwmmc@fe310000 {
 322                 compatible = "rockchip,rk3399-dw-mshc",
 323                              "rockchip,rk3288-dw-mshc";
 324                 reg = <0x0 0xfe310000 0x0 0x4000>;
 325                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 326                 clock-freq-min-max = <400000 150000000>;
 327                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 328                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 329                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 330                 fifo-depth = <0x100>;
 331                 status = "disabled";
 332         };
 333
 334         sdmmc: dwmmc@fe320000 {
 335                 compatible = "rockchip,rk3399-dw-mshc",
 336                              "rockchip,rk3288-dw-mshc";
 337                 reg = <0x0 0xfe320000 0x0 0x4000>;
 338                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 339                 clock-freq-min-max = <400000 150000000>;
 340                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 341                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 342                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 343                 fifo-depth = <0x100>;
 344                 status = "disabled";
 345         };
 346
 347         sdhci: sdhci@fe330000 {
 348                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 349                 reg = <0x0 0xfe330000 0x0 0x10000>;
 350                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 352                 clock-names = "clk_xin", "clk_ahb";
 353                 assigned-clocks = <&cru SCLK_EMMC>;
 354                 assigned-clock-parents = <&cru PLL_CPLL>;
 355                 assigned-clock-rates = <200000000>;
 356                 phys = <&emmc_phy>;
 357                 phy-names = "phy_arasan";
 358                 status = "disabled";
 359         };
 360
 361         usb2phy: usb2phy {
 362                 compatible = "rockchip,rk3399-usb-phy";
 363                 rockchip,grf = <&grf>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366
 367                 usb2phy0: usb2-phy0 {
 368                         #phy-cells = <0>;
 369                         #clock-cells = <0>;
 370                         reg = <0xe458>;
 371                 };
 372
 373                 usb2phy1: usb2-phy1 {
 374                         #phy-cells = <0>;
 375                         #clock-cells = <0>;
 376                         reg = <0xe468>;
 377                 };
 378         };
 379
 380         usb_host0_ehci: usb@fe380000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0x0 0xfe380000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 385                 clock-names = "hclk_host0", "hclk_host0_arb";
 386                 phys = <&usb2phy0>;
 387                 phy-names = "usb2_phy0";
 388                 status = "disabled";
 389         };
 390
 391         usb_host0_ohci: usb@fe3a0000 {
 392                 compatible = "generic-ohci";
 393                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 status = "disabled";
 398         };
 399
 400         usb_host1_ehci: usb@fe3c0000 {
 401                 compatible = "generic-ehci";
 402                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 403                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 405                 clock-names = "hclk_host1", "hclk_host1_arb";
 406                 phys = <&usb2phy1>;
 407                 phy-names = "usb2_phy1";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ohci: usb@fe3e0000 {
 412                 compatible = "generic-ohci";
 413                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 status = "disabled";
 418         };
 419
 420         usbdrd3_0: usb@fe800000 {
 421                 compatible = "rockchip,dwc3";
 422                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 423                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 424                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 425                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 426                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 427                               "aclk_usb3", "aclk_usb3_grf";
 428                 #address-cells = <2>;
 429                 #size-cells = <2>;
 430                 ranges;
 431                 status = "disabled";
 432                 usbdrd_dwc3_0: dwc3 {
 433                         compatible = "snps,dwc3";
 434                         reg = <0x0 0xfe800000 0x0 0x100000>;
 435                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 436                         dr_mode = "otg";
 437                         tx-fifo-resize;
 438                         snps,dis_enblslpm_quirk;
 439                         snps,phyif_utmi_16_bits;
 440                         snps,dis_u2_freeclk_exists_quirk;
 441                         snps,dis_del_phy_power_chg_quirk;
 442                         snps,xhci_slow_suspend_quirk;
 443                         status = "disabled";
 444                 };
 445         };
 446
 447         usbdrd3_1: usb@fe900000 {
 448                 compatible = "rockchip,dwc3";
 449                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 450                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 451                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 452                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 453                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 454                               "aclk_usb3", "aclk_usb3_grf";
 455                 #address-cells = <2>;
 456                 #size-cells = <2>;
 457                 ranges;
 458                 status = "disabled";
 459                 usbdrd_dwc3_1: dwc3 {
 460                         compatible = "snps,dwc3";
 461                         reg = <0x0 0xfe900000 0x0 0x100000>;
 462                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 463                         dr_mode = "otg";
 464                         tx-fifo-resize;
 465                         snps,dis_enblslpm_quirk;
 466                         snps,phyif_utmi_16_bits;
 467                         snps,dis_u2_freeclk_exists_quirk;
 468                         snps,dis_del_phy_power_chg_quirk;
 469                         snps,xhci_slow_suspend_quirk;
 470                         status = "disabled";
 471                 };
 472         };
 473
 474         gic: interrupt-controller@fee00000 {
 475                 compatible = "arm,gic-v3";
 476                 #interrupt-cells = <3>;
 477                 #address-cells = <2>;
 478                 #size-cells = <2>;
 479                 ranges;
 480                 interrupt-controller;
 481
 482                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 483                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 484                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 485                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 486                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 487                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 488                 its: interrupt-controller@fee20000 {
 489                         compatible = "arm,gic-v3-its";
 490                         msi-controller;
 491                         reg = <0x0 0xfee20000 0x0 0x20000>;
 492                 };
 493         };
 494
 495         saradc: saradc@ff100000 {
 496                 compatible = "rockchip,rk3399-saradc";
 497                 reg = <0x0 0xff100000 0x0 0x100>;
 498                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 499                 #io-channel-cells = <1>;
 500                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 501                 clock-names = "saradc", "apb_pclk";
 502                 status = "disabled";
 503         };
 504
 505         i2c0: i2c@ff3c0000 {
 506                 compatible = "rockchip,rk3399-i2c";
 507                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 508                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 509                 clock-names = "i2c", "pclk";
 510                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c0_xfer>;
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 status = "disabled";
 516         };
 517
 518         i2c1: i2c@ff110000 {
 519                 compatible = "rockchip,rk3399-i2c";
 520                 reg = <0x0 0xff110000 0x0 0x1000>;
 521                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 522                 clock-names = "i2c", "pclk";
 523                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c1_xfer>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         i2c2: i2c@ff120000 {
 532                 compatible = "rockchip,rk3399-i2c";
 533                 reg = <0x0 0xff120000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 535                 clock-names = "i2c", "pclk";
 536                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c2_xfer>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         i2c3: i2c@ff130000 {
 545                 compatible = "rockchip,rk3399-i2c";
 546                 reg = <0x0 0xff130000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c3_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c5: i2c@ff140000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff140000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 561                 clock-names = "i2c", "pclk";
 562                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c5_xfer>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c6: i2c@ff150000 {
 571                 compatible = "rockchip,rk3399-i2c";
 572                 reg = <0x0 0xff150000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c6_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c7: i2c@ff160000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff160000 0x0 0x1000>;
 586                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c7_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         uart0: serial@ff180000 {
 597                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 598                 reg = <0x0 0xff180000 0x0 0x100>;
 599                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 600                 clock-names = "baudclk", "apb_pclk";
 601                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 602                 reg-shift = <2>;
 603                 reg-io-width = <4>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 606                 status = "disabled";
 607         };
 608
 609         uart1: serial@ff190000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff190000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&uart1_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         uart2: serial@ff1a0000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff1a0000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart2c_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart3: serial@ff1b0000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff1b0000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 645                 status = "disabled";
 646         };
 647
 648         spi0: spi@ff1c0000 {
 649                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 650                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 651                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 652                 clock-names = "spiclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 status = "disabled";
 659         };
 660
 661         spi1: spi@ff1d0000 {
 662                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 663                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 664                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 665                 clock-names = "spiclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         spi2: spi@ff1e0000 {
 675                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 676                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 677                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 678                 clock-names = "spiclk", "apb_pclk";
 679                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         spi4: spi@ff1f0000 {
 688                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 689                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 690                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 691                 clock-names = "spiclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi5: spi@ff200000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff200000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         thermal-zones {
 714                 soc_thermal: soc-thermal {
 715                         polling-delay-passive = <100>; /* milliseconds */
 716                         polling-delay = <1000>; /* milliseconds */
 717                         sustainable-power = <2600>; /* milliwatts */
 718
 719                         thermal-sensors = <&tsadc 0>;
 720
 721                         trips {
 722                                 threshold: trip-point@0 {
 723                                         temperature = <70000>; /* millicelsius */
 724                                         hysteresis = <2000>; /* millicelsius */
 725                                         type = "passive";
 726                                 };
 727                                 target: trip-point@1 {
 728                                         temperature = <85000>; /* millicelsius */
 729                                         hysteresis = <2000>; /* millicelsius */
 730                                         type = "passive";
 731                                 };
 732                                 soc_crit: soc-crit {
 733                                         temperature = <95000>; /* millicelsius */
 734                                         hysteresis = <2000>; /* millicelsius */
 735                                         type = "critical";
 736                                 };
 737                         };
 738
 739                         cooling-maps {
 740                                 map0 {
 741                                         trip = <&target>;
 742                                         cooling-device =
 743                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 744                                 };
 745                                 map1 {
 746                                         trip = <&target>;
 747                                         cooling-device =
 748                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 749                                 };
 750                                 map2 {
 751                                         trip = <&target>;
 752                                         cooling-device =
 753                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 754                                 };
 755                         };
 756                 };
 757
 758                 gpu_thermal: gpu-thermal {
 759                         polling-delay-passive = <100>; /* milliseconds */
 760                         polling-delay = <1000>; /* milliseconds */
 761
 762                         thermal-sensors = <&tsadc 1>;
 763                 };
 764         };
 765
 766         tsadc: tsadc@ff260000 {
 767                 compatible = "rockchip,rk3399-tsadc";
 768                 reg = <0x0 0xff260000 0x0 0x100>;
 769                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 770                 rockchip,grf = <&grf>;
 771                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 772                 clock-names = "tsadc", "apb_pclk";
 773                 assigned-clocks = <&cru SCLK_TSADC>;
 774                 assigned-clock-rates = <750000>;
 775                 resets = <&cru SRST_TSADC>;
 776                 reset-names = "tsadc-apb";
 777                 pinctrl-names = "init", "default", "sleep";
 778                 pinctrl-0 = <&otp_gpio>;
 779                 pinctrl-1 = <&otp_out>;
 780                 pinctrl-2 = <&otp_gpio>;
 781                 #thermal-sensor-cells = <1>;
 782                 rockchip,hw-tshut-temp = <95000>;
 783                 status = "disabled";
 784         };
 785
 786         qos_gpu: qos_gpu@0xffae0000 {
 787                 compatible ="syscon";
 788                 reg = <0x0 0xffae0000 0x0 0x20>;
 789         };
 790         qos_video_m0: qos_video_m0@0xffab8000 {
 791                 compatible ="syscon";
 792                 reg = <0x0 0xffab8000 0x0 0x20>;
 793         };
 794         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 795                 compatible ="syscon";
 796                 reg = <0x0 0xffac0000 0x0 0x20>;
 797         };
 798         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 799                 compatible ="syscon";
 800                 reg = <0x0 0xffac0080 0x0 0x20>;
 801         };
 802         qos_rga_r: qos_rga_r@0xffab0000 {
 803                 compatible ="syscon";
 804                 reg = <0x0 0xffab0000 0x0 0x20>;
 805         };
 806         qos_rga_w: qos_rga_w@0xffab0080 {
 807                 compatible ="syscon";
 808                 reg = <0x0 0xffab0000 0x0 0x20>;
 809         };
 810         qos_iep: qos_iep@0xffa98000 {
 811                 compatible ="syscon";
 812                 reg = <0x0 0xffa98000 0x0 0x20>;
 813         };
 814         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 815                 compatible ="syscon";
 816                 reg = <0x0 0xffac8000 0x0 0x20>;
 817         };
 818         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 819                 compatible ="syscon";
 820                 reg = <0x0 0xffac8080 0x0 0x20>;
 821         };
 822         qos_vop_little: qos_vop_little@0xffad0000 {
 823                 compatible ="syscon";
 824                 reg = <0x0 0xffad0000 0x0 0x20>;
 825         };
 826         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 827                 compatible ="syscon";
 828                 reg = <0x0 0xffaa0000 0x0 0x20>;
 829         };
 830         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 831                 compatible ="syscon";
 832                 reg = <0x0 0xffaa0080 0x0 0x20>;
 833         };
 834         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 835                 compatible ="syscon";
 836                 reg = <0x0 0xffaa8000 0x0 0x20>;
 837         };
 838         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 839                 compatible ="syscon";
 840                 reg = <0x0 0xffaa8080 0x0 0x20>;
 841         };
 842         qos_hdcp: qos_hdcp@0xffa90000 {
 843                 compatible ="syscon";
 844                 reg = <0x0 0xffa90000 0x0 0x20>;
 845         };
 846
 847         pmu: power-management@ff310000 {
 848                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 849                 reg = <0x0 0xff310000 0x0 0x1000>;
 850
 851                 power: power-controller {
 852                         status = "disabled";
 853                         compatible = "rockchip,rk3399-power-controller";
 854                         #power-domain-cells = <1>;
 855                         #address-cells = <1>;
 856                         #size-cells = <0>;
 857
 858                         pd_center {
 859                                 reg = <RK3399_PD_CENTER>;
 860                                 #address-cells = <1>;
 861                                 #size-cells = <0>;
 862
 863                                 pd_vdu {
 864                                         reg = <RK3399_PD_VDU>;
 865                                         pm_qos = <&qos_video_m1_r>,
 866                                                  <&qos_video_m1_w>;
 867                                 };
 868                                 pd_vcodec {
 869                                         reg = <RK3399_PD_VCODEC>;
 870                                         pm_qos = <&qos_video_m0>;
 871                                 };
 872                                 pd_iep {
 873                                         reg = <RK3399_PD_IEP>;
 874                                         pm_qos = <&qos_iep>;
 875                                 };
 876                                 pd_rga {
 877                                         reg = <RK3399_PD_RGA>;
 878                                         pm_qos = <&qos_rga_r>,
 879                                                  <&qos_rga_w>;
 880                                 };
 881                         };
 882                         pd_vio {
 883                                 reg = <RK3399_PD_VIO>;
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886
 887                                 pd_isp0 {
 888                                         reg = <RK3399_PD_ISP0>;
 889                                         pm_qos = <&qos_isp0_m0>,
 890                                                  <&qos_isp0_m1>;
 891                                 };
 892                                 pd_isp1 {
 893                                         reg = <RK3399_PD_ISP1>;
 894                                         pm_qos = <&qos_isp1_m0>,
 895                                                  <&qos_isp1_m1>;
 896                                 };
 897                                 pd_hdcp {
 898                                         reg = <RK3399_PD_HDCP>;
 899                                         pm_qos = <&qos_hdcp>;
 900                                 };
 901                                 pd_vo {
 902                                         reg = <RK3399_PD_VO>;
 903                                         #address-cells = <1>;
 904                                         #size-cells = <0>;
 905
 906                                         pd_vopb {
 907                                                 reg = <RK3399_PD_VOPB>;
 908                                                 pm_qos = <&qos_vop_big_r>,
 909                                                          <&qos_vop_big_w>;
 910                                         };
 911                                         pd_vopl {
 912                                                 reg = <RK3399_PD_VOPL>;
 913                                                 pm_qos = <&qos_vop_little>;
 914                                         };
 915                                 };
 916                         };
 917                         pd_gpu {
 918                                 reg = <RK3399_PD_GPU>;
 919                                 pm_qos = <&qos_gpu>;
 920                         };
 921                 };
 922         };
 923
 924         pmugrf: syscon@ff320000 {
 925                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 926                 reg = <0x0 0xff320000 0x0 0x1000>;
 927
 928                 reboot-mode {
 929                         compatible = "syscon-reboot-mode";
 930                         offset = <0x300>;
 931                         mode-normal = <BOOT_NORMAL>;
 932                         mode-recovery = <BOOT_RECOVERY>;
 933                         mode-bootloader = <BOOT_FASTBOOT>;
 934                         mode-loader = <BOOT_LOADER>;
 935                 };
 936         };
 937
 938         spi3: spi@ff350000 {
 939                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 940                 reg = <0x0 0xff350000 0x0 0x1000>;
 941                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 942                 clock-names = "spiclk", "apb_pclk";
 943                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 944                 pinctrl-names = "default";
 945                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 946                 #address-cells = <1>;
 947                 #size-cells = <0>;
 948                 status = "disabled";
 949         };
 950
 951         uart4: serial@ff370000 {
 952                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 953                 reg = <0x0 0xff370000 0x0 0x100>;
 954                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 955                 clock-names = "baudclk", "apb_pclk";
 956                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 957                 reg-shift = <2>;
 958                 reg-io-width = <4>;
 959                 pinctrl-names = "default";
 960                 pinctrl-0 = <&uart4_xfer>;
 961                 status = "disabled";
 962         };
 963
 964         i2c4: i2c@ff3d0000 {
 965                 compatible = "rockchip,rk3399-i2c";
 966                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 967                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 968                 clock-names = "i2c", "pclk";
 969                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 970                 pinctrl-names = "default";
 971                 pinctrl-0 = <&i2c4_xfer>;
 972                 #address-cells = <1>;
 973                 #size-cells = <0>;
 974                 status = "disabled";
 975         };
 976
 977         i2c8: i2c@ff3e0000 {
 978                 compatible = "rockchip,rk3399-i2c";
 979                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 980                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 981                 clock-names = "i2c", "pclk";
 982                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 983                 pinctrl-names = "default";
 984                 pinctrl-0 = <&i2c8_xfer>;
 985                 #address-cells = <1>;
 986                 #size-cells = <0>;
 987                 status = "disabled";
 988         };
 989
 990         pcie0: pcie@f8000000 {
 991                 compatible = "rockchip,rk3399-pcie";
 992                 #address-cells = <3>;
 993                 #size-cells = <2>;
 994                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 995                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
 996                 clock-names = "aclk_pcie", "aclk_perf_pcie",
 997                               "hclk_pcie", "clk_pciephy_ref";
 998                 bus-range = <0x0 0x1>;
 999                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1000                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1001                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1002                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1003                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1004                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1005                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1006                       < 0x0 0xfd000000 0x0 0x1000000 >;
1007                 reg-name = "axi-base", "apb-base";
1008                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1009                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1010                          <&cru SRST_PCIE_PIPE>;
1011                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1012                               "mgmt-sticky-rst", "pipe-rst";
1013                 rockchip,grf = <&grf>;
1014                 pcie-conf = <0xe220>;
1015                 pcie-status = <0xe2a4>;
1016                 pcie-laneoff = <0xe214>;
1017                 msi-parent = <&its>;
1018                 #interrupt-cells = <1>;
1019                 interrupt-map-mask = <0 0 0 7>;
1020                 interrupt-map = <0 0 0 1 &pcie0 1>,
1021                                 <0 0 0 2 &pcie0 2>,
1022                                 <0 0 0 3 &pcie0 3>,
1023                                 <0 0 0 4 &pcie0 4>;
1024                 status = "disabled";
1025                 pcie_intc: interrupt-controller {
1026                         interrupt-controller;
1027                         #address-cells = <0>;
1028                         #interrupt-cells = <1>;
1029                 };
1030         };
1031
1032         pwm0: pwm@ff420000 {
1033                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1034                 reg = <0x0 0xff420000 0x0 0x10>;
1035                 #pwm-cells = <3>;
1036                 pinctrl-names = "default";
1037                 pinctrl-0 = <&pwm0_pin>;
1038                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1039                 clock-names = "pwm";
1040                 status = "disabled";
1041         };
1042
1043         pwm1: pwm@ff420010 {
1044                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1045                 reg = <0x0 0xff420010 0x0 0x10>;
1046                 #pwm-cells = <3>;
1047                 pinctrl-names = "default";
1048                 pinctrl-0 = <&pwm1_pin>;
1049                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1050                 clock-names = "pwm";
1051                 status = "disabled";
1052         };
1053
1054         pwm2: pwm@ff420020 {
1055                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1056                 reg = <0x0 0xff420020 0x0 0x10>;
1057                 #pwm-cells = <3>;
1058                 pinctrl-names = "default";
1059                 pinctrl-0 = <&pwm2_pin>;
1060                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1061                 clock-names = "pwm";
1062                 status = "disabled";
1063         };
1064
1065         pwm3: pwm@ff420030 {
1066                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1067                 reg = <0x0 0xff420030 0x0 0x10>;
1068                 #pwm-cells = <3>;
1069                 pinctrl-names = "default";
1070                 pinctrl-0 = <&pwm3a_pin>;
1071                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1072                 clock-names = "pwm";
1073                 status = "disabled";
1074         };
1075
1076         rga: rga@ff680000 {
1077                 compatible = "rockchip,rk3399-rga";
1078                 reg = <0x0 0xff680000 0x0 0x10000>;
1079                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1080                 interrupt-names = "rga";
1081                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1082                 clock-names = "aclk", "hclk", "sclk";
1083                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1084                 reset-names = "core", "axi", "ahb";
1085                 status = "disabled";
1086         };
1087
1088         pmucru: pmu-clock-controller@ff750000 {
1089                 compatible = "rockchip,rk3399-pmucru";
1090                 reg = <0x0 0xff750000 0x0 0x1000>;
1091                 #clock-cells = <1>;
1092                 #reset-cells = <1>;
1093                 assigned-clocks = <&pmucru PLL_PPLL>;
1094                 assigned-clock-rates = <676000000>;
1095         };
1096
1097         cru: clock-controller@ff760000 {
1098                 compatible = "rockchip,rk3399-cru";
1099                 reg = <0x0 0xff760000 0x0 0x1000>;
1100                 #clock-cells = <1>;
1101                 #reset-cells = <1>;
1102                 assigned-clocks =
1103                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1104                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1105                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1106                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1107                         <&cru PLL_NPLL>,
1108                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1109                         <&cru PCLK_PERIHP>,
1110                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1111                         <&cru PCLK_PERILP0>,
1112                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1113                 assigned-clock-rates =
1114                          <400000000>,  <200000000>,
1115                          <400000000>,  <200000000>,
1116                          <816000000>, <816000000>,
1117                          <594000000>,  <800000000>,
1118                         <1000000000>,
1119                          <150000000>,   <75000000>,
1120                           <37500000>,
1121                          <100000000>,  <100000000>,
1122                           <50000000>,
1123                          <100000000>,   <50000000>;
1124         };
1125
1126         grf: syscon@ff770000 {
1127                 compatible = "rockchip,rk3399-grf", "syscon";
1128                 reg = <0x0 0xff770000 0x0 0x10000>;
1129         };
1130
1131         watchdog@ff840000 {
1132                 compatible = "snps,dw-wdt";
1133                 reg = <0x0 0xff840000 0x0 0x100>;
1134                 clocks = <&cru PCLK_WDT>;
1135                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1136         };
1137
1138         rktimer: rktimer@ff850000 {
1139                 compatible = "rockchip,rk3399-timer";
1140                 reg = <0x0 0xff850000 0x0 0x1000>;
1141                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1142                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1143                 clock-names = "pclk", "timer";
1144         };
1145
1146         spdif: spdif@ff870000 {
1147                 compatible = "rockchip,rk3399-spdif";
1148                 reg = <0x0 0xff870000 0x0 0x1000>;
1149                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1150                 dmas = <&dmac_bus 7>;
1151                 dma-names = "tx";
1152                 clock-names = "mclk", "hclk";
1153                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1154                 pinctrl-names = "default";
1155                 pinctrl-0 = <&spdif_bus>;
1156                 status = "disabled";
1157         };
1158
1159         i2s0: i2s@ff880000 {
1160                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1161                 reg = <0x0 0xff880000 0x0 0x1000>;
1162                 rockchip,grf = <&grf>;
1163                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1164                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1165                 dma-names = "tx", "rx";
1166                 clock-names = "i2s_clk", "i2s_hclk";
1167                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1168                 pinctrl-names = "default";
1169                 pinctrl-0 = <&i2s0_8ch_bus>;
1170                 status = "disabled";
1171         };
1172
1173         i2s1: i2s@ff890000 {
1174                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1175                 reg = <0x0 0xff890000 0x0 0x1000>;
1176                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1177                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1178                 dma-names = "tx", "rx";
1179                 clock-names = "i2s_clk", "i2s_hclk";
1180                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1181                 pinctrl-names = "default";
1182                 pinctrl-0 = <&i2s1_2ch_bus>;
1183                 status = "disabled";
1184         };
1185
1186         i2s2: i2s@ff8a0000 {
1187                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1188                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1189                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1190                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1191                 dma-names = "tx", "rx";
1192                 clock-names = "i2s_clk", "i2s_hclk";
1193                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1194                 status = "disabled";
1195         };
1196
1197         gpu: gpu@ff9a0000 {
1198                 compatible = "arm,malit860",
1199                              "arm,malit86x",
1200                              "arm,malit8xx",
1201                              "arm,mali-midgard";
1202
1203                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1204
1205                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1206                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1207                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1208                 interrupt-names = "GPU", "JOB", "MMU";
1209
1210                 clocks = <&cru ACLK_GPU>;
1211                 clock-names = "clk_mali";
1212                 #cooling-cells = <2>; /* min followed by max */
1213                 operating-points-v2 = <&gpu_opp_table>;
1214
1215                 status = "disabled";
1216
1217                 power_model {
1218                         compatible = "arm,mali-simple-power-model";
1219                         voltage = <900>;
1220                         frequency = <500>;
1221                         static-power = <300>;
1222                         dynamic-power = <1780>;
1223                         ts = <32000 4700 (-80) 2>;
1224                         thermal-zone = "gpu-thermal";
1225                 };
1226         };
1227
1228         gpu_opp_table: gpu_opp_table {
1229                 compatible = "operating-points-v2";
1230                 opp-shared;
1231
1232                 opp00 {
1233                         opp-hz = /bits/ 64 <200000000>;
1234                         opp-microvolt = <900000>;
1235                 };
1236                 opp01 {
1237                         opp-hz = /bits/ 64 <300000000>;
1238                         opp-microvolt = <900000>;
1239                 };
1240                 opp02 {
1241                         opp-hz = /bits/ 64 <400000000>;
1242                         opp-microvolt = <900000>;
1243                 };
1244
1245         };
1246
1247         vopl: vop@ff8f0000 {
1248                 compatible = "rockchip,rk3399-vop-lit";
1249                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1250                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1251                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1252                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1253                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1254                 reset-names = "axi", "ahb", "dclk";
1255                 iommus = <&vopl_mmu>;
1256                 status = "disabled";
1257
1258                 vopl_out: port {
1259                         #address-cells = <1>;
1260                         #size-cells = <0>;
1261
1262                         vopl_out_mipi: endpoint@0 {
1263                                 reg = <0>;
1264                                 remote-endpoint = <&mipi_in_vopl>;
1265                         };
1266
1267                         vopl_out_edp: endpoint@1 {
1268                                 reg = <1>;
1269                                 remote-endpoint = <&edp_in_vopl>;
1270                         };
1271                 };
1272         };
1273
1274         vopl_mmu: iommu@ff8f3f00 {
1275                 compatible = "rockchip,iommu";
1276                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1277                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1278                 interrupt-names = "vopl_mmu";
1279                 #iommu-cells = <0>;
1280                 status = "disabled";
1281         };
1282
1283         vopb: vop@ff900000 {
1284                 compatible = "rockchip,rk3399-vop-big";
1285                 reg = <0x0 0xff900000 0x0 0x3efc>;
1286                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1287                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1288                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1289                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1290                 reset-names = "axi", "ahb", "dclk";
1291                 iommus = <&vopb_mmu>;
1292                 status = "disabled";
1293
1294                 vopb_out: port {
1295                         #address-cells = <1>;
1296                         #size-cells = <0>;
1297
1298                         vopb_out_edp: endpoint@0 {
1299                                 reg = <0>;
1300                                 remote-endpoint = <&edp_in_vopb>;
1301                         };
1302
1303                         vopb_out_mipi: endpoint@1 {
1304                                 reg = <1>;
1305                                 remote-endpoint = <&mipi_in_vopb>;
1306                         };
1307                 };
1308         };
1309
1310         vopb_mmu: iommu@ff903f00 {
1311                 compatible = "rockchip,iommu";
1312                 reg = <0x0 0xff903f00 0x0 0x100>;
1313                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1314                 interrupt-names = "vopb_mmu";
1315                 #iommu-cells = <0>;
1316                 status = "disabled";
1317         };
1318
1319         mipi_dsi: mipi@ff960000 {
1320                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1321                 reg = <0x0 0xff960000 0x0 0x8000>;
1322                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1323                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1324                          <&cru SCLK_DPHY_TX0_CFG>;
1325                 clock-names = "ref", "pclk", "phy_cfg";
1326                 rockchip,grf = <&grf>;
1327                 #address-cells = <1>;
1328                 #size-cells = <0>;
1329                 status = "disabled";
1330
1331                 ports {
1332                         #address-cells = <1>;
1333                         #size-cells = <0>;
1334                         reg = <1>;
1335
1336                         mipi_in: port {
1337                                 #address-cells = <1>;
1338                                 #size-cells = <0>;
1339
1340                                 mipi_in_vopb: endpoint@0 {
1341                                         reg = <0>;
1342                                         remote-endpoint = <&vopb_out_mipi>;
1343                                 };
1344                                 mipi_in_vopl: endpoint@1 {
1345                                         reg = <1>;
1346                                         remote-endpoint = <&vopl_out_mipi>;
1347                                 };
1348                         };
1349                 };
1350         };
1351
1352         edp: edp@ff970000 {
1353                 compatible = "rockchip,rk3399-edp";
1354                 reg = <0x0 0xff970000 0x0 0x8000>;
1355                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1356                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1357                 clock-names = "dp", "pclk";
1358                 resets = <&cru SRST_P_EDP_CTRL>;
1359                 reset-names = "dp";
1360                 rockchip,grf = <&grf>;
1361                 status = "disabled";
1362                 pinctrl-names = "default";
1363                 pinctrl-0 = <&edp_hpd>;
1364
1365                 ports {
1366                         #address-cells = <1>;
1367                         #size-cells = <0>;
1368
1369                         edp_in: port@0 {
1370                                 reg = <0>;
1371                                 #address-cells = <1>;
1372                                 #size-cells = <0>;
1373
1374                                 edp_in_vopb: endpoint@0 {
1375                                         reg = <0>;
1376                                         remote-endpoint = <&vopb_out_edp>;
1377                                 };
1378
1379                                 edp_in_vopl: endpoint@1 {
1380                                         reg = <1>;
1381                                         remote-endpoint = <&vopl_out_edp>;
1382                                 };
1383                         };
1384                 };
1385         };
1386
1387         display_subsystem: display-subsystem {
1388                 compatible = "rockchip,display-subsystem";
1389                 ports = <&vopl_out>, <&vopb_out>;
1390                 status = "disabled";
1391         };
1392
1393         pinctrl: pinctrl {
1394                 compatible = "rockchip,rk3399-pinctrl";
1395                 rockchip,grf = <&grf>;
1396                 rockchip,pmu = <&pmugrf>;
1397                 #address-cells = <0x2>;
1398                 #size-cells = <0x2>;
1399                 ranges;
1400
1401                 gpio0: gpio0@ff720000 {
1402                         compatible = "rockchip,gpio-bank";
1403                         reg = <0x0 0xff720000 0x0 0x100>;
1404                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1405                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1406
1407                         gpio-controller;
1408                         #gpio-cells = <0x2>;
1409
1410                         interrupt-controller;
1411                         #interrupt-cells = <0x2>;
1412                 };
1413
1414                 gpio1: gpio1@ff730000 {
1415                         compatible = "rockchip,gpio-bank";
1416                         reg = <0x0 0xff730000 0x0 0x100>;
1417                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1418                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1419
1420                         gpio-controller;
1421                         #gpio-cells = <0x2>;
1422
1423                         interrupt-controller;
1424                         #interrupt-cells = <0x2>;
1425                 };
1426
1427                 gpio2: gpio2@ff780000 {
1428                         compatible = "rockchip,gpio-bank";
1429                         reg = <0x0 0xff780000 0x0 0x100>;
1430                         clocks = <&cru PCLK_GPIO2>;
1431                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1432
1433                         gpio-controller;
1434                         #gpio-cells = <0x2>;
1435
1436                         interrupt-controller;
1437                         #interrupt-cells = <0x2>;
1438                 };
1439
1440                 gpio3: gpio3@ff788000 {
1441                         compatible = "rockchip,gpio-bank";
1442                         reg = <0x0 0xff788000 0x0 0x100>;
1443                         clocks = <&cru PCLK_GPIO3>;
1444                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1445
1446                         gpio-controller;
1447                         #gpio-cells = <0x2>;
1448
1449                         interrupt-controller;
1450                         #interrupt-cells = <0x2>;
1451                 };
1452
1453                 gpio4: gpio4@ff790000 {
1454                         compatible = "rockchip,gpio-bank";
1455                         reg = <0x0 0xff790000 0x0 0x100>;
1456                         clocks = <&cru PCLK_GPIO4>;
1457                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1458
1459                         gpio-controller;
1460                         #gpio-cells = <0x2>;
1461
1462                         interrupt-controller;
1463                         #interrupt-cells = <0x2>;
1464                 };
1465
1466                 pcfg_pull_up: pcfg-pull-up {
1467                         bias-pull-up;
1468                 };
1469
1470                 pcfg_pull_down: pcfg-pull-down {
1471                         bias-pull-down;
1472                 };
1473
1474                 pcfg_pull_none: pcfg-pull-none {
1475                         bias-disable;
1476                 };
1477
1478                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1479                         bias-disable;
1480                         drive-strength = <12>;
1481                 };
1482
1483                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484                         bias-pull-up;
1485                         drive-strength = <8>;
1486                 };
1487
1488                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1489                         bias-pull-down;
1490                         drive-strength = <4>;
1491                 };
1492
1493                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1494                         bias-pull-up;
1495                         drive-strength = <2>;
1496                 };
1497
1498                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1499                         bias-pull-down;
1500                         drive-strength = <12>;
1501                 };
1502
1503                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1504                         bias-disable;
1505                         drive-strength = <13>;
1506                 };
1507
1508                 emmc {
1509                         emmc_pwr: emmc-pwr {
1510                                 rockchip,pins =
1511                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1512                         };
1513                 };
1514
1515                 gmac {
1516                         rgmii_pins: rgmii-pins {
1517                                 rockchip,pins =
1518                                         /* mac_txclk */
1519                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1520                                         /* mac_rxclk */
1521                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1522                                         /* mac_mdio */
1523                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1524                                         /* mac_txen */
1525                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1526                                         /* mac_clk */
1527                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1528                                         /* mac_rxdv */
1529                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1530                                         /* mac_mdc */
1531                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1532                                         /* mac_rxd1 */
1533                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1534                                         /* mac_rxd0 */
1535                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_txd1 */
1537                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1538                                         /* mac_txd0 */
1539                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1540                                         /* mac_rxd3 */
1541                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1542                                         /* mac_rxd2 */
1543                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1544                                         /* mac_txd3 */
1545                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1546                                         /* mac_txd2 */
1547                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1548                         };
1549
1550                         rmii_pins: rmii-pins {
1551                                 rockchip,pins =
1552                                         /* mac_mdio */
1553                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1554                                         /* mac_txen */
1555                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1556                                         /* mac_clk */
1557                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1558                                         /* mac_rxer */
1559                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1560                                         /* mac_rxdv */
1561                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1562                                         /* mac_mdc */
1563                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_rxd1 */
1565                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_rxd0 */
1567                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_txd1 */
1569                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1570                                         /* mac_txd0 */
1571                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1572                         };
1573                 };
1574
1575                 i2c0 {
1576                         i2c0_xfer: i2c0-xfer {
1577                                 rockchip,pins =
1578                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1579                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1580                         };
1581                 };
1582
1583                 i2c1 {
1584                         i2c1_xfer: i2c1-xfer {
1585                                 rockchip,pins =
1586                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1587                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1588                         };
1589                 };
1590
1591                 i2c2 {
1592                         i2c2_xfer: i2c2-xfer {
1593                                 rockchip,pins =
1594                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1595                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1596                         };
1597                 };
1598
1599                 i2c3 {
1600                         i2c3_xfer: i2c3-xfer {
1601                                 rockchip,pins =
1602                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1603                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605
1606                         i2c3_gpio: i2c3_gpio {
1607                                 rockchip,pins =
1608                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1609                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1610                         };
1611
1612                 };
1613
1614                 i2c4 {
1615                         i2c4_xfer: i2c4-xfer {
1616                                 rockchip,pins =
1617                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1618                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1619                         };
1620                 };
1621
1622                 i2c5 {
1623                         i2c5_xfer: i2c5-xfer {
1624                                 rockchip,pins =
1625                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1626                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1627                         };
1628                 };
1629
1630                 i2c6 {
1631                         i2c6_xfer: i2c6-xfer {
1632                                 rockchip,pins =
1633                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1634                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1635                         };
1636                 };
1637
1638                 i2c7 {
1639                         i2c7_xfer: i2c7-xfer {
1640                                 rockchip,pins =
1641                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1642                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 i2c8 {
1647                         i2c8_xfer: i2c8-xfer {
1648                                 rockchip,pins =
1649                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1650                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1651                         };
1652                 };
1653
1654                 i2s0 {
1655                         i2s0_8ch_bus: i2s0-8ch-bus {
1656                                 rockchip,pins =
1657                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1658                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1659                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1660                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1661                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1662                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1663                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1664                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1665                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667                 };
1668
1669                 i2s1 {
1670                         i2s1_2ch_bus: i2s1-2ch-bus {
1671                                 rockchip,pins =
1672                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1673                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1674                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1675                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1676                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1677                         };
1678                 };
1679
1680                 sdio0 {
1681                         sdio0_bus1: sdio0-bus1 {
1682                                 rockchip,pins =
1683                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1684                         };
1685
1686                         sdio0_bus4: sdio0-bus4 {
1687                                 rockchip,pins =
1688                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1689                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1690                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1691                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693
1694                         sdio0_cmd: sdio0-cmd {
1695                                 rockchip,pins =
1696                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1697                         };
1698
1699                         sdio0_clk: sdio0-clk {
1700                                 rockchip,pins =
1701                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         sdio0_cd: sdio0-cd {
1705                                 rockchip,pins =
1706                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1707                         };
1708
1709                         sdio0_pwr: sdio0-pwr {
1710                                 rockchip,pins =
1711                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1712                         };
1713
1714                         sdio0_bkpwr: sdio0-bkpwr {
1715                                 rockchip,pins =
1716                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_wp: sdio0-wp {
1720                                 rockchip,pins =
1721                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723
1724                         sdio0_int: sdio0-int {
1725                                 rockchip,pins =
1726                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1727                         };
1728                 };
1729
1730                 sdmmc {
1731                         sdmmc_bus1: sdmmc-bus1 {
1732                                 rockchip,pins =
1733                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1734                         };
1735
1736                         sdmmc_bus4: sdmmc-bus4 {
1737                                 rockchip,pins =
1738                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1739                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1740                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1741                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1742                         };
1743
1744                         sdmmc_clk: sdmmc-clk {
1745                                 rockchip,pins =
1746                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1747                         };
1748
1749                         sdmmc_cmd: sdmmc-cmd {
1750                                 rockchip,pins =
1751                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1752                         };
1753
1754                         sdmmc_cd: sdmcc-cd {
1755                                 rockchip,pins =
1756                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1757                         };
1758
1759                         sdmmc_wp: sdmmc-wp {
1760                                 rockchip,pins =
1761                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1762                         };
1763                 };
1764
1765                 spdif {
1766                         spdif_bus: spdif-bus {
1767                                 rockchip,pins =
1768                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1769                         };
1770                 };
1771
1772                 spi0 {
1773                         spi0_clk: spi0-clk {
1774                                 rockchip,pins =
1775                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1776                         };
1777                         spi0_cs0: spi0-cs0 {
1778                                 rockchip,pins =
1779                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1780                         };
1781                         spi0_cs1: spi0-cs1 {
1782                                 rockchip,pins =
1783                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1784                         };
1785                         spi0_tx: spi0-tx {
1786                                 rockchip,pins =
1787                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi0_rx: spi0-rx {
1790                                 rockchip,pins =
1791                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1792                         };
1793                 };
1794
1795                 spi1 {
1796                         spi1_clk: spi1-clk {
1797                                 rockchip,pins =
1798                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1799                         };
1800                         spi1_cs0: spi1-cs0 {
1801                                 rockchip,pins =
1802                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1803                         };
1804                         spi1_rx: spi1-rx {
1805                                 rockchip,pins =
1806                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1807                         };
1808                         spi1_tx: spi1-tx {
1809                                 rockchip,pins =
1810                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1811                         };
1812                 };
1813
1814                 spi2 {
1815                         spi2_clk: spi2-clk {
1816                                 rockchip,pins =
1817                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1818                         };
1819                         spi2_cs0: spi2-cs0 {
1820                                 rockchip,pins =
1821                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1822                         };
1823                         spi2_rx: spi2-rx {
1824                                 rockchip,pins =
1825                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1826                         };
1827                         spi2_tx: spi2-tx {
1828                                 rockchip,pins =
1829                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1830                         };
1831                 };
1832
1833                 spi3 {
1834                         spi3_clk: spi3-clk {
1835                                 rockchip,pins =
1836                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1837                         };
1838                         spi3_cs0: spi3-cs0 {
1839                                 rockchip,pins =
1840                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1841                         };
1842                         spi3_rx: spi3-rx {
1843                                 rockchip,pins =
1844                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1845                         };
1846                         spi3_tx: spi3-tx {
1847                                 rockchip,pins =
1848                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1849                         };
1850                 };
1851
1852                 spi4 {
1853                         spi4_clk: spi4-clk {
1854                                 rockchip,pins =
1855                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1856                         };
1857                         spi4_cs0: spi4-cs0 {
1858                                 rockchip,pins =
1859                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1860                         };
1861                         spi4_rx: spi4-rx {
1862                                 rockchip,pins =
1863                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1864                         };
1865                         spi4_tx: spi4-tx {
1866                                 rockchip,pins =
1867                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1868                         };
1869                 };
1870
1871                 spi5 {
1872                         spi5_clk: spi5-clk {
1873                                 rockchip,pins =
1874                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1875                         };
1876                         spi5_cs0: spi5-cs0 {
1877                                 rockchip,pins =
1878                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1879                         };
1880                         spi5_rx: spi5-rx {
1881                                 rockchip,pins =
1882                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1883                         };
1884                         spi5_tx: spi5-tx {
1885                                 rockchip,pins =
1886                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1887                         };
1888                 };
1889
1890                 tsadc {
1891                         otp_gpio: otp-gpio {
1892                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1893                         };
1894
1895                         otp_out: otp-out {
1896                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1897                         };
1898                 };
1899
1900                 uart0 {
1901                         uart0_xfer: uart0-xfer {
1902                                 rockchip,pins =
1903                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1904                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1905                         };
1906
1907                         uart0_cts: uart0-cts {
1908                                 rockchip,pins =
1909                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1910                         };
1911
1912                         uart0_rts: uart0-rts {
1913                                 rockchip,pins =
1914                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1915                         };
1916                 };
1917
1918                 uart1 {
1919                         uart1_xfer: uart1-xfer {
1920                                 rockchip,pins =
1921                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1922                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1923                         };
1924                 };
1925
1926                 uart2a {
1927                         uart2a_xfer: uart2a-xfer {
1928                                 rockchip,pins =
1929                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1930                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1931                         };
1932                 };
1933
1934                 uart2b {
1935                         uart2b_xfer: uart2b-xfer {
1936                                 rockchip,pins =
1937                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1938                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1939                         };
1940                 };
1941
1942                 uart2c {
1943                         uart2c_xfer: uart2c-xfer {
1944                                 rockchip,pins =
1945                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1946                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1947                         };
1948                 };
1949
1950                 uart3 {
1951                         uart3_xfer: uart3-xfer {
1952                                 rockchip,pins =
1953                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1954                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1955                         };
1956
1957                         uart3_cts: uart3-cts {
1958                                 rockchip,pins =
1959                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1960                         };
1961
1962                         uart3_rts: uart3-rts {
1963                                 rockchip,pins =
1964                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1965                         };
1966                 };
1967
1968                 uart4 {
1969                         uart4_xfer: uart4-xfer {
1970                                 rockchip,pins =
1971                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1972                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1973                         };
1974                 };
1975
1976                 uarthdcp {
1977                         uarthdcp_xfer: uarthdcp-xfer {
1978                                 rockchip,pins =
1979                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1980                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1981                         };
1982                 };
1983
1984                 pwm0 {
1985                         pwm0_pin: pwm0-pin {
1986                                 rockchip,pins =
1987                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1988                         };
1989
1990                         vop0_pwm_pin: vop0-pwm-pin {
1991                                 rockchip,pins =
1992                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1993                         };
1994                 };
1995
1996                 pwm1 {
1997                         pwm1_pin: pwm1-pin {
1998                                 rockchip,pins =
1999                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2000                         };
2001
2002                         vop1_pwm_pin: vop1-pwm-pin {
2003                                 rockchip,pins =
2004                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2005                         };
2006                 };
2007
2008                 pwm2 {
2009                         pwm2_pin: pwm2-pin {
2010                                 rockchip,pins =
2011                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2012                         };
2013                 };
2014
2015                 pwm3a {
2016                         pwm3a_pin: pwm3a-pin {
2017                                 rockchip,pins =
2018                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2019                         };
2020                 };
2021
2022                 pwm3b {
2023                         pwm3b_pin: pwm3b-pin {
2024                                 rockchip,pins =
2025                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2026                         };
2027                 };
2028
2029                 edp {
2030                         edp_hpd: edp-hpd {
2031                                 rockchip,pins =
2032                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2033                         };
2034                 };
2035
2036                 hdmi {
2037                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2038                                 rockchip,pins =
2039                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2040                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2041                         };
2042
2043                         hdmi_cec: hdmi-cec {
2044                                 rockchip,pins =
2045                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2046                         };
2047                 };
2048
2049                 pcie {
2050                         pcie_clkreqn: pci-clkreqn {
2051                                 rockchip,pins =
2052                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2053                         };
2054
2055                         pcie_clkreqnb: pci-clkreqnb {
2056                                 rockchip,pins =
2057                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2058                         };
2059                 };
2060         };
2061 };