2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <121>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 enable-method = "psci";
128 clocks = <&cru ARMCLKL>;
129 cpu-idle-states = <&cpu_sleep>;
130 operating-points-v2 = <&cluster0_opp>;
135 compatible = "arm,cortex-a53", "arm,armv8";
137 enable-method = "psci";
138 clocks = <&cru ARMCLKL>;
139 cpu-idle-states = <&cpu_sleep>;
140 operating-points-v2 = <&cluster0_opp>;
145 compatible = "arm,cortex-a53", "arm,armv8";
147 enable-method = "psci";
148 clocks = <&cru ARMCLKL>;
149 cpu-idle-states = <&cpu_sleep>;
150 operating-points-v2 = <&cluster0_opp>;
155 compatible = "arm,cortex-a72", "arm,armv8";
157 enable-method = "psci";
158 #cooling-cells = <2>; /* min followed by max */
159 dynamic-power-coefficient = <1068>;
160 clocks = <&cru ARMCLKB>;
161 cpu-idle-states = <&cpu_sleep>;
162 operating-points-v2 = <&cluster1_opp>;
167 compatible = "arm,cortex-a72", "arm,armv8";
169 enable-method = "psci";
170 clocks = <&cru ARMCLKB>;
171 cpu-idle-states = <&cpu_sleep>;
172 operating-points-v2 = <&cluster1_opp>;
176 entry-method = "psci";
177 cpu_sleep: cpu-sleep-0 {
178 compatible = "arm,idle-state";
180 arm,psci-suspend-param = <0x0010000>;
181 entry-latency-us = <350>;
182 exit-latency-us = <600>;
183 min-residency-us = <1150>;
188 cluster0_opp: opp_table0 {
189 compatible = "operating-points-v2";
193 opp-hz = /bits/ 64 <408000000>;
194 opp-microvolt = <800000>;
195 clock-latency-ns = <40000>;
198 opp-hz = /bits/ 64 <600000000>;
199 opp-microvolt = <800000>;
202 opp-hz = /bits/ 64 <816000000>;
203 opp-microvolt = <800000>;
206 opp-hz = /bits/ 64 <1008000000>;
207 opp-microvolt = <875000>;
210 opp-hz = /bits/ 64 <1200000000>;
211 opp-microvolt = <925000>;
214 opp-hz = /bits/ 64 <1416000000>;
215 opp-microvolt = <1025000>;
219 cluster1_opp: opp_table1 {
220 compatible = "operating-points-v2";
224 opp-hz = /bits/ 64 <408000000>;
225 opp-microvolt = <800000>;
226 clock-latency-ns = <40000>;
229 opp-hz = /bits/ 64 <600000000>;
230 opp-microvolt = <800000>;
233 opp-hz = /bits/ 64 <816000000>;
234 opp-microvolt = <800000>;
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <850000>;
241 opp-hz = /bits/ 64 <1200000000>;
242 opp-microvolt = <925000>;
247 compatible = "arm,armv8-timer";
248 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
249 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
250 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
251 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
255 compatible = "arm,armv8-pmuv3";
256 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
260 compatible = "fixed-clock";
262 clock-frequency = <24000000>;
263 clock-output-names = "xin24m";
267 compatible = "arm,amba-bus";
268 #address-cells = <2>;
272 dmac_bus: dma-controller@ff6d0000 {
273 compatible = "arm,pl330", "arm,primecell";
274 reg = <0x0 0xff6d0000 0x0 0x4000>;
275 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&cru ACLK_DMAC0_PERILP>;
279 clock-names = "apb_pclk";
282 dmac_peri: dma-controller@ff6e0000 {
283 compatible = "arm,pl330", "arm,primecell";
284 reg = <0x0 0xff6e0000 0x0 0x4000>;
285 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&cru ACLK_DMAC1_PERILP>;
289 clock-names = "apb_pclk";
294 compatible = "rockchip,rk3399-gmac";
295 reg = <0x0 0xfe300000 0x0 0x10000>;
296 rockchip,grf = <&grf>;
297 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-names = "macirq";
299 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
300 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
301 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
303 clock-names = "stmmaceth", "mac_clk_rx",
304 "mac_clk_tx", "clk_mac_ref",
305 "clk_mac_refout", "aclk_mac",
307 resets = <&cru SRST_A_GMAC>;
308 reset-names = "stmmaceth";
313 compatible = "rockchip,rk3399-emmc-phy";
314 reg-offset = <0xf780>;
316 rockchip,grf = <&grf>;
317 ctrl-base = <0xfe330000>;
321 sdio0: dwmmc@fe310000 {
322 compatible = "rockchip,rk3399-dw-mshc",
323 "rockchip,rk3288-dw-mshc";
324 reg = <0x0 0xfe310000 0x0 0x4000>;
325 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
326 clock-freq-min-max = <400000 150000000>;
327 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
328 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
329 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
330 fifo-depth = <0x100>;
334 sdmmc: dwmmc@fe320000 {
335 compatible = "rockchip,rk3399-dw-mshc",
336 "rockchip,rk3288-dw-mshc";
337 reg = <0x0 0xfe320000 0x0 0x4000>;
338 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
339 clock-freq-min-max = <400000 150000000>;
340 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
341 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
343 fifo-depth = <0x100>;
347 sdhci: sdhci@fe330000 {
348 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
349 reg = <0x0 0xfe330000 0x0 0x10000>;
350 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
352 clock-names = "clk_xin", "clk_ahb";
353 assigned-clocks = <&cru SCLK_EMMC>;
354 assigned-clock-parents = <&cru PLL_CPLL>;
355 assigned-clock-rates = <200000000>;
357 phy-names = "phy_arasan";
362 compatible = "rockchip,rk3399-usb-phy";
363 rockchip,grf = <&grf>;
364 #address-cells = <1>;
367 usb2phy0: usb2-phy0 {
373 usb2phy1: usb2-phy1 {
380 usb_host0_ehci: usb@fe380000 {
381 compatible = "generic-ehci";
382 reg = <0x0 0xfe380000 0x0 0x20000>;
383 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
385 clock-names = "hclk_host0", "hclk_host0_arb";
387 phy-names = "usb2_phy0";
391 usb_host0_ohci: usb@fe3a0000 {
392 compatible = "generic-ohci";
393 reg = <0x0 0xfe3a0000 0x0 0x20000>;
394 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
396 clock-names = "hclk_host0", "hclk_host0_arb";
400 usb_host1_ehci: usb@fe3c0000 {
401 compatible = "generic-ehci";
402 reg = <0x0 0xfe3c0000 0x0 0x20000>;
403 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
405 clock-names = "hclk_host1", "hclk_host1_arb";
407 phy-names = "usb2_phy1";
411 usb_host1_ohci: usb@fe3e0000 {
412 compatible = "generic-ohci";
413 reg = <0x0 0xfe3e0000 0x0 0x20000>;
414 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
416 clock-names = "hclk_host1", "hclk_host1_arb";
420 usbdrd3_0: usb@fe800000 {
421 compatible = "rockchip,dwc3";
422 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
423 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
424 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
425 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
426 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
427 "aclk_usb3", "aclk_usb3_grf";
428 #address-cells = <2>;
432 usbdrd_dwc3_0: dwc3 {
433 compatible = "snps,dwc3";
434 reg = <0x0 0xfe800000 0x0 0x100000>;
435 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
438 snps,dis_enblslpm_quirk;
439 snps,phyif_utmi_16_bits;
440 snps,dis_u2_freeclk_exists_quirk;
441 snps,dis_del_phy_power_chg_quirk;
442 snps,xhci_slow_suspend_quirk;
447 usbdrd3_1: usb@fe900000 {
448 compatible = "rockchip,dwc3";
449 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
450 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
451 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
452 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
453 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
454 "aclk_usb3", "aclk_usb3_grf";
455 #address-cells = <2>;
459 usbdrd_dwc3_1: dwc3 {
460 compatible = "snps,dwc3";
461 reg = <0x0 0xfe900000 0x0 0x100000>;
462 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
465 snps,dis_enblslpm_quirk;
466 snps,phyif_utmi_16_bits;
467 snps,dis_u2_freeclk_exists_quirk;
468 snps,dis_del_phy_power_chg_quirk;
469 snps,xhci_slow_suspend_quirk;
474 gic: interrupt-controller@fee00000 {
475 compatible = "arm,gic-v3";
476 #interrupt-cells = <3>;
477 #address-cells = <2>;
480 interrupt-controller;
482 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
483 <0x0 0xfef00000 0 0xc0000>, /* GICR */
484 <0x0 0xfff00000 0 0x10000>, /* GICC */
485 <0x0 0xfff10000 0 0x10000>, /* GICH */
486 <0x0 0xfff20000 0 0x10000>; /* GICV */
487 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
488 its: interrupt-controller@fee20000 {
489 compatible = "arm,gic-v3-its";
491 reg = <0x0 0xfee20000 0x0 0x20000>;
495 saradc: saradc@ff100000 {
496 compatible = "rockchip,rk3399-saradc";
497 reg = <0x0 0xff100000 0x0 0x100>;
498 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
499 #io-channel-cells = <1>;
500 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
501 clock-names = "saradc", "apb_pclk";
506 compatible = "rockchip,rk3399-i2c";
507 reg = <0x0 0xff3c0000 0x0 0x1000>;
508 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
509 clock-names = "i2c", "pclk";
510 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&i2c0_xfer>;
513 #address-cells = <1>;
519 compatible = "rockchip,rk3399-i2c";
520 reg = <0x0 0xff110000 0x0 0x1000>;
521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
522 clock-names = "i2c", "pclk";
523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
532 compatible = "rockchip,rk3399-i2c";
533 reg = <0x0 0xff120000 0x0 0x1000>;
534 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
535 clock-names = "i2c", "pclk";
536 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c2_xfer>;
539 #address-cells = <1>;
545 compatible = "rockchip,rk3399-i2c";
546 reg = <0x0 0xff130000 0x0 0x1000>;
547 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
548 clock-names = "i2c", "pclk";
549 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c3_xfer>;
552 #address-cells = <1>;
558 compatible = "rockchip,rk3399-i2c";
559 reg = <0x0 0xff140000 0x0 0x1000>;
560 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
561 clock-names = "i2c", "pclk";
562 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2c5_xfer>;
565 #address-cells = <1>;
571 compatible = "rockchip,rk3399-i2c";
572 reg = <0x0 0xff150000 0x0 0x1000>;
573 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
574 clock-names = "i2c", "pclk";
575 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c6_xfer>;
578 #address-cells = <1>;
584 compatible = "rockchip,rk3399-i2c";
585 reg = <0x0 0xff160000 0x0 0x1000>;
586 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
587 clock-names = "i2c", "pclk";
588 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&i2c7_xfer>;
591 #address-cells = <1>;
596 uart0: serial@ff180000 {
597 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff180000 0x0 0x100>;
599 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
600 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
609 uart1: serial@ff190000 {
610 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
611 reg = <0x0 0xff190000 0x0 0x100>;
612 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
613 clock-names = "baudclk", "apb_pclk";
614 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart1_xfer>;
622 uart2: serial@ff1a0000 {
623 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
624 reg = <0x0 0xff1a0000 0x0 0x100>;
625 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
626 clock-names = "baudclk", "apb_pclk";
627 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&uart2c_xfer>;
635 uart3: serial@ff1b0000 {
636 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
637 reg = <0x0 0xff1b0000 0x0 0x100>;
638 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
639 clock-names = "baudclk", "apb_pclk";
640 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
649 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
650 reg = <0x0 0xff1c0000 0x0 0x1000>;
651 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
652 clock-names = "spiclk", "apb_pclk";
653 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
656 #address-cells = <1>;
662 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
663 reg = <0x0 0xff1d0000 0x0 0x1000>;
664 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
665 clock-names = "spiclk", "apb_pclk";
666 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
669 #address-cells = <1>;
675 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
676 reg = <0x0 0xff1e0000 0x0 0x1000>;
677 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
678 clock-names = "spiclk", "apb_pclk";
679 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
682 #address-cells = <1>;
688 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
689 reg = <0x0 0xff1f0000 0x0 0x1000>;
690 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
691 clock-names = "spiclk", "apb_pclk";
692 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
695 #address-cells = <1>;
701 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
702 reg = <0x0 0xff200000 0x0 0x1000>;
703 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
704 clock-names = "spiclk", "apb_pclk";
705 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
708 #address-cells = <1>;
714 soc_thermal: soc-thermal {
715 polling-delay-passive = <100>; /* milliseconds */
716 polling-delay = <1000>; /* milliseconds */
717 sustainable-power = <2600>; /* milliwatts */
719 thermal-sensors = <&tsadc 0>;
722 threshold: trip-point@0 {
723 temperature = <70000>; /* millicelsius */
724 hysteresis = <2000>; /* millicelsius */
727 target: trip-point@1 {
728 temperature = <85000>; /* millicelsius */
729 hysteresis = <2000>; /* millicelsius */
733 temperature = <95000>; /* millicelsius */
734 hysteresis = <2000>; /* millicelsius */
743 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
748 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
753 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
758 gpu_thermal: gpu-thermal {
759 polling-delay-passive = <100>; /* milliseconds */
760 polling-delay = <1000>; /* milliseconds */
762 thermal-sensors = <&tsadc 1>;
766 tsadc: tsadc@ff260000 {
767 compatible = "rockchip,rk3399-tsadc";
768 reg = <0x0 0xff260000 0x0 0x100>;
769 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
770 rockchip,grf = <&grf>;
771 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
772 clock-names = "tsadc", "apb_pclk";
773 assigned-clocks = <&cru SCLK_TSADC>;
774 assigned-clock-rates = <750000>;
775 resets = <&cru SRST_TSADC>;
776 reset-names = "tsadc-apb";
777 pinctrl-names = "init", "default", "sleep";
778 pinctrl-0 = <&otp_gpio>;
779 pinctrl-1 = <&otp_out>;
780 pinctrl-2 = <&otp_gpio>;
781 #thermal-sensor-cells = <1>;
782 rockchip,hw-tshut-temp = <95000>;
786 qos_gpu: qos_gpu@0xffae0000 {
787 compatible ="syscon";
788 reg = <0x0 0xffae0000 0x0 0x20>;
790 qos_video_m0: qos_video_m0@0xffab8000 {
791 compatible ="syscon";
792 reg = <0x0 0xffab8000 0x0 0x20>;
794 qos_video_m1_r: qos_video_m1_r@0xffac0000 {
795 compatible ="syscon";
796 reg = <0x0 0xffac0000 0x0 0x20>;
798 qos_video_m1_w: qos_video_m1_w@0xffac0080 {
799 compatible ="syscon";
800 reg = <0x0 0xffac0080 0x0 0x20>;
802 qos_rga_r: qos_rga_r@0xffab0000 {
803 compatible ="syscon";
804 reg = <0x0 0xffab0000 0x0 0x20>;
806 qos_rga_w: qos_rga_w@0xffab0080 {
807 compatible ="syscon";
808 reg = <0x0 0xffab0000 0x0 0x20>;
810 qos_iep: qos_iep@0xffa98000 {
811 compatible ="syscon";
812 reg = <0x0 0xffa98000 0x0 0x20>;
814 qos_vop_big_r: qos_vop_big_r@0xffac8000 {
815 compatible ="syscon";
816 reg = <0x0 0xffac8000 0x0 0x20>;
818 qos_vop_big_w: qos_vop_big_w@0xffac8080 {
819 compatible ="syscon";
820 reg = <0x0 0xffac8080 0x0 0x20>;
822 qos_vop_little: qos_vop_little@0xffad0000 {
823 compatible ="syscon";
824 reg = <0x0 0xffad0000 0x0 0x20>;
826 qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
827 compatible ="syscon";
828 reg = <0x0 0xffaa0000 0x0 0x20>;
830 qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
831 compatible ="syscon";
832 reg = <0x0 0xffaa0080 0x0 0x20>;
834 qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
835 compatible ="syscon";
836 reg = <0x0 0xffaa8000 0x0 0x20>;
838 qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
839 compatible ="syscon";
840 reg = <0x0 0xffaa8080 0x0 0x20>;
842 qos_hdcp: qos_hdcp@0xffa90000 {
843 compatible ="syscon";
844 reg = <0x0 0xffa90000 0x0 0x20>;
847 pmu: power-management@ff310000 {
848 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
849 reg = <0x0 0xff310000 0x0 0x1000>;
851 power: power-controller {
853 compatible = "rockchip,rk3399-power-controller";
854 #power-domain-cells = <1>;
855 #address-cells = <1>;
859 reg = <RK3399_PD_CENTER>;
860 #address-cells = <1>;
864 reg = <RK3399_PD_VDU>;
865 pm_qos = <&qos_video_m1_r>,
869 reg = <RK3399_PD_VCODEC>;
870 pm_qos = <&qos_video_m0>;
873 reg = <RK3399_PD_IEP>;
877 reg = <RK3399_PD_RGA>;
878 pm_qos = <&qos_rga_r>,
883 reg = <RK3399_PD_VIO>;
884 #address-cells = <1>;
888 reg = <RK3399_PD_ISP0>;
889 pm_qos = <&qos_isp0_m0>,
893 reg = <RK3399_PD_ISP1>;
894 pm_qos = <&qos_isp1_m0>,
898 reg = <RK3399_PD_HDCP>;
899 pm_qos = <&qos_hdcp>;
902 reg = <RK3399_PD_VO>;
903 #address-cells = <1>;
907 reg = <RK3399_PD_VOPB>;
908 pm_qos = <&qos_vop_big_r>,
912 reg = <RK3399_PD_VOPL>;
913 pm_qos = <&qos_vop_little>;
918 reg = <RK3399_PD_GPU>;
924 pmugrf: syscon@ff320000 {
925 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
926 reg = <0x0 0xff320000 0x0 0x1000>;
929 compatible = "syscon-reboot-mode";
931 mode-normal = <BOOT_NORMAL>;
932 mode-recovery = <BOOT_RECOVERY>;
933 mode-bootloader = <BOOT_FASTBOOT>;
934 mode-loader = <BOOT_LOADER>;
939 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
940 reg = <0x0 0xff350000 0x0 0x1000>;
941 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
942 clock-names = "spiclk", "apb_pclk";
943 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
946 #address-cells = <1>;
951 uart4: serial@ff370000 {
952 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
953 reg = <0x0 0xff370000 0x0 0x100>;
954 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
955 clock-names = "baudclk", "apb_pclk";
956 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&uart4_xfer>;
965 compatible = "rockchip,rk3399-i2c";
966 reg = <0x0 0xff3d0000 0x0 0x1000>;
967 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
968 clock-names = "i2c", "pclk";
969 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
970 pinctrl-names = "default";
971 pinctrl-0 = <&i2c4_xfer>;
972 #address-cells = <1>;
978 compatible = "rockchip,rk3399-i2c";
979 reg = <0x0 0xff3e0000 0x0 0x1000>;
980 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
981 clock-names = "i2c", "pclk";
982 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&i2c8_xfer>;
985 #address-cells = <1>;
990 pcie0: pcie@f8000000 {
991 compatible = "rockchip,rk3399-pcie";
992 #address-cells = <3>;
994 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
995 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
996 clock-names = "aclk_pcie", "aclk_perf_pcie",
997 "hclk_pcie", "clk_pciephy_ref";
998 bus-range = <0x0 0x1>;
999 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1002 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1003 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1004 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1005 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1006 < 0x0 0xfd000000 0x0 0x1000000 >;
1007 reg-name = "axi-base", "apb-base";
1008 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1009 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1010 <&cru SRST_PCIE_PIPE>;
1011 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1012 "mgmt-sticky-rst", "pipe-rst";
1013 rockchip,grf = <&grf>;
1014 pcie-conf = <0xe220>;
1015 pcie-status = <0xe2a4>;
1016 pcie-laneoff = <0xe214>;
1017 msi-parent = <&its>;
1018 #interrupt-cells = <1>;
1019 interrupt-map-mask = <0 0 0 7>;
1020 interrupt-map = <0 0 0 1 &pcie0 1>,
1024 status = "disabled";
1025 pcie_intc: interrupt-controller {
1026 interrupt-controller;
1027 #address-cells = <0>;
1028 #interrupt-cells = <1>;
1032 pwm0: pwm@ff420000 {
1033 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1034 reg = <0x0 0xff420000 0x0 0x10>;
1036 pinctrl-names = "default";
1037 pinctrl-0 = <&pwm0_pin>;
1038 clocks = <&pmucru PCLK_RKPWM_PMU>;
1039 clock-names = "pwm";
1040 status = "disabled";
1043 pwm1: pwm@ff420010 {
1044 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1045 reg = <0x0 0xff420010 0x0 0x10>;
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&pwm1_pin>;
1049 clocks = <&pmucru PCLK_RKPWM_PMU>;
1050 clock-names = "pwm";
1051 status = "disabled";
1054 pwm2: pwm@ff420020 {
1055 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1056 reg = <0x0 0xff420020 0x0 0x10>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&pwm2_pin>;
1060 clocks = <&pmucru PCLK_RKPWM_PMU>;
1061 clock-names = "pwm";
1062 status = "disabled";
1065 pwm3: pwm@ff420030 {
1066 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1067 reg = <0x0 0xff420030 0x0 0x10>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&pwm3a_pin>;
1071 clocks = <&pmucru PCLK_RKPWM_PMU>;
1072 clock-names = "pwm";
1073 status = "disabled";
1077 compatible = "rockchip,rk3399-rga";
1078 reg = <0x0 0xff680000 0x0 0x10000>;
1079 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1080 interrupt-names = "rga";
1081 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1082 clock-names = "aclk", "hclk", "sclk";
1083 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1084 reset-names = "core", "axi", "ahb";
1085 status = "disabled";
1088 pmucru: pmu-clock-controller@ff750000 {
1089 compatible = "rockchip,rk3399-pmucru";
1090 reg = <0x0 0xff750000 0x0 0x1000>;
1093 assigned-clocks = <&pmucru PLL_PPLL>;
1094 assigned-clock-rates = <676000000>;
1097 cru: clock-controller@ff760000 {
1098 compatible = "rockchip,rk3399-cru";
1099 reg = <0x0 0xff760000 0x0 0x1000>;
1103 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1104 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1105 <&cru ARMCLKL>, <&cru ARMCLKB>,
1106 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1108 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1110 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1111 <&cru PCLK_PERILP0>,
1112 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1113 assigned-clock-rates =
1114 <400000000>, <200000000>,
1115 <400000000>, <200000000>,
1116 <816000000>, <816000000>,
1117 <594000000>, <800000000>,
1119 <150000000>, <75000000>,
1121 <100000000>, <100000000>,
1123 <100000000>, <50000000>;
1126 grf: syscon@ff770000 {
1127 compatible = "rockchip,rk3399-grf", "syscon";
1128 reg = <0x0 0xff770000 0x0 0x10000>;
1132 compatible = "snps,dw-wdt";
1133 reg = <0x0 0xff840000 0x0 0x100>;
1134 clocks = <&cru PCLK_WDT>;
1135 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1138 rktimer: rktimer@ff850000 {
1139 compatible = "rockchip,rk3399-timer";
1140 reg = <0x0 0xff850000 0x0 0x1000>;
1141 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1143 clock-names = "pclk", "timer";
1146 spdif: spdif@ff870000 {
1147 compatible = "rockchip,rk3399-spdif";
1148 reg = <0x0 0xff870000 0x0 0x1000>;
1149 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1150 dmas = <&dmac_bus 7>;
1152 clock-names = "mclk", "hclk";
1153 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&spdif_bus>;
1156 status = "disabled";
1159 i2s0: i2s@ff880000 {
1160 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1161 reg = <0x0 0xff880000 0x0 0x1000>;
1162 rockchip,grf = <&grf>;
1163 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1165 dma-names = "tx", "rx";
1166 clock-names = "i2s_clk", "i2s_hclk";
1167 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2s0_8ch_bus>;
1170 status = "disabled";
1173 i2s1: i2s@ff890000 {
1174 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1175 reg = <0x0 0xff890000 0x0 0x1000>;
1176 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1177 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1178 dma-names = "tx", "rx";
1179 clock-names = "i2s_clk", "i2s_hclk";
1180 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&i2s1_2ch_bus>;
1183 status = "disabled";
1186 i2s2: i2s@ff8a0000 {
1187 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1188 reg = <0x0 0xff8a0000 0x0 0x1000>;
1189 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1190 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1191 dma-names = "tx", "rx";
1192 clock-names = "i2s_clk", "i2s_hclk";
1193 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1194 status = "disabled";
1198 compatible = "arm,malit860",
1203 reg = <0x0 0xff9a0000 0x0 0x10000>;
1205 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "GPU", "JOB", "MMU";
1210 clocks = <&cru ACLK_GPU>;
1211 clock-names = "clk_mali";
1212 #cooling-cells = <2>; /* min followed by max */
1213 operating-points-v2 = <&gpu_opp_table>;
1215 status = "disabled";
1218 compatible = "arm,mali-simple-power-model";
1221 static-power = <300>;
1222 dynamic-power = <1780>;
1223 ts = <32000 4700 (-80) 2>;
1224 thermal-zone = "gpu-thermal";
1228 gpu_opp_table: gpu_opp_table {
1229 compatible = "operating-points-v2";
1233 opp-hz = /bits/ 64 <200000000>;
1234 opp-microvolt = <900000>;
1237 opp-hz = /bits/ 64 <300000000>;
1238 opp-microvolt = <900000>;
1241 opp-hz = /bits/ 64 <400000000>;
1242 opp-microvolt = <900000>;
1247 vopl: vop@ff8f0000 {
1248 compatible = "rockchip,rk3399-vop-lit";
1249 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1250 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1252 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1253 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1254 reset-names = "axi", "ahb", "dclk";
1255 iommus = <&vopl_mmu>;
1256 status = "disabled";
1259 #address-cells = <1>;
1262 vopl_out_mipi: endpoint@0 {
1264 remote-endpoint = <&mipi_in_vopl>;
1267 vopl_out_edp: endpoint@1 {
1269 remote-endpoint = <&edp_in_vopl>;
1274 vopl_mmu: iommu@ff8f3f00 {
1275 compatible = "rockchip,iommu";
1276 reg = <0x0 0xff8f3f00 0x0 0x100>;
1277 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1278 interrupt-names = "vopl_mmu";
1280 status = "disabled";
1283 vopb: vop@ff900000 {
1284 compatible = "rockchip,rk3399-vop-big";
1285 reg = <0x0 0xff900000 0x0 0x3efc>;
1286 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1288 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1289 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1290 reset-names = "axi", "ahb", "dclk";
1291 iommus = <&vopb_mmu>;
1292 status = "disabled";
1295 #address-cells = <1>;
1298 vopb_out_edp: endpoint@0 {
1300 remote-endpoint = <&edp_in_vopb>;
1303 vopb_out_mipi: endpoint@1 {
1305 remote-endpoint = <&mipi_in_vopb>;
1310 vopb_mmu: iommu@ff903f00 {
1311 compatible = "rockchip,iommu";
1312 reg = <0x0 0xff903f00 0x0 0x100>;
1313 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1314 interrupt-names = "vopb_mmu";
1316 status = "disabled";
1319 mipi_dsi: mipi@ff960000 {
1320 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1321 reg = <0x0 0xff960000 0x0 0x8000>;
1322 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1324 <&cru SCLK_DPHY_TX0_CFG>;
1325 clock-names = "ref", "pclk", "phy_cfg";
1326 rockchip,grf = <&grf>;
1327 #address-cells = <1>;
1329 status = "disabled";
1332 #address-cells = <1>;
1337 #address-cells = <1>;
1340 mipi_in_vopb: endpoint@0 {
1342 remote-endpoint = <&vopb_out_mipi>;
1344 mipi_in_vopl: endpoint@1 {
1346 remote-endpoint = <&vopl_out_mipi>;
1353 compatible = "rockchip,rk3399-edp";
1354 reg = <0x0 0xff970000 0x0 0x8000>;
1355 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1356 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1357 clock-names = "dp", "pclk";
1358 resets = <&cru SRST_P_EDP_CTRL>;
1360 rockchip,grf = <&grf>;
1361 status = "disabled";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&edp_hpd>;
1366 #address-cells = <1>;
1371 #address-cells = <1>;
1374 edp_in_vopb: endpoint@0 {
1376 remote-endpoint = <&vopb_out_edp>;
1379 edp_in_vopl: endpoint@1 {
1381 remote-endpoint = <&vopl_out_edp>;
1387 display_subsystem: display-subsystem {
1388 compatible = "rockchip,display-subsystem";
1389 ports = <&vopl_out>, <&vopb_out>;
1390 status = "disabled";
1394 compatible = "rockchip,rk3399-pinctrl";
1395 rockchip,grf = <&grf>;
1396 rockchip,pmu = <&pmugrf>;
1397 #address-cells = <0x2>;
1398 #size-cells = <0x2>;
1401 gpio0: gpio0@ff720000 {
1402 compatible = "rockchip,gpio-bank";
1403 reg = <0x0 0xff720000 0x0 0x100>;
1404 clocks = <&pmucru PCLK_GPIO0_PMU>;
1405 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1408 #gpio-cells = <0x2>;
1410 interrupt-controller;
1411 #interrupt-cells = <0x2>;
1414 gpio1: gpio1@ff730000 {
1415 compatible = "rockchip,gpio-bank";
1416 reg = <0x0 0xff730000 0x0 0x100>;
1417 clocks = <&pmucru PCLK_GPIO1_PMU>;
1418 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1421 #gpio-cells = <0x2>;
1423 interrupt-controller;
1424 #interrupt-cells = <0x2>;
1427 gpio2: gpio2@ff780000 {
1428 compatible = "rockchip,gpio-bank";
1429 reg = <0x0 0xff780000 0x0 0x100>;
1430 clocks = <&cru PCLK_GPIO2>;
1431 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1434 #gpio-cells = <0x2>;
1436 interrupt-controller;
1437 #interrupt-cells = <0x2>;
1440 gpio3: gpio3@ff788000 {
1441 compatible = "rockchip,gpio-bank";
1442 reg = <0x0 0xff788000 0x0 0x100>;
1443 clocks = <&cru PCLK_GPIO3>;
1444 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1447 #gpio-cells = <0x2>;
1449 interrupt-controller;
1450 #interrupt-cells = <0x2>;
1453 gpio4: gpio4@ff790000 {
1454 compatible = "rockchip,gpio-bank";
1455 reg = <0x0 0xff790000 0x0 0x100>;
1456 clocks = <&cru PCLK_GPIO4>;
1457 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1460 #gpio-cells = <0x2>;
1462 interrupt-controller;
1463 #interrupt-cells = <0x2>;
1466 pcfg_pull_up: pcfg-pull-up {
1470 pcfg_pull_down: pcfg-pull-down {
1474 pcfg_pull_none: pcfg-pull-none {
1478 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1480 drive-strength = <12>;
1483 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1485 drive-strength = <8>;
1488 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1490 drive-strength = <4>;
1493 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1495 drive-strength = <2>;
1498 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1500 drive-strength = <12>;
1503 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1505 drive-strength = <13>;
1509 emmc_pwr: emmc-pwr {
1511 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1516 rgmii_pins: rgmii-pins {
1519 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1521 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1523 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1525 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1527 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1529 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1531 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1533 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1535 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1537 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1539 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1541 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1543 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1545 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1547 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1550 rmii_pins: rmii-pins {
1553 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1555 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1557 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1559 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1561 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1563 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1565 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1567 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1569 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1571 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1576 i2c0_xfer: i2c0-xfer {
1578 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1579 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1584 i2c1_xfer: i2c1-xfer {
1586 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1587 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1592 i2c2_xfer: i2c2-xfer {
1594 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1595 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1600 i2c3_xfer: i2c3-xfer {
1602 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1603 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1606 i2c3_gpio: i2c3_gpio {
1608 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1609 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1615 i2c4_xfer: i2c4-xfer {
1617 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1618 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1623 i2c5_xfer: i2c5-xfer {
1625 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1626 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1631 i2c6_xfer: i2c6-xfer {
1633 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1634 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1639 i2c7_xfer: i2c7-xfer {
1641 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1642 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1647 i2c8_xfer: i2c8-xfer {
1649 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1650 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1655 i2s0_8ch_bus: i2s0-8ch-bus {
1657 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1658 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1659 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1660 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1661 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1662 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1663 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1664 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1665 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1670 i2s1_2ch_bus: i2s1-2ch-bus {
1672 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1673 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1674 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1675 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1676 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1681 sdio0_bus1: sdio0-bus1 {
1683 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1686 sdio0_bus4: sdio0-bus4 {
1688 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1689 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1690 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1691 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1694 sdio0_cmd: sdio0-cmd {
1696 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1699 sdio0_clk: sdio0-clk {
1701 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1704 sdio0_cd: sdio0-cd {
1706 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1709 sdio0_pwr: sdio0-pwr {
1711 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1714 sdio0_bkpwr: sdio0-bkpwr {
1716 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1719 sdio0_wp: sdio0-wp {
1721 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1724 sdio0_int: sdio0-int {
1726 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1731 sdmmc_bus1: sdmmc-bus1 {
1733 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1736 sdmmc_bus4: sdmmc-bus4 {
1738 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1739 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1740 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1741 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1744 sdmmc_clk: sdmmc-clk {
1746 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1749 sdmmc_cmd: sdmmc-cmd {
1751 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1754 sdmmc_cd: sdmcc-cd {
1756 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1759 sdmmc_wp: sdmmc-wp {
1761 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1766 spdif_bus: spdif-bus {
1768 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1773 spi0_clk: spi0-clk {
1775 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1777 spi0_cs0: spi0-cs0 {
1779 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1781 spi0_cs1: spi0-cs1 {
1783 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1787 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1791 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1796 spi1_clk: spi1-clk {
1798 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1800 spi1_cs0: spi1-cs0 {
1802 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1806 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1810 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1815 spi2_clk: spi2-clk {
1817 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1819 spi2_cs0: spi2-cs0 {
1821 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1825 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1829 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1834 spi3_clk: spi3-clk {
1836 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1838 spi3_cs0: spi3-cs0 {
1840 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1844 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1848 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1853 spi4_clk: spi4-clk {
1855 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1857 spi4_cs0: spi4-cs0 {
1859 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1863 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1867 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1872 spi5_clk: spi5-clk {
1874 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1876 spi5_cs0: spi5-cs0 {
1878 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1882 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1886 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1891 otp_gpio: otp-gpio {
1892 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1896 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1901 uart0_xfer: uart0-xfer {
1903 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1904 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1907 uart0_cts: uart0-cts {
1909 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1912 uart0_rts: uart0-rts {
1914 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1919 uart1_xfer: uart1-xfer {
1921 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1922 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1927 uart2a_xfer: uart2a-xfer {
1929 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1930 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1935 uart2b_xfer: uart2b-xfer {
1937 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1938 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1943 uart2c_xfer: uart2c-xfer {
1945 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1946 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1951 uart3_xfer: uart3-xfer {
1953 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1954 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1957 uart3_cts: uart3-cts {
1959 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1962 uart3_rts: uart3-rts {
1964 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1969 uart4_xfer: uart4-xfer {
1971 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1972 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1977 uarthdcp_xfer: uarthdcp-xfer {
1979 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1980 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1985 pwm0_pin: pwm0-pin {
1987 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1990 vop0_pwm_pin: vop0-pwm-pin {
1992 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1997 pwm1_pin: pwm1-pin {
1999 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2002 vop1_pwm_pin: vop1-pwm-pin {
2004 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2009 pwm2_pin: pwm2-pin {
2011 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2016 pwm3a_pin: pwm3a-pin {
2018 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2023 pwm3b_pin: pwm3b-pin {
2025 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2032 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2037 hdmi_i2c_xfer: hdmi-i2c-xfer {
2039 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2040 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2043 hdmi_cec: hdmi-cec {
2045 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2050 pcie_clkreqn: pci-clkreqn {
2052 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2055 pcie_clkreqnb: pci-clkreqnb {
2057 <4 24 RK_FUNC_1 &pcfg_pull_none>;