arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                 };
 122
 123                 cpu_l1: cpu@1 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x1>;
 127                         enable-method = "psci";
 128                         clocks = <&cru ARMCLKL>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         operating-points-v2 = <&cluster0_opp>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         operating-points-v2 = <&cluster0_opp>;
 141                 };
 142
 143                 cpu_l3: cpu@3 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         reg = <0x0 0x3>;
 147                         enable-method = "psci";
 148                         clocks = <&cru ARMCLKL>;
 149                         cpu-idle-states = <&cpu_sleep>;
 150                         operating-points-v2 = <&cluster0_opp>;
 151                 };
 152
 153                 cpu_b0: cpu@100 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a72", "arm,armv8";
 156                         reg = <0x0 0x100>;
 157                         enable-method = "psci";
 158                         #cooling-cells = <2>; /* min followed by max */
 159                         dynamic-power-coefficient = <1068>;
 160                         clocks = <&cru ARMCLKB>;
 161                         cpu-idle-states = <&cpu_sleep>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164
 165                 cpu_b1: cpu@101 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a72", "arm,armv8";
 168                         reg = <0x0 0x101>;
 169                         enable-method = "psci";
 170                         clocks = <&cru ARMCLKB>;
 171                         cpu-idle-states = <&cpu_sleep>;
 172                         operating-points-v2 = <&cluster1_opp>;
 173                 };
 174
 175                 idle-states {
 176                         entry-method = "psci";
 177                         cpu_sleep: cpu-sleep-0 {
 178                                 compatible = "arm,idle-state";
 179                                 local-timer-stop;
 180                                 arm,psci-suspend-param = <0x0010000>;
 181                                 entry-latency-us = <350>;
 182                                 exit-latency-us = <600>;
 183                                 min-residency-us = <1150>;
 184                         };
 185                 };
 186         };
 187
 188         cluster0_opp: opp_table0 {
 189                 compatible = "operating-points-v2";
 190                 opp-shared;
 191
 192                 opp00 {
 193                         opp-hz = /bits/ 64 <408000000>;
 194                         opp-microvolt = <800000>;
 195                         clock-latency-ns = <40000>;
 196                 };
 197                 opp01 {
 198                         opp-hz = /bits/ 64 <600000000>;
 199                         opp-microvolt = <800000>;
 200                 };
 201                 opp02 {
 202                         opp-hz = /bits/ 64 <816000000>;
 203                         opp-microvolt = <800000>;
 204                 };
 205                 opp03 {
 206                         opp-hz = /bits/ 64 <1008000000>;
 207                         opp-microvolt = <875000>;
 208                 };
 209                 opp04 {
 210                         opp-hz = /bits/ 64 <1200000000>;
 211                         opp-microvolt = <925000>;
 212                 };
 213                 opp05 {
 214                         opp-hz = /bits/ 64 <1416000000>;
 215                         opp-microvolt = <1025000>;
 216                 };
 217         };
 218
 219         cluster1_opp: opp_table1 {
 220                 compatible = "operating-points-v2";
 221                 opp-shared;
 222
 223                 opp00 {
 224                         opp-hz = /bits/ 64 <408000000>;
 225                         opp-microvolt = <800000>;
 226                         clock-latency-ns = <40000>;
 227                 };
 228                 opp01 {
 229                         opp-hz = /bits/ 64 <600000000>;
 230                         opp-microvolt = <800000>;
 231                 };
 232                 opp02 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <800000>;
 235                 };
 236                 opp03 {
 237                         opp-hz = /bits/ 64 <1008000000>;
 238                         opp-microvolt = <850000>;
 239                 };
 240                 opp04 {
 241                         opp-hz = /bits/ 64 <1200000000>;
 242                         opp-microvolt = <925000>;
 243                 };
 244         };
 245
 246         timer {
 247                 compatible = "arm,armv8-timer";
 248                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 251                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 252         };
 253
 254         arm-pmu {
 255                 compatible = "arm,armv8-pmuv3";
 256                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 257         };
 258
 259         xin24m: xin24m {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <24000000>;
 263                 clock-output-names = "xin24m";
 264         };
 265
 266         amba {
 267                 compatible = "arm,amba-bus";
 268                 #address-cells = <2>;
 269                 #size-cells = <2>;
 270                 ranges;
 271
 272                 dmac_bus: dma-controller@ff6d0000 {
 273                         compatible = "arm,pl330", "arm,primecell";
 274                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 275                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 277                         #dma-cells = <1>;
 278                         clocks = <&cru ACLK_DMAC0_PERILP>;
 279                         clock-names = "apb_pclk";
 280                 };
 281
 282                 dmac_peri: dma-controller@ff6e0000 {
 283                         compatible = "arm,pl330", "arm,primecell";
 284                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 285                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 287                         #dma-cells = <1>;
 288                         clocks = <&cru ACLK_DMAC1_PERILP>;
 289                         clock-names = "apb_pclk";
 290                 };
 291         };
 292
 293         gmac: eth@fe300000 {
 294                 compatible = "rockchip,rk3399-gmac";
 295                 reg = <0x0 0xfe300000 0x0 0x10000>;
 296                 rockchip,grf = <&grf>;
 297                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 298                 interrupt-names = "macirq";
 299                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 300                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 301                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 302                          <&cru PCLK_GMAC>;
 303                 clock-names = "stmmaceth", "mac_clk_rx",
 304                               "mac_clk_tx", "clk_mac_ref",
 305                               "clk_mac_refout", "aclk_mac",
 306                               "pclk_mac";
 307                 resets = <&cru SRST_A_GMAC>;
 308                 reset-names = "stmmaceth";
 309                 status = "disabled";
 310         };
 311
 312         emmc_phy: phy {
 313                 compatible = "rockchip,rk3399-emmc-phy";
 314                 reg-offset = <0xf780>;
 315                 #phy-cells = <0>;
 316                 rockchip,grf = <&grf>;
 317                 ctrl-base = <0xfe330000>;
 318                 status = "disabled";
 319         };
 320
 321         sdio0: dwmmc@fe310000 {
 322                 compatible = "rockchip,rk3399-dw-mshc",
 323                              "rockchip,rk3288-dw-mshc";
 324                 reg = <0x0 0xfe310000 0x0 0x4000>;
 325                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 326                 clock-freq-min-max = <400000 150000000>;
 327                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 328                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 329                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 330                 fifo-depth = <0x100>;
 331                 status = "disabled";
 332         };
 333
 334         sdmmc: dwmmc@fe320000 {
 335                 compatible = "rockchip,rk3399-dw-mshc",
 336                              "rockchip,rk3288-dw-mshc";
 337                 reg = <0x0 0xfe320000 0x0 0x4000>;
 338                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 339                 clock-freq-min-max = <400000 150000000>;
 340                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 341                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 342                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 343                 fifo-depth = <0x100>;
 344                 status = "disabled";
 345         };
 346
 347         sdhci: sdhci@fe330000 {
 348                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 349                 reg = <0x0 0xfe330000 0x0 0x10000>;
 350                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 352                 clock-names = "clk_xin", "clk_ahb";
 353                 assigned-clocks = <&cru SCLK_EMMC>;
 354                 assigned-clock-parents = <&cru PLL_CPLL>;
 355                 assigned-clock-rates = <200000000>;
 356                 phys = <&emmc_phy>;
 357                 phy-names = "phy_arasan";
 358                 status = "disabled";
 359         };
 360
 361         usb2phy: usb2phy {
 362                 compatible = "rockchip,rk3399-usb-phy";
 363                 rockchip,grf = <&grf>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366
 367                 usb2phy0: usb2-phy0 {
 368                         #phy-cells = <0>;
 369                         #clock-cells = <0>;
 370                         reg = <0xe458>;
 371                 };
 372
 373                 usb2phy1: usb2-phy1 {
 374                         #phy-cells = <0>;
 375                         #clock-cells = <0>;
 376                         reg = <0xe468>;
 377                 };
 378         };
 379
 380         usb_host0_ehci: usb@fe380000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0x0 0xfe380000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 385                 clock-names = "hclk_host0", "hclk_host0_arb";
 386                 phys = <&usb2phy0>;
 387                 phy-names = "usb2_phy0";
 388                 status = "disabled";
 389         };
 390
 391         usb_host0_ohci: usb@fe3a0000 {
 392                 compatible = "generic-ohci";
 393                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 status = "disabled";
 398         };
 399
 400         usb_host1_ehci: usb@fe3c0000 {
 401                 compatible = "generic-ehci";
 402                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 403                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 405                 clock-names = "hclk_host1", "hclk_host1_arb";
 406                 phys = <&usb2phy1>;
 407                 phy-names = "usb2_phy1";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ohci: usb@fe3e0000 {
 412                 compatible = "generic-ohci";
 413                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 status = "disabled";
 418         };
 419
 420         usbdrd3_0: usb@fe800000 {
 421                 compatible = "rockchip,dwc3";
 422                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 423                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 424                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 425                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 426                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 427                               "aclk_usb3", "aclk_usb3_grf";
 428                 #address-cells = <2>;
 429                 #size-cells = <2>;
 430                 ranges;
 431                 status = "disabled";
 432                 usbdrd_dwc3_0: dwc3@fe800000 {
 433                         compatible = "snps,dwc3";
 434                         reg = <0x0 0xfe800000 0x0 0x100000>;
 435                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 436                         dr_mode = "otg";
 437                         snps,dis_enblslpm_quirk;
 438                         snps,phyif_utmi_16_bits;
 439                         snps,dis_u2_freeclk_exists_quirk;
 440                         snps,dis_del_phy_power_chg_quirk;
 441                         snps,xhci_slow_suspend_quirk;
 442                         status = "disabled";
 443                 };
 444         };
 445
 446         usbdrd3_1: usb@fe900000 {
 447                 compatible = "rockchip,dwc3";
 448                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 449                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 450                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 451                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 452                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 453                               "aclk_usb3", "aclk_usb3_grf";
 454                 #address-cells = <2>;
 455                 #size-cells = <2>;
 456                 ranges;
 457                 status = "disabled";
 458                 usbdrd_dwc3_1: dwc3@fe900000 {
 459                         compatible = "snps,dwc3";
 460                         reg = <0x0 0xfe900000 0x0 0x100000>;
 461                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 462                         dr_mode = "otg";
 463                         snps,dis_enblslpm_quirk;
 464                         snps,phyif_utmi_16_bits;
 465                         snps,dis_u2_freeclk_exists_quirk;
 466                         snps,dis_del_phy_power_chg_quirk;
 467                         snps,xhci_slow_suspend_quirk;
 468                         status = "disabled";
 469                 };
 470         };
 471
 472         gic: interrupt-controller@fee00000 {
 473                 compatible = "arm,gic-v3";
 474                 #interrupt-cells = <3>;
 475                 #address-cells = <2>;
 476                 #size-cells = <2>;
 477                 ranges;
 478                 interrupt-controller;
 479
 480                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 481                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 482                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 483                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 484                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 485                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 486                 its: interrupt-controller@fee20000 {
 487                         compatible = "arm,gic-v3-its";
 488                         msi-controller;
 489                         reg = <0x0 0xfee20000 0x0 0x20000>;
 490                 };
 491         };
 492
 493         saradc: saradc@ff100000 {
 494                 compatible = "rockchip,rk3399-saradc";
 495                 reg = <0x0 0xff100000 0x0 0x100>;
 496                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 497                 #io-channel-cells = <1>;
 498                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 499                 clock-names = "saradc", "apb_pclk";
 500                 status = "disabled";
 501         };
 502
 503         i2c0: i2c@ff3c0000 {
 504                 compatible = "rockchip,rk3399-i2c";
 505                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 506                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 507                 clock-names = "i2c", "pclk";
 508                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&i2c0_xfer>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 status = "disabled";
 514         };
 515
 516         i2c1: i2c@ff110000 {
 517                 compatible = "rockchip,rk3399-i2c";
 518                 reg = <0x0 0xff110000 0x0 0x1000>;
 519                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 520                 clock-names = "i2c", "pclk";
 521                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&i2c1_xfer>;
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 status = "disabled";
 527         };
 528
 529         i2c2: i2c@ff120000 {
 530                 compatible = "rockchip,rk3399-i2c";
 531                 reg = <0x0 0xff120000 0x0 0x1000>;
 532                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c2_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c3: i2c@ff130000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff130000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 546                 clock-names = "i2c", "pclk";
 547                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c3_xfer>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         i2c5: i2c@ff140000 {
 556                 compatible = "rockchip,rk3399-i2c";
 557                 reg = <0x0 0xff140000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c5_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c6: i2c@ff150000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff150000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c6_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c7: i2c@ff160000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff160000 0x0 0x1000>;
 584                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c7_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         uart0: serial@ff180000 {
 595                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 596                 reg = <0x0 0xff180000 0x0 0x100>;
 597                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 598                 clock-names = "baudclk", "apb_pclk";
 599                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 600                 reg-shift = <2>;
 601                 reg-io-width = <4>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 604                 status = "disabled";
 605         };
 606
 607         uart1: serial@ff190000 {
 608                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 609                 reg = <0x0 0xff190000 0x0 0x100>;
 610                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 611                 clock-names = "baudclk", "apb_pclk";
 612                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 613                 reg-shift = <2>;
 614                 reg-io-width = <4>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart1_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         uart2: serial@ff1a0000 {
 621                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff1a0000 0x0 0x100>;
 623                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 624                 clock-names = "baudclk", "apb_pclk";
 625                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 626                 reg-shift = <2>;
 627                 reg-io-width = <4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&uart2c_xfer>;
 630                 status = "disabled";
 631         };
 632
 633         uart3: serial@ff1b0000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff1b0000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 643                 status = "disabled";
 644         };
 645
 646         spi0: spi@ff1c0000 {
 647                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 648                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 649                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 650                 clock-names = "spiclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 status = "disabled";
 657         };
 658
 659         spi1: spi@ff1d0000 {
 660                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 661                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 662                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 663                 clock-names = "spiclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 status = "disabled";
 670         };
 671
 672         spi2: spi@ff1e0000 {
 673                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 674                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 675                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 676                 clock-names = "spiclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         spi4: spi@ff1f0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         spi5: spi@ff200000 {
 699                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 700                 reg = <0x0 0xff200000 0x0 0x1000>;
 701                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 702                 clock-names = "spiclk", "apb_pclk";
 703                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 status = "disabled";
 709         };
 710
 711         thermal-zones {
 712                 soc_thermal: soc-thermal {
 713                         polling-delay-passive = <100>; /* milliseconds */
 714                         polling-delay = <1000>; /* milliseconds */
 715                         sustainable-power = <2600>; /* milliwatts */
 716
 717                         thermal-sensors = <&tsadc 0>;
 718
 719                         trips {
 720                                 threshold: trip-point@0 {
 721                                         temperature = <70000>; /* millicelsius */
 722                                         hysteresis = <2000>; /* millicelsius */
 723                                         type = "passive";
 724                                 };
 725                                 target: trip-point@1 {
 726                                         temperature = <85000>; /* millicelsius */
 727                                         hysteresis = <2000>; /* millicelsius */
 728                                         type = "passive";
 729                                 };
 730                                 soc_crit: soc-crit {
 731                                         temperature = <95000>; /* millicelsius */
 732                                         hysteresis = <2000>; /* millicelsius */
 733                                         type = "critical";
 734                                 };
 735                         };
 736
 737                         cooling-maps {
 738                                 map0 {
 739                                         trip = <&target>;
 740                                         cooling-device =
 741                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 742                                 };
 743                                 map1 {
 744                                         trip = <&target>;
 745                                         cooling-device =
 746                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 747                                 };
 748                                 map2 {
 749                                         trip = <&target>;
 750                                         cooling-device =
 751                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 752                                 };
 753                         };
 754                 };
 755
 756                 gpu_thermal: gpu-thermal {
 757                         polling-delay-passive = <100>; /* milliseconds */
 758                         polling-delay = <1000>; /* milliseconds */
 759
 760                         thermal-sensors = <&tsadc 1>;
 761                 };
 762         };
 763
 764         tsadc: tsadc@ff260000 {
 765                 compatible = "rockchip,rk3399-tsadc";
 766                 reg = <0x0 0xff260000 0x0 0x100>;
 767                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 768                 rockchip,grf = <&grf>;
 769                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 770                 clock-names = "tsadc", "apb_pclk";
 771                 assigned-clocks = <&cru SCLK_TSADC>;
 772                 assigned-clock-rates = <750000>;
 773                 resets = <&cru SRST_TSADC>;
 774                 reset-names = "tsadc-apb";
 775                 pinctrl-names = "init", "default", "sleep";
 776                 pinctrl-0 = <&otp_gpio>;
 777                 pinctrl-1 = <&otp_out>;
 778                 pinctrl-2 = <&otp_gpio>;
 779                 #thermal-sensor-cells = <1>;
 780                 rockchip,hw-tshut-temp = <95000>;
 781                 status = "disabled";
 782         };
 783
 784         qos_gpu: qos_gpu@0xffae0000 {
 785                 compatible ="syscon";
 786                 reg = <0x0 0xffae0000 0x0 0x20>;
 787         };
 788         qos_video_m0: qos_video_m0@0xffab8000 {
 789                 compatible ="syscon";
 790                 reg = <0x0 0xffab8000 0x0 0x20>;
 791         };
 792         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 793                 compatible ="syscon";
 794                 reg = <0x0 0xffac0000 0x0 0x20>;
 795         };
 796         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 797                 compatible ="syscon";
 798                 reg = <0x0 0xffac0080 0x0 0x20>;
 799         };
 800         qos_rga_r: qos_rga_r@0xffab0000 {
 801                 compatible ="syscon";
 802                 reg = <0x0 0xffab0000 0x0 0x20>;
 803         };
 804         qos_rga_w: qos_rga_w@0xffab0080 {
 805                 compatible ="syscon";
 806                 reg = <0x0 0xffab0000 0x0 0x20>;
 807         };
 808         qos_iep: qos_iep@0xffa98000 {
 809                 compatible ="syscon";
 810                 reg = <0x0 0xffa98000 0x0 0x20>;
 811         };
 812         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 813                 compatible ="syscon";
 814                 reg = <0x0 0xffac8000 0x0 0x20>;
 815         };
 816         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 817                 compatible ="syscon";
 818                 reg = <0x0 0xffac8080 0x0 0x20>;
 819         };
 820         qos_vop_little: qos_vop_little@0xffad0000 {
 821                 compatible ="syscon";
 822                 reg = <0x0 0xffad0000 0x0 0x20>;
 823         };
 824         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 825                 compatible ="syscon";
 826                 reg = <0x0 0xffaa0000 0x0 0x20>;
 827         };
 828         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 829                 compatible ="syscon";
 830                 reg = <0x0 0xffaa0080 0x0 0x20>;
 831         };
 832         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 833                 compatible ="syscon";
 834                 reg = <0x0 0xffaa8000 0x0 0x20>;
 835         };
 836         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 837                 compatible ="syscon";
 838                 reg = <0x0 0xffaa8080 0x0 0x20>;
 839         };
 840         qos_hdcp: qos_hdcp@0xffa90000 {
 841                 compatible ="syscon";
 842                 reg = <0x0 0xffa90000 0x0 0x20>;
 843         };
 844
 845         pmu: power-management@ff310000 {
 846                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 847                 reg = <0x0 0xff310000 0x0 0x1000>;
 848
 849                 power: power-controller {
 850                         status = "okay";
 851                         compatible = "rockchip,rk3399-power-controller";
 852                         #power-domain-cells = <1>;
 853                         #address-cells = <1>;
 854                         #size-cells = <0>;
 855
 856
 857                         pd_vdu {
 858                                 reg = <RK3399_PD_VDU>;
 859                                 pm_qos = <&qos_video_m1_r>,
 860                                          <&qos_video_m1_w>;
 861                         };
 862                         pd_vcodec {
 863                                 reg = <RK3399_PD_VCODEC>;
 864                                 pm_qos = <&qos_video_m0>;
 865                         };
 866                         pd_iep {
 867                                 reg = <RK3399_PD_IEP>;
 868                                 pm_qos = <&qos_iep>;
 869                         };
 870                         pd_rga {
 871                                 reg = <RK3399_PD_RGA>;
 872                                 pm_qos = <&qos_rga_r>,
 873                                          <&qos_rga_w>;
 874                         };
 875                         pd_vio {
 876                                 reg = <RK3399_PD_VIO>;
 877                                 #address-cells = <1>;
 878                                 #size-cells = <0>;
 879
 880                                 pd_isp0 {
 881                                         reg = <RK3399_PD_ISP0>;
 882                                         pm_qos = <&qos_isp0_m0>,
 883                                                  <&qos_isp0_m1>;
 884                                 };
 885                                 pd_isp1 {
 886                                         reg = <RK3399_PD_ISP1>;
 887                                         pm_qos = <&qos_isp1_m0>,
 888                                                  <&qos_isp1_m1>;
 889                                 };
 890                                 pd_hdcp {
 891                                         reg = <RK3399_PD_HDCP>;
 892                                         pm_qos = <&qos_hdcp>;
 893                                 };
 894                                 pd_vo {
 895                                         reg = <RK3399_PD_VO>;
 896                                         #address-cells = <1>;
 897                                         #size-cells = <0>;
 898
 899                                         pd_vopb {
 900                                                 reg = <RK3399_PD_VOPB>;
 901                                                 pm_qos = <&qos_vop_big_r>,
 902                                                          <&qos_vop_big_w>;
 903                                         };
 904                                         pd_vopl {
 905                                                 reg = <RK3399_PD_VOPL>;
 906                                                 pm_qos = <&qos_vop_little>;
 907                                         };
 908                                 };
 909                         };
 910                         pd_gpu {
 911                                 reg = <RK3399_PD_GPU>;
 912                                 pm_qos = <&qos_gpu>;
 913                         };
 914                 };
 915         };
 916
 917         pmugrf: syscon@ff320000 {
 918                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 919                 reg = <0x0 0xff320000 0x0 0x1000>;
 920
 921                 reboot-mode {
 922                         compatible = "syscon-reboot-mode";
 923                         offset = <0x300>;
 924                         mode-normal = <BOOT_NORMAL>;
 925                         mode-recovery = <BOOT_RECOVERY>;
 926                         mode-bootloader = <BOOT_FASTBOOT>;
 927                         mode-loader = <BOOT_LOADER>;
 928                 };
 929         };
 930
 931         spi3: spi@ff350000 {
 932                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 933                 reg = <0x0 0xff350000 0x0 0x1000>;
 934                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 935                 clock-names = "spiclk", "apb_pclk";
 936                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 937                 pinctrl-names = "default";
 938                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 939                 #address-cells = <1>;
 940                 #size-cells = <0>;
 941                 status = "disabled";
 942         };
 943
 944         uart4: serial@ff370000 {
 945                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 946                 reg = <0x0 0xff370000 0x0 0x100>;
 947                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 948                 clock-names = "baudclk", "apb_pclk";
 949                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 950                 reg-shift = <2>;
 951                 reg-io-width = <4>;
 952                 pinctrl-names = "default";
 953                 pinctrl-0 = <&uart4_xfer>;
 954                 status = "disabled";
 955         };
 956
 957         i2c4: i2c@ff3d0000 {
 958                 compatible = "rockchip,rk3399-i2c";
 959                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 960                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 961                 clock-names = "i2c", "pclk";
 962                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 963                 pinctrl-names = "default";
 964                 pinctrl-0 = <&i2c4_xfer>;
 965                 #address-cells = <1>;
 966                 #size-cells = <0>;
 967                 status = "disabled";
 968         };
 969
 970         i2c8: i2c@ff3e0000 {
 971                 compatible = "rockchip,rk3399-i2c";
 972                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 973                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 974                 clock-names = "i2c", "pclk";
 975                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 976                 pinctrl-names = "default";
 977                 pinctrl-0 = <&i2c8_xfer>;
 978                 #address-cells = <1>;
 979                 #size-cells = <0>;
 980                 status = "disabled";
 981         };
 982
 983         pcie0: pcie@f8000000 {
 984                 compatible = "rockchip,rk3399-pcie";
 985                 #address-cells = <3>;
 986                 #size-cells = <2>;
 987                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 988                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
 989                 clock-names = "aclk_pcie", "aclk_perf_pcie",
 990                               "hclk_pcie", "clk_pciephy_ref";
 991                 bus-range = <0x0 0x1>;
 992                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 993                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 994                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 995                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
 996                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
 997                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
 998                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
 999                       < 0x0 0xfd000000 0x0 0x1000000 >;
1000                 reg-name = "axi-base", "apb-base";
1001                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1002                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1003                          <&cru SRST_PCIE_PIPE>;
1004                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1005                               "mgmt-sticky-rst", "pipe-rst";
1006                 rockchip,grf = <&grf>;
1007                 pcie-conf = <0xe220>;
1008                 pcie-status = <0xe2a4>;
1009                 pcie-laneoff = <0xe214>;
1010                 msi-parent = <&its>;
1011                 #interrupt-cells = <1>;
1012                 interrupt-map-mask = <0 0 0 7>;
1013                 interrupt-map = <0 0 0 1 &pcie0 1>,
1014                                 <0 0 0 2 &pcie0 2>,
1015                                 <0 0 0 3 &pcie0 3>,
1016                                 <0 0 0 4 &pcie0 4>;
1017                 status = "disabled";
1018                 pcie_intc: interrupt-controller {
1019                         interrupt-controller;
1020                         #address-cells = <0>;
1021                         #interrupt-cells = <1>;
1022                 };
1023         };
1024
1025         pwm0: pwm@ff420000 {
1026                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1027                 reg = <0x0 0xff420000 0x0 0x10>;
1028                 #pwm-cells = <3>;
1029                 pinctrl-names = "default";
1030                 pinctrl-0 = <&pwm0_pin>;
1031                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1032                 clock-names = "pwm";
1033                 status = "disabled";
1034         };
1035
1036         pwm1: pwm@ff420010 {
1037                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1038                 reg = <0x0 0xff420010 0x0 0x10>;
1039                 #pwm-cells = <3>;
1040                 pinctrl-names = "default";
1041                 pinctrl-0 = <&pwm1_pin>;
1042                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1043                 clock-names = "pwm";
1044                 status = "disabled";
1045         };
1046
1047         pwm2: pwm@ff420020 {
1048                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1049                 reg = <0x0 0xff420020 0x0 0x10>;
1050                 #pwm-cells = <3>;
1051                 pinctrl-names = "default";
1052                 pinctrl-0 = <&pwm2_pin>;
1053                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1054                 clock-names = "pwm";
1055                 status = "disabled";
1056         };
1057
1058         pwm3: pwm@ff420030 {
1059                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1060                 reg = <0x0 0xff420030 0x0 0x10>;
1061                 #pwm-cells = <3>;
1062                 pinctrl-names = "default";
1063                 pinctrl-0 = <&pwm3a_pin>;
1064                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1065                 clock-names = "pwm";
1066                 status = "disabled";
1067         };
1068
1069         rga: rga@ff680000 {
1070                 compatible = "rockchip,rk3399-rga";
1071                 reg = <0x0 0xff680000 0x0 0x10000>;
1072                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1073                 interrupt-names = "rga";
1074                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1075                 clock-names = "aclk", "hclk", "sclk";
1076                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1077                 reset-names = "core", "axi", "ahb";
1078                 status = "disabled";
1079         };
1080
1081         pmucru: pmu-clock-controller@ff750000 {
1082                 compatible = "rockchip,rk3399-pmucru";
1083                 reg = <0x0 0xff750000 0x0 0x1000>;
1084                 #clock-cells = <1>;
1085                 #reset-cells = <1>;
1086                 assigned-clocks = <&pmucru PLL_PPLL>;
1087                 assigned-clock-rates = <676000000>;
1088         };
1089
1090         cru: clock-controller@ff760000 {
1091                 compatible = "rockchip,rk3399-cru";
1092                 reg = <0x0 0xff760000 0x0 0x1000>;
1093                 #clock-cells = <1>;
1094                 #reset-cells = <1>;
1095                 assigned-clocks =
1096                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1097                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1098                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1099                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1100                         <&cru PLL_NPLL>,
1101                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1102                         <&cru PCLK_PERIHP>,
1103                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1104                         <&cru PCLK_PERILP0>,
1105                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1106                 assigned-clock-rates =
1107                          <400000000>,  <200000000>,
1108                          <400000000>,  <200000000>,
1109                          <816000000>, <816000000>,
1110                          <594000000>,  <800000000>,
1111                         <1000000000>,
1112                          <150000000>,   <75000000>,
1113                           <37500000>,
1114                          <100000000>,  <100000000>,
1115                           <50000000>,
1116                          <100000000>,   <50000000>;
1117         };
1118
1119         grf: syscon@ff770000 {
1120                 compatible = "rockchip,rk3399-grf", "syscon";
1121                 reg = <0x0 0xff770000 0x0 0x10000>;
1122         };
1123
1124         watchdog@ff840000 {
1125                 compatible = "snps,dw-wdt";
1126                 reg = <0x0 0xff840000 0x0 0x100>;
1127                 clocks = <&cru PCLK_WDT>;
1128                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1129         };
1130
1131         rktimer: rktimer@ff850000 {
1132                 compatible = "rockchip,rk3399-timer";
1133                 reg = <0x0 0xff850000 0x0 0x1000>;
1134                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1135                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1136                 clock-names = "pclk", "timer";
1137         };
1138
1139         spdif: spdif@ff870000 {
1140                 compatible = "rockchip,rk3399-spdif";
1141                 reg = <0x0 0xff870000 0x0 0x1000>;
1142                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1143                 dmas = <&dmac_bus 7>;
1144                 dma-names = "tx";
1145                 clock-names = "mclk", "hclk";
1146                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1147                 pinctrl-names = "default";
1148                 pinctrl-0 = <&spdif_bus>;
1149                 status = "disabled";
1150         };
1151
1152         i2s0: i2s@ff880000 {
1153                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1154                 reg = <0x0 0xff880000 0x0 0x1000>;
1155                 rockchip,grf = <&grf>;
1156                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1157                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1158                 dma-names = "tx", "rx";
1159                 clock-names = "i2s_clk", "i2s_hclk";
1160                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1161                 pinctrl-names = "default";
1162                 pinctrl-0 = <&i2s0_8ch_bus>;
1163                 status = "disabled";
1164         };
1165
1166         i2s1: i2s@ff890000 {
1167                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1168                 reg = <0x0 0xff890000 0x0 0x1000>;
1169                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1170                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1171                 dma-names = "tx", "rx";
1172                 clock-names = "i2s_clk", "i2s_hclk";
1173                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1174                 pinctrl-names = "default";
1175                 pinctrl-0 = <&i2s1_2ch_bus>;
1176                 status = "disabled";
1177         };
1178
1179         i2s2: i2s@ff8a0000 {
1180                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1181                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1182                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1183                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1184                 dma-names = "tx", "rx";
1185                 clock-names = "i2s_clk", "i2s_hclk";
1186                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1187                 status = "disabled";
1188         };
1189
1190         gpu: gpu@ff9a0000 {
1191                 compatible = "arm,malit860",
1192                              "arm,malit86x",
1193                              "arm,malit8xx",
1194                              "arm,mali-midgard";
1195
1196                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1197
1198                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1199                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1200                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1201                 interrupt-names = "GPU", "JOB", "MMU";
1202
1203                 clocks = <&cru ACLK_GPU>;
1204                 clock-names = "clk_mali";
1205                 #cooling-cells = <2>; /* min followed by max */
1206                 operating-points-v2 = <&gpu_opp_table>;
1207                 power-domains = <&power RK3399_PD_GPU>;
1208                 status = "disabled";
1209
1210                 power_model {
1211                         compatible = "arm,mali-simple-power-model";
1212                         voltage = <900>;
1213                         frequency = <500>;
1214                         static-power = <300>;
1215                         dynamic-power = <1780>;
1216                         ts = <32000 4700 (-80) 2>;
1217                         thermal-zone = "gpu-thermal";
1218                 };
1219         };
1220
1221         gpu_opp_table: gpu_opp_table {
1222                 compatible = "operating-points-v2";
1223                 opp-shared;
1224
1225                 opp00 {
1226                         opp-hz = /bits/ 64 <200000000>;
1227                         opp-microvolt = <900000>;
1228                 };
1229                 opp01 {
1230                         opp-hz = /bits/ 64 <300000000>;
1231                         opp-microvolt = <900000>;
1232                 };
1233                 opp02 {
1234                         opp-hz = /bits/ 64 <400000000>;
1235                         opp-microvolt = <900000>;
1236                 };
1237
1238         };
1239
1240         vopl: vop@ff8f0000 {
1241                 compatible = "rockchip,rk3399-vop-lit";
1242                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1243                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1244                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1245                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1246                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1247                 reset-names = "axi", "ahb", "dclk";
1248                 iommus = <&vopl_mmu>;
1249                 status = "disabled";
1250
1251                 vopl_out: port {
1252                         #address-cells = <1>;
1253                         #size-cells = <0>;
1254
1255                         vopl_out_mipi: endpoint@0 {
1256                                 reg = <0>;
1257                                 remote-endpoint = <&mipi_in_vopl>;
1258                         };
1259
1260                         vopl_out_edp: endpoint@1 {
1261                                 reg = <1>;
1262                                 remote-endpoint = <&edp_in_vopl>;
1263                         };
1264                 };
1265         };
1266
1267         vopl_mmu: iommu@ff8f3f00 {
1268                 compatible = "rockchip,iommu";
1269                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1270                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1271                 interrupt-names = "vopl_mmu";
1272                 #iommu-cells = <0>;
1273                 status = "disabled";
1274         };
1275
1276         vopb: vop@ff900000 {
1277                 compatible = "rockchip,rk3399-vop-big";
1278                 reg = <0x0 0xff900000 0x0 0x3efc>;
1279                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1280                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1281                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1282                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1283                 reset-names = "axi", "ahb", "dclk";
1284                 iommus = <&vopb_mmu>;
1285                 status = "disabled";
1286
1287                 vopb_out: port {
1288                         #address-cells = <1>;
1289                         #size-cells = <0>;
1290
1291                         vopb_out_edp: endpoint@0 {
1292                                 reg = <0>;
1293                                 remote-endpoint = <&edp_in_vopb>;
1294                         };
1295
1296                         vopb_out_mipi: endpoint@1 {
1297                                 reg = <1>;
1298                                 remote-endpoint = <&mipi_in_vopb>;
1299                         };
1300                 };
1301         };
1302
1303         vopb_mmu: iommu@ff903f00 {
1304                 compatible = "rockchip,iommu";
1305                 reg = <0x0 0xff903f00 0x0 0x100>;
1306                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1307                 interrupt-names = "vopb_mmu";
1308                 #iommu-cells = <0>;
1309                 status = "disabled";
1310         };
1311
1312         mipi_dsi: mipi@ff960000 {
1313                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1314                 reg = <0x0 0xff960000 0x0 0x8000>;
1315                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1316                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1317                          <&cru SCLK_DPHY_TX0_CFG>;
1318                 clock-names = "ref", "pclk", "phy_cfg";
1319                 rockchip,grf = <&grf>;
1320                 #address-cells = <1>;
1321                 #size-cells = <0>;
1322                 status = "disabled";
1323
1324                 ports {
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327                         reg = <1>;
1328
1329                         mipi_in: port {
1330                                 #address-cells = <1>;
1331                                 #size-cells = <0>;
1332
1333                                 mipi_in_vopb: endpoint@0 {
1334                                         reg = <0>;
1335                                         remote-endpoint = <&vopb_out_mipi>;
1336                                 };
1337                                 mipi_in_vopl: endpoint@1 {
1338                                         reg = <1>;
1339                                         remote-endpoint = <&vopl_out_mipi>;
1340                                 };
1341                         };
1342                 };
1343         };
1344
1345         edp: edp@ff970000 {
1346                 compatible = "rockchip,rk3399-edp";
1347                 reg = <0x0 0xff970000 0x0 0x8000>;
1348                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1349                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1350                 clock-names = "dp", "pclk";
1351                 resets = <&cru SRST_P_EDP_CTRL>;
1352                 reset-names = "dp";
1353                 rockchip,grf = <&grf>;
1354                 status = "disabled";
1355                 pinctrl-names = "default";
1356                 pinctrl-0 = <&edp_hpd>;
1357
1358                 ports {
1359                         #address-cells = <1>;
1360                         #size-cells = <0>;
1361
1362                         edp_in: port@0 {
1363                                 reg = <0>;
1364                                 #address-cells = <1>;
1365                                 #size-cells = <0>;
1366
1367                                 edp_in_vopb: endpoint@0 {
1368                                         reg = <0>;
1369                                         remote-endpoint = <&vopb_out_edp>;
1370                                 };
1371
1372                                 edp_in_vopl: endpoint@1 {
1373                                         reg = <1>;
1374                                         remote-endpoint = <&vopl_out_edp>;
1375                                 };
1376                         };
1377                 };
1378         };
1379
1380         display_subsystem: display-subsystem {
1381                 compatible = "rockchip,display-subsystem";
1382                 ports = <&vopl_out>, <&vopb_out>;
1383                 status = "disabled";
1384         };
1385
1386         pinctrl: pinctrl {
1387                 compatible = "rockchip,rk3399-pinctrl";
1388                 rockchip,grf = <&grf>;
1389                 rockchip,pmu = <&pmugrf>;
1390                 #address-cells = <0x2>;
1391                 #size-cells = <0x2>;
1392                 ranges;
1393
1394                 gpio0: gpio0@ff720000 {
1395                         compatible = "rockchip,gpio-bank";
1396                         reg = <0x0 0xff720000 0x0 0x100>;
1397                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1398                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1399
1400                         gpio-controller;
1401                         #gpio-cells = <0x2>;
1402
1403                         interrupt-controller;
1404                         #interrupt-cells = <0x2>;
1405                 };
1406
1407                 gpio1: gpio1@ff730000 {
1408                         compatible = "rockchip,gpio-bank";
1409                         reg = <0x0 0xff730000 0x0 0x100>;
1410                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1411                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1412
1413                         gpio-controller;
1414                         #gpio-cells = <0x2>;
1415
1416                         interrupt-controller;
1417                         #interrupt-cells = <0x2>;
1418                 };
1419
1420                 gpio2: gpio2@ff780000 {
1421                         compatible = "rockchip,gpio-bank";
1422                         reg = <0x0 0xff780000 0x0 0x100>;
1423                         clocks = <&cru PCLK_GPIO2>;
1424                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1425
1426                         gpio-controller;
1427                         #gpio-cells = <0x2>;
1428
1429                         interrupt-controller;
1430                         #interrupt-cells = <0x2>;
1431                 };
1432
1433                 gpio3: gpio3@ff788000 {
1434                         compatible = "rockchip,gpio-bank";
1435                         reg = <0x0 0xff788000 0x0 0x100>;
1436                         clocks = <&cru PCLK_GPIO3>;
1437                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1438
1439                         gpio-controller;
1440                         #gpio-cells = <0x2>;
1441
1442                         interrupt-controller;
1443                         #interrupt-cells = <0x2>;
1444                 };
1445
1446                 gpio4: gpio4@ff790000 {
1447                         compatible = "rockchip,gpio-bank";
1448                         reg = <0x0 0xff790000 0x0 0x100>;
1449                         clocks = <&cru PCLK_GPIO4>;
1450                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1451
1452                         gpio-controller;
1453                         #gpio-cells = <0x2>;
1454
1455                         interrupt-controller;
1456                         #interrupt-cells = <0x2>;
1457                 };
1458
1459                 pcfg_pull_up: pcfg-pull-up {
1460                         bias-pull-up;
1461                 };
1462
1463                 pcfg_pull_down: pcfg-pull-down {
1464                         bias-pull-down;
1465                 };
1466
1467                 pcfg_pull_none: pcfg-pull-none {
1468                         bias-disable;
1469                 };
1470
1471                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1472                         bias-disable;
1473                         drive-strength = <12>;
1474                 };
1475
1476                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1477                         bias-pull-up;
1478                         drive-strength = <8>;
1479                 };
1480
1481                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1482                         bias-pull-down;
1483                         drive-strength = <4>;
1484                 };
1485
1486                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1487                         bias-pull-up;
1488                         drive-strength = <2>;
1489                 };
1490
1491                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1492                         bias-pull-down;
1493                         drive-strength = <12>;
1494                 };
1495
1496                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1497                         bias-disable;
1498                         drive-strength = <13>;
1499                 };
1500
1501                 emmc {
1502                         emmc_pwr: emmc-pwr {
1503                                 rockchip,pins =
1504                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506                 };
1507
1508                 gmac {
1509                         rgmii_pins: rgmii-pins {
1510                                 rockchip,pins =
1511                                         /* mac_txclk */
1512                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1513                                         /* mac_rxclk */
1514                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_mdio */
1516                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1517                                         /* mac_txen */
1518                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1519                                         /* mac_clk */
1520                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1521                                         /* mac_rxdv */
1522                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1523                                         /* mac_mdc */
1524                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1525                                         /* mac_rxd1 */
1526                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1527                                         /* mac_rxd0 */
1528                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1529                                         /* mac_txd1 */
1530                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1531                                         /* mac_txd0 */
1532                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1533                                         /* mac_rxd3 */
1534                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1535                                         /* mac_rxd2 */
1536                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1537                                         /* mac_txd3 */
1538                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1539                                         /* mac_txd2 */
1540                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1541                         };
1542
1543                         rmii_pins: rmii-pins {
1544                                 rockchip,pins =
1545                                         /* mac_mdio */
1546                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1547                                         /* mac_txen */
1548                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1549                                         /* mac_clk */
1550                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1551                                         /* mac_rxer */
1552                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1553                                         /* mac_rxdv */
1554                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1555                                         /* mac_mdc */
1556                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1557                                         /* mac_rxd1 */
1558                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxd0 */
1560                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_txd1 */
1562                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1563                                         /* mac_txd0 */
1564                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1565                         };
1566                 };
1567
1568                 i2c0 {
1569                         i2c0_xfer: i2c0-xfer {
1570                                 rockchip,pins =
1571                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1572                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1573                         };
1574                 };
1575
1576                 i2c1 {
1577                         i2c1_xfer: i2c1-xfer {
1578                                 rockchip,pins =
1579                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1580                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582                 };
1583
1584                 i2c2 {
1585                         i2c2_xfer: i2c2-xfer {
1586                                 rockchip,pins =
1587                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1588                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1589                         };
1590                 };
1591
1592                 i2c3 {
1593                         i2c3_xfer: i2c3-xfer {
1594                                 rockchip,pins =
1595                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1596                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1597                         };
1598
1599                         i2c3_gpio: i2c3_gpio {
1600                                 rockchip,pins =
1601                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1602                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1603                         };
1604
1605                 };
1606
1607                 i2c4 {
1608                         i2c4_xfer: i2c4-xfer {
1609                                 rockchip,pins =
1610                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1611                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1612                         };
1613                 };
1614
1615                 i2c5 {
1616                         i2c5_xfer: i2c5-xfer {
1617                                 rockchip,pins =
1618                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1619                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1620                         };
1621                 };
1622
1623                 i2c6 {
1624                         i2c6_xfer: i2c6-xfer {
1625                                 rockchip,pins =
1626                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1627                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1628                         };
1629                 };
1630
1631                 i2c7 {
1632                         i2c7_xfer: i2c7-xfer {
1633                                 rockchip,pins =
1634                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1635                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 i2c8 {
1640                         i2c8_xfer: i2c8-xfer {
1641                                 rockchip,pins =
1642                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1643                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 i2s0 {
1648                         i2s0_8ch_bus: i2s0-8ch-bus {
1649                                 rockchip,pins =
1650                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1651                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1652                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1653                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1654                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1655                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1656                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1657                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1658                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1659                         };
1660                 };
1661
1662                 i2s1 {
1663                         i2s1_2ch_bus: i2s1-2ch-bus {
1664                                 rockchip,pins =
1665                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1666                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1667                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1668                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1669                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671                 };
1672
1673                 sdio0 {
1674                         sdio0_bus1: sdio0-bus1 {
1675                                 rockchip,pins =
1676                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1677                         };
1678
1679                         sdio0_bus4: sdio0-bus4 {
1680                                 rockchip,pins =
1681                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1682                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1683                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1684                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1685                         };
1686
1687                         sdio0_cmd: sdio0-cmd {
1688                                 rockchip,pins =
1689                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1690                         };
1691
1692                         sdio0_clk: sdio0-clk {
1693                                 rockchip,pins =
1694                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1695                         };
1696
1697                         sdio0_cd: sdio0-cd {
1698                                 rockchip,pins =
1699                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1700                         };
1701
1702                         sdio0_pwr: sdio0-pwr {
1703                                 rockchip,pins =
1704                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706
1707                         sdio0_bkpwr: sdio0-bkpwr {
1708                                 rockchip,pins =
1709                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1710                         };
1711
1712                         sdio0_wp: sdio0-wp {
1713                                 rockchip,pins =
1714                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio0_int: sdio0-int {
1718                                 rockchip,pins =
1719                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1720                         };
1721                 };
1722
1723                 sdmmc {
1724                         sdmmc_bus1: sdmmc-bus1 {
1725                                 rockchip,pins =
1726                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1727                         };
1728
1729                         sdmmc_bus4: sdmmc-bus4 {
1730                                 rockchip,pins =
1731                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1732                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1733                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1734                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1735                         };
1736
1737                         sdmmc_clk: sdmmc-clk {
1738                                 rockchip,pins =
1739                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1740                         };
1741
1742                         sdmmc_cmd: sdmmc-cmd {
1743                                 rockchip,pins =
1744                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1745                         };
1746
1747                         sdmmc_cd: sdmcc-cd {
1748                                 rockchip,pins =
1749                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1750                         };
1751
1752                         sdmmc_wp: sdmmc-wp {
1753                                 rockchip,pins =
1754                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1755                         };
1756                 };
1757
1758                 spdif {
1759                         spdif_bus: spdif-bus {
1760                                 rockchip,pins =
1761                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1762                         };
1763                 };
1764
1765                 spi0 {
1766                         spi0_clk: spi0-clk {
1767                                 rockchip,pins =
1768                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1769                         };
1770                         spi0_cs0: spi0-cs0 {
1771                                 rockchip,pins =
1772                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1773                         };
1774                         spi0_cs1: spi0-cs1 {
1775                                 rockchip,pins =
1776                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1777                         };
1778                         spi0_tx: spi0-tx {
1779                                 rockchip,pins =
1780                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1781                         };
1782                         spi0_rx: spi0-rx {
1783                                 rockchip,pins =
1784                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1785                         };
1786                 };
1787
1788                 spi1 {
1789                         spi1_clk: spi1-clk {
1790                                 rockchip,pins =
1791                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1792                         };
1793                         spi1_cs0: spi1-cs0 {
1794                                 rockchip,pins =
1795                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1796                         };
1797                         spi1_rx: spi1-rx {
1798                                 rockchip,pins =
1799                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1800                         };
1801                         spi1_tx: spi1-tx {
1802                                 rockchip,pins =
1803                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1804                         };
1805                 };
1806
1807                 spi2 {
1808                         spi2_clk: spi2-clk {
1809                                 rockchip,pins =
1810                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1811                         };
1812                         spi2_cs0: spi2-cs0 {
1813                                 rockchip,pins =
1814                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1815                         };
1816                         spi2_rx: spi2-rx {
1817                                 rockchip,pins =
1818                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1819                         };
1820                         spi2_tx: spi2-tx {
1821                                 rockchip,pins =
1822                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1823                         };
1824                 };
1825
1826                 spi3 {
1827                         spi3_clk: spi3-clk {
1828                                 rockchip,pins =
1829                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1830                         };
1831                         spi3_cs0: spi3-cs0 {
1832                                 rockchip,pins =
1833                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835                         spi3_rx: spi3-rx {
1836                                 rockchip,pins =
1837                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839                         spi3_tx: spi3-tx {
1840                                 rockchip,pins =
1841                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1842                         };
1843                 };
1844
1845                 spi4 {
1846                         spi4_clk: spi4-clk {
1847                                 rockchip,pins =
1848                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1849                         };
1850                         spi4_cs0: spi4-cs0 {
1851                                 rockchip,pins =
1852                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1853                         };
1854                         spi4_rx: spi4-rx {
1855                                 rockchip,pins =
1856                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1857                         };
1858                         spi4_tx: spi4-tx {
1859                                 rockchip,pins =
1860                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1861                         };
1862                 };
1863
1864                 spi5 {
1865                         spi5_clk: spi5-clk {
1866                                 rockchip,pins =
1867                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1868                         };
1869                         spi5_cs0: spi5-cs0 {
1870                                 rockchip,pins =
1871                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1872                         };
1873                         spi5_rx: spi5-rx {
1874                                 rockchip,pins =
1875                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1876                         };
1877                         spi5_tx: spi5-tx {
1878                                 rockchip,pins =
1879                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1880                         };
1881                 };
1882
1883                 tsadc {
1884                         otp_gpio: otp-gpio {
1885                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1886                         };
1887
1888                         otp_out: otp-out {
1889                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1890                         };
1891                 };
1892
1893                 uart0 {
1894                         uart0_xfer: uart0-xfer {
1895                                 rockchip,pins =
1896                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1897                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1898                         };
1899
1900                         uart0_cts: uart0-cts {
1901                                 rockchip,pins =
1902                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1903                         };
1904
1905                         uart0_rts: uart0-rts {
1906                                 rockchip,pins =
1907                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1908                         };
1909                 };
1910
1911                 uart1 {
1912                         uart1_xfer: uart1-xfer {
1913                                 rockchip,pins =
1914                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1915                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1916                         };
1917                 };
1918
1919                 uart2a {
1920                         uart2a_xfer: uart2a-xfer {
1921                                 rockchip,pins =
1922                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1923                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1924                         };
1925                 };
1926
1927                 uart2b {
1928                         uart2b_xfer: uart2b-xfer {
1929                                 rockchip,pins =
1930                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1931                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1932                         };
1933                 };
1934
1935                 uart2c {
1936                         uart2c_xfer: uart2c-xfer {
1937                                 rockchip,pins =
1938                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1939                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 uart3 {
1944                         uart3_xfer: uart3-xfer {
1945                                 rockchip,pins =
1946                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1947                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1948                         };
1949
1950                         uart3_cts: uart3-cts {
1951                                 rockchip,pins =
1952                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1953                         };
1954
1955                         uart3_rts: uart3-rts {
1956                                 rockchip,pins =
1957                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1958                         };
1959                 };
1960
1961                 uart4 {
1962                         uart4_xfer: uart4-xfer {
1963                                 rockchip,pins =
1964                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1965                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1966                         };
1967                 };
1968
1969                 uarthdcp {
1970                         uarthdcp_xfer: uarthdcp-xfer {
1971                                 rockchip,pins =
1972                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1973                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1974                         };
1975                 };
1976
1977                 pwm0 {
1978                         pwm0_pin: pwm0-pin {
1979                                 rockchip,pins =
1980                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1981                         };
1982
1983                         vop0_pwm_pin: vop0-pwm-pin {
1984                                 rockchip,pins =
1985                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1986                         };
1987                 };
1988
1989                 pwm1 {
1990                         pwm1_pin: pwm1-pin {
1991                                 rockchip,pins =
1992                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1993                         };
1994
1995                         vop1_pwm_pin: vop1-pwm-pin {
1996                                 rockchip,pins =
1997                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1998                         };
1999                 };
2000
2001                 pwm2 {
2002                         pwm2_pin: pwm2-pin {
2003                                 rockchip,pins =
2004                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2005                         };
2006                 };
2007
2008                 pwm3a {
2009                         pwm3a_pin: pwm3a-pin {
2010                                 rockchip,pins =
2011                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2012                         };
2013                 };
2014
2015                 pwm3b {
2016                         pwm3b_pin: pwm3b-pin {
2017                                 rockchip,pins =
2018                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2019                         };
2020                 };
2021
2022                 edp {
2023                         edp_hpd: edp-hpd {
2024                                 rockchip,pins =
2025                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2026                         };
2027                 };
2028
2029                 hdmi {
2030                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2031                                 rockchip,pins =
2032                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2033                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2034                         };
2035
2036                         hdmi_cec: hdmi-cec {
2037                                 rockchip,pins =
2038                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2039                         };
2040                 };
2041
2042                 pcie {
2043                         pcie_clkreqn: pci-clkreqn {
2044                                 rockchip,pins =
2045                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2046                         };
2047
2048                         pcie_clkreqnb: pci-clkreqnb {
2049                                 rockchip,pins =
2050                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2051                         };
2052                 };
2053         };
2054 };